hw/arm/bcm2836.c

   1 /*
   2  * Raspberry Pi emulation (c) 2012 Gregory Estrade
   3  * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous
   4  *
   5  * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft
   6  * Written by Andrew Baumann
   7  *
   8  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   9  * See the COPYING file in the top-level directory.
  10  */
  11
  12 #include "qemu/osdep.h"
  13 #include "qapi/error.h"
  14 #include "qemu/module.h"
  15 #include "hw/arm/bcm2836.h"
  16 #include "hw/arm/raspi_platform.h"
  17 #include "hw/sysbus.h"
  18 #include "target/arm/cpu-qom.h"
  19 #include "target/arm/gtimer.h"
  20
  21 struct BCM283XClass {
  22     /*< private >*/
  23     DeviceClass parent_class;
  24     /*< public >*/
  25     const char *name;
  26     const char *cpu_type;
  27     unsigned core_count;
  28     hwaddr peri_base; /* Peripheral base address seen by the CPU */
  29     hwaddr ctrl_base; /* Interrupt controller and mailboxes etc. */
  30     int clusterid;
  31 };
  32
  33 static Property bcm2836_enabled_cores_property =
  34     DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus, 0);
  35
  36 static void bcm2836_init(Object *obj)
  37 {
  38     BCM283XState *s = BCM283X(obj);
  39     BCM283XClass *bc = BCM283X_GET_CLASS(obj);
  40     int n;
  41
  42     for (n = 0; n < bc->core_count; n++) {
  43         object_initialize_child(obj, "cpu[*]", &s->cpu[n].core,
  44                                 bc->cpu_type);
  45     }
  46     if (bc->core_count > 1) {
  47         qdev_property_add_static(DEVICE(obj), &bcm2836_enabled_cores_property);
  48         qdev_prop_set_uint32(DEVICE(obj), "enabled-cpus", bc->core_count);
  49     }
  50
  51     if (bc->ctrl_base) {
  52         object_initialize_child(obj, "control", &s->control,
  53                                 TYPE_BCM2836_CONTROL);
  54     }
  55
  56     object_initialize_child(obj, "peripherals", &s->peripherals,
  57                             TYPE_BCM2835_PERIPHERALS);
  58     object_property_add_alias(obj, "board-rev", OBJECT(&s->peripherals),
  59                               "board-rev");
  60     object_property_add_alias(obj, "command-line", OBJECT(&s->peripherals),
  61                               "command-line");
  62     object_property_add_alias(obj, "vcram-size", OBJECT(&s->peripherals),
  63                               "vcram-size");
  64 }
  65
  66 static bool bcm283x_common_realize(DeviceState *dev, Error **errp)
  67 {
  68     BCM283XState *s = BCM283X(dev);
  69     BCM283XClass *bc = BCM283X_GET_CLASS(dev);
  70     Object *obj;
  71
  72     /* common peripherals from bcm2835 */
  73
  74     obj = object_property_get_link(OBJECT(dev), "ram", &error_abort);
  75
  76     object_property_add_const_link(OBJECT(&s->peripherals), "ram", obj);
  77
  78     if (!sysbus_realize(SYS_BUS_DEVICE(&s->peripherals), errp)) {
  79         return false;
  80     }
  81
  82     object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->peripherals),
  83                               "sd-bus");
  84
  85     sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->peripherals), 0,
  86                             bc->peri_base, 1);
  87     return true;
  88 }
  89
  90 static void bcm2835_realize(DeviceState *dev, Error **errp)
  91 {
  92     BCM283XState *s = BCM283X(dev);
  93
  94     if (!bcm283x_common_realize(dev, errp)) {
  95         return;
  96     }
  97
  98     if (!qdev_realize(DEVICE(&s->cpu[0].core), NULL, errp)) {
  99         return;
 100     }
 101
 102     /* Connect irq/fiq outputs from the interrupt controller. */
 103     sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0,
 104             qdev_get_gpio_in(DEVICE(&s->cpu[0].core), ARM_CPU_IRQ));
 105     sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1,
 106             qdev_get_gpio_in(DEVICE(&s->cpu[0].core), ARM_CPU_FIQ));
 107 }
 108
 109 static void bcm2836_realize(DeviceState *dev, Error **errp)
 110 {
 111     BCM283XState *s = BCM283X(dev);
 112     BCM283XClass *bc = BCM283X_GET_CLASS(dev);
 113     int n;
 114
 115     if (!bcm283x_common_realize(dev, errp)) {
 116         return;
 117     }
 118
 119     /* bcm2836 interrupt controller (and mailboxes, etc.) */
 120     if (!sysbus_realize(SYS_BUS_DEVICE(&s->control), errp)) {
 121         return;
 122     }
 123
 124     sysbus_mmio_map(SYS_BUS_DEVICE(&s->control), 0, bc->ctrl_base);
 125
 126     sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0,
 127         qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-irq", 0));
 128     sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1,
 129         qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0));
 130
 131     for (n = 0; n < BCM283X_NCPUS; n++) {
 132         object_property_set_int(OBJECT(&s->cpu[n].core), "mp-affinity",
 133                                 (bc->clusterid << 8) | n, &error_abort);
 134
 135         /* set periphbase/CBAR value for CPU-local registers */
 136         object_property_set_int(OBJECT(&s->cpu[n].core), "reset-cbar",
 137                                 bc->peri_base, &error_abort);
 138
 139         /* start powered off if not enabled */
 140         object_property_set_bool(OBJECT(&s->cpu[n].core), "start-powered-off",
 141                                  n >= s->enabled_cpus, &error_abort);
 142
 143         if (!qdev_realize(DEVICE(&s->cpu[n].core), NULL, errp)) {
 144             return;
 145         }
 146
 147         /* Connect irq/fiq outputs from the interrupt controller. */
 148         qdev_connect_gpio_out_named(DEVICE(&s->control), "irq", n,
 149                 qdev_get_gpio_in(DEVICE(&s->cpu[n].core), ARM_CPU_IRQ));
 150         qdev_connect_gpio_out_named(DEVICE(&s->control), "fiq", n,
 151                 qdev_get_gpio_in(DEVICE(&s->cpu[n].core), ARM_CPU_FIQ));
 152
 153         /* Connect timers from the CPU to the interrupt controller */
 154         qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_PHYS,
 155                 qdev_get_gpio_in_named(DEVICE(&s->control), "cntpnsirq", n));
 156         qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_VIRT,
 157                 qdev_get_gpio_in_named(DEVICE(&s->control), "cntvirq", n));
 158         qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_HYP,
 159                 qdev_get_gpio_in_named(DEVICE(&s->control), "cnthpirq", n));
 160         qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_SEC,
 161                 qdev_get_gpio_in_named(DEVICE(&s->control), "cntpsirq", n));
 162     }
 163 }
 164
 165 static void bcm283x_class_init(ObjectClass *oc, void *data)
 166 {
 167     DeviceClass *dc = DEVICE_CLASS(oc);
 168
 169     /* Reason: Must be wired up in code (see raspi_init() function) */
 170     dc->user_creatable = false;
 171 }
 172
 173 static void bcm2835_class_init(ObjectClass *oc, void *data)
 174 {
 175     DeviceClass *dc = DEVICE_CLASS(oc);
 176     BCM283XClass *bc = BCM283X_CLASS(oc);
 177
 178     bc->cpu_type = ARM_CPU_TYPE_NAME("arm1176");
 179     bc->core_count = 1;
 180     bc->peri_base = 0x20000000;
 181     dc->realize = bcm2835_realize;
 182 };
 183
 184 static void bcm2836_class_init(ObjectClass *oc, void *data)
 185 {
 186     DeviceClass *dc = DEVICE_CLASS(oc);
 187     BCM283XClass *bc = BCM283X_CLASS(oc);
 188
 189     bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
 190     bc->core_count = BCM283X_NCPUS;
 191     bc->peri_base = 0x3f000000;
 192     bc->ctrl_base = 0x40000000;
 193     bc->clusterid = 0xf;
 194     dc->realize = bcm2836_realize;
 195 };
 196
 197 #ifdef TARGET_AARCH64
 198 static void bcm2837_class_init(ObjectClass *oc, void *data)
 199 {
 200     DeviceClass *dc = DEVICE_CLASS(oc);
 201     BCM283XClass *bc = BCM283X_CLASS(oc);
 202
 203     bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a53");
 204     bc->core_count = BCM283X_NCPUS;
 205     bc->peri_base = 0x3f000000;
 206     bc->ctrl_base = 0x40000000;
 207     bc->clusterid = 0x0;
 208     dc->realize = bcm2836_realize;
 209 };
 210 #endif
 211
 212 static const TypeInfo bcm283x_types[] = {
 213     {
 214         .name           = TYPE_BCM2835,
 215         .parent         = TYPE_BCM283X,
 216         .class_init     = bcm2835_class_init,
 217     }, {
 218         .name           = TYPE_BCM2836,
 219         .parent         = TYPE_BCM283X,
 220         .class_init     = bcm2836_class_init,
 221 #ifdef TARGET_AARCH64
 222     }, {
 223         .name           = TYPE_BCM2837,
 224         .parent         = TYPE_BCM283X,
 225         .class_init     = bcm2837_class_init,
 226 #endif
 227     }, {
 228         .name           = TYPE_BCM283X,
 229         .parent         = TYPE_DEVICE,
 230         .instance_size  = sizeof(BCM283XState),
 231         .instance_init  = bcm2836_init,
 232         .class_size     = sizeof(BCM283XClass),
 233         .class_init     = bcm283x_class_init,
 234         .abstract       = true,
 235     }
 236 };
 237
 238 DEFINE_TYPES(bcm283x_types)