hw/arm/xlnx-versal.c

   1 /*
   2  * Xilinx Versal SoC model.
   3  *
   4  * Copyright (c) 2018 Xilinx Inc.
   5  * Written by Edgar E. Iglesias
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 or
   9  * (at your option) any later version.
  10  */
  11
  12 #include "qemu/osdep.h"
  13 #include "qapi/error.h"
  14 #include "qemu/log.h"
  15 #include "qemu/module.h"
  16 #include "hw/sysbus.h"
  17 #include "net/net.h"
  18 #include "sysemu/sysemu.h"
  19 #include "sysemu/kvm.h"
  20 #include "hw/arm/boot.h"
  21 #include "kvm_arm.h"
  22 #include "hw/misc/unimp.h"
  23 #include "hw/arm/xlnx-versal.h"
  24
  25 #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72")
  26 #define GEM_REVISION        0x40070106
  27
  28 static void versal_create_apu_cpus(Versal *s)
  29 {
  30     int i;
  31
  32     for (i = 0; i < ARRAY_SIZE(s->fpd.apu.cpu); i++) {
  33         Object *obj;
  34
  35         object_initialize_child(OBJECT(s), "apu-cpu[*]", &s->fpd.apu.cpu[i],
  36                                 XLNX_VERSAL_ACPU_TYPE);
  37         obj = OBJECT(&s->fpd.apu.cpu[i]);
  38         object_property_set_int(obj, "psci-conduit", s->cfg.psci_conduit,
  39                                 &error_abort);
  40         if (i) {
  41             /* Secondary CPUs start in PSCI powered-down state */
  42             object_property_set_bool(obj, "start-powered-off", true,
  43                                      &error_abort);
  44         }
  45
  46         object_property_set_int(obj, "core-count", ARRAY_SIZE(s->fpd.apu.cpu),
  47                                 &error_abort);
  48         object_property_set_link(obj, "memory", OBJECT(&s->fpd.apu.mr),
  49                                  &error_abort);
  50         qdev_realize(DEVICE(obj), NULL, &error_fatal);
  51     }
  52 }
  53
  54 static void versal_create_apu_gic(Versal *s, qemu_irq *pic)
  55 {
  56     static const uint64_t addrs[] = {
  57         MM_GIC_APU_DIST_MAIN,
  58         MM_GIC_APU_REDIST_0
  59     };
  60     SysBusDevice *gicbusdev;
  61     DeviceState *gicdev;
  62     int nr_apu_cpus = ARRAY_SIZE(s->fpd.apu.cpu);
  63     int i;
  64
  65     object_initialize_child(OBJECT(s), "apu-gic", &s->fpd.apu.gic,
  66                             gicv3_class_name());
  67     gicbusdev = SYS_BUS_DEVICE(&s->fpd.apu.gic);
  68     gicdev = DEVICE(&s->fpd.apu.gic);
  69     qdev_prop_set_uint32(gicdev, "revision", 3);
  70     qdev_prop_set_uint32(gicdev, "num-cpu", 2);
  71     qdev_prop_set_uint32(gicdev, "num-irq", XLNX_VERSAL_NR_IRQS + 32);
  72     qdev_prop_set_uint32(gicdev, "len-redist-region-count", 1);
  73     qdev_prop_set_uint32(gicdev, "redist-region-count[0]", 2);
  74     qdev_prop_set_bit(gicdev, "has-security-extensions", true);
  75
  76     sysbus_realize(SYS_BUS_DEVICE(&s->fpd.apu.gic), &error_fatal);
  77
  78     for (i = 0; i < ARRAY_SIZE(addrs); i++) {
  79         MemoryRegion *mr;
  80
  81         mr = sysbus_mmio_get_region(gicbusdev, i);
  82         memory_region_add_subregion(&s->fpd.apu.mr, addrs[i], mr);
  83     }
  84
  85     for (i = 0; i < nr_apu_cpus; i++) {
  86         DeviceState *cpudev = DEVICE(&s->fpd.apu.cpu[i]);
  87         int ppibase = XLNX_VERSAL_NR_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
  88         qemu_irq maint_irq;
  89         int ti;
  90         /* Mapping from the output timer irq lines from the CPU to the
  91          * GIC PPI inputs.
  92          */
  93         const int timer_irq[] = {
  94             [GTIMER_PHYS] = VERSAL_TIMER_NS_EL1_IRQ,
  95             [GTIMER_VIRT] = VERSAL_TIMER_VIRT_IRQ,
  96             [GTIMER_HYP]  = VERSAL_TIMER_NS_EL2_IRQ,
  97             [GTIMER_SEC]  = VERSAL_TIMER_S_EL1_IRQ,
  98         };
  99
 100         for (ti = 0; ti < ARRAY_SIZE(timer_irq); ti++) {
 101             qdev_connect_gpio_out(cpudev, ti,
 102                                   qdev_get_gpio_in(gicdev,
 103                                                    ppibase + timer_irq[ti]));
 104         }
 105         maint_irq = qdev_get_gpio_in(gicdev,
 106                                         ppibase + VERSAL_GIC_MAINT_IRQ);
 107         qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
 108                                     0, maint_irq);
 109         sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
 110         sysbus_connect_irq(gicbusdev, i + nr_apu_cpus,
 111                            qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
 112         sysbus_connect_irq(gicbusdev, i + 2 * nr_apu_cpus,
 113                            qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
 114         sysbus_connect_irq(gicbusdev, i + 3 * nr_apu_cpus,
 115                            qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
 116     }
 117
 118     for (i = 0; i < XLNX_VERSAL_NR_IRQS; i++) {
 119         pic[i] = qdev_get_gpio_in(gicdev, i);
 120     }
 121 }
 122
 123 static void versal_create_uarts(Versal *s, qemu_irq *pic)
 124 {
 125     int i;
 126
 127     for (i = 0; i < ARRAY_SIZE(s->lpd.iou.uart); i++) {
 128         static const int irqs[] = { VERSAL_UART0_IRQ_0, VERSAL_UART1_IRQ_0};
 129         static const uint64_t addrs[] = { MM_UART0, MM_UART1 };
 130         char *name = g_strdup_printf("uart%d", i);
 131         DeviceState *dev;
 132         MemoryRegion *mr;
 133
 134         object_initialize_child(OBJECT(s), name, &s->lpd.iou.uart[i],
 135                                 TYPE_PL011);
 136         dev = DEVICE(&s->lpd.iou.uart[i]);
 137         qdev_prop_set_chr(dev, "chardev", serial_hd(i));
 138         sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
 139
 140         mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
 141         memory_region_add_subregion(&s->mr_ps, addrs[i], mr);
 142
 143         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irqs[i]]);
 144         g_free(name);
 145     }
 146 }
 147
 148 static void versal_create_gems(Versal *s, qemu_irq *pic)
 149 {
 150     int i;
 151
 152     for (i = 0; i < ARRAY_SIZE(s->lpd.iou.gem); i++) {
 153         static const int irqs[] = { VERSAL_GEM0_IRQ_0, VERSAL_GEM1_IRQ_0};
 154         static const uint64_t addrs[] = { MM_GEM0, MM_GEM1 };
 155         char *name = g_strdup_printf("gem%d", i);
 156         NICInfo *nd = &nd_table[i];
 157         DeviceState *dev;
 158         MemoryRegion *mr;
 159
 160         object_initialize_child(OBJECT(s), name, &s->lpd.iou.gem[i],
 161                                 TYPE_CADENCE_GEM);
 162         dev = DEVICE(&s->lpd.iou.gem[i]);
 163         if (nd->used) {
 164             qemu_check_nic_model(nd, "cadence_gem");
 165             qdev_set_nic_properties(dev, nd);
 166         }
 167         object_property_set_int(OBJECT(dev), "num-priority-queues", 2,
 168                                 &error_abort);
 169         object_property_set_link(OBJECT(dev), "dma", OBJECT(&s->mr_ps),
 170                                  &error_abort);
 171         sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
 172
 173         mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
 174         memory_region_add_subregion(&s->mr_ps, addrs[i], mr);
 175
 176         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irqs[i]]);
 177         g_free(name);
 178     }
 179 }
 180
 181 static void versal_create_admas(Versal *s, qemu_irq *pic)
 182 {
 183     int i;
 184
 185     for (i = 0; i < ARRAY_SIZE(s->lpd.iou.adma); i++) {
 186         char *name = g_strdup_printf("adma%d", i);
 187         DeviceState *dev;
 188         MemoryRegion *mr;
 189
 190         object_initialize_child(OBJECT(s), name, &s->lpd.iou.adma[i],
 191                                 TYPE_XLNX_ZDMA);
 192         dev = DEVICE(&s->lpd.iou.adma[i]);
 193         object_property_set_int(OBJECT(dev), "bus-width", 128, &error_abort);
 194         sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
 195
 196         mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
 197         memory_region_add_subregion(&s->mr_ps,
 198                                     MM_ADMA_CH0 + i * MM_ADMA_CH0_SIZE, mr);
 199
 200         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[VERSAL_ADMA_IRQ_0 + i]);
 201         g_free(name);
 202     }
 203 }
 204
 205 #define SDHCI_CAPABILITIES  0x280737ec6481 /* Same as on ZynqMP.  */
 206 static void versal_create_sds(Versal *s, qemu_irq *pic)
 207 {
 208     int i;
 209
 210     for (i = 0; i < ARRAY_SIZE(s->pmc.iou.sd); i++) {
 211         DeviceState *dev;
 212         MemoryRegion *mr;
 213
 214         object_initialize_child(OBJECT(s), "sd[*]", &s->pmc.iou.sd[i],
 215                                 TYPE_SYSBUS_SDHCI);
 216         dev = DEVICE(&s->pmc.iou.sd[i]);
 217
 218         object_property_set_uint(OBJECT(dev), "sd-spec-version", 3,
 219                                  &error_fatal);
 220         object_property_set_uint(OBJECT(dev), "capareg", SDHCI_CAPABILITIES,
 221                                  &error_fatal);
 222         object_property_set_uint(OBJECT(dev), "uhs", UHS_I, &error_fatal);
 223         sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
 224
 225         mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
 226         memory_region_add_subregion(&s->mr_ps,
 227                                     MM_PMC_SD0 + i * MM_PMC_SD0_SIZE, mr);
 228
 229         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
 230                            pic[VERSAL_SD0_IRQ_0 + i * 2]);
 231     }
 232 }
 233
 234 static void versal_create_rtc(Versal *s, qemu_irq *pic)
 235 {
 236     SysBusDevice *sbd;
 237     MemoryRegion *mr;
 238
 239     object_initialize_child(OBJECT(s), "rtc", &s->pmc.rtc,
 240                             TYPE_XLNX_ZYNQMP_RTC);
 241     sbd = SYS_BUS_DEVICE(&s->pmc.rtc);
 242     sysbus_realize(SYS_BUS_DEVICE(sbd), &error_fatal);
 243
 244     mr = sysbus_mmio_get_region(sbd, 0);
 245     memory_region_add_subregion(&s->mr_ps, MM_PMC_RTC, mr);
 246
 247     /*
 248      * TODO: Connect the ALARM and SECONDS interrupts once our RTC model
 249      * supports them.
 250      */
 251     sysbus_connect_irq(sbd, 1, pic[VERSAL_RTC_APB_ERR_IRQ]);
 252 }
 253
 254 /* This takes the board allocated linear DDR memory and creates aliases
 255  * for each split DDR range/aperture on the Versal address map.
 256  */
 257 static void versal_map_ddr(Versal *s)
 258 {
 259     uint64_t size = memory_region_size(s->cfg.mr_ddr);
 260     /* Describes the various split DDR access regions.  */
 261     static const struct {
 262         uint64_t base;
 263         uint64_t size;
 264     } addr_ranges[] = {
 265         { MM_TOP_DDR, MM_TOP_DDR_SIZE },
 266         { MM_TOP_DDR_2, MM_TOP_DDR_2_SIZE },
 267         { MM_TOP_DDR_3, MM_TOP_DDR_3_SIZE },
 268         { MM_TOP_DDR_4, MM_TOP_DDR_4_SIZE }
 269     };
 270     uint64_t offset = 0;
 271     int i;
 272
 273     assert(ARRAY_SIZE(addr_ranges) == ARRAY_SIZE(s->noc.mr_ddr_ranges));
 274     for (i = 0; i < ARRAY_SIZE(addr_ranges) && size; i++) {
 275         char *name;
 276         uint64_t mapsize;
 277
 278         mapsize = size < addr_ranges[i].size ? size : addr_ranges[i].size;
 279         name = g_strdup_printf("noc-ddr-range%d", i);
 280         /* Create the MR alias.  */
 281         memory_region_init_alias(&s->noc.mr_ddr_ranges[i], OBJECT(s),
 282                                  name, s->cfg.mr_ddr,
 283                                  offset, mapsize);
 284
 285         /* Map it onto the NoC MR.  */
 286         memory_region_add_subregion(&s->mr_ps, addr_ranges[i].base,
 287                                     &s->noc.mr_ddr_ranges[i]);
 288         offset += mapsize;
 289         size -= mapsize;
 290         g_free(name);
 291     }
 292 }
 293
 294 static void versal_unimp_area(Versal *s, const char *name,
 295                                 MemoryRegion *mr,
 296                                 hwaddr base, hwaddr size)
 297 {
 298     DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);
 299     MemoryRegion *mr_dev;
 300
 301     qdev_prop_set_string(dev, "name", name);
 302     qdev_prop_set_uint64(dev, "size", size);
 303     object_property_add_child(OBJECT(s), name, OBJECT(dev));
 304     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 305
 306     mr_dev = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
 307     memory_region_add_subregion(mr, base, mr_dev);
 308 }
 309
 310 static void versal_unimp(Versal *s)
 311 {
 312     versal_unimp_area(s, "psm", &s->mr_ps,
 313                         MM_PSM_START, MM_PSM_END - MM_PSM_START);
 314     versal_unimp_area(s, "crl", &s->mr_ps,
 315                         MM_CRL, MM_CRL_SIZE);
 316     versal_unimp_area(s, "crf", &s->mr_ps,
 317                         MM_FPD_CRF, MM_FPD_CRF_SIZE);
 318     versal_unimp_area(s, "crp", &s->mr_ps,
 319                         MM_PMC_CRP, MM_PMC_CRP_SIZE);
 320     versal_unimp_area(s, "iou-scntr", &s->mr_ps,
 321                         MM_IOU_SCNTR, MM_IOU_SCNTR_SIZE);
 322     versal_unimp_area(s, "iou-scntr-seucre", &s->mr_ps,
 323                         MM_IOU_SCNTRS, MM_IOU_SCNTRS_SIZE);
 324 }
 325
 326 static void versal_realize(DeviceState *dev, Error **errp)
 327 {
 328     Versal *s = XLNX_VERSAL(dev);
 329     qemu_irq pic[XLNX_VERSAL_NR_IRQS];
 330
 331     versal_create_apu_cpus(s);
 332     versal_create_apu_gic(s, pic);
 333     versal_create_uarts(s, pic);
 334     versal_create_gems(s, pic);
 335     versal_create_admas(s, pic);
 336     versal_create_sds(s, pic);
 337     versal_create_rtc(s, pic);
 338     versal_map_ddr(s);
 339     versal_unimp(s);
 340
 341     /* Create the On Chip Memory (OCM).  */
 342     memory_region_init_ram(&s->lpd.mr_ocm, OBJECT(s), "ocm",
 343                            MM_OCM_SIZE, &error_fatal);
 344
 345     memory_region_add_subregion_overlap(&s->mr_ps, MM_OCM, &s->lpd.mr_ocm, 0);
 346     memory_region_add_subregion_overlap(&s->fpd.apu.mr, 0, &s->mr_ps, 0);
 347 }
 348
 349 static void versal_init(Object *obj)
 350 {
 351     Versal *s = XLNX_VERSAL(obj);
 352
 353     memory_region_init(&s->fpd.apu.mr, obj, "mr-apu", UINT64_MAX);
 354     memory_region_init(&s->mr_ps, obj, "mr-ps-switch", UINT64_MAX);
 355 }
 356
 357 static Property versal_properties[] = {
 358     DEFINE_PROP_LINK("ddr", Versal, cfg.mr_ddr, TYPE_MEMORY_REGION,
 359                      MemoryRegion *),
 360     DEFINE_PROP_UINT32("psci-conduit", Versal, cfg.psci_conduit, 0),
 361     DEFINE_PROP_END_OF_LIST()
 362 };
 363
 364 static void versal_class_init(ObjectClass *klass, void *data)
 365 {
 366     DeviceClass *dc = DEVICE_CLASS(klass);
 367
 368     dc->realize = versal_realize;
 369     device_class_set_props(dc, versal_properties);
 370     /* No VMSD since we haven't got any top-level SoC state to save.  */
 371 }
 372
 373 static const TypeInfo versal_info = {
 374     .name = TYPE_XLNX_VERSAL,
 375     .parent = TYPE_SYS_BUS_DEVICE,
 376     .instance_size = sizeof(Versal),
 377     .instance_init = versal_init,
 378     .class_init = versal_class_init,
 379 };
 380
 381 static void versal_register_types(void)
 382 {
 383     type_register_static(&versal_info);
 384 }
 385
 386 type_init(versal_register_types);