hw/intc/xics.c

   1 /*
   2  * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
   3  *
   4  * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
   5  *
   6  * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  *
  26  */
  27
  28 #include "qemu/osdep.h"
  29 #include "qapi/error.h"
  30 #include "cpu.h"
  31 #include "trace.h"
  32 #include "qemu/timer.h"
  33 #include "hw/ppc/xics.h"
  34 #include "hw/qdev-properties.h"
  35 #include "qemu/error-report.h"
  36 #include "qemu/module.h"
  37 #include "qapi/visitor.h"
  38 #include "migration/vmstate.h"
  39 #include "monitor/monitor.h"
  40 #include "hw/intc/intc.h"
  41 #include "hw/irq.h"
  42 #include "sysemu/kvm.h"
  43 #include "sysemu/reset.h"
  44
  45 void icp_pic_print_info(ICPState *icp, Monitor *mon)
  46 {
  47     int cpu_index;
  48
  49     /* Skip partially initialized vCPUs. This can happen on sPAPR when vCPUs
  50      * are hot plugged or unplugged.
  51      */
  52     if (!icp) {
  53         return;
  54     }
  55
  56     cpu_index = icp->cs ? icp->cs->cpu_index : -1;
  57
  58     if (!icp->output) {
  59         return;
  60     }
  61
  62     if (kvm_irqchip_in_kernel()) {
  63         icp_synchronize_state(icp);
  64     }
  65
  66     monitor_printf(mon, "CPU %d XIRR=%08x (%p) PP=%02x MFRR=%02x\n",
  67                    cpu_index, icp->xirr, icp->xirr_owner,
  68                    icp->pending_priority, icp->mfrr);
  69 }
  70
  71 void ics_pic_print_info(ICSState *ics, Monitor *mon)
  72 {
  73     uint32_t i;
  74
  75     monitor_printf(mon, "ICS %4x..%4x %p\n",
  76                    ics->offset, ics->offset + ics->nr_irqs - 1, ics);
  77
  78     if (!ics->irqs) {
  79         return;
  80     }
  81
  82     if (kvm_irqchip_in_kernel()) {
  83         ics_synchronize_state(ics);
  84     }
  85
  86     for (i = 0; i < ics->nr_irqs; i++) {
  87         ICSIRQState *irq = ics->irqs + i;
  88
  89         if (!(irq->flags & XICS_FLAGS_IRQ_MASK)) {
  90             continue;
  91         }
  92         monitor_printf(mon, "  %4x %s %02x %02x\n",
  93                        ics->offset + i,
  94                        (irq->flags & XICS_FLAGS_IRQ_LSI) ?
  95                        "LSI" : "MSI",
  96                        irq->priority, irq->status);
  97     }
  98 }
  99
 100 /*
 101  * ICP: Presentation layer
 102  */
 103
 104 #define XISR_MASK  0x00ffffff
 105 #define CPPR_MASK  0xff000000
 106
 107 #define XISR(icp)   (((icp)->xirr) & XISR_MASK)
 108 #define CPPR(icp)   (((icp)->xirr) >> 24)
 109
 110 static void ics_reject(ICSState *ics, uint32_t nr);
 111 static void ics_eoi(ICSState *ics, uint32_t nr);
 112
 113 static void icp_check_ipi(ICPState *icp)
 114 {
 115     if (XISR(icp) && (icp->pending_priority <= icp->mfrr)) {
 116         return;
 117     }
 118
 119     trace_xics_icp_check_ipi(icp->cs->cpu_index, icp->mfrr);
 120
 121     if (XISR(icp) && icp->xirr_owner) {
 122         ics_reject(icp->xirr_owner, XISR(icp));
 123     }
 124
 125     icp->xirr = (icp->xirr & ~XISR_MASK) | XICS_IPI;
 126     icp->pending_priority = icp->mfrr;
 127     icp->xirr_owner = NULL;
 128     qemu_irq_raise(icp->output);
 129 }
 130
 131 void icp_resend(ICPState *icp)
 132 {
 133     XICSFabric *xi = icp->xics;
 134     XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
 135
 136     if (icp->mfrr < CPPR(icp)) {
 137         icp_check_ipi(icp);
 138     }
 139
 140     xic->ics_resend(xi);
 141 }
 142
 143 void icp_set_cppr(ICPState *icp, uint8_t cppr)
 144 {
 145     uint8_t old_cppr;
 146     uint32_t old_xisr;
 147
 148     old_cppr = CPPR(icp);
 149     icp->xirr = (icp->xirr & ~CPPR_MASK) | (cppr << 24);
 150
 151     if (cppr < old_cppr) {
 152         if (XISR(icp) && (cppr <= icp->pending_priority)) {
 153             old_xisr = XISR(icp);
 154             icp->xirr &= ~XISR_MASK; /* Clear XISR */
 155             icp->pending_priority = 0xff;
 156             qemu_irq_lower(icp->output);
 157             if (icp->xirr_owner) {
 158                 ics_reject(icp->xirr_owner, old_xisr);
 159                 icp->xirr_owner = NULL;
 160             }
 161         }
 162     } else {
 163         if (!XISR(icp)) {
 164             icp_resend(icp);
 165         }
 166     }
 167 }
 168
 169 void icp_set_mfrr(ICPState *icp, uint8_t mfrr)
 170 {
 171     icp->mfrr = mfrr;
 172     if (mfrr < CPPR(icp)) {
 173         icp_check_ipi(icp);
 174     }
 175 }
 176
 177 uint32_t icp_accept(ICPState *icp)
 178 {
 179     uint32_t xirr = icp->xirr;
 180
 181     qemu_irq_lower(icp->output);
 182     icp->xirr = icp->pending_priority << 24;
 183     icp->pending_priority = 0xff;
 184     icp->xirr_owner = NULL;
 185
 186     trace_xics_icp_accept(xirr, icp->xirr);
 187
 188     return xirr;
 189 }
 190
 191 uint32_t icp_ipoll(ICPState *icp, uint32_t *mfrr)
 192 {
 193     if (mfrr) {
 194         *mfrr = icp->mfrr;
 195     }
 196     return icp->xirr;
 197 }
 198
 199 void icp_eoi(ICPState *icp, uint32_t xirr)
 200 {
 201     XICSFabric *xi = icp->xics;
 202     XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
 203     ICSState *ics;
 204     uint32_t irq;
 205
 206     /* Send EOI -> ICS */
 207     icp->xirr = (icp->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK);
 208     trace_xics_icp_eoi(icp->cs->cpu_index, xirr, icp->xirr);
 209     irq = xirr & XISR_MASK;
 210
 211     ics = xic->ics_get(xi, irq);
 212     if (ics) {
 213         ics_eoi(ics, irq);
 214     }
 215     if (!XISR(icp)) {
 216         icp_resend(icp);
 217     }
 218 }
 219
 220 void icp_irq(ICSState *ics, int server, int nr, uint8_t priority)
 221 {
 222     ICPState *icp = xics_icp_get(ics->xics, server);
 223
 224     trace_xics_icp_irq(server, nr, priority);
 225
 226     if ((priority >= CPPR(icp))
 227         || (XISR(icp) && (icp->pending_priority <= priority))) {
 228         ics_reject(ics, nr);
 229     } else {
 230         if (XISR(icp) && icp->xirr_owner) {
 231             ics_reject(icp->xirr_owner, XISR(icp));
 232             icp->xirr_owner = NULL;
 233         }
 234         icp->xirr = (icp->xirr & ~XISR_MASK) | (nr & XISR_MASK);
 235         icp->xirr_owner = ics;
 236         icp->pending_priority = priority;
 237         trace_xics_icp_raise(icp->xirr, icp->pending_priority);
 238         qemu_irq_raise(icp->output);
 239     }
 240 }
 241
 242 static int icp_pre_save(void *opaque)
 243 {
 244     ICPState *icp = opaque;
 245
 246     if (kvm_irqchip_in_kernel()) {
 247         icp_get_kvm_state(icp);
 248     }
 249
 250     return 0;
 251 }
 252
 253 static int icp_post_load(void *opaque, int version_id)
 254 {
 255     ICPState *icp = opaque;
 256
 257     if (kvm_irqchip_in_kernel()) {
 258         Error *local_err = NULL;
 259         int ret;
 260
 261         ret = icp_set_kvm_state(icp, &local_err);
 262         if (ret < 0) {
 263             error_report_err(local_err);
 264             return ret;
 265         }
 266     }
 267
 268     return 0;
 269 }
 270
 271 static const VMStateDescription vmstate_icp_server = {
 272     .name = "icp/server",
 273     .version_id = 1,
 274     .minimum_version_id = 1,
 275     .pre_save = icp_pre_save,
 276     .post_load = icp_post_load,
 277     .fields = (VMStateField[]) {
 278         /* Sanity check */
 279         VMSTATE_UINT32(xirr, ICPState),
 280         VMSTATE_UINT8(pending_priority, ICPState),
 281         VMSTATE_UINT8(mfrr, ICPState),
 282         VMSTATE_END_OF_LIST()
 283     },
 284 };
 285
 286 void icp_reset(ICPState *icp)
 287 {
 288     icp->xirr = 0;
 289     icp->pending_priority = 0xff;
 290     icp->mfrr = 0xff;
 291
 292     if (kvm_irqchip_in_kernel()) {
 293         Error *local_err = NULL;
 294
 295         icp_set_kvm_state(icp, &local_err);
 296         if (local_err) {
 297             error_report_err(local_err);
 298         }
 299     }
 300 }
 301
 302 static void icp_realize(DeviceState *dev, Error **errp)
 303 {
 304     ICPState *icp = ICP(dev);
 305     CPUPPCState *env;
 306     Error *err = NULL;
 307
 308     assert(icp->xics);
 309     assert(icp->cs);
 310
 311     env = &POWERPC_CPU(icp->cs)->env;
 312     switch (PPC_INPUT(env)) {
 313     case PPC_FLAGS_INPUT_POWER7:
 314         icp->output = env->irq_inputs[POWER7_INPUT_INT];
 315         break;
 316     case PPC_FLAGS_INPUT_POWER9: /* For SPAPR xics emulation */
 317         icp->output = env->irq_inputs[POWER9_INPUT_INT];
 318         break;
 319
 320     case PPC_FLAGS_INPUT_970:
 321         icp->output = env->irq_inputs[PPC970_INPUT_INT];
 322         break;
 323
 324     default:
 325         error_setg(errp, "XICS interrupt controller does not support this CPU bus model");
 326         return;
 327     }
 328
 329     /* Connect the presenter to the VCPU (required for CPU hotplug) */
 330     if (kvm_irqchip_in_kernel()) {
 331         icp_kvm_realize(dev, &err);
 332         if (err) {
 333             error_propagate(errp, err);
 334             return;
 335         }
 336     }
 337
 338     vmstate_register(NULL, icp->cs->cpu_index, &vmstate_icp_server, icp);
 339 }
 340
 341 static void icp_unrealize(DeviceState *dev)
 342 {
 343     ICPState *icp = ICP(dev);
 344
 345     vmstate_unregister(NULL, &vmstate_icp_server, icp);
 346 }
 347
 348 static Property icp_properties[] = {
 349     DEFINE_PROP_LINK(ICP_PROP_XICS, ICPState, xics, TYPE_XICS_FABRIC,
 350                      XICSFabric *),
 351     DEFINE_PROP_LINK(ICP_PROP_CPU, ICPState, cs, TYPE_CPU, CPUState *),
 352     DEFINE_PROP_END_OF_LIST(),
 353 };
 354
 355 static void icp_class_init(ObjectClass *klass, void *data)
 356 {
 357     DeviceClass *dc = DEVICE_CLASS(klass);
 358
 359     dc->realize = icp_realize;
 360     dc->unrealize = icp_unrealize;
 361     device_class_set_props(dc, icp_properties);
 362     /*
 363      * Reason: part of XICS interrupt controller, needs to be wired up
 364      * by icp_create().
 365      */
 366     dc->user_creatable = false;
 367 }
 368
 369 static const TypeInfo icp_info = {
 370     .name = TYPE_ICP,
 371     .parent = TYPE_DEVICE,
 372     .instance_size = sizeof(ICPState),
 373     .class_init = icp_class_init,
 374     .class_size = sizeof(ICPStateClass),
 375 };
 376
 377 Object *icp_create(Object *cpu, const char *type, XICSFabric *xi, Error **errp)
 378 {
 379     Error *local_err = NULL;
 380     Object *obj;
 381
 382     obj = object_new(type);
 383     object_property_add_child(cpu, type, obj);
 384     object_unref(obj);
 385     object_property_set_link(obj, ICP_PROP_XICS, OBJECT(xi), &error_abort);
 386     object_property_set_link(obj, ICP_PROP_CPU, cpu, &error_abort);
 387     if (!qdev_realize(DEVICE(obj), NULL, &local_err)) {
 388         object_unparent(obj);
 389         error_propagate(errp, local_err);
 390         obj = NULL;
 391     }
 392
 393     return obj;
 394 }
 395
 396 void icp_destroy(ICPState *icp)
 397 {
 398     Object *obj = OBJECT(icp);
 399
 400     object_unparent(obj);
 401 }
 402
 403 /*
 404  * ICS: Source layer
 405  */
 406 static void ics_resend_msi(ICSState *ics, int srcno)
 407 {
 408     ICSIRQState *irq = ics->irqs + srcno;
 409
 410     /* FIXME: filter by server#? */
 411     if (irq->status & XICS_STATUS_REJECTED) {
 412         irq->status &= ~XICS_STATUS_REJECTED;
 413         if (irq->priority != 0xff) {
 414             icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 415         }
 416     }
 417 }
 418
 419 static void ics_resend_lsi(ICSState *ics, int srcno)
 420 {
 421     ICSIRQState *irq = ics->irqs + srcno;
 422
 423     if ((irq->priority != 0xff)
 424         && (irq->status & XICS_STATUS_ASSERTED)
 425         && !(irq->status & XICS_STATUS_SENT)) {
 426         irq->status |= XICS_STATUS_SENT;
 427         icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 428     }
 429 }
 430
 431 static void ics_set_irq_msi(ICSState *ics, int srcno, int val)
 432 {
 433     ICSIRQState *irq = ics->irqs + srcno;
 434
 435     trace_xics_ics_set_irq_msi(srcno, srcno + ics->offset);
 436
 437     if (val) {
 438         if (irq->priority == 0xff) {
 439             irq->status |= XICS_STATUS_MASKED_PENDING;
 440             trace_xics_masked_pending();
 441         } else  {
 442             icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 443         }
 444     }
 445 }
 446
 447 static void ics_set_irq_lsi(ICSState *ics, int srcno, int val)
 448 {
 449     ICSIRQState *irq = ics->irqs + srcno;
 450
 451     trace_xics_ics_set_irq_lsi(srcno, srcno + ics->offset);
 452     if (val) {
 453         irq->status |= XICS_STATUS_ASSERTED;
 454     } else {
 455         irq->status &= ~XICS_STATUS_ASSERTED;
 456     }
 457     ics_resend_lsi(ics, srcno);
 458 }
 459
 460 void ics_set_irq(void *opaque, int srcno, int val)
 461 {
 462     ICSState *ics = (ICSState *)opaque;
 463
 464     if (kvm_irqchip_in_kernel()) {
 465         ics_kvm_set_irq(ics, srcno, val);
 466         return;
 467     }
 468
 469     if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
 470         ics_set_irq_lsi(ics, srcno, val);
 471     } else {
 472         ics_set_irq_msi(ics, srcno, val);
 473     }
 474 }
 475
 476 static void ics_write_xive_msi(ICSState *ics, int srcno)
 477 {
 478     ICSIRQState *irq = ics->irqs + srcno;
 479
 480     if (!(irq->status & XICS_STATUS_MASKED_PENDING)
 481         || (irq->priority == 0xff)) {
 482         return;
 483     }
 484
 485     irq->status &= ~XICS_STATUS_MASKED_PENDING;
 486     icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 487 }
 488
 489 static void ics_write_xive_lsi(ICSState *ics, int srcno)
 490 {
 491     ics_resend_lsi(ics, srcno);
 492 }
 493
 494 void ics_write_xive(ICSState *ics, int srcno, int server,
 495                     uint8_t priority, uint8_t saved_priority)
 496 {
 497     ICSIRQState *irq = ics->irqs + srcno;
 498
 499     irq->server = server;
 500     irq->priority = priority;
 501     irq->saved_priority = saved_priority;
 502
 503     trace_xics_ics_write_xive(ics->offset + srcno, srcno, server, priority);
 504
 505     if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
 506         ics_write_xive_lsi(ics, srcno);
 507     } else {
 508         ics_write_xive_msi(ics, srcno);
 509     }
 510 }
 511
 512 static void ics_reject(ICSState *ics, uint32_t nr)
 513 {
 514     ICSStateClass *isc = ICS_GET_CLASS(ics);
 515     ICSIRQState *irq = ics->irqs + nr - ics->offset;
 516
 517     if (isc->reject) {
 518         isc->reject(ics, nr);
 519         return;
 520     }
 521
 522     trace_xics_ics_reject(nr, nr - ics->offset);
 523     if (irq->flags & XICS_FLAGS_IRQ_MSI) {
 524         irq->status |= XICS_STATUS_REJECTED;
 525     } else if (irq->flags & XICS_FLAGS_IRQ_LSI) {
 526         irq->status &= ~XICS_STATUS_SENT;
 527     }
 528 }
 529
 530 void ics_resend(ICSState *ics)
 531 {
 532     ICSStateClass *isc = ICS_GET_CLASS(ics);
 533     int i;
 534
 535     if (isc->resend) {
 536         isc->resend(ics);
 537         return;
 538     }
 539
 540     for (i = 0; i < ics->nr_irqs; i++) {
 541         /* FIXME: filter by server#? */
 542         if (ics->irqs[i].flags & XICS_FLAGS_IRQ_LSI) {
 543             ics_resend_lsi(ics, i);
 544         } else {
 545             ics_resend_msi(ics, i);
 546         }
 547     }
 548 }
 549
 550 static void ics_eoi(ICSState *ics, uint32_t nr)
 551 {
 552     int srcno = nr - ics->offset;
 553     ICSIRQState *irq = ics->irqs + srcno;
 554
 555     trace_xics_ics_eoi(nr);
 556
 557     if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
 558         irq->status &= ~XICS_STATUS_SENT;
 559     }
 560 }
 561
 562 static void ics_reset_irq(ICSIRQState *irq)
 563 {
 564     irq->priority = 0xff;
 565     irq->saved_priority = 0xff;
 566 }
 567
 568 static void ics_reset(DeviceState *dev)
 569 {
 570     ICSState *ics = ICS(dev);
 571     int i;
 572     uint8_t flags[ics->nr_irqs];
 573
 574     for (i = 0; i < ics->nr_irqs; i++) {
 575         flags[i] = ics->irqs[i].flags;
 576     }
 577
 578     memset(ics->irqs, 0, sizeof(ICSIRQState) * ics->nr_irqs);
 579
 580     for (i = 0; i < ics->nr_irqs; i++) {
 581         ics_reset_irq(ics->irqs + i);
 582         ics->irqs[i].flags = flags[i];
 583     }
 584
 585     if (kvm_irqchip_in_kernel()) {
 586         Error *local_err = NULL;
 587
 588         ics_set_kvm_state(ICS(dev), &local_err);
 589         if (local_err) {
 590             error_report_err(local_err);
 591         }
 592     }
 593 }
 594
 595 static void ics_reset_handler(void *dev)
 596 {
 597     ics_reset(dev);
 598 }
 599
 600 static void ics_realize(DeviceState *dev, Error **errp)
 601 {
 602     ICSState *ics = ICS(dev);
 603
 604     assert(ics->xics);
 605
 606     if (!ics->nr_irqs) {
 607         error_setg(errp, "Number of interrupts needs to be greater 0");
 608         return;
 609     }
 610     ics->irqs = g_malloc0(ics->nr_irqs * sizeof(ICSIRQState));
 611
 612     qemu_register_reset(ics_reset_handler, ics);
 613 }
 614
 615 static void ics_instance_init(Object *obj)
 616 {
 617     ICSState *ics = ICS(obj);
 618
 619     ics->offset = XICS_IRQ_BASE;
 620 }
 621
 622 static int ics_pre_save(void *opaque)
 623 {
 624     ICSState *ics = opaque;
 625
 626     if (kvm_irqchip_in_kernel()) {
 627         ics_get_kvm_state(ics);
 628     }
 629
 630     return 0;
 631 }
 632
 633 static int ics_post_load(void *opaque, int version_id)
 634 {
 635     ICSState *ics = opaque;
 636
 637     if (kvm_irqchip_in_kernel()) {
 638         Error *local_err = NULL;
 639         int ret;
 640
 641         ret = ics_set_kvm_state(ics, &local_err);
 642         if (ret < 0) {
 643             error_report_err(local_err);
 644             return ret;
 645         }
 646     }
 647
 648     return 0;
 649 }
 650
 651 static const VMStateDescription vmstate_ics_irq = {
 652     .name = "ics/irq",
 653     .version_id = 2,
 654     .minimum_version_id = 1,
 655     .fields = (VMStateField[]) {
 656         VMSTATE_UINT32(server, ICSIRQState),
 657         VMSTATE_UINT8(priority, ICSIRQState),
 658         VMSTATE_UINT8(saved_priority, ICSIRQState),
 659         VMSTATE_UINT8(status, ICSIRQState),
 660         VMSTATE_UINT8(flags, ICSIRQState),
 661         VMSTATE_END_OF_LIST()
 662     },
 663 };
 664
 665 static const VMStateDescription vmstate_ics = {
 666     .name = "ics",
 667     .version_id = 1,
 668     .minimum_version_id = 1,
 669     .pre_save = ics_pre_save,
 670     .post_load = ics_post_load,
 671     .fields = (VMStateField[]) {
 672         /* Sanity check */
 673         VMSTATE_UINT32_EQUAL(nr_irqs, ICSState, NULL),
 674
 675         VMSTATE_STRUCT_VARRAY_POINTER_UINT32(irqs, ICSState, nr_irqs,
 676                                              vmstate_ics_irq,
 677                                              ICSIRQState),
 678         VMSTATE_END_OF_LIST()
 679     },
 680 };
 681
 682 static Property ics_properties[] = {
 683     DEFINE_PROP_UINT32("nr-irqs", ICSState, nr_irqs, 0),
 684     DEFINE_PROP_LINK(ICS_PROP_XICS, ICSState, xics, TYPE_XICS_FABRIC,
 685                      XICSFabric *),
 686     DEFINE_PROP_END_OF_LIST(),
 687 };
 688
 689 static void ics_class_init(ObjectClass *klass, void *data)
 690 {
 691     DeviceClass *dc = DEVICE_CLASS(klass);
 692
 693     dc->realize = ics_realize;
 694     device_class_set_props(dc, ics_properties);
 695     dc->reset = ics_reset;
 696     dc->vmsd = &vmstate_ics;
 697     /*
 698      * Reason: part of XICS interrupt controller, needs to be wired up,
 699      * e.g. by spapr_irq_init().
 700      */
 701     dc->user_creatable = false;
 702 }
 703
 704 static const TypeInfo ics_info = {
 705     .name = TYPE_ICS,
 706     .parent = TYPE_DEVICE,
 707     .instance_size = sizeof(ICSState),
 708     .instance_init = ics_instance_init,
 709     .class_init = ics_class_init,
 710     .class_size = sizeof(ICSStateClass),
 711 };
 712
 713 static const TypeInfo xics_fabric_info = {
 714     .name = TYPE_XICS_FABRIC,
 715     .parent = TYPE_INTERFACE,
 716     .class_size = sizeof(XICSFabricClass),
 717 };
 718
 719 /*
 720  * Exported functions
 721  */
 722 ICPState *xics_icp_get(XICSFabric *xi, int server)
 723 {
 724     XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
 725
 726     return xic->icp_get(xi, server);
 727 }
 728
 729 void ics_set_irq_type(ICSState *ics, int srcno, bool lsi)
 730 {
 731     assert(!(ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MASK));
 732
 733     ics->irqs[srcno].flags |=
 734         lsi ? XICS_FLAGS_IRQ_LSI : XICS_FLAGS_IRQ_MSI;
 735
 736     if (kvm_irqchip_in_kernel()) {
 737         Error *local_err = NULL;
 738
 739         ics_reset_irq(ics->irqs + srcno);
 740         ics_set_kvm_state_one(ics, srcno, &local_err);
 741         if (local_err) {
 742             error_report_err(local_err);
 743         }
 744     }
 745 }
 746
 747 static void xics_register_types(void)
 748 {
 749     type_register_static(&ics_info);
 750     type_register_static(&icp_info);
 751     type_register_static(&xics_fabric_info);
 752 }
 753
 754 type_init(xics_register_types)