4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
21 #include "qemu/osdep.h"
22 #include "qemu/qemu-print.h"
23 #include "qemu/timer.h"
25 #include "exec/page-vary.h"
26 #include "target/arm/idau.h"
27 #include "qemu/module.h"
28 #include "qapi/error.h"
31 #include "hw/core/tcg-cpu-ops.h"
32 #endif /* CONFIG_TCG */
33 #include "internals.h"
34 #include "cpu-features.h"
35 #include "exec/exec-all.h"
36 #include "hw/qdev-properties.h"
37 #if !defined(CONFIG_USER_ONLY)
38 #include "hw/loader.h"
39 #include "hw/boards.h"
41 #include "hw/intc/armv7m_nvic.h"
42 #endif /* CONFIG_TCG */
43 #endif /* !CONFIG_USER_ONLY */
44 #include "sysemu/tcg.h"
45 #include "sysemu/qtest.h"
46 #include "sysemu/hw_accel.h"
48 #include "disas/capstone.h"
49 #include "fpu/softfloat.h"
51 #include "target/arm/cpu-qom.h"
52 #include "target/arm/gtimer.h"
54 static void arm_cpu_set_pc(CPUState
*cs
, vaddr value
)
56 ARMCPU
*cpu
= ARM_CPU(cs
);
57 CPUARMState
*env
= &cpu
->env
;
63 env
->regs
[15] = value
& ~1;
64 env
->thumb
= value
& 1;
68 static vaddr
arm_cpu_get_pc(CPUState
*cs
)
70 ARMCPU
*cpu
= ARM_CPU(cs
);
71 CPUARMState
*env
= &cpu
->env
;
81 void arm_cpu_synchronize_from_tb(CPUState
*cs
,
82 const TranslationBlock
*tb
)
84 /* The program counter is always up to date with CF_PCREL. */
85 if (!(tb_cflags(tb
) & CF_PCREL
)) {
86 CPUARMState
*env
= cpu_env(cs
);
88 * It's OK to look at env for the current mode here, because it's
89 * never possible for an AArch64 TB to chain to an AArch32 TB.
94 env
->regs
[15] = tb
->pc
;
99 void arm_restore_state_to_opc(CPUState
*cs
,
100 const TranslationBlock
*tb
,
101 const uint64_t *data
)
103 CPUARMState
*env
= cpu_env(cs
);
106 if (tb_cflags(tb
) & CF_PCREL
) {
107 env
->pc
= (env
->pc
& TARGET_PAGE_MASK
) | data
[0];
111 env
->condexec_bits
= 0;
112 env
->exception
.syndrome
= data
[2] << ARM_INSN_START_WORD2_SHIFT
;
114 if (tb_cflags(tb
) & CF_PCREL
) {
115 env
->regs
[15] = (env
->regs
[15] & TARGET_PAGE_MASK
) | data
[0];
117 env
->regs
[15] = data
[0];
119 env
->condexec_bits
= data
[1];
120 env
->exception
.syndrome
= data
[2] << ARM_INSN_START_WORD2_SHIFT
;
123 #endif /* CONFIG_TCG */
125 static bool arm_cpu_has_work(CPUState
*cs
)
127 ARMCPU
*cpu
= ARM_CPU(cs
);
129 return (cpu
->power_state
!= PSCI_OFF
)
130 && cs
->interrupt_request
&
131 (CPU_INTERRUPT_FIQ
| CPU_INTERRUPT_HARD
132 | CPU_INTERRUPT_VFIQ
| CPU_INTERRUPT_VIRQ
| CPU_INTERRUPT_VSERR
133 | CPU_INTERRUPT_EXITTB
);
136 void arm_register_pre_el_change_hook(ARMCPU
*cpu
, ARMELChangeHookFn
*hook
,
139 ARMELChangeHook
*entry
= g_new0(ARMELChangeHook
, 1);
142 entry
->opaque
= opaque
;
144 QLIST_INSERT_HEAD(&cpu
->pre_el_change_hooks
, entry
, node
);
147 void arm_register_el_change_hook(ARMCPU
*cpu
, ARMELChangeHookFn
*hook
,
150 ARMELChangeHook
*entry
= g_new0(ARMELChangeHook
, 1);
153 entry
->opaque
= opaque
;
155 QLIST_INSERT_HEAD(&cpu
->el_change_hooks
, entry
, node
);
158 static void cp_reg_reset(gpointer key
, gpointer value
, gpointer opaque
)
160 /* Reset a single ARMCPRegInfo register */
161 ARMCPRegInfo
*ri
= value
;
162 ARMCPU
*cpu
= opaque
;
164 if (ri
->type
& (ARM_CP_SPECIAL_MASK
| ARM_CP_ALIAS
)) {
169 ri
->resetfn(&cpu
->env
, ri
);
173 /* A zero offset is never possible as it would be regs[0]
174 * so we use it to indicate that reset is being handled elsewhere.
175 * This is basically only used for fields in non-core coprocessors
176 * (like the pxa2xx ones).
178 if (!ri
->fieldoffset
) {
182 if (cpreg_field_is_64bit(ri
)) {
183 CPREG_FIELD64(&cpu
->env
, ri
) = ri
->resetvalue
;
185 CPREG_FIELD32(&cpu
->env
, ri
) = ri
->resetvalue
;
189 static void cp_reg_check_reset(gpointer key
, gpointer value
, gpointer opaque
)
191 /* Purely an assertion check: we've already done reset once,
192 * so now check that running the reset for the cpreg doesn't
193 * change its value. This traps bugs where two different cpregs
194 * both try to reset the same state field but to different values.
196 ARMCPRegInfo
*ri
= value
;
197 ARMCPU
*cpu
= opaque
;
198 uint64_t oldvalue
, newvalue
;
200 if (ri
->type
& (ARM_CP_SPECIAL_MASK
| ARM_CP_ALIAS
| ARM_CP_NO_RAW
)) {
204 oldvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
205 cp_reg_reset(key
, value
, opaque
);
206 newvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
207 assert(oldvalue
== newvalue
);
210 static void arm_cpu_reset_hold(Object
*obj
)
212 CPUState
*s
= CPU(obj
);
213 ARMCPU
*cpu
= ARM_CPU(s
);
214 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(cpu
);
215 CPUARMState
*env
= &cpu
->env
;
217 if (acc
->parent_phases
.hold
) {
218 acc
->parent_phases
.hold(obj
);
221 memset(env
, 0, offsetof(CPUARMState
, end_reset_fields
));
223 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_reset
, cpu
);
224 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_check_reset
, cpu
);
226 env
->vfp
.xregs
[ARM_VFP_FPSID
] = cpu
->reset_fpsid
;
227 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = cpu
->isar
.mvfr0
;
228 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = cpu
->isar
.mvfr1
;
229 env
->vfp
.xregs
[ARM_VFP_MVFR2
] = cpu
->isar
.mvfr2
;
231 cpu
->power_state
= s
->start_powered_off
? PSCI_OFF
: PSCI_ON
;
233 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
234 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
237 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
238 /* 64 bit CPUs always start in 64 bit mode */
240 #if defined(CONFIG_USER_ONLY)
241 env
->pstate
= PSTATE_MODE_EL0t
;
242 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
243 env
->cp15
.sctlr_el
[1] |= SCTLR_UCT
| SCTLR_UCI
| SCTLR_DZE
;
244 /* Enable all PAC keys. */
245 env
->cp15
.sctlr_el
[1] |= (SCTLR_EnIA
| SCTLR_EnIB
|
246 SCTLR_EnDA
| SCTLR_EnDB
);
247 /* Trap on btype=3 for PACIxSP. */
248 env
->cp15
.sctlr_el
[1] |= SCTLR_BT0
;
249 /* Trap on implementation defined registers. */
250 if (cpu_isar_feature(aa64_tidcp1
, cpu
)) {
251 env
->cp15
.sctlr_el
[1] |= SCTLR_TIDCP
;
253 /* and to the FP/Neon instructions */
254 env
->cp15
.cpacr_el1
= FIELD_DP64(env
->cp15
.cpacr_el1
,
256 /* and to the SVE instructions, with default vector length */
257 if (cpu_isar_feature(aa64_sve
, cpu
)) {
258 env
->cp15
.cpacr_el1
= FIELD_DP64(env
->cp15
.cpacr_el1
,
260 env
->vfp
.zcr_el
[1] = cpu
->sve_default_vq
- 1;
262 /* and for SME instructions, with default vector length, and TPIDR2 */
263 if (cpu_isar_feature(aa64_sme
, cpu
)) {
264 env
->cp15
.sctlr_el
[1] |= SCTLR_EnTP2
;
265 env
->cp15
.cpacr_el1
= FIELD_DP64(env
->cp15
.cpacr_el1
,
267 env
->vfp
.smcr_el
[1] = cpu
->sme_default_vq
- 1;
268 if (cpu_isar_feature(aa64_sme_fa64
, cpu
)) {
269 env
->vfp
.smcr_el
[1] = FIELD_DP64(env
->vfp
.smcr_el
[1],
274 * Enable 48-bit address space (TODO: take reserved_va into account).
275 * Enable TBI0 but not TBI1.
276 * Note that this must match useronly_clean_ptr.
278 env
->cp15
.tcr_el
[1] = 5 | (1ULL << 37);
281 if (cpu_isar_feature(aa64_mte
, cpu
)) {
282 /* Enable tag access, but leave TCF0 as No Effect (0). */
283 env
->cp15
.sctlr_el
[1] |= SCTLR_ATA0
;
285 * Exclude all tags, so that tag 0 is always used.
286 * This corresponds to Linux current->thread.gcr_incl = 0.
288 * Set RRND, so that helper_irg() will generate a seed later.
289 * Here in cpu_reset(), the crypto subsystem has not yet been
292 env
->cp15
.gcr_el1
= 0x1ffff;
295 * Disable access to SCXTNUM_EL0 from CSV2_1p2.
296 * This is not yet exposed from the Linux kernel in any way.
298 env
->cp15
.sctlr_el
[1] |= SCTLR_TSCXT
;
299 /* Disable access to Debug Communication Channel (DCC). */
300 env
->cp15
.mdscr_el1
|= 1 << 12;
301 /* Enable FEAT_MOPS */
302 env
->cp15
.sctlr_el
[1] |= SCTLR_MSCEN
;
304 /* Reset into the highest available EL */
305 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
306 env
->pstate
= PSTATE_MODE_EL3h
;
307 } else if (arm_feature(env
, ARM_FEATURE_EL2
)) {
308 env
->pstate
= PSTATE_MODE_EL2h
;
310 env
->pstate
= PSTATE_MODE_EL1h
;
313 /* Sample rvbar at reset. */
314 env
->cp15
.rvbar
= cpu
->rvbar_prop
;
315 env
->pc
= env
->cp15
.rvbar
;
318 #if defined(CONFIG_USER_ONLY)
319 /* Userspace expects access to cp10 and cp11 for FP/Neon */
320 env
->cp15
.cpacr_el1
= FIELD_DP64(env
->cp15
.cpacr_el1
,
322 env
->cp15
.cpacr_el1
= FIELD_DP64(env
->cp15
.cpacr_el1
,
325 if (arm_feature(env
, ARM_FEATURE_V8
)) {
326 env
->cp15
.rvbar
= cpu
->rvbar_prop
;
327 env
->regs
[15] = cpu
->rvbar_prop
;
331 #if defined(CONFIG_USER_ONLY)
332 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
333 /* For user mode we must enable access to coprocessors */
334 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
335 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
336 env
->cp15
.c15_cpar
= 3;
337 } else if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
338 env
->cp15
.c15_cpar
= 1;
343 * If the highest available EL is EL2, AArch32 will start in Hyp
344 * mode; otherwise it starts in SVC. Note that if we start in
345 * AArch64 then these values in the uncached_cpsr will be ignored.
347 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
348 !arm_feature(env
, ARM_FEATURE_EL3
)) {
349 env
->uncached_cpsr
= ARM_CPU_MODE_HYP
;
351 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
;
353 env
->daif
= PSTATE_D
| PSTATE_A
| PSTATE_I
| PSTATE_F
;
355 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently
356 * executing as AArch32 then check if highvecs are enabled and
357 * adjust the PC accordingly.
359 if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
360 env
->regs
[15] = 0xFFFF0000;
363 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
366 if (arm_feature(env
, ARM_FEATURE_M
)) {
367 #ifndef CONFIG_USER_ONLY
368 uint32_t initial_msp
; /* Loaded from 0x0 */
369 uint32_t initial_pc
; /* Loaded from 0x4 */
374 if (cpu_isar_feature(aa32_lob
, cpu
)) {
376 * LTPSIZE is constant 4 if MVE not implemented, and resets
377 * to an UNKNOWN value if MVE is implemented. We choose to
380 env
->v7m
.ltpsize
= 4;
381 /* The LTPSIZE field in FPDSCR is constant and reads as 4. */
382 env
->v7m
.fpdscr
[M_REG_NS
] = 4 << FPCR_LTPSIZE_SHIFT
;
383 env
->v7m
.fpdscr
[M_REG_S
] = 4 << FPCR_LTPSIZE_SHIFT
;
386 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
387 env
->v7m
.secure
= true;
389 /* This bit resets to 0 if security is supported, but 1 if
390 * it is not. The bit is not present in v7M, but we set it
391 * here so we can avoid having to make checks on it conditional
392 * on ARM_FEATURE_V8 (we don't let the guest see the bit).
394 env
->v7m
.aircr
= R_V7M_AIRCR_BFHFNMINS_MASK
;
396 * Set NSACR to indicate "NS access permitted to everything";
397 * this avoids having to have all the tests of it being
398 * conditional on ARM_FEATURE_M_SECURITY. Note also that from
399 * v8.1M the guest-visible value of NSACR in a CPU without the
400 * Security Extension is 0xcff.
402 env
->v7m
.nsacr
= 0xcff;
405 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends
406 * that it resets to 1, so QEMU always does that rather than making
407 * it dependent on CPU model. In v8M it is RES1.
409 env
->v7m
.ccr
[M_REG_NS
] = R_V7M_CCR_STKALIGN_MASK
;
410 env
->v7m
.ccr
[M_REG_S
] = R_V7M_CCR_STKALIGN_MASK
;
411 if (arm_feature(env
, ARM_FEATURE_V8
)) {
412 /* in v8M the NONBASETHRDENA bit [0] is RES1 */
413 env
->v7m
.ccr
[M_REG_NS
] |= R_V7M_CCR_NONBASETHRDENA_MASK
;
414 env
->v7m
.ccr
[M_REG_S
] |= R_V7M_CCR_NONBASETHRDENA_MASK
;
416 if (!arm_feature(env
, ARM_FEATURE_M_MAIN
)) {
417 env
->v7m
.ccr
[M_REG_NS
] |= R_V7M_CCR_UNALIGN_TRP_MASK
;
418 env
->v7m
.ccr
[M_REG_S
] |= R_V7M_CCR_UNALIGN_TRP_MASK
;
421 if (cpu_isar_feature(aa32_vfp_simd
, cpu
)) {
422 env
->v7m
.fpccr
[M_REG_NS
] = R_V7M_FPCCR_ASPEN_MASK
;
423 env
->v7m
.fpccr
[M_REG_S
] = R_V7M_FPCCR_ASPEN_MASK
|
424 R_V7M_FPCCR_LSPEN_MASK
| R_V7M_FPCCR_S_MASK
;
427 #ifndef CONFIG_USER_ONLY
428 /* Unlike A/R profile, M profile defines the reset LR value */
429 env
->regs
[14] = 0xffffffff;
431 env
->v7m
.vecbase
[M_REG_S
] = cpu
->init_svtor
& 0xffffff80;
432 env
->v7m
.vecbase
[M_REG_NS
] = cpu
->init_nsvtor
& 0xffffff80;
434 /* Load the initial SP and PC from offset 0 and 4 in the vector table */
435 vecbase
= env
->v7m
.vecbase
[env
->v7m
.secure
];
436 rom
= rom_ptr_for_as(s
->as
, vecbase
, 8);
438 /* Address zero is covered by ROM which hasn't yet been
439 * copied into physical memory.
441 initial_msp
= ldl_p(rom
);
442 initial_pc
= ldl_p(rom
+ 4);
444 /* Address zero not covered by a ROM blob, or the ROM blob
445 * is in non-modifiable memory and this is a second reset after
446 * it got copied into memory. In the latter case, rom_ptr
447 * will return a NULL pointer and we should use ldl_phys instead.
449 initial_msp
= ldl_phys(s
->as
, vecbase
);
450 initial_pc
= ldl_phys(s
->as
, vecbase
+ 4);
453 qemu_log_mask(CPU_LOG_INT
,
454 "Loaded reset SP 0x%x PC 0x%x from vector table\n",
455 initial_msp
, initial_pc
);
457 env
->regs
[13] = initial_msp
& 0xFFFFFFFC;
458 env
->regs
[15] = initial_pc
& ~1;
459 env
->thumb
= initial_pc
& 1;
462 * For user mode we run non-secure and with access to the FPU.
463 * The FPU context is active (ie does not need further setup)
464 * and is owned by non-secure.
466 env
->v7m
.secure
= false;
467 env
->v7m
.nsacr
= 0xcff;
468 env
->v7m
.cpacr
[M_REG_NS
] = 0xf0ffff;
469 env
->v7m
.fpccr
[M_REG_S
] &=
470 ~(R_V7M_FPCCR_LSPEN_MASK
| R_V7M_FPCCR_S_MASK
);
471 env
->v7m
.control
[M_REG_S
] |= R_V7M_CONTROL_FPCA_MASK
;
475 /* M profile requires that reset clears the exclusive monitor;
476 * A profile does not, but clearing it makes more sense than having it
477 * set with an exclusive access on address zero.
479 arm_clear_exclusive(env
);
481 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
482 if (cpu
->pmsav7_dregion
> 0) {
483 if (arm_feature(env
, ARM_FEATURE_V8
)) {
484 memset(env
->pmsav8
.rbar
[M_REG_NS
], 0,
485 sizeof(*env
->pmsav8
.rbar
[M_REG_NS
])
486 * cpu
->pmsav7_dregion
);
487 memset(env
->pmsav8
.rlar
[M_REG_NS
], 0,
488 sizeof(*env
->pmsav8
.rlar
[M_REG_NS
])
489 * cpu
->pmsav7_dregion
);
490 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
491 memset(env
->pmsav8
.rbar
[M_REG_S
], 0,
492 sizeof(*env
->pmsav8
.rbar
[M_REG_S
])
493 * cpu
->pmsav7_dregion
);
494 memset(env
->pmsav8
.rlar
[M_REG_S
], 0,
495 sizeof(*env
->pmsav8
.rlar
[M_REG_S
])
496 * cpu
->pmsav7_dregion
);
498 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
499 memset(env
->pmsav7
.drbar
, 0,
500 sizeof(*env
->pmsav7
.drbar
) * cpu
->pmsav7_dregion
);
501 memset(env
->pmsav7
.drsr
, 0,
502 sizeof(*env
->pmsav7
.drsr
) * cpu
->pmsav7_dregion
);
503 memset(env
->pmsav7
.dracr
, 0,
504 sizeof(*env
->pmsav7
.dracr
) * cpu
->pmsav7_dregion
);
508 if (cpu
->pmsav8r_hdregion
> 0) {
509 memset(env
->pmsav8
.hprbar
, 0,
510 sizeof(*env
->pmsav8
.hprbar
) * cpu
->pmsav8r_hdregion
);
511 memset(env
->pmsav8
.hprlar
, 0,
512 sizeof(*env
->pmsav8
.hprlar
) * cpu
->pmsav8r_hdregion
);
515 env
->pmsav7
.rnr
[M_REG_NS
] = 0;
516 env
->pmsav7
.rnr
[M_REG_S
] = 0;
517 env
->pmsav8
.mair0
[M_REG_NS
] = 0;
518 env
->pmsav8
.mair0
[M_REG_S
] = 0;
519 env
->pmsav8
.mair1
[M_REG_NS
] = 0;
520 env
->pmsav8
.mair1
[M_REG_S
] = 0;
523 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
524 if (cpu
->sau_sregion
> 0) {
525 memset(env
->sau
.rbar
, 0, sizeof(*env
->sau
.rbar
) * cpu
->sau_sregion
);
526 memset(env
->sau
.rlar
, 0, sizeof(*env
->sau
.rlar
) * cpu
->sau_sregion
);
529 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what
530 * the Cortex-M33 does.
535 set_flush_to_zero(1, &env
->vfp
.standard_fp_status
);
536 set_flush_inputs_to_zero(1, &env
->vfp
.standard_fp_status
);
537 set_default_nan_mode(1, &env
->vfp
.standard_fp_status
);
538 set_default_nan_mode(1, &env
->vfp
.standard_fp_status_f16
);
539 set_float_detect_tininess(float_tininess_before_rounding
,
540 &env
->vfp
.fp_status
);
541 set_float_detect_tininess(float_tininess_before_rounding
,
542 &env
->vfp
.standard_fp_status
);
543 set_float_detect_tininess(float_tininess_before_rounding
,
544 &env
->vfp
.fp_status_f16
);
545 set_float_detect_tininess(float_tininess_before_rounding
,
546 &env
->vfp
.standard_fp_status_f16
);
547 #ifndef CONFIG_USER_ONLY
549 kvm_arm_reset_vcpu(cpu
);
554 hw_breakpoint_update_all(cpu
);
555 hw_watchpoint_update_all(cpu
);
557 arm_rebuild_hflags(env
);
561 void arm_emulate_firmware_reset(CPUState
*cpustate
, int target_el
)
563 ARMCPU
*cpu
= ARM_CPU(cpustate
);
564 CPUARMState
*env
= &cpu
->env
;
565 bool have_el3
= arm_feature(env
, ARM_FEATURE_EL3
);
566 bool have_el2
= arm_feature(env
, ARM_FEATURE_EL2
);
569 * Check we have the EL we're aiming for. If that is the
570 * highest implemented EL, then cpu_reset has already done
584 if (!have_el3
&& !have_el2
) {
589 g_assert_not_reached();
594 * Set the EL3 state so code can run at EL2. This should match
595 * the requirements set by Linux in its booting spec.
598 env
->cp15
.scr_el3
|= SCR_RW
;
599 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
600 env
->cp15
.scr_el3
|= SCR_API
| SCR_APK
;
602 if (cpu_isar_feature(aa64_mte
, cpu
)) {
603 env
->cp15
.scr_el3
|= SCR_ATA
;
605 if (cpu_isar_feature(aa64_sve
, cpu
)) {
606 env
->cp15
.cptr_el
[3] |= R_CPTR_EL3_EZ_MASK
;
607 env
->vfp
.zcr_el
[3] = 0xf;
609 if (cpu_isar_feature(aa64_sme
, cpu
)) {
610 env
->cp15
.cptr_el
[3] |= R_CPTR_EL3_ESM_MASK
;
611 env
->cp15
.scr_el3
|= SCR_ENTP2
;
612 env
->vfp
.smcr_el
[3] = 0xf;
614 if (cpu_isar_feature(aa64_hcx
, cpu
)) {
615 env
->cp15
.scr_el3
|= SCR_HXEN
;
617 if (cpu_isar_feature(aa64_fgt
, cpu
)) {
618 env
->cp15
.scr_el3
|= SCR_FGTEN
;
622 if (target_el
== 2) {
623 /* If the guest is at EL2 then Linux expects the HVC insn to work */
624 env
->cp15
.scr_el3
|= SCR_HCE
;
627 /* Put CPU into non-secure state */
628 env
->cp15
.scr_el3
|= SCR_NS
;
629 /* Set NSACR.{CP11,CP10} so NS can access the FPU */
630 env
->cp15
.nsacr
|= 3 << 10;
633 if (have_el2
&& target_el
< 2) {
634 /* Set EL2 state so code can run at EL1. */
636 env
->cp15
.hcr_el2
|= HCR_RW
;
640 /* Set the CPU to the desired state */
642 env
->pstate
= aarch64_pstate_mode(target_el
, true);
644 static const uint32_t mode_for_el
[] = {
651 cpsr_write(env
, mode_for_el
[target_el
], CPSR_M
, CPSRWriteRaw
);
656 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
658 static inline bool arm_excp_unmasked(CPUState
*cs
, unsigned int excp_idx
,
659 unsigned int target_el
,
660 unsigned int cur_el
, bool secure
,
663 CPUARMState
*env
= cpu_env(cs
);
664 bool pstate_unmasked
;
665 bool unmasked
= false;
668 * Don't take exceptions if they target a lower EL.
669 * This check should catch any exceptions that would not be taken
672 if (cur_el
> target_el
) {
678 pstate_unmasked
= !(env
->daif
& PSTATE_F
);
682 pstate_unmasked
= !(env
->daif
& PSTATE_I
);
686 if (!(hcr_el2
& HCR_FMO
) || (hcr_el2
& HCR_TGE
)) {
687 /* VFIQs are only taken when hypervized. */
690 return !(env
->daif
& PSTATE_F
);
692 if (!(hcr_el2
& HCR_IMO
) || (hcr_el2
& HCR_TGE
)) {
693 /* VIRQs are only taken when hypervized. */
696 return !(env
->daif
& PSTATE_I
);
698 if (!(hcr_el2
& HCR_AMO
) || (hcr_el2
& HCR_TGE
)) {
699 /* VIRQs are only taken when hypervized. */
702 return !(env
->daif
& PSTATE_A
);
704 g_assert_not_reached();
708 * Use the target EL, current execution state and SCR/HCR settings to
709 * determine whether the corresponding CPSR bit is used to mask the
712 if ((target_el
> cur_el
) && (target_el
!= 1)) {
713 /* Exceptions targeting a higher EL may not be maskable */
714 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
718 * According to ARM DDI 0487H.a, an interrupt can be masked
719 * when HCR_E2H and HCR_TGE are both set regardless of the
720 * current Security state. Note that we need to revisit this
721 * part again once we need to support NMI.
723 if ((hcr_el2
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
728 /* Interrupt cannot be masked when the target EL is 3 */
732 g_assert_not_reached();
736 * The old 32-bit-only environment has a more complicated
737 * masking setup. HCR and SCR bits not only affect interrupt
738 * routing but also change the behaviour of masking.
745 * If FIQs are routed to EL3 or EL2 then there are cases where
746 * we override the CPSR.F in determining if the exception is
747 * masked or not. If neither of these are set then we fall back
748 * to the CPSR.F setting otherwise we further assess the state
751 hcr
= hcr_el2
& HCR_FMO
;
752 scr
= (env
->cp15
.scr_el3
& SCR_FIQ
);
755 * When EL3 is 32-bit, the SCR.FW bit controls whether the
756 * CPSR.F bit masks FIQ interrupts when taken in non-secure
757 * state. If SCR.FW is set then FIQs can be masked by CPSR.F
758 * when non-secure but only when FIQs are only routed to EL3.
760 scr
= scr
&& !((env
->cp15
.scr_el3
& SCR_FW
) && !hcr
);
764 * When EL3 execution state is 32-bit, if HCR.IMO is set then
765 * we may override the CPSR.I masking when in non-secure state.
766 * The SCR.IRQ setting has already been taken into consideration
767 * when setting the target EL, so it does not have a further
770 hcr
= hcr_el2
& HCR_IMO
;
774 g_assert_not_reached();
777 if ((scr
|| hcr
) && !secure
) {
784 * The PSTATE bits only mask the interrupt if we have not overridden the
787 return unmasked
|| pstate_unmasked
;
790 static bool arm_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
792 CPUClass
*cc
= CPU_GET_CLASS(cs
);
793 CPUARMState
*env
= cpu_env(cs
);
794 uint32_t cur_el
= arm_current_el(env
);
795 bool secure
= arm_is_secure(env
);
796 uint64_t hcr_el2
= arm_hcr_el2_eff(env
);
800 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */
802 if (interrupt_request
& CPU_INTERRUPT_FIQ
) {
804 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
805 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
806 cur_el
, secure
, hcr_el2
)) {
810 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
812 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
813 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
814 cur_el
, secure
, hcr_el2
)) {
818 if (interrupt_request
& CPU_INTERRUPT_VIRQ
) {
819 excp_idx
= EXCP_VIRQ
;
821 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
822 cur_el
, secure
, hcr_el2
)) {
826 if (interrupt_request
& CPU_INTERRUPT_VFIQ
) {
827 excp_idx
= EXCP_VFIQ
;
829 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
830 cur_el
, secure
, hcr_el2
)) {
834 if (interrupt_request
& CPU_INTERRUPT_VSERR
) {
835 excp_idx
= EXCP_VSERR
;
837 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
838 cur_el
, secure
, hcr_el2
)) {
839 /* Taking a virtual abort clears HCR_EL2.VSE */
840 env
->cp15
.hcr_el2
&= ~HCR_VSE
;
841 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VSERR
);
848 cs
->exception_index
= excp_idx
;
849 env
->exception
.target_el
= target_el
;
850 cc
->tcg_ops
->do_interrupt(cs
);
854 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
856 void arm_cpu_update_virq(ARMCPU
*cpu
)
859 * Update the interrupt level for VIRQ, which is the logical OR of
860 * the HCR_EL2.VI bit and the input line level from the GIC.
862 CPUARMState
*env
= &cpu
->env
;
863 CPUState
*cs
= CPU(cpu
);
865 bool new_state
= (env
->cp15
.hcr_el2
& HCR_VI
) ||
866 (env
->irq_line_state
& CPU_INTERRUPT_VIRQ
);
868 if (new_state
!= ((cs
->interrupt_request
& CPU_INTERRUPT_VIRQ
) != 0)) {
870 cpu_interrupt(cs
, CPU_INTERRUPT_VIRQ
);
872 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VIRQ
);
877 void arm_cpu_update_vfiq(ARMCPU
*cpu
)
880 * Update the interrupt level for VFIQ, which is the logical OR of
881 * the HCR_EL2.VF bit and the input line level from the GIC.
883 CPUARMState
*env
= &cpu
->env
;
884 CPUState
*cs
= CPU(cpu
);
886 bool new_state
= (env
->cp15
.hcr_el2
& HCR_VF
) ||
887 (env
->irq_line_state
& CPU_INTERRUPT_VFIQ
);
889 if (new_state
!= ((cs
->interrupt_request
& CPU_INTERRUPT_VFIQ
) != 0)) {
891 cpu_interrupt(cs
, CPU_INTERRUPT_VFIQ
);
893 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VFIQ
);
898 void arm_cpu_update_vserr(ARMCPU
*cpu
)
901 * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit.
903 CPUARMState
*env
= &cpu
->env
;
904 CPUState
*cs
= CPU(cpu
);
906 bool new_state
= env
->cp15
.hcr_el2
& HCR_VSE
;
908 if (new_state
!= ((cs
->interrupt_request
& CPU_INTERRUPT_VSERR
) != 0)) {
910 cpu_interrupt(cs
, CPU_INTERRUPT_VSERR
);
912 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VSERR
);
917 #ifndef CONFIG_USER_ONLY
918 static void arm_cpu_set_irq(void *opaque
, int irq
, int level
)
920 ARMCPU
*cpu
= opaque
;
921 CPUARMState
*env
= &cpu
->env
;
922 CPUState
*cs
= CPU(cpu
);
923 static const int mask
[] = {
924 [ARM_CPU_IRQ
] = CPU_INTERRUPT_HARD
,
925 [ARM_CPU_FIQ
] = CPU_INTERRUPT_FIQ
,
926 [ARM_CPU_VIRQ
] = CPU_INTERRUPT_VIRQ
,
927 [ARM_CPU_VFIQ
] = CPU_INTERRUPT_VFIQ
930 if (!arm_feature(env
, ARM_FEATURE_EL2
) &&
931 (irq
== ARM_CPU_VIRQ
|| irq
== ARM_CPU_VFIQ
)) {
933 * The GIC might tell us about VIRQ and VFIQ state, but if we don't
934 * have EL2 support we don't care. (Unless the guest is doing something
935 * silly this will only be calls saying "level is still 0".)
941 env
->irq_line_state
|= mask
[irq
];
943 env
->irq_line_state
&= ~mask
[irq
];
948 arm_cpu_update_virq(cpu
);
951 arm_cpu_update_vfiq(cpu
);
956 cpu_interrupt(cs
, mask
[irq
]);
958 cpu_reset_interrupt(cs
, mask
[irq
]);
962 g_assert_not_reached();
966 static void arm_cpu_kvm_set_irq(void *opaque
, int irq
, int level
)
969 ARMCPU
*cpu
= opaque
;
970 CPUARMState
*env
= &cpu
->env
;
971 CPUState
*cs
= CPU(cpu
);
972 uint32_t linestate_bit
;
977 irq_id
= KVM_ARM_IRQ_CPU_IRQ
;
978 linestate_bit
= CPU_INTERRUPT_HARD
;
981 irq_id
= KVM_ARM_IRQ_CPU_FIQ
;
982 linestate_bit
= CPU_INTERRUPT_FIQ
;
985 g_assert_not_reached();
989 env
->irq_line_state
|= linestate_bit
;
991 env
->irq_line_state
&= ~linestate_bit
;
993 kvm_arm_set_irq(cs
->cpu_index
, KVM_ARM_IRQ_TYPE_CPU
, irq_id
, !!level
);
997 static bool arm_cpu_virtio_is_big_endian(CPUState
*cs
)
999 ARMCPU
*cpu
= ARM_CPU(cs
);
1000 CPUARMState
*env
= &cpu
->env
;
1002 cpu_synchronize_state(cs
);
1003 return arm_cpu_data_is_big_endian(env
);
1008 static void arm_disas_set_info(CPUState
*cpu
, disassemble_info
*info
)
1010 ARMCPU
*ac
= ARM_CPU(cpu
);
1011 CPUARMState
*env
= &ac
->env
;
1015 info
->cap_arch
= CS_ARCH_ARM64
;
1016 info
->cap_insn_unit
= 4;
1017 info
->cap_insn_split
= 4;
1021 info
->cap_insn_unit
= 2;
1022 info
->cap_insn_split
= 4;
1023 cap_mode
= CS_MODE_THUMB
;
1025 info
->cap_insn_unit
= 4;
1026 info
->cap_insn_split
= 4;
1027 cap_mode
= CS_MODE_ARM
;
1029 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1030 cap_mode
|= CS_MODE_V8
;
1032 if (arm_feature(env
, ARM_FEATURE_M
)) {
1033 cap_mode
|= CS_MODE_MCLASS
;
1035 info
->cap_arch
= CS_ARCH_ARM
;
1036 info
->cap_mode
= cap_mode
;
1039 sctlr_b
= arm_sctlr_b(env
);
1040 if (bswap_code(sctlr_b
)) {
1041 #if TARGET_BIG_ENDIAN
1042 info
->endian
= BFD_ENDIAN_LITTLE
;
1044 info
->endian
= BFD_ENDIAN_BIG
;
1047 info
->flags
&= ~INSN_ARM_BE32
;
1048 #ifndef CONFIG_USER_ONLY
1050 info
->flags
|= INSN_ARM_BE32
;
1055 #ifdef TARGET_AARCH64
1057 static void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
1059 ARMCPU
*cpu
= ARM_CPU(cs
);
1060 CPUARMState
*env
= &cpu
->env
;
1061 uint32_t psr
= pstate_read(env
);
1063 int el
= arm_current_el(env
);
1064 uint64_t hcr
= arm_hcr_el2_eff(env
);
1065 const char *ns_status
;
1068 qemu_fprintf(f
, " PC=%016" PRIx64
" ", env
->pc
);
1069 for (i
= 0; i
< 32; i
++) {
1071 qemu_fprintf(f
, " SP=%016" PRIx64
"\n", env
->xregs
[i
]);
1073 qemu_fprintf(f
, "X%02d=%016" PRIx64
"%s", i
, env
->xregs
[i
],
1074 (i
+ 2) % 3 ? " " : "\n");
1078 if (arm_feature(env
, ARM_FEATURE_EL3
) && el
!= 3) {
1079 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
1083 qemu_fprintf(f
, "PSTATE=%08x %c%c%c%c %sEL%d%c",
1085 psr
& PSTATE_N
? 'N' : '-',
1086 psr
& PSTATE_Z
? 'Z' : '-',
1087 psr
& PSTATE_C
? 'C' : '-',
1088 psr
& PSTATE_V
? 'V' : '-',
1091 psr
& PSTATE_SP
? 'h' : 't');
1093 if (cpu_isar_feature(aa64_sme
, cpu
)) {
1094 qemu_fprintf(f
, " SVCR=%08" PRIx64
" %c%c",
1096 (FIELD_EX64(env
->svcr
, SVCR
, ZA
) ? 'Z' : '-'),
1097 (FIELD_EX64(env
->svcr
, SVCR
, SM
) ? 'S' : '-'));
1099 if (cpu_isar_feature(aa64_bti
, cpu
)) {
1100 qemu_fprintf(f
, " BTYPE=%d", (psr
& PSTATE_BTYPE
) >> 10);
1102 qemu_fprintf(f
, "%s%s%s",
1103 (hcr
& HCR_NV
) ? " NV" : "",
1104 (hcr
& HCR_NV1
) ? " NV1" : "",
1105 (hcr
& HCR_NV2
) ? " NV2" : "");
1106 if (!(flags
& CPU_DUMP_FPU
)) {
1107 qemu_fprintf(f
, "\n");
1110 if (fp_exception_el(env
, el
) != 0) {
1111 qemu_fprintf(f
, " FPU disabled\n");
1114 qemu_fprintf(f
, " FPCR=%08x FPSR=%08x\n",
1115 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
1117 if (cpu_isar_feature(aa64_sme
, cpu
) && FIELD_EX64(env
->svcr
, SVCR
, SM
)) {
1118 sve
= sme_exception_el(env
, el
) == 0;
1119 } else if (cpu_isar_feature(aa64_sve
, cpu
)) {
1120 sve
= sve_exception_el(env
, el
) == 0;
1126 int zcr_len
= sve_vqm1_for_el(env
, el
);
1128 for (i
= 0; i
<= FFR_PRED_NUM
; i
++) {
1130 if (i
== FFR_PRED_NUM
) {
1131 qemu_fprintf(f
, "FFR=");
1132 /* It's last, so end the line. */
1135 qemu_fprintf(f
, "P%02d=", i
);
1148 /* More than one quadword per predicate. */
1153 for (j
= zcr_len
/ 4; j
>= 0; j
--) {
1155 if (j
* 4 + 4 <= zcr_len
+ 1) {
1158 digits
= (zcr_len
% 4 + 1) * 4;
1160 qemu_fprintf(f
, "%0*" PRIx64
"%s", digits
,
1161 env
->vfp
.pregs
[i
].p
[j
],
1162 j
? ":" : eol
? "\n" : " ");
1168 * With vl=16, there are only 37 columns per register,
1169 * so output two registers per line.
1171 for (i
= 0; i
< 32; i
++) {
1172 qemu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
"%s",
1173 i
, env
->vfp
.zregs
[i
].d
[1],
1174 env
->vfp
.zregs
[i
].d
[0], i
& 1 ? "\n" : " ");
1177 for (i
= 0; i
< 32; i
++) {
1178 qemu_fprintf(f
, "Z%02d=", i
);
1179 for (j
= zcr_len
; j
>= 0; j
--) {
1180 qemu_fprintf(f
, "%016" PRIx64
":%016" PRIx64
"%s",
1181 env
->vfp
.zregs
[i
].d
[j
* 2 + 1],
1182 env
->vfp
.zregs
[i
].d
[j
* 2 + 0],
1188 for (i
= 0; i
< 32; i
++) {
1189 uint64_t *q
= aa64_vfp_qreg(env
, i
);
1190 qemu_fprintf(f
, "Q%02d=%016" PRIx64
":%016" PRIx64
"%s",
1191 i
, q
[1], q
[0], (i
& 1 ? "\n" : " "));
1195 if (cpu_isar_feature(aa64_sme
, cpu
) &&
1196 FIELD_EX64(env
->svcr
, SVCR
, ZA
) &&
1197 sme_exception_el(env
, el
) == 0) {
1198 int zcr_len
= sve_vqm1_for_el_sm(env
, el
, true);
1199 int svl
= (zcr_len
+ 1) * 16;
1200 int svl_lg10
= svl
< 100 ? 2 : 3;
1202 for (i
= 0; i
< svl
; i
++) {
1203 qemu_fprintf(f
, "ZA[%0*d]=", svl_lg10
, i
);
1204 for (j
= zcr_len
; j
>= 0; --j
) {
1205 qemu_fprintf(f
, "%016" PRIx64
":%016" PRIx64
"%c",
1206 env
->zarray
[i
].d
[2 * j
+ 1],
1207 env
->zarray
[i
].d
[2 * j
],
1216 static inline void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
1218 g_assert_not_reached();
1223 static void arm_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
1225 ARMCPU
*cpu
= ARM_CPU(cs
);
1226 CPUARMState
*env
= &cpu
->env
;
1230 aarch64_cpu_dump_state(cs
, f
, flags
);
1234 for (i
= 0; i
< 16; i
++) {
1235 qemu_fprintf(f
, "R%02d=%08x", i
, env
->regs
[i
]);
1237 qemu_fprintf(f
, "\n");
1239 qemu_fprintf(f
, " ");
1243 if (arm_feature(env
, ARM_FEATURE_M
)) {
1244 uint32_t xpsr
= xpsr_read(env
);
1246 const char *ns_status
= "";
1248 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
1249 ns_status
= env
->v7m
.secure
? "S " : "NS ";
1252 if (xpsr
& XPSR_EXCP
) {
1255 if (env
->v7m
.control
[env
->v7m
.secure
] & R_V7M_CONTROL_NPRIV_MASK
) {
1256 mode
= "unpriv-thread";
1258 mode
= "priv-thread";
1262 qemu_fprintf(f
, "XPSR=%08x %c%c%c%c %c %s%s\n",
1264 xpsr
& XPSR_N
? 'N' : '-',
1265 xpsr
& XPSR_Z
? 'Z' : '-',
1266 xpsr
& XPSR_C
? 'C' : '-',
1267 xpsr
& XPSR_V
? 'V' : '-',
1268 xpsr
& XPSR_T
? 'T' : 'A',
1272 uint32_t psr
= cpsr_read(env
);
1273 const char *ns_status
= "";
1275 if (arm_feature(env
, ARM_FEATURE_EL3
) &&
1276 (psr
& CPSR_M
) != ARM_CPU_MODE_MON
) {
1277 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
1280 qemu_fprintf(f
, "PSR=%08x %c%c%c%c %c %s%s%d\n",
1282 psr
& CPSR_N
? 'N' : '-',
1283 psr
& CPSR_Z
? 'Z' : '-',
1284 psr
& CPSR_C
? 'C' : '-',
1285 psr
& CPSR_V
? 'V' : '-',
1286 psr
& CPSR_T
? 'T' : 'A',
1288 aarch32_mode_name(psr
), (psr
& 0x10) ? 32 : 26);
1291 if (flags
& CPU_DUMP_FPU
) {
1293 if (cpu_isar_feature(aa32_simd_r32
, cpu
)) {
1295 } else if (cpu_isar_feature(aa32_vfp_simd
, cpu
)) {
1298 for (i
= 0; i
< numvfpregs
; i
++) {
1299 uint64_t v
= *aa32_vfp_dreg(env
, i
);
1300 qemu_fprintf(f
, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64
"\n",
1302 i
* 2 + 1, (uint32_t)(v
>> 32),
1305 qemu_fprintf(f
, "FPSCR: %08x\n", vfp_get_fpscr(env
));
1306 if (cpu_isar_feature(aa32_mve
, cpu
)) {
1307 qemu_fprintf(f
, "VPR: %08x\n", env
->v7m
.vpr
);
1312 uint64_t arm_build_mp_affinity(int idx
, uint8_t clustersz
)
1314 uint32_t Aff1
= idx
/ clustersz
;
1315 uint32_t Aff0
= idx
% clustersz
;
1316 return (Aff1
<< ARM_AFF1_SHIFT
) | Aff0
;
1319 uint64_t arm_cpu_mp_affinity(ARMCPU
*cpu
)
1321 return cpu
->mp_affinity
;
1324 static void arm_cpu_initfn(Object
*obj
)
1326 ARMCPU
*cpu
= ARM_CPU(obj
);
1328 cpu
->cp_regs
= g_hash_table_new_full(g_direct_hash
, g_direct_equal
,
1331 QLIST_INIT(&cpu
->pre_el_change_hooks
);
1332 QLIST_INIT(&cpu
->el_change_hooks
);
1334 #ifdef CONFIG_USER_ONLY
1335 # ifdef TARGET_AARCH64
1337 * The linux kernel defaults to 512-bit for SVE, and 256-bit for SME.
1338 * These values were chosen to fit within the default signal frame.
1339 * See documentation for /proc/sys/abi/{sve,sme}_default_vector_length,
1340 * and our corresponding cpu property.
1342 cpu
->sve_default_vq
= 4;
1343 cpu
->sme_default_vq
= 2;
1346 /* Our inbound IRQ and FIQ lines */
1347 if (kvm_enabled()) {
1348 /* VIRQ and VFIQ are unused with KVM but we add them to maintain
1349 * the same interface as non-KVM CPUs.
1351 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_kvm_set_irq
, 4);
1353 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_set_irq
, 4);
1356 qdev_init_gpio_out(DEVICE(cpu
), cpu
->gt_timer_outputs
,
1357 ARRAY_SIZE(cpu
->gt_timer_outputs
));
1359 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->gicv3_maintenance_interrupt
,
1360 "gicv3-maintenance-interrupt", 1);
1361 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->pmu_interrupt
,
1362 "pmu-interrupt", 1);
1365 /* DTB consumers generally don't in fact care what the 'compatible'
1366 * string is, so always provide some string and trust that a hypothetical
1367 * picky DTB consumer will also provide a helpful error message.
1369 cpu
->dtb_compatible
= "qemu,unknown";
1370 cpu
->psci_version
= QEMU_PSCI_VERSION_0_1
; /* By default assume PSCI v0.1 */
1371 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_NONE
;
1373 if (tcg_enabled() || hvf_enabled()) {
1374 /* TCG and HVF implement PSCI 1.1 */
1375 cpu
->psci_version
= QEMU_PSCI_VERSION_1_1
;
1379 static Property arm_cpu_gt_cntfrq_property
=
1380 DEFINE_PROP_UINT64("cntfrq", ARMCPU
, gt_cntfrq_hz
,
1381 NANOSECONDS_PER_SECOND
/ GTIMER_SCALE
);
1383 static Property arm_cpu_reset_cbar_property
=
1384 DEFINE_PROP_UINT64("reset-cbar", ARMCPU
, reset_cbar
, 0);
1386 static Property arm_cpu_reset_hivecs_property
=
1387 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU
, reset_hivecs
, false);
1389 #ifndef CONFIG_USER_ONLY
1390 static Property arm_cpu_has_el2_property
=
1391 DEFINE_PROP_BOOL("has_el2", ARMCPU
, has_el2
, true);
1393 static Property arm_cpu_has_el3_property
=
1394 DEFINE_PROP_BOOL("has_el3", ARMCPU
, has_el3
, true);
1397 static Property arm_cpu_cfgend_property
=
1398 DEFINE_PROP_BOOL("cfgend", ARMCPU
, cfgend
, false);
1400 static Property arm_cpu_has_vfp_property
=
1401 DEFINE_PROP_BOOL("vfp", ARMCPU
, has_vfp
, true);
1403 static Property arm_cpu_has_vfp_d32_property
=
1404 DEFINE_PROP_BOOL("vfp-d32", ARMCPU
, has_vfp_d32
, true);
1406 static Property arm_cpu_has_neon_property
=
1407 DEFINE_PROP_BOOL("neon", ARMCPU
, has_neon
, true);
1409 static Property arm_cpu_has_dsp_property
=
1410 DEFINE_PROP_BOOL("dsp", ARMCPU
, has_dsp
, true);
1412 static Property arm_cpu_has_mpu_property
=
1413 DEFINE_PROP_BOOL("has-mpu", ARMCPU
, has_mpu
, true);
1415 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value,
1416 * because the CPU initfn will have already set cpu->pmsav7_dregion to
1417 * the right value for that particular CPU type, and we don't want
1418 * to override that with an incorrect constant value.
1420 static Property arm_cpu_pmsav7_dregion_property
=
1421 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU
,
1423 qdev_prop_uint32
, uint32_t);
1425 static bool arm_get_pmu(Object
*obj
, Error
**errp
)
1427 ARMCPU
*cpu
= ARM_CPU(obj
);
1429 return cpu
->has_pmu
;
1432 static void arm_set_pmu(Object
*obj
, bool value
, Error
**errp
)
1434 ARMCPU
*cpu
= ARM_CPU(obj
);
1437 if (kvm_enabled() && !kvm_arm_pmu_supported()) {
1438 error_setg(errp
, "'pmu' feature not supported by KVM on this host");
1441 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
1443 unset_feature(&cpu
->env
, ARM_FEATURE_PMU
);
1445 cpu
->has_pmu
= value
;
1448 unsigned int gt_cntfrq_period_ns(ARMCPU
*cpu
)
1451 * The exact approach to calculating guest ticks is:
1453 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz,
1454 * NANOSECONDS_PER_SECOND);
1456 * We don't do that. Rather we intentionally use integer division
1457 * truncation below and in the caller for the conversion of host monotonic
1458 * time to guest ticks to provide the exact inverse for the semantics of
1459 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so
1460 * it loses precision when representing frequencies where
1461 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to
1462 * provide an exact inverse leads to scheduling timers with negative
1463 * periods, which in turn leads to sticky behaviour in the guest.
1465 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor
1466 * cannot become zero.
1468 return NANOSECONDS_PER_SECOND
> cpu
->gt_cntfrq_hz
?
1469 NANOSECONDS_PER_SECOND
/ cpu
->gt_cntfrq_hz
: 1;
1472 static void arm_cpu_propagate_feature_implications(ARMCPU
*cpu
)
1474 CPUARMState
*env
= &cpu
->env
;
1475 bool no_aa32
= false;
1478 * Some features automatically imply others: set the feature
1479 * bits explicitly for these cases.
1482 if (arm_feature(env
, ARM_FEATURE_M
)) {
1483 set_feature(env
, ARM_FEATURE_PMSA
);
1486 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1487 if (arm_feature(env
, ARM_FEATURE_M
)) {
1488 set_feature(env
, ARM_FEATURE_V7
);
1490 set_feature(env
, ARM_FEATURE_V7VE
);
1495 * There exist AArch64 cpus without AArch32 support. When KVM
1496 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
1497 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
1498 * As a general principle, we also do not make ID register
1499 * consistency checks anywhere unless using TCG, because only
1500 * for TCG would a consistency-check failure be a QEMU bug.
1502 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1503 no_aa32
= !cpu_isar_feature(aa64_aa32
, cpu
);
1506 if (arm_feature(env
, ARM_FEATURE_V7VE
)) {
1508 * v7 Virtualization Extensions. In real hardware this implies
1509 * EL2 and also the presence of the Security Extensions.
1510 * For QEMU, for backwards-compatibility we implement some
1511 * CPUs or CPU configs which have no actual EL2 or EL3 but do
1512 * include the various other features that V7VE implies.
1513 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
1514 * Security Extensions is ARM_FEATURE_EL3.
1516 assert(!tcg_enabled() || no_aa32
||
1517 cpu_isar_feature(aa32_arm_div
, cpu
));
1518 set_feature(env
, ARM_FEATURE_LPAE
);
1519 set_feature(env
, ARM_FEATURE_V7
);
1521 if (arm_feature(env
, ARM_FEATURE_V7
)) {
1522 set_feature(env
, ARM_FEATURE_VAPA
);
1523 set_feature(env
, ARM_FEATURE_THUMB2
);
1524 set_feature(env
, ARM_FEATURE_MPIDR
);
1525 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1526 set_feature(env
, ARM_FEATURE_V6K
);
1528 set_feature(env
, ARM_FEATURE_V6
);
1532 * Always define VBAR for V7 CPUs even if it doesn't exist in
1533 * non-EL3 configs. This is needed by some legacy boards.
1535 set_feature(env
, ARM_FEATURE_VBAR
);
1537 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
1538 set_feature(env
, ARM_FEATURE_V6
);
1539 set_feature(env
, ARM_FEATURE_MVFR
);
1541 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1542 set_feature(env
, ARM_FEATURE_V5
);
1543 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1544 assert(!tcg_enabled() || no_aa32
||
1545 cpu_isar_feature(aa32_jazelle
, cpu
));
1546 set_feature(env
, ARM_FEATURE_AUXCR
);
1549 if (arm_feature(env
, ARM_FEATURE_V5
)) {
1550 set_feature(env
, ARM_FEATURE_V4T
);
1552 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
1553 set_feature(env
, ARM_FEATURE_V7MP
);
1555 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
1556 set_feature(env
, ARM_FEATURE_CBAR
);
1558 if (arm_feature(env
, ARM_FEATURE_THUMB2
) &&
1559 !arm_feature(env
, ARM_FEATURE_M
)) {
1560 set_feature(env
, ARM_FEATURE_THUMB_DSP
);
1564 void arm_cpu_post_init(Object
*obj
)
1566 ARMCPU
*cpu
= ARM_CPU(obj
);
1569 * Some features imply others. Figure this out now, because we
1570 * are going to look at the feature bits in deciding which
1571 * properties to add.
1573 arm_cpu_propagate_feature_implications(cpu
);
1575 if (arm_feature(&cpu
->env
, ARM_FEATURE_CBAR
) ||
1576 arm_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
)) {
1577 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_cbar_property
);
1580 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
1581 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_hivecs_property
);
1584 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1585 object_property_add_uint64_ptr(obj
, "rvbar",
1587 OBJ_PROP_FLAG_READWRITE
);
1590 #ifndef CONFIG_USER_ONLY
1591 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL3
)) {
1592 /* Add the has_el3 state CPU property only if EL3 is allowed. This will
1593 * prevent "has_el3" from existing on CPUs which cannot support EL3.
1595 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el3_property
);
1597 object_property_add_link(obj
, "secure-memory",
1599 (Object
**)&cpu
->secure_memory
,
1600 qdev_prop_allow_set_link_before_realize
,
1601 OBJ_PROP_LINK_STRONG
);
1604 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL2
)) {
1605 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el2_property
);
1609 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMU
)) {
1610 cpu
->has_pmu
= true;
1611 object_property_add_bool(obj
, "pmu", arm_get_pmu
, arm_set_pmu
);
1615 * Allow user to turn off VFP and Neon support, but only for TCG --
1616 * KVM does not currently allow us to lie to the guest about its
1617 * ID/feature registers, so the guest always sees what the host has.
1619 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1620 if (cpu_isar_feature(aa64_fp_simd
, cpu
)) {
1621 cpu
->has_vfp
= true;
1622 cpu
->has_vfp_d32
= true;
1623 if (tcg_enabled() || qtest_enabled()) {
1624 qdev_property_add_static(DEVICE(obj
),
1625 &arm_cpu_has_vfp_property
);
1628 } else if (cpu_isar_feature(aa32_vfp
, cpu
)) {
1629 cpu
->has_vfp
= true;
1630 if (cpu_isar_feature(aa32_simd_r32
, cpu
)) {
1631 cpu
->has_vfp_d32
= true;
1633 * The permitted values of the SIMDReg bits [3:0] on
1634 * Armv8-A are either 0b0000 and 0b0010. On such CPUs,
1635 * make sure that has_vfp_d32 can not be set to false.
1637 if ((tcg_enabled() || qtest_enabled())
1638 && !(arm_feature(&cpu
->env
, ARM_FEATURE_V8
)
1639 && !arm_feature(&cpu
->env
, ARM_FEATURE_M
))) {
1640 qdev_property_add_static(DEVICE(obj
),
1641 &arm_cpu_has_vfp_d32_property
);
1646 if (arm_feature(&cpu
->env
, ARM_FEATURE_NEON
)) {
1647 cpu
->has_neon
= true;
1648 if (!kvm_enabled()) {
1649 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_neon_property
);
1653 if (arm_feature(&cpu
->env
, ARM_FEATURE_M
) &&
1654 arm_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
)) {
1655 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_dsp_property
);
1658 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMSA
)) {
1659 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_mpu_property
);
1660 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
1661 qdev_property_add_static(DEVICE(obj
),
1662 &arm_cpu_pmsav7_dregion_property
);
1666 if (arm_feature(&cpu
->env
, ARM_FEATURE_M_SECURITY
)) {
1667 object_property_add_link(obj
, "idau", TYPE_IDAU_INTERFACE
, &cpu
->idau
,
1668 qdev_prop_allow_set_link_before_realize
,
1669 OBJ_PROP_LINK_STRONG
);
1671 * M profile: initial value of the Secure VTOR. We can't just use
1672 * a simple DEFINE_PROP_UINT32 for this because we want to permit
1673 * the property to be set after realize.
1675 object_property_add_uint32_ptr(obj
, "init-svtor",
1677 OBJ_PROP_FLAG_READWRITE
);
1679 if (arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
1681 * Initial value of the NS VTOR (for cores without the Security
1682 * extension, this is the only VTOR)
1684 object_property_add_uint32_ptr(obj
, "init-nsvtor",
1686 OBJ_PROP_FLAG_READWRITE
);
1689 /* Not DEFINE_PROP_UINT32: we want this to be settable after realize */
1690 object_property_add_uint32_ptr(obj
, "psci-conduit",
1692 OBJ_PROP_FLAG_READWRITE
);
1694 qdev_property_add_static(DEVICE(obj
), &arm_cpu_cfgend_property
);
1696 if (arm_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
)) {
1697 qdev_property_add_static(DEVICE(cpu
), &arm_cpu_gt_cntfrq_property
);
1700 if (kvm_enabled()) {
1701 kvm_arm_add_vcpu_properties(cpu
);
1704 #ifndef CONFIG_USER_ONLY
1705 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
) &&
1706 cpu_isar_feature(aa64_mte
, cpu
)) {
1707 object_property_add_link(obj
, "tag-memory",
1709 (Object
**)&cpu
->tag_memory
,
1710 qdev_prop_allow_set_link_before_realize
,
1711 OBJ_PROP_LINK_STRONG
);
1713 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL3
)) {
1714 object_property_add_link(obj
, "secure-tag-memory",
1716 (Object
**)&cpu
->secure_tag_memory
,
1717 qdev_prop_allow_set_link_before_realize
,
1718 OBJ_PROP_LINK_STRONG
);
1724 static void arm_cpu_finalizefn(Object
*obj
)
1726 ARMCPU
*cpu
= ARM_CPU(obj
);
1727 ARMELChangeHook
*hook
, *next
;
1729 g_hash_table_destroy(cpu
->cp_regs
);
1731 QLIST_FOREACH_SAFE(hook
, &cpu
->pre_el_change_hooks
, node
, next
) {
1732 QLIST_REMOVE(hook
, node
);
1735 QLIST_FOREACH_SAFE(hook
, &cpu
->el_change_hooks
, node
, next
) {
1736 QLIST_REMOVE(hook
, node
);
1739 #ifndef CONFIG_USER_ONLY
1740 if (cpu
->pmu_timer
) {
1741 timer_free(cpu
->pmu_timer
);
1746 void arm_cpu_finalize_features(ARMCPU
*cpu
, Error
**errp
)
1748 Error
*local_err
= NULL
;
1750 #ifdef TARGET_AARCH64
1751 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1752 arm_cpu_sve_finalize(cpu
, &local_err
);
1753 if (local_err
!= NULL
) {
1754 error_propagate(errp
, local_err
);
1759 * FEAT_SME is not architecturally dependent on FEAT_SVE (unless
1760 * FEAT_SME_FA64 is present). However our implementation currently
1761 * assumes it, so if the user asked for sve=off then turn off SME also.
1762 * (KVM doesn't currently support SME at all.)
1764 if (cpu_isar_feature(aa64_sme
, cpu
) && !cpu_isar_feature(aa64_sve
, cpu
)) {
1765 object_property_set_bool(OBJECT(cpu
), "sme", false, &error_abort
);
1768 arm_cpu_sme_finalize(cpu
, &local_err
);
1769 if (local_err
!= NULL
) {
1770 error_propagate(errp
, local_err
);
1774 arm_cpu_pauth_finalize(cpu
, &local_err
);
1775 if (local_err
!= NULL
) {
1776 error_propagate(errp
, local_err
);
1780 arm_cpu_lpa2_finalize(cpu
, &local_err
);
1781 if (local_err
!= NULL
) {
1782 error_propagate(errp
, local_err
);
1788 if (kvm_enabled()) {
1789 kvm_arm_steal_time_finalize(cpu
, &local_err
);
1790 if (local_err
!= NULL
) {
1791 error_propagate(errp
, local_err
);
1797 static void arm_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
1799 CPUState
*cs
= CPU(dev
);
1800 ARMCPU
*cpu
= ARM_CPU(dev
);
1801 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(dev
);
1802 CPUARMState
*env
= &cpu
->env
;
1804 Error
*local_err
= NULL
;
1806 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
1807 /* Use pc-relative instructions in system-mode */
1808 cs
->tcg_cflags
|= CF_PCREL
;
1811 /* If we needed to query the host kernel for the CPU features
1812 * then it's possible that might have failed in the initfn, but
1813 * this is the first point where we can report it.
1815 if (cpu
->host_cpu_probe_failed
) {
1816 if (!kvm_enabled() && !hvf_enabled()) {
1817 error_setg(errp
, "The 'host' CPU type can only be used with KVM or HVF");
1819 error_setg(errp
, "Failed to retrieve host CPU features");
1824 #ifndef CONFIG_USER_ONLY
1825 /* The NVIC and M-profile CPU are two halves of a single piece of
1826 * hardware; trying to use one without the other is a command line
1827 * error and will result in segfaults if not caught here.
1829 if (arm_feature(env
, ARM_FEATURE_M
)) {
1831 error_setg(errp
, "This board cannot be used with Cortex-M CPUs");
1836 error_setg(errp
, "This board can only be used with Cortex-M CPUs");
1841 if (!tcg_enabled() && !qtest_enabled()) {
1843 * We assume that no accelerator except TCG (and the "not really an
1844 * accelerator" qtest) can handle these features, because Arm hardware
1845 * virtualization can't virtualize them.
1847 * Catch all the cases which might cause us to create more than one
1848 * address space for the CPU (otherwise we will assert() later in
1849 * cpu_address_space_init()).
1851 if (arm_feature(env
, ARM_FEATURE_M
)) {
1853 "Cannot enable %s when using an M-profile guest CPU",
1854 current_accel_name());
1859 "Cannot enable %s when guest CPU has EL3 enabled",
1860 current_accel_name());
1863 if (cpu
->tag_memory
) {
1865 "Cannot enable %s when guest CPUs has MTE enabled",
1866 current_accel_name());
1874 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
1875 if (!cpu
->gt_cntfrq_hz
) {
1876 error_setg(errp
, "Invalid CNTFRQ: %"PRId64
"Hz",
1880 scale
= gt_cntfrq_period_ns(cpu
);
1882 scale
= GTIMER_SCALE
;
1885 cpu
->gt_timer
[GTIMER_PHYS
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1886 arm_gt_ptimer_cb
, cpu
);
1887 cpu
->gt_timer
[GTIMER_VIRT
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1888 arm_gt_vtimer_cb
, cpu
);
1889 cpu
->gt_timer
[GTIMER_HYP
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1890 arm_gt_htimer_cb
, cpu
);
1891 cpu
->gt_timer
[GTIMER_SEC
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1892 arm_gt_stimer_cb
, cpu
);
1893 cpu
->gt_timer
[GTIMER_HYPVIRT
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1894 arm_gt_hvtimer_cb
, cpu
);
1898 cpu_exec_realizefn(cs
, &local_err
);
1899 if (local_err
!= NULL
) {
1900 error_propagate(errp
, local_err
);
1904 arm_cpu_finalize_features(cpu
, &local_err
);
1905 if (local_err
!= NULL
) {
1906 error_propagate(errp
, local_err
);
1910 #ifdef CONFIG_USER_ONLY
1912 * User mode relies on IC IVAU instructions to catch modification of
1915 * Clear CTR_EL0.DIC to ensure that software that honors these flags uses
1916 * IC IVAU even if the emulated processor does not normally require it.
1918 cpu
->ctr
= FIELD_DP64(cpu
->ctr
, CTR_EL0
, DIC
, 0);
1921 if (arm_feature(env
, ARM_FEATURE_AARCH64
) &&
1922 cpu
->has_vfp
!= cpu
->has_neon
) {
1924 * This is an architectural requirement for AArch64; AArch32 is
1925 * more flexible and permits VFP-no-Neon and Neon-no-VFP.
1928 "AArch64 CPUs must have both VFP and Neon or neither");
1932 if (cpu
->has_vfp_d32
!= cpu
->has_neon
) {
1933 error_setg(errp
, "ARM CPUs must have both VFP-D32 and Neon or neither");
1937 if (!cpu
->has_vfp_d32
) {
1940 u
= cpu
->isar
.mvfr0
;
1941 u
= FIELD_DP32(u
, MVFR0
, SIMDREG
, 1); /* 16 registers */
1942 cpu
->isar
.mvfr0
= u
;
1945 if (!cpu
->has_vfp
) {
1949 t
= cpu
->isar
.id_aa64isar1
;
1950 t
= FIELD_DP64(t
, ID_AA64ISAR1
, JSCVT
, 0);
1951 cpu
->isar
.id_aa64isar1
= t
;
1953 t
= cpu
->isar
.id_aa64pfr0
;
1954 t
= FIELD_DP64(t
, ID_AA64PFR0
, FP
, 0xf);
1955 cpu
->isar
.id_aa64pfr0
= t
;
1957 u
= cpu
->isar
.id_isar6
;
1958 u
= FIELD_DP32(u
, ID_ISAR6
, JSCVT
, 0);
1959 u
= FIELD_DP32(u
, ID_ISAR6
, BF16
, 0);
1960 cpu
->isar
.id_isar6
= u
;
1962 u
= cpu
->isar
.mvfr0
;
1963 u
= FIELD_DP32(u
, MVFR0
, FPSP
, 0);
1964 u
= FIELD_DP32(u
, MVFR0
, FPDP
, 0);
1965 u
= FIELD_DP32(u
, MVFR0
, FPDIVIDE
, 0);
1966 u
= FIELD_DP32(u
, MVFR0
, FPSQRT
, 0);
1967 u
= FIELD_DP32(u
, MVFR0
, FPROUND
, 0);
1968 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1969 u
= FIELD_DP32(u
, MVFR0
, FPTRAP
, 0);
1970 u
= FIELD_DP32(u
, MVFR0
, FPSHVEC
, 0);
1972 cpu
->isar
.mvfr0
= u
;
1974 u
= cpu
->isar
.mvfr1
;
1975 u
= FIELD_DP32(u
, MVFR1
, FPFTZ
, 0);
1976 u
= FIELD_DP32(u
, MVFR1
, FPDNAN
, 0);
1977 u
= FIELD_DP32(u
, MVFR1
, FPHP
, 0);
1978 if (arm_feature(env
, ARM_FEATURE_M
)) {
1979 u
= FIELD_DP32(u
, MVFR1
, FP16
, 0);
1981 cpu
->isar
.mvfr1
= u
;
1983 u
= cpu
->isar
.mvfr2
;
1984 u
= FIELD_DP32(u
, MVFR2
, FPMISC
, 0);
1985 cpu
->isar
.mvfr2
= u
;
1988 if (!cpu
->has_neon
) {
1992 unset_feature(env
, ARM_FEATURE_NEON
);
1994 t
= cpu
->isar
.id_aa64isar0
;
1995 t
= FIELD_DP64(t
, ID_AA64ISAR0
, AES
, 0);
1996 t
= FIELD_DP64(t
, ID_AA64ISAR0
, SHA1
, 0);
1997 t
= FIELD_DP64(t
, ID_AA64ISAR0
, SHA2
, 0);
1998 t
= FIELD_DP64(t
, ID_AA64ISAR0
, SHA3
, 0);
1999 t
= FIELD_DP64(t
, ID_AA64ISAR0
, SM3
, 0);
2000 t
= FIELD_DP64(t
, ID_AA64ISAR0
, SM4
, 0);
2001 t
= FIELD_DP64(t
, ID_AA64ISAR0
, DP
, 0);
2002 cpu
->isar
.id_aa64isar0
= t
;
2004 t
= cpu
->isar
.id_aa64isar1
;
2005 t
= FIELD_DP64(t
, ID_AA64ISAR1
, FCMA
, 0);
2006 t
= FIELD_DP64(t
, ID_AA64ISAR1
, BF16
, 0);
2007 t
= FIELD_DP64(t
, ID_AA64ISAR1
, I8MM
, 0);
2008 cpu
->isar
.id_aa64isar1
= t
;
2010 t
= cpu
->isar
.id_aa64pfr0
;
2011 t
= FIELD_DP64(t
, ID_AA64PFR0
, ADVSIMD
, 0xf);
2012 cpu
->isar
.id_aa64pfr0
= t
;
2014 u
= cpu
->isar
.id_isar5
;
2015 u
= FIELD_DP32(u
, ID_ISAR5
, AES
, 0);
2016 u
= FIELD_DP32(u
, ID_ISAR5
, SHA1
, 0);
2017 u
= FIELD_DP32(u
, ID_ISAR5
, SHA2
, 0);
2018 u
= FIELD_DP32(u
, ID_ISAR5
, RDM
, 0);
2019 u
= FIELD_DP32(u
, ID_ISAR5
, VCMA
, 0);
2020 cpu
->isar
.id_isar5
= u
;
2022 u
= cpu
->isar
.id_isar6
;
2023 u
= FIELD_DP32(u
, ID_ISAR6
, DP
, 0);
2024 u
= FIELD_DP32(u
, ID_ISAR6
, FHM
, 0);
2025 u
= FIELD_DP32(u
, ID_ISAR6
, BF16
, 0);
2026 u
= FIELD_DP32(u
, ID_ISAR6
, I8MM
, 0);
2027 cpu
->isar
.id_isar6
= u
;
2029 if (!arm_feature(env
, ARM_FEATURE_M
)) {
2030 u
= cpu
->isar
.mvfr1
;
2031 u
= FIELD_DP32(u
, MVFR1
, SIMDLS
, 0);
2032 u
= FIELD_DP32(u
, MVFR1
, SIMDINT
, 0);
2033 u
= FIELD_DP32(u
, MVFR1
, SIMDSP
, 0);
2034 u
= FIELD_DP32(u
, MVFR1
, SIMDHP
, 0);
2035 cpu
->isar
.mvfr1
= u
;
2037 u
= cpu
->isar
.mvfr2
;
2038 u
= FIELD_DP32(u
, MVFR2
, SIMDMISC
, 0);
2039 cpu
->isar
.mvfr2
= u
;
2043 if (!cpu
->has_neon
&& !cpu
->has_vfp
) {
2047 t
= cpu
->isar
.id_aa64isar0
;
2048 t
= FIELD_DP64(t
, ID_AA64ISAR0
, FHM
, 0);
2049 cpu
->isar
.id_aa64isar0
= t
;
2051 t
= cpu
->isar
.id_aa64isar1
;
2052 t
= FIELD_DP64(t
, ID_AA64ISAR1
, FRINTTS
, 0);
2053 cpu
->isar
.id_aa64isar1
= t
;
2055 u
= cpu
->isar
.mvfr0
;
2056 u
= FIELD_DP32(u
, MVFR0
, SIMDREG
, 0);
2057 cpu
->isar
.mvfr0
= u
;
2059 /* Despite the name, this field covers both VFP and Neon */
2060 u
= cpu
->isar
.mvfr1
;
2061 u
= FIELD_DP32(u
, MVFR1
, SIMDFMAC
, 0);
2062 cpu
->isar
.mvfr1
= u
;
2065 if (arm_feature(env
, ARM_FEATURE_M
) && !cpu
->has_dsp
) {
2068 unset_feature(env
, ARM_FEATURE_THUMB_DSP
);
2070 u
= cpu
->isar
.id_isar1
;
2071 u
= FIELD_DP32(u
, ID_ISAR1
, EXTEND
, 1);
2072 cpu
->isar
.id_isar1
= u
;
2074 u
= cpu
->isar
.id_isar2
;
2075 u
= FIELD_DP32(u
, ID_ISAR2
, MULTU
, 1);
2076 u
= FIELD_DP32(u
, ID_ISAR2
, MULTS
, 1);
2077 cpu
->isar
.id_isar2
= u
;
2079 u
= cpu
->isar
.id_isar3
;
2080 u
= FIELD_DP32(u
, ID_ISAR3
, SIMD
, 1);
2081 u
= FIELD_DP32(u
, ID_ISAR3
, SATURATE
, 0);
2082 cpu
->isar
.id_isar3
= u
;
2087 * We rely on no XScale CPU having VFP so we can use the same bits in the
2088 * TB flags field for VECSTRIDE and XSCALE_CPAR.
2090 assert(arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
) ||
2091 !cpu_isar_feature(aa32_vfp_simd
, cpu
) ||
2092 !arm_feature(env
, ARM_FEATURE_XSCALE
));
2094 if (arm_feature(env
, ARM_FEATURE_V7
) &&
2095 !arm_feature(env
, ARM_FEATURE_M
) &&
2096 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
2097 /* v7VMSA drops support for the old ARMv5 tiny pages, so we
2102 /* For CPUs which might have tiny 1K pages, or which have an
2103 * MPU and might have small region sizes, stick with 1K pages.
2107 if (!set_preferred_target_page_bits(pagebits
)) {
2108 /* This can only ever happen for hotplugging a CPU, or if
2109 * the board code incorrectly creates a CPU which it has
2110 * promised via minimum_page_size that it will not.
2112 error_setg(errp
, "This CPU requires a smaller page size than the "
2117 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
2118 * We don't support setting cluster ID ([16..23]) (known as Aff2
2119 * in later ARM ARM versions), or any of the higher affinity level fields,
2120 * so these bits always RAZ.
2122 if (cpu
->mp_affinity
== ARM64_AFFINITY_INVALID
) {
2123 cpu
->mp_affinity
= arm_build_mp_affinity(cs
->cpu_index
,
2124 ARM_DEFAULT_CPUS_PER_CLUSTER
);
2127 if (cpu
->reset_hivecs
) {
2128 cpu
->reset_sctlr
|= (1 << 13);
2132 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
2133 cpu
->reset_sctlr
|= SCTLR_EE
;
2135 cpu
->reset_sctlr
|= SCTLR_B
;
2139 if (!arm_feature(env
, ARM_FEATURE_M
) && !cpu
->has_el3
) {
2140 /* If the has_el3 CPU property is disabled then we need to disable the
2143 unset_feature(env
, ARM_FEATURE_EL3
);
2146 * Disable the security extension feature bits in the processor
2147 * feature registers as well.
2149 cpu
->isar
.id_pfr1
= FIELD_DP32(cpu
->isar
.id_pfr1
, ID_PFR1
, SECURITY
, 0);
2150 cpu
->isar
.id_dfr0
= FIELD_DP32(cpu
->isar
.id_dfr0
, ID_DFR0
, COPSDBG
, 0);
2151 cpu
->isar
.id_aa64pfr0
= FIELD_DP64(cpu
->isar
.id_aa64pfr0
,
2152 ID_AA64PFR0
, EL3
, 0);
2154 /* Disable the realm management extension, which requires EL3. */
2155 cpu
->isar
.id_aa64pfr0
= FIELD_DP64(cpu
->isar
.id_aa64pfr0
,
2156 ID_AA64PFR0
, RME
, 0);
2159 if (!cpu
->has_el2
) {
2160 unset_feature(env
, ARM_FEATURE_EL2
);
2163 if (!cpu
->has_pmu
) {
2164 unset_feature(env
, ARM_FEATURE_PMU
);
2166 if (arm_feature(env
, ARM_FEATURE_PMU
)) {
2169 if (!kvm_enabled()) {
2170 arm_register_pre_el_change_hook(cpu
, &pmu_pre_el_change
, 0);
2171 arm_register_el_change_hook(cpu
, &pmu_post_el_change
, 0);
2174 #ifndef CONFIG_USER_ONLY
2175 cpu
->pmu_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, arm_pmu_timer_cb
,
2179 cpu
->isar
.id_aa64dfr0
=
2180 FIELD_DP64(cpu
->isar
.id_aa64dfr0
, ID_AA64DFR0
, PMUVER
, 0);
2181 cpu
->isar
.id_dfr0
= FIELD_DP32(cpu
->isar
.id_dfr0
, ID_DFR0
, PERFMON
, 0);
2186 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
2188 * Disable the hypervisor feature bits in the processor feature
2189 * registers if we don't have EL2.
2191 cpu
->isar
.id_aa64pfr0
= FIELD_DP64(cpu
->isar
.id_aa64pfr0
,
2192 ID_AA64PFR0
, EL2
, 0);
2193 cpu
->isar
.id_pfr1
= FIELD_DP32(cpu
->isar
.id_pfr1
,
2194 ID_PFR1
, VIRTUALIZATION
, 0);
2197 if (cpu_isar_feature(aa64_mte
, cpu
)) {
2199 * The architectural range of GM blocksize is 2-6, however qemu
2200 * doesn't support blocksize of 2 (see HELPER(ldgm)).
2202 if (tcg_enabled()) {
2203 assert(cpu
->gm_blocksize
>= 3 && cpu
->gm_blocksize
<= 6);
2206 #ifndef CONFIG_USER_ONLY
2208 * If we do not have tag-memory provided by the machine,
2209 * reduce MTE support to instructions enabled at EL0.
2210 * This matches Cortex-A710 BROADCASTMTE input being LOW.
2212 if (cpu
->tag_memory
== NULL
) {
2213 cpu
->isar
.id_aa64pfr1
=
2214 FIELD_DP64(cpu
->isar
.id_aa64pfr1
, ID_AA64PFR1
, MTE
, 1);
2219 if (tcg_enabled()) {
2221 * Don't report some architectural features in the ID registers
2222 * where TCG does not yet implement it (not even a minimal
2223 * stub version). This avoids guests falling over when they
2224 * try to access the non-existent system registers for them.
2226 /* FEAT_SPE (Statistical Profiling Extension) */
2227 cpu
->isar
.id_aa64dfr0
=
2228 FIELD_DP64(cpu
->isar
.id_aa64dfr0
, ID_AA64DFR0
, PMSVER
, 0);
2229 /* FEAT_TRBE (Trace Buffer Extension) */
2230 cpu
->isar
.id_aa64dfr0
=
2231 FIELD_DP64(cpu
->isar
.id_aa64dfr0
, ID_AA64DFR0
, TRACEBUFFER
, 0);
2232 /* FEAT_TRF (Self-hosted Trace Extension) */
2233 cpu
->isar
.id_aa64dfr0
=
2234 FIELD_DP64(cpu
->isar
.id_aa64dfr0
, ID_AA64DFR0
, TRACEFILT
, 0);
2236 FIELD_DP32(cpu
->isar
.id_dfr0
, ID_DFR0
, TRACEFILT
, 0);
2237 /* Trace Macrocell system register access */
2238 cpu
->isar
.id_aa64dfr0
=
2239 FIELD_DP64(cpu
->isar
.id_aa64dfr0
, ID_AA64DFR0
, TRACEVER
, 0);
2241 FIELD_DP32(cpu
->isar
.id_dfr0
, ID_DFR0
, COPTRC
, 0);
2242 /* Memory mapped trace */
2244 FIELD_DP32(cpu
->isar
.id_dfr0
, ID_DFR0
, MMAPTRC
, 0);
2245 /* FEAT_AMU (Activity Monitors Extension) */
2246 cpu
->isar
.id_aa64pfr0
=
2247 FIELD_DP64(cpu
->isar
.id_aa64pfr0
, ID_AA64PFR0
, AMU
, 0);
2249 FIELD_DP32(cpu
->isar
.id_pfr0
, ID_PFR0
, AMU
, 0);
2250 /* FEAT_MPAM (Memory Partitioning and Monitoring Extension) */
2251 cpu
->isar
.id_aa64pfr0
=
2252 FIELD_DP64(cpu
->isar
.id_aa64pfr0
, ID_AA64PFR0
, MPAM
, 0);
2255 /* MPU can be configured out of a PMSA CPU either by setting has-mpu
2256 * to false or by setting pmsav7-dregion to 0.
2258 if (!cpu
->has_mpu
|| cpu
->pmsav7_dregion
== 0) {
2259 cpu
->has_mpu
= false;
2260 cpu
->pmsav7_dregion
= 0;
2261 cpu
->pmsav8r_hdregion
= 0;
2264 if (arm_feature(env
, ARM_FEATURE_PMSA
) &&
2265 arm_feature(env
, ARM_FEATURE_V7
)) {
2266 uint32_t nr
= cpu
->pmsav7_dregion
;
2269 error_setg(errp
, "PMSAv7 MPU #regions invalid %" PRIu32
, nr
);
2274 if (arm_feature(env
, ARM_FEATURE_V8
)) {
2276 env
->pmsav8
.rbar
[M_REG_NS
] = g_new0(uint32_t, nr
);
2277 env
->pmsav8
.rlar
[M_REG_NS
] = g_new0(uint32_t, nr
);
2278 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
2279 env
->pmsav8
.rbar
[M_REG_S
] = g_new0(uint32_t, nr
);
2280 env
->pmsav8
.rlar
[M_REG_S
] = g_new0(uint32_t, nr
);
2283 env
->pmsav7
.drbar
= g_new0(uint32_t, nr
);
2284 env
->pmsav7
.drsr
= g_new0(uint32_t, nr
);
2285 env
->pmsav7
.dracr
= g_new0(uint32_t, nr
);
2289 if (cpu
->pmsav8r_hdregion
> 0xff) {
2290 error_setg(errp
, "PMSAv8 MPU EL2 #regions invalid %" PRIu32
,
2291 cpu
->pmsav8r_hdregion
);
2295 if (cpu
->pmsav8r_hdregion
) {
2296 env
->pmsav8
.hprbar
= g_new0(uint32_t,
2297 cpu
->pmsav8r_hdregion
);
2298 env
->pmsav8
.hprlar
= g_new0(uint32_t,
2299 cpu
->pmsav8r_hdregion
);
2303 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
2304 uint32_t nr
= cpu
->sau_sregion
;
2307 error_setg(errp
, "v8M SAU #regions invalid %" PRIu32
, nr
);
2312 env
->sau
.rbar
= g_new0(uint32_t, nr
);
2313 env
->sau
.rlar
= g_new0(uint32_t, nr
);
2317 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
2318 set_feature(env
, ARM_FEATURE_VBAR
);
2321 #ifndef CONFIG_USER_ONLY
2322 if (tcg_enabled() && cpu_isar_feature(aa64_rme
, cpu
)) {
2323 arm_register_el_change_hook(cpu
, >_rme_post_el_change
, 0);
2327 register_cp_regs_for_features(cpu
);
2328 arm_cpu_register_gdb_regs_for_features(cpu
);
2330 init_cpreg_list(cpu
);
2332 #ifndef CONFIG_USER_ONLY
2333 MachineState
*ms
= MACHINE(qdev_get_machine());
2334 unsigned int smp_cpus
= ms
->smp
.cpus
;
2335 bool has_secure
= cpu
->has_el3
|| arm_feature(env
, ARM_FEATURE_M_SECURITY
);
2338 * We must set cs->num_ases to the final value before
2339 * the first call to cpu_address_space_init.
2341 if (cpu
->tag_memory
!= NULL
) {
2342 cs
->num_ases
= 3 + has_secure
;
2344 cs
->num_ases
= 1 + has_secure
;
2348 if (!cpu
->secure_memory
) {
2349 cpu
->secure_memory
= cs
->memory
;
2351 cpu_address_space_init(cs
, ARMASIdx_S
, "cpu-secure-memory",
2352 cpu
->secure_memory
);
2355 if (cpu
->tag_memory
!= NULL
) {
2356 cpu_address_space_init(cs
, ARMASIdx_TagNS
, "cpu-tag-memory",
2359 cpu_address_space_init(cs
, ARMASIdx_TagS
, "cpu-tag-memory",
2360 cpu
->secure_tag_memory
);
2364 cpu_address_space_init(cs
, ARMASIdx_NS
, "cpu-memory", cs
->memory
);
2366 /* No core_count specified, default to smp_cpus. */
2367 if (cpu
->core_count
== -1) {
2368 cpu
->core_count
= smp_cpus
;
2372 if (tcg_enabled()) {
2373 int dcz_blocklen
= 4 << cpu
->dcz_blocksize
;
2376 * We only support DCZ blocklen that fits on one page.
2378 * Architectually this is always true. However TARGET_PAGE_SIZE
2379 * is variable and, for compatibility with -machine virt-2.7,
2380 * is only 1KiB, as an artifact of legacy ARMv5 subpage support.
2381 * But even then, while the largest architectural DCZ blocklen
2382 * is 2KiB, no cpu actually uses such a large blocklen.
2384 assert(dcz_blocklen
<= TARGET_PAGE_SIZE
);
2387 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say
2388 * both nibbles of each byte storing tag data may be written at once.
2389 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32.
2391 if (cpu_isar_feature(aa64_mte
, cpu
)) {
2392 assert(dcz_blocklen
>= 2 * TAG_GRANULE
);
2399 acc
->parent_realize(dev
, errp
);
2402 static ObjectClass
*arm_cpu_class_by_name(const char *cpu_model
)
2407 const char *cpunamestr
;
2409 cpuname
= g_strsplit(cpu_model
, ",", 1);
2410 cpunamestr
= cpuname
[0];
2411 #ifdef CONFIG_USER_ONLY
2412 /* For backwards compatibility usermode emulation allows "-cpu any",
2413 * which has the same semantics as "-cpu max".
2415 if (!strcmp(cpunamestr
, "any")) {
2419 typename
= g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr
);
2420 oc
= object_class_by_name(typename
);
2421 g_strfreev(cpuname
);
2427 static Property arm_cpu_properties
[] = {
2428 DEFINE_PROP_UINT64("midr", ARMCPU
, midr
, 0),
2429 DEFINE_PROP_UINT64("mp-affinity", ARMCPU
,
2430 mp_affinity
, ARM64_AFFINITY_INVALID
),
2431 DEFINE_PROP_INT32("node-id", ARMCPU
, node_id
, CPU_UNSET_NUMA_NODE_ID
),
2432 DEFINE_PROP_INT32("core-count", ARMCPU
, core_count
, -1),
2433 DEFINE_PROP_END_OF_LIST()
2436 static const gchar
*arm_gdb_arch_name(CPUState
*cs
)
2438 ARMCPU
*cpu
= ARM_CPU(cs
);
2439 CPUARMState
*env
= &cpu
->env
;
2441 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
2447 #ifndef CONFIG_USER_ONLY
2448 #include "hw/core/sysemu-cpu-ops.h"
2450 static const struct SysemuCPUOps arm_sysemu_ops
= {
2451 .get_phys_page_attrs_debug
= arm_cpu_get_phys_page_attrs_debug
,
2452 .asidx_from_attrs
= arm_asidx_from_attrs
,
2453 .write_elf32_note
= arm_cpu_write_elf32_note
,
2454 .write_elf64_note
= arm_cpu_write_elf64_note
,
2455 .virtio_is_big_endian
= arm_cpu_virtio_is_big_endian
,
2456 .legacy_vmsd
= &vmstate_arm_cpu
,
2461 static const struct TCGCPUOps arm_tcg_ops
= {
2462 .initialize
= arm_translate_init
,
2463 .synchronize_from_tb
= arm_cpu_synchronize_from_tb
,
2464 .debug_excp_handler
= arm_debug_excp_handler
,
2465 .restore_state_to_opc
= arm_restore_state_to_opc
,
2467 #ifdef CONFIG_USER_ONLY
2468 .record_sigsegv
= arm_cpu_record_sigsegv
,
2469 .record_sigbus
= arm_cpu_record_sigbus
,
2471 .tlb_fill
= arm_cpu_tlb_fill
,
2472 .cpu_exec_interrupt
= arm_cpu_exec_interrupt
,
2473 .do_interrupt
= arm_cpu_do_interrupt
,
2474 .do_transaction_failed
= arm_cpu_do_transaction_failed
,
2475 .do_unaligned_access
= arm_cpu_do_unaligned_access
,
2476 .adjust_watchpoint_address
= arm_adjust_watchpoint_address
,
2477 .debug_check_watchpoint
= arm_debug_check_watchpoint
,
2478 .debug_check_breakpoint
= arm_debug_check_breakpoint
,
2479 #endif /* !CONFIG_USER_ONLY */
2481 #endif /* CONFIG_TCG */
2483 static void arm_cpu_class_init(ObjectClass
*oc
, void *data
)
2485 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
2486 CPUClass
*cc
= CPU_CLASS(acc
);
2487 DeviceClass
*dc
= DEVICE_CLASS(oc
);
2488 ResettableClass
*rc
= RESETTABLE_CLASS(oc
);
2490 device_class_set_parent_realize(dc
, arm_cpu_realizefn
,
2491 &acc
->parent_realize
);
2493 device_class_set_props(dc
, arm_cpu_properties
);
2495 resettable_class_set_parent_phases(rc
, NULL
, arm_cpu_reset_hold
, NULL
,
2496 &acc
->parent_phases
);
2498 cc
->class_by_name
= arm_cpu_class_by_name
;
2499 cc
->has_work
= arm_cpu_has_work
;
2500 cc
->dump_state
= arm_cpu_dump_state
;
2501 cc
->set_pc
= arm_cpu_set_pc
;
2502 cc
->get_pc
= arm_cpu_get_pc
;
2503 cc
->gdb_read_register
= arm_cpu_gdb_read_register
;
2504 cc
->gdb_write_register
= arm_cpu_gdb_write_register
;
2505 #ifndef CONFIG_USER_ONLY
2506 cc
->sysemu_ops
= &arm_sysemu_ops
;
2508 cc
->gdb_num_core_regs
= 26;
2509 cc
->gdb_arch_name
= arm_gdb_arch_name
;
2510 cc
->gdb_get_dynamic_xml
= arm_gdb_get_dynamic_xml
;
2511 cc
->gdb_stop_before_watchpoint
= true;
2512 cc
->disas_set_info
= arm_disas_set_info
;
2515 cc
->tcg_ops
= &arm_tcg_ops
;
2516 #endif /* CONFIG_TCG */
2519 static void arm_cpu_instance_init(Object
*obj
)
2521 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(obj
);
2523 acc
->info
->initfn(obj
);
2524 arm_cpu_post_init(obj
);
2527 static void cpu_register_class_init(ObjectClass
*oc
, void *data
)
2529 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
2530 CPUClass
*cc
= CPU_CLASS(acc
);
2533 cc
->gdb_core_xml_file
= "arm-core.xml";
2536 void arm_cpu_register(const ARMCPUInfo
*info
)
2538 TypeInfo type_info
= {
2539 .parent
= TYPE_ARM_CPU
,
2540 .instance_init
= arm_cpu_instance_init
,
2541 .class_init
= info
->class_init
?: cpu_register_class_init
,
2542 .class_data
= (void *)info
,
2545 type_info
.name
= g_strdup_printf("%s-" TYPE_ARM_CPU
, info
->name
);
2546 type_register(&type_info
);
2547 g_free((void *)type_info
.name
);
2550 static const TypeInfo arm_cpu_type_info
= {
2551 .name
= TYPE_ARM_CPU
,
2553 .instance_size
= sizeof(ARMCPU
),
2554 .instance_align
= __alignof__(ARMCPU
),
2555 .instance_init
= arm_cpu_initfn
,
2556 .instance_finalize
= arm_cpu_finalizefn
,
2558 .class_size
= sizeof(ARMCPUClass
),
2559 .class_init
= arm_cpu_class_init
,
2562 static void arm_cpu_register_types(void)
2564 type_register_static(&arm_cpu_type_info
);
2567 type_init(arm_cpu_register_types
)