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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Dynamic DMA mapping support. | |
3 | * | |
563aaf06 | 4 | * This implementation is a fallback for platforms that do not support |
1da177e4 LT |
5 | * I/O TLBs (aka DMA address translation hardware). |
6 | * Copyright (C) 2000 Asit Mallick <Asit.K.Mallick@intel.com> | |
7 | * Copyright (C) 2000 Goutham Rao <goutham.rao@intel.com> | |
8 | * Copyright (C) 2000, 2003 Hewlett-Packard Co | |
9 | * David Mosberger-Tang <davidm@hpl.hp.com> | |
10 | * | |
11 | * 03/05/07 davidm Switch from PCI-DMA to generic device DMA API. | |
12 | * 00/12/13 davidm Rename to swiotlb.c and add mark_clean() to avoid | |
13 | * unnecessary i-cache flushing. | |
569c8bf5 JL |
14 | * 04/07/.. ak Better overflow handling. Assorted fixes. |
15 | * 05/09/10 linville Add support for syncing ranges, support syncing for | |
16 | * DMA_BIDIRECTIONAL mappings, miscellaneous cleanup. | |
fb05a379 | 17 | * 08/12/11 beckyb Add highmem support |
1da177e4 LT |
18 | */ |
19 | ||
20 | #include <linux/cache.h> | |
17e5ad6c | 21 | #include <linux/dma-mapping.h> |
1da177e4 | 22 | #include <linux/mm.h> |
8bc3bcc9 | 23 | #include <linux/export.h> |
1da177e4 LT |
24 | #include <linux/spinlock.h> |
25 | #include <linux/string.h> | |
0016fdee | 26 | #include <linux/swiotlb.h> |
fb05a379 | 27 | #include <linux/pfn.h> |
1da177e4 LT |
28 | #include <linux/types.h> |
29 | #include <linux/ctype.h> | |
ef9b1893 | 30 | #include <linux/highmem.h> |
5a0e3ad6 | 31 | #include <linux/gfp.h> |
84be456f | 32 | #include <linux/scatterlist.h> |
1da177e4 LT |
33 | |
34 | #include <asm/io.h> | |
1da177e4 LT |
35 | #include <asm/dma.h> |
36 | ||
37 | #include <linux/init.h> | |
38 | #include <linux/bootmem.h> | |
a8522509 | 39 | #include <linux/iommu-helper.h> |
1da177e4 | 40 | |
ce5be5a1 | 41 | #define CREATE_TRACE_POINTS |
2b2b614d ZK |
42 | #include <trace/events/swiotlb.h> |
43 | ||
1da177e4 LT |
44 | #define OFFSET(val,align) ((unsigned long) \ |
45 | ( (val) & ( (align) - 1))) | |
46 | ||
0b9afede AW |
47 | #define SLABS_PER_PAGE (1 << (PAGE_SHIFT - IO_TLB_SHIFT)) |
48 | ||
49 | /* | |
50 | * Minimum IO TLB size to bother booting with. Systems with mainly | |
51 | * 64bit capable cards will only lightly use the swiotlb. If we can't | |
52 | * allocate a contiguous 1MB, we're probably in trouble anyway. | |
53 | */ | |
54 | #define IO_TLB_MIN_SLABS ((1<<20) >> IO_TLB_SHIFT) | |
55 | ||
ae7871be | 56 | enum swiotlb_force swiotlb_force; |
1da177e4 LT |
57 | |
58 | /* | |
bfc5501f KRW |
59 | * Used to do a quick range check in swiotlb_tbl_unmap_single and |
60 | * swiotlb_tbl_sync_single_*, to see if the memory was in fact allocated by this | |
1da177e4 LT |
61 | * API. |
62 | */ | |
ff7204a7 | 63 | static phys_addr_t io_tlb_start, io_tlb_end; |
1da177e4 LT |
64 | |
65 | /* | |
b595076a | 66 | * The number of IO TLB blocks (in groups of 64) between io_tlb_start and |
1da177e4 LT |
67 | * io_tlb_end. This is command line adjustable via setup_io_tlb_npages. |
68 | */ | |
69 | static unsigned long io_tlb_nslabs; | |
70 | ||
71 | /* | |
72 | * When the IOMMU overflows we return a fallback buffer. This sets the size. | |
73 | */ | |
74 | static unsigned long io_tlb_overflow = 32*1024; | |
75 | ||
ee3f6ba8 | 76 | static phys_addr_t io_tlb_overflow_buffer; |
1da177e4 LT |
77 | |
78 | /* | |
79 | * This is a free list describing the number of free entries available from | |
80 | * each index | |
81 | */ | |
82 | static unsigned int *io_tlb_list; | |
83 | static unsigned int io_tlb_index; | |
84 | ||
85 | /* | |
86 | * We need to save away the original address corresponding to a mapped entry | |
87 | * for the sync operations. | |
88 | */ | |
8e0629c1 | 89 | #define INVALID_PHYS_ADDR (~(phys_addr_t)0) |
bc40ac66 | 90 | static phys_addr_t *io_tlb_orig_addr; |
1da177e4 LT |
91 | |
92 | /* | |
93 | * Protect the above data structures in the map and unmap calls | |
94 | */ | |
95 | static DEFINE_SPINLOCK(io_tlb_lock); | |
96 | ||
5740afdb FT |
97 | static int late_alloc; |
98 | ||
1da177e4 LT |
99 | static int __init |
100 | setup_io_tlb_npages(char *str) | |
101 | { | |
102 | if (isdigit(*str)) { | |
e8579e72 | 103 | io_tlb_nslabs = simple_strtoul(str, &str, 0); |
1da177e4 LT |
104 | /* avoid tail segment of size < IO_TLB_SEGSIZE */ |
105 | io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE); | |
106 | } | |
107 | if (*str == ',') | |
108 | ++str; | |
fff5d992 | 109 | if (!strcmp(str, "force")) { |
ae7871be | 110 | swiotlb_force = SWIOTLB_FORCE; |
fff5d992 GU |
111 | } else if (!strcmp(str, "noforce")) { |
112 | swiotlb_force = SWIOTLB_NO_FORCE; | |
113 | io_tlb_nslabs = 1; | |
114 | } | |
b18485e7 | 115 | |
c729de8f | 116 | return 0; |
1da177e4 | 117 | } |
c729de8f | 118 | early_param("swiotlb", setup_io_tlb_npages); |
1da177e4 LT |
119 | /* make io_tlb_overflow tunable too? */ |
120 | ||
f21ffe9f | 121 | unsigned long swiotlb_nr_tbl(void) |
5f98ecdb FT |
122 | { |
123 | return io_tlb_nslabs; | |
124 | } | |
f21ffe9f | 125 | EXPORT_SYMBOL_GPL(swiotlb_nr_tbl); |
c729de8f YL |
126 | |
127 | /* default to 64MB */ | |
128 | #define IO_TLB_DEFAULT_SIZE (64UL<<20) | |
129 | unsigned long swiotlb_size_or_default(void) | |
130 | { | |
131 | unsigned long size; | |
132 | ||
133 | size = io_tlb_nslabs << IO_TLB_SHIFT; | |
134 | ||
135 | return size ? size : (IO_TLB_DEFAULT_SIZE); | |
136 | } | |
137 | ||
02ca646e | 138 | /* Note that this doesn't work with highmem page */ |
70a7d3cc JF |
139 | static dma_addr_t swiotlb_virt_to_bus(struct device *hwdev, |
140 | volatile void *address) | |
e08e1f7a | 141 | { |
862d196b | 142 | return phys_to_dma(hwdev, virt_to_phys(address)); |
e08e1f7a IC |
143 | } |
144 | ||
ac2cbab2 YL |
145 | static bool no_iotlb_memory; |
146 | ||
ad32e8cb | 147 | void swiotlb_print_info(void) |
2e5b2b86 | 148 | { |
ad32e8cb | 149 | unsigned long bytes = io_tlb_nslabs << IO_TLB_SHIFT; |
ff7204a7 | 150 | unsigned char *vstart, *vend; |
2e5b2b86 | 151 | |
ac2cbab2 YL |
152 | if (no_iotlb_memory) { |
153 | pr_warn("software IO TLB: No low mem\n"); | |
154 | return; | |
155 | } | |
156 | ||
ff7204a7 | 157 | vstart = phys_to_virt(io_tlb_start); |
c40dba06 | 158 | vend = phys_to_virt(io_tlb_end); |
2e5b2b86 | 159 | |
3af684c7 | 160 | printk(KERN_INFO "software IO TLB [mem %#010llx-%#010llx] (%luMB) mapped at [%p-%p]\n", |
ff7204a7 | 161 | (unsigned long long)io_tlb_start, |
c40dba06 | 162 | (unsigned long long)io_tlb_end, |
ff7204a7 | 163 | bytes >> 20, vstart, vend - 1); |
2e5b2b86 IC |
164 | } |
165 | ||
ac2cbab2 | 166 | int __init swiotlb_init_with_tbl(char *tlb, unsigned long nslabs, int verbose) |
1da177e4 | 167 | { |
ee3f6ba8 | 168 | void *v_overflow_buffer; |
563aaf06 | 169 | unsigned long i, bytes; |
1da177e4 | 170 | |
abbceff7 | 171 | bytes = nslabs << IO_TLB_SHIFT; |
1da177e4 | 172 | |
abbceff7 | 173 | io_tlb_nslabs = nslabs; |
ff7204a7 AD |
174 | io_tlb_start = __pa(tlb); |
175 | io_tlb_end = io_tlb_start + bytes; | |
1da177e4 | 176 | |
ee3f6ba8 AD |
177 | /* |
178 | * Get the overflow emergency buffer | |
179 | */ | |
ad6492b8 | 180 | v_overflow_buffer = memblock_virt_alloc_low_nopanic( |
457ff1de SS |
181 | PAGE_ALIGN(io_tlb_overflow), |
182 | PAGE_SIZE); | |
ee3f6ba8 | 183 | if (!v_overflow_buffer) |
ac2cbab2 | 184 | return -ENOMEM; |
ee3f6ba8 AD |
185 | |
186 | io_tlb_overflow_buffer = __pa(v_overflow_buffer); | |
187 | ||
1da177e4 LT |
188 | /* |
189 | * Allocate and initialize the free list array. This array is used | |
190 | * to find contiguous free memory regions of size up to IO_TLB_SEGSIZE | |
191 | * between io_tlb_start and io_tlb_end. | |
192 | */ | |
457ff1de SS |
193 | io_tlb_list = memblock_virt_alloc( |
194 | PAGE_ALIGN(io_tlb_nslabs * sizeof(int)), | |
195 | PAGE_SIZE); | |
457ff1de SS |
196 | io_tlb_orig_addr = memblock_virt_alloc( |
197 | PAGE_ALIGN(io_tlb_nslabs * sizeof(phys_addr_t)), | |
198 | PAGE_SIZE); | |
8e0629c1 JB |
199 | for (i = 0; i < io_tlb_nslabs; i++) { |
200 | io_tlb_list[i] = IO_TLB_SEGSIZE - OFFSET(i, IO_TLB_SEGSIZE); | |
201 | io_tlb_orig_addr[i] = INVALID_PHYS_ADDR; | |
202 | } | |
203 | io_tlb_index = 0; | |
1da177e4 | 204 | |
ad32e8cb FT |
205 | if (verbose) |
206 | swiotlb_print_info(); | |
ac2cbab2 YL |
207 | |
208 | return 0; | |
1da177e4 LT |
209 | } |
210 | ||
abbceff7 FT |
211 | /* |
212 | * Statically reserve bounce buffer space and initialize bounce buffer data | |
213 | * structures for the software IO TLB used to implement the DMA API. | |
214 | */ | |
ac2cbab2 YL |
215 | void __init |
216 | swiotlb_init(int verbose) | |
abbceff7 | 217 | { |
c729de8f | 218 | size_t default_size = IO_TLB_DEFAULT_SIZE; |
ff7204a7 | 219 | unsigned char *vstart; |
abbceff7 FT |
220 | unsigned long bytes; |
221 | ||
222 | if (!io_tlb_nslabs) { | |
223 | io_tlb_nslabs = (default_size >> IO_TLB_SHIFT); | |
224 | io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE); | |
225 | } | |
226 | ||
227 | bytes = io_tlb_nslabs << IO_TLB_SHIFT; | |
228 | ||
ac2cbab2 | 229 | /* Get IO TLB memory from the low pages */ |
ad6492b8 | 230 | vstart = memblock_virt_alloc_low_nopanic(PAGE_ALIGN(bytes), PAGE_SIZE); |
ac2cbab2 YL |
231 | if (vstart && !swiotlb_init_with_tbl(vstart, io_tlb_nslabs, verbose)) |
232 | return; | |
abbceff7 | 233 | |
ac2cbab2 | 234 | if (io_tlb_start) |
457ff1de SS |
235 | memblock_free_early(io_tlb_start, |
236 | PAGE_ALIGN(io_tlb_nslabs << IO_TLB_SHIFT)); | |
ac2cbab2 YL |
237 | pr_warn("Cannot allocate SWIOTLB buffer"); |
238 | no_iotlb_memory = true; | |
1da177e4 LT |
239 | } |
240 | ||
0b9afede AW |
241 | /* |
242 | * Systems with larger DMA zones (those that don't support ISA) can | |
243 | * initialize the swiotlb later using the slab allocator if needed. | |
244 | * This should be just like above, but with some error catching. | |
245 | */ | |
246 | int | |
563aaf06 | 247 | swiotlb_late_init_with_default_size(size_t default_size) |
0b9afede | 248 | { |
74838b75 | 249 | unsigned long bytes, req_nslabs = io_tlb_nslabs; |
ff7204a7 | 250 | unsigned char *vstart = NULL; |
0b9afede | 251 | unsigned int order; |
74838b75 | 252 | int rc = 0; |
0b9afede AW |
253 | |
254 | if (!io_tlb_nslabs) { | |
255 | io_tlb_nslabs = (default_size >> IO_TLB_SHIFT); | |
256 | io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE); | |
257 | } | |
258 | ||
259 | /* | |
260 | * Get IO TLB memory from the low pages | |
261 | */ | |
563aaf06 | 262 | order = get_order(io_tlb_nslabs << IO_TLB_SHIFT); |
0b9afede | 263 | io_tlb_nslabs = SLABS_PER_PAGE << order; |
563aaf06 | 264 | bytes = io_tlb_nslabs << IO_TLB_SHIFT; |
0b9afede AW |
265 | |
266 | while ((SLABS_PER_PAGE << order) > IO_TLB_MIN_SLABS) { | |
ff7204a7 AD |
267 | vstart = (void *)__get_free_pages(GFP_DMA | __GFP_NOWARN, |
268 | order); | |
269 | if (vstart) | |
0b9afede AW |
270 | break; |
271 | order--; | |
272 | } | |
273 | ||
ff7204a7 | 274 | if (!vstart) { |
74838b75 KRW |
275 | io_tlb_nslabs = req_nslabs; |
276 | return -ENOMEM; | |
277 | } | |
563aaf06 | 278 | if (order != get_order(bytes)) { |
0b9afede AW |
279 | printk(KERN_WARNING "Warning: only able to allocate %ld MB " |
280 | "for software IO TLB\n", (PAGE_SIZE << order) >> 20); | |
281 | io_tlb_nslabs = SLABS_PER_PAGE << order; | |
282 | } | |
ff7204a7 | 283 | rc = swiotlb_late_init_with_tbl(vstart, io_tlb_nslabs); |
74838b75 | 284 | if (rc) |
ff7204a7 | 285 | free_pages((unsigned long)vstart, order); |
74838b75 KRW |
286 | return rc; |
287 | } | |
288 | ||
289 | int | |
290 | swiotlb_late_init_with_tbl(char *tlb, unsigned long nslabs) | |
291 | { | |
292 | unsigned long i, bytes; | |
ee3f6ba8 | 293 | unsigned char *v_overflow_buffer; |
74838b75 KRW |
294 | |
295 | bytes = nslabs << IO_TLB_SHIFT; | |
296 | ||
297 | io_tlb_nslabs = nslabs; | |
ff7204a7 AD |
298 | io_tlb_start = virt_to_phys(tlb); |
299 | io_tlb_end = io_tlb_start + bytes; | |
74838b75 | 300 | |
ff7204a7 | 301 | memset(tlb, 0, bytes); |
0b9afede | 302 | |
ee3f6ba8 AD |
303 | /* |
304 | * Get the overflow emergency buffer | |
305 | */ | |
306 | v_overflow_buffer = (void *)__get_free_pages(GFP_DMA, | |
307 | get_order(io_tlb_overflow)); | |
308 | if (!v_overflow_buffer) | |
309 | goto cleanup2; | |
310 | ||
311 | io_tlb_overflow_buffer = virt_to_phys(v_overflow_buffer); | |
312 | ||
0b9afede AW |
313 | /* |
314 | * Allocate and initialize the free list array. This array is used | |
315 | * to find contiguous free memory regions of size up to IO_TLB_SEGSIZE | |
316 | * between io_tlb_start and io_tlb_end. | |
317 | */ | |
318 | io_tlb_list = (unsigned int *)__get_free_pages(GFP_KERNEL, | |
319 | get_order(io_tlb_nslabs * sizeof(int))); | |
320 | if (!io_tlb_list) | |
ee3f6ba8 | 321 | goto cleanup3; |
0b9afede | 322 | |
bc40ac66 BB |
323 | io_tlb_orig_addr = (phys_addr_t *) |
324 | __get_free_pages(GFP_KERNEL, | |
325 | get_order(io_tlb_nslabs * | |
326 | sizeof(phys_addr_t))); | |
0b9afede | 327 | if (!io_tlb_orig_addr) |
ee3f6ba8 | 328 | goto cleanup4; |
0b9afede | 329 | |
8e0629c1 JB |
330 | for (i = 0; i < io_tlb_nslabs; i++) { |
331 | io_tlb_list[i] = IO_TLB_SEGSIZE - OFFSET(i, IO_TLB_SEGSIZE); | |
332 | io_tlb_orig_addr[i] = INVALID_PHYS_ADDR; | |
333 | } | |
334 | io_tlb_index = 0; | |
0b9afede | 335 | |
ad32e8cb | 336 | swiotlb_print_info(); |
0b9afede | 337 | |
5740afdb FT |
338 | late_alloc = 1; |
339 | ||
0b9afede AW |
340 | return 0; |
341 | ||
342 | cleanup4: | |
25667d67 TL |
343 | free_pages((unsigned long)io_tlb_list, get_order(io_tlb_nslabs * |
344 | sizeof(int))); | |
0b9afede | 345 | io_tlb_list = NULL; |
ee3f6ba8 AD |
346 | cleanup3: |
347 | free_pages((unsigned long)v_overflow_buffer, | |
348 | get_order(io_tlb_overflow)); | |
349 | io_tlb_overflow_buffer = 0; | |
0b9afede | 350 | cleanup2: |
c40dba06 | 351 | io_tlb_end = 0; |
ff7204a7 | 352 | io_tlb_start = 0; |
74838b75 | 353 | io_tlb_nslabs = 0; |
0b9afede AW |
354 | return -ENOMEM; |
355 | } | |
356 | ||
5740afdb FT |
357 | void __init swiotlb_free(void) |
358 | { | |
ee3f6ba8 | 359 | if (!io_tlb_orig_addr) |
5740afdb FT |
360 | return; |
361 | ||
362 | if (late_alloc) { | |
ee3f6ba8 | 363 | free_pages((unsigned long)phys_to_virt(io_tlb_overflow_buffer), |
5740afdb FT |
364 | get_order(io_tlb_overflow)); |
365 | free_pages((unsigned long)io_tlb_orig_addr, | |
366 | get_order(io_tlb_nslabs * sizeof(phys_addr_t))); | |
367 | free_pages((unsigned long)io_tlb_list, get_order(io_tlb_nslabs * | |
368 | sizeof(int))); | |
ff7204a7 | 369 | free_pages((unsigned long)phys_to_virt(io_tlb_start), |
5740afdb FT |
370 | get_order(io_tlb_nslabs << IO_TLB_SHIFT)); |
371 | } else { | |
457ff1de SS |
372 | memblock_free_late(io_tlb_overflow_buffer, |
373 | PAGE_ALIGN(io_tlb_overflow)); | |
374 | memblock_free_late(__pa(io_tlb_orig_addr), | |
375 | PAGE_ALIGN(io_tlb_nslabs * sizeof(phys_addr_t))); | |
376 | memblock_free_late(__pa(io_tlb_list), | |
377 | PAGE_ALIGN(io_tlb_nslabs * sizeof(int))); | |
378 | memblock_free_late(io_tlb_start, | |
379 | PAGE_ALIGN(io_tlb_nslabs << IO_TLB_SHIFT)); | |
5740afdb | 380 | } |
f21ffe9f | 381 | io_tlb_nslabs = 0; |
5740afdb FT |
382 | } |
383 | ||
9c5a3621 | 384 | int is_swiotlb_buffer(phys_addr_t paddr) |
640aebfe | 385 | { |
ff7204a7 | 386 | return paddr >= io_tlb_start && paddr < io_tlb_end; |
640aebfe FT |
387 | } |
388 | ||
fb05a379 BB |
389 | /* |
390 | * Bounce: copy the swiotlb buffer back to the original dma location | |
391 | */ | |
af51a9f1 AD |
392 | static void swiotlb_bounce(phys_addr_t orig_addr, phys_addr_t tlb_addr, |
393 | size_t size, enum dma_data_direction dir) | |
fb05a379 | 394 | { |
af51a9f1 AD |
395 | unsigned long pfn = PFN_DOWN(orig_addr); |
396 | unsigned char *vaddr = phys_to_virt(tlb_addr); | |
fb05a379 BB |
397 | |
398 | if (PageHighMem(pfn_to_page(pfn))) { | |
399 | /* The buffer does not have a mapping. Map it in and copy */ | |
af51a9f1 | 400 | unsigned int offset = orig_addr & ~PAGE_MASK; |
fb05a379 BB |
401 | char *buffer; |
402 | unsigned int sz = 0; | |
403 | unsigned long flags; | |
404 | ||
405 | while (size) { | |
67131ad0 | 406 | sz = min_t(size_t, PAGE_SIZE - offset, size); |
fb05a379 BB |
407 | |
408 | local_irq_save(flags); | |
c3eede8e | 409 | buffer = kmap_atomic(pfn_to_page(pfn)); |
fb05a379 | 410 | if (dir == DMA_TO_DEVICE) |
af51a9f1 | 411 | memcpy(vaddr, buffer + offset, sz); |
ef9b1893 | 412 | else |
af51a9f1 | 413 | memcpy(buffer + offset, vaddr, sz); |
c3eede8e | 414 | kunmap_atomic(buffer); |
ef9b1893 | 415 | local_irq_restore(flags); |
fb05a379 BB |
416 | |
417 | size -= sz; | |
418 | pfn++; | |
af51a9f1 | 419 | vaddr += sz; |
fb05a379 | 420 | offset = 0; |
ef9b1893 | 421 | } |
af51a9f1 AD |
422 | } else if (dir == DMA_TO_DEVICE) { |
423 | memcpy(vaddr, phys_to_virt(orig_addr), size); | |
ef9b1893 | 424 | } else { |
af51a9f1 | 425 | memcpy(phys_to_virt(orig_addr), vaddr, size); |
ef9b1893 | 426 | } |
1b548f66 JF |
427 | } |
428 | ||
e05ed4d1 AD |
429 | phys_addr_t swiotlb_tbl_map_single(struct device *hwdev, |
430 | dma_addr_t tbl_dma_addr, | |
431 | phys_addr_t orig_addr, size_t size, | |
0443fa00 AD |
432 | enum dma_data_direction dir, |
433 | unsigned long attrs) | |
1da177e4 LT |
434 | { |
435 | unsigned long flags; | |
e05ed4d1 | 436 | phys_addr_t tlb_addr; |
1da177e4 LT |
437 | unsigned int nslots, stride, index, wrap; |
438 | int i; | |
681cc5cd FT |
439 | unsigned long mask; |
440 | unsigned long offset_slots; | |
441 | unsigned long max_slots; | |
442 | ||
ac2cbab2 YL |
443 | if (no_iotlb_memory) |
444 | panic("Can not allocate SWIOTLB buffer earlier and can't now provide you with the DMA bounce buffer"); | |
445 | ||
681cc5cd | 446 | mask = dma_get_seg_boundary(hwdev); |
681cc5cd | 447 | |
eb605a57 FT |
448 | tbl_dma_addr &= mask; |
449 | ||
450 | offset_slots = ALIGN(tbl_dma_addr, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT; | |
a5ddde4a IC |
451 | |
452 | /* | |
453 | * Carefully handle integer overflow which can occur when mask == ~0UL. | |
454 | */ | |
b15a3891 JB |
455 | max_slots = mask + 1 |
456 | ? ALIGN(mask + 1, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT | |
457 | : 1UL << (BITS_PER_LONG - IO_TLB_SHIFT); | |
1da177e4 LT |
458 | |
459 | /* | |
460 | * For mappings greater than a page, we limit the stride (and | |
461 | * hence alignment) to a page size. | |
462 | */ | |
463 | nslots = ALIGN(size, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT; | |
464 | if (size > PAGE_SIZE) | |
465 | stride = (1 << (PAGE_SHIFT - IO_TLB_SHIFT)); | |
466 | else | |
467 | stride = 1; | |
468 | ||
34814545 | 469 | BUG_ON(!nslots); |
1da177e4 LT |
470 | |
471 | /* | |
472 | * Find suitable number of IO TLB entries size that will fit this | |
473 | * request and allocate a buffer from that IO TLB pool. | |
474 | */ | |
475 | spin_lock_irqsave(&io_tlb_lock, flags); | |
a7133a15 AM |
476 | index = ALIGN(io_tlb_index, stride); |
477 | if (index >= io_tlb_nslabs) | |
478 | index = 0; | |
479 | wrap = index; | |
480 | ||
481 | do { | |
a8522509 FT |
482 | while (iommu_is_span_boundary(index, nslots, offset_slots, |
483 | max_slots)) { | |
b15a3891 JB |
484 | index += stride; |
485 | if (index >= io_tlb_nslabs) | |
486 | index = 0; | |
a7133a15 AM |
487 | if (index == wrap) |
488 | goto not_found; | |
489 | } | |
490 | ||
491 | /* | |
492 | * If we find a slot that indicates we have 'nslots' number of | |
493 | * contiguous buffers, we allocate the buffers from that slot | |
494 | * and mark the entries as '0' indicating unavailable. | |
495 | */ | |
496 | if (io_tlb_list[index] >= nslots) { | |
497 | int count = 0; | |
498 | ||
499 | for (i = index; i < (int) (index + nslots); i++) | |
500 | io_tlb_list[i] = 0; | |
501 | for (i = index - 1; (OFFSET(i, IO_TLB_SEGSIZE) != IO_TLB_SEGSIZE - 1) && io_tlb_list[i]; i--) | |
502 | io_tlb_list[i] = ++count; | |
e05ed4d1 | 503 | tlb_addr = io_tlb_start + (index << IO_TLB_SHIFT); |
1da177e4 | 504 | |
a7133a15 AM |
505 | /* |
506 | * Update the indices to avoid searching in the next | |
507 | * round. | |
508 | */ | |
509 | io_tlb_index = ((index + nslots) < io_tlb_nslabs | |
510 | ? (index + nslots) : 0); | |
511 | ||
512 | goto found; | |
513 | } | |
514 | index += stride; | |
515 | if (index >= io_tlb_nslabs) | |
516 | index = 0; | |
517 | } while (index != wrap); | |
518 | ||
519 | not_found: | |
520 | spin_unlock_irqrestore(&io_tlb_lock, flags); | |
0cb637bf KRW |
521 | if (printk_ratelimit()) |
522 | dev_warn(hwdev, "swiotlb buffer is full (sz: %zd bytes)\n", size); | |
e05ed4d1 | 523 | return SWIOTLB_MAP_ERROR; |
a7133a15 | 524 | found: |
1da177e4 LT |
525 | spin_unlock_irqrestore(&io_tlb_lock, flags); |
526 | ||
527 | /* | |
528 | * Save away the mapping from the original address to the DMA address. | |
529 | * This is needed when we sync the memory. Then we sync the buffer if | |
530 | * needed. | |
531 | */ | |
bc40ac66 | 532 | for (i = 0; i < nslots; i++) |
e05ed4d1 | 533 | io_tlb_orig_addr[index+i] = orig_addr + (i << IO_TLB_SHIFT); |
0443fa00 AD |
534 | if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC) && |
535 | (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL)) | |
af51a9f1 | 536 | swiotlb_bounce(orig_addr, tlb_addr, size, DMA_TO_DEVICE); |
1da177e4 | 537 | |
e05ed4d1 | 538 | return tlb_addr; |
1da177e4 | 539 | } |
d7ef1533 | 540 | EXPORT_SYMBOL_GPL(swiotlb_tbl_map_single); |
1da177e4 | 541 | |
eb605a57 FT |
542 | /* |
543 | * Allocates bounce buffer and returns its kernel virtual address. | |
544 | */ | |
545 | ||
023600f1 AC |
546 | static phys_addr_t |
547 | map_single(struct device *hwdev, phys_addr_t phys, size_t size, | |
0443fa00 | 548 | enum dma_data_direction dir, unsigned long attrs) |
eb605a57 | 549 | { |
fff5d992 GU |
550 | dma_addr_t start_dma_addr; |
551 | ||
552 | if (swiotlb_force == SWIOTLB_NO_FORCE) { | |
553 | dev_warn_ratelimited(hwdev, "Cannot do DMA to address %pa\n", | |
554 | &phys); | |
555 | return SWIOTLB_MAP_ERROR; | |
556 | } | |
eb605a57 | 557 | |
fff5d992 | 558 | start_dma_addr = phys_to_dma(hwdev, io_tlb_start); |
0443fa00 AD |
559 | return swiotlb_tbl_map_single(hwdev, start_dma_addr, phys, size, |
560 | dir, attrs); | |
eb605a57 FT |
561 | } |
562 | ||
1da177e4 LT |
563 | /* |
564 | * dma_addr is the kernel virtual address of the bounce buffer to unmap. | |
565 | */ | |
61ca08c3 | 566 | void swiotlb_tbl_unmap_single(struct device *hwdev, phys_addr_t tlb_addr, |
0443fa00 AD |
567 | size_t size, enum dma_data_direction dir, |
568 | unsigned long attrs) | |
1da177e4 LT |
569 | { |
570 | unsigned long flags; | |
571 | int i, count, nslots = ALIGN(size, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT; | |
61ca08c3 AD |
572 | int index = (tlb_addr - io_tlb_start) >> IO_TLB_SHIFT; |
573 | phys_addr_t orig_addr = io_tlb_orig_addr[index]; | |
1da177e4 LT |
574 | |
575 | /* | |
576 | * First, sync the memory before unmapping the entry | |
577 | */ | |
8e0629c1 | 578 | if (orig_addr != INVALID_PHYS_ADDR && |
0443fa00 | 579 | !(attrs & DMA_ATTR_SKIP_CPU_SYNC) && |
8e0629c1 | 580 | ((dir == DMA_FROM_DEVICE) || (dir == DMA_BIDIRECTIONAL))) |
af51a9f1 | 581 | swiotlb_bounce(orig_addr, tlb_addr, size, DMA_FROM_DEVICE); |
1da177e4 LT |
582 | |
583 | /* | |
584 | * Return the buffer to the free list by setting the corresponding | |
af901ca1 | 585 | * entries to indicate the number of contiguous entries available. |
1da177e4 LT |
586 | * While returning the entries to the free list, we merge the entries |
587 | * with slots below and above the pool being returned. | |
588 | */ | |
589 | spin_lock_irqsave(&io_tlb_lock, flags); | |
590 | { | |
591 | count = ((index + nslots) < ALIGN(index + 1, IO_TLB_SEGSIZE) ? | |
592 | io_tlb_list[index + nslots] : 0); | |
593 | /* | |
594 | * Step 1: return the slots to the free list, merging the | |
595 | * slots with superceeding slots | |
596 | */ | |
8e0629c1 | 597 | for (i = index + nslots - 1; i >= index; i--) { |
1da177e4 | 598 | io_tlb_list[i] = ++count; |
8e0629c1 JB |
599 | io_tlb_orig_addr[i] = INVALID_PHYS_ADDR; |
600 | } | |
1da177e4 LT |
601 | /* |
602 | * Step 2: merge the returned slots with the preceding slots, | |
603 | * if available (non zero) | |
604 | */ | |
605 | for (i = index - 1; (OFFSET(i, IO_TLB_SEGSIZE) != IO_TLB_SEGSIZE -1) && io_tlb_list[i]; i--) | |
606 | io_tlb_list[i] = ++count; | |
607 | } | |
608 | spin_unlock_irqrestore(&io_tlb_lock, flags); | |
609 | } | |
d7ef1533 | 610 | EXPORT_SYMBOL_GPL(swiotlb_tbl_unmap_single); |
1da177e4 | 611 | |
fbfda893 AD |
612 | void swiotlb_tbl_sync_single(struct device *hwdev, phys_addr_t tlb_addr, |
613 | size_t size, enum dma_data_direction dir, | |
614 | enum dma_sync_target target) | |
1da177e4 | 615 | { |
fbfda893 AD |
616 | int index = (tlb_addr - io_tlb_start) >> IO_TLB_SHIFT; |
617 | phys_addr_t orig_addr = io_tlb_orig_addr[index]; | |
bc40ac66 | 618 | |
8e0629c1 JB |
619 | if (orig_addr == INVALID_PHYS_ADDR) |
620 | return; | |
fbfda893 | 621 | orig_addr += (unsigned long)tlb_addr & ((1 << IO_TLB_SHIFT) - 1); |
df336d1c | 622 | |
de69e0f0 JL |
623 | switch (target) { |
624 | case SYNC_FOR_CPU: | |
625 | if (likely(dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)) | |
af51a9f1 | 626 | swiotlb_bounce(orig_addr, tlb_addr, |
fbfda893 | 627 | size, DMA_FROM_DEVICE); |
34814545 ES |
628 | else |
629 | BUG_ON(dir != DMA_TO_DEVICE); | |
de69e0f0 JL |
630 | break; |
631 | case SYNC_FOR_DEVICE: | |
632 | if (likely(dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL)) | |
af51a9f1 | 633 | swiotlb_bounce(orig_addr, tlb_addr, |
fbfda893 | 634 | size, DMA_TO_DEVICE); |
34814545 ES |
635 | else |
636 | BUG_ON(dir != DMA_FROM_DEVICE); | |
de69e0f0 JL |
637 | break; |
638 | default: | |
1da177e4 | 639 | BUG(); |
de69e0f0 | 640 | } |
1da177e4 | 641 | } |
d7ef1533 | 642 | EXPORT_SYMBOL_GPL(swiotlb_tbl_sync_single); |
1da177e4 LT |
643 | |
644 | void * | |
645 | swiotlb_alloc_coherent(struct device *hwdev, size_t size, | |
06a54497 | 646 | dma_addr_t *dma_handle, gfp_t flags) |
1da177e4 | 647 | { |
563aaf06 | 648 | dma_addr_t dev_addr; |
1da177e4 LT |
649 | void *ret; |
650 | int order = get_order(size); | |
284901a9 | 651 | u64 dma_mask = DMA_BIT_MASK(32); |
1e74f300 FT |
652 | |
653 | if (hwdev && hwdev->coherent_dma_mask) | |
654 | dma_mask = hwdev->coherent_dma_mask; | |
1da177e4 | 655 | |
25667d67 | 656 | ret = (void *)__get_free_pages(flags, order); |
e05ed4d1 AD |
657 | if (ret) { |
658 | dev_addr = swiotlb_virt_to_bus(hwdev, ret); | |
659 | if (dev_addr + size - 1 > dma_mask) { | |
660 | /* | |
661 | * The allocated memory isn't reachable by the device. | |
662 | */ | |
663 | free_pages((unsigned long) ret, order); | |
664 | ret = NULL; | |
665 | } | |
1da177e4 LT |
666 | } |
667 | if (!ret) { | |
668 | /* | |
bfc5501f KRW |
669 | * We are either out of memory or the device can't DMA to |
670 | * GFP_DMA memory; fall back on map_single(), which | |
ceb5ac32 | 671 | * will grab memory from the lowest available address range. |
1da177e4 | 672 | */ |
0443fa00 AD |
673 | phys_addr_t paddr = map_single(hwdev, 0, size, |
674 | DMA_FROM_DEVICE, 0); | |
e05ed4d1 | 675 | if (paddr == SWIOTLB_MAP_ERROR) |
94cc81f9 | 676 | goto err_warn; |
1da177e4 | 677 | |
e05ed4d1 AD |
678 | ret = phys_to_virt(paddr); |
679 | dev_addr = phys_to_dma(hwdev, paddr); | |
1da177e4 | 680 | |
61ca08c3 AD |
681 | /* Confirm address can be DMA'd by device */ |
682 | if (dev_addr + size - 1 > dma_mask) { | |
683 | printk("hwdev DMA mask = 0x%016Lx, dev_addr = 0x%016Lx\n", | |
684 | (unsigned long long)dma_mask, | |
685 | (unsigned long long)dev_addr); | |
a2b89b59 | 686 | |
0443fa00 AD |
687 | /* |
688 | * DMA_TO_DEVICE to avoid memcpy in unmap_single. | |
689 | * The DMA_ATTR_SKIP_CPU_SYNC is optional. | |
690 | */ | |
61ca08c3 | 691 | swiotlb_tbl_unmap_single(hwdev, paddr, |
0443fa00 AD |
692 | size, DMA_TO_DEVICE, |
693 | DMA_ATTR_SKIP_CPU_SYNC); | |
94cc81f9 | 694 | goto err_warn; |
61ca08c3 | 695 | } |
1da177e4 | 696 | } |
e05ed4d1 | 697 | |
1da177e4 | 698 | *dma_handle = dev_addr; |
e05ed4d1 AD |
699 | memset(ret, 0, size); |
700 | ||
1da177e4 | 701 | return ret; |
94cc81f9 JR |
702 | |
703 | err_warn: | |
704 | pr_warn("swiotlb: coherent allocation failed for device %s size=%zu\n", | |
705 | dev_name(hwdev), size); | |
706 | dump_stack(); | |
707 | ||
708 | return NULL; | |
1da177e4 | 709 | } |
874d6a95 | 710 | EXPORT_SYMBOL(swiotlb_alloc_coherent); |
1da177e4 LT |
711 | |
712 | void | |
713 | swiotlb_free_coherent(struct device *hwdev, size_t size, void *vaddr, | |
02ca646e | 714 | dma_addr_t dev_addr) |
1da177e4 | 715 | { |
862d196b | 716 | phys_addr_t paddr = dma_to_phys(hwdev, dev_addr); |
02ca646e | 717 | |
aa24886e | 718 | WARN_ON(irqs_disabled()); |
02ca646e FT |
719 | if (!is_swiotlb_buffer(paddr)) |
720 | free_pages((unsigned long)vaddr, get_order(size)); | |
1da177e4 | 721 | else |
0443fa00 AD |
722 | /* |
723 | * DMA_TO_DEVICE to avoid memcpy in swiotlb_tbl_unmap_single. | |
724 | * DMA_ATTR_SKIP_CPU_SYNC is optional. | |
725 | */ | |
726 | swiotlb_tbl_unmap_single(hwdev, paddr, size, DMA_TO_DEVICE, | |
727 | DMA_ATTR_SKIP_CPU_SYNC); | |
1da177e4 | 728 | } |
874d6a95 | 729 | EXPORT_SYMBOL(swiotlb_free_coherent); |
1da177e4 LT |
730 | |
731 | static void | |
22d48269 KRW |
732 | swiotlb_full(struct device *dev, size_t size, enum dma_data_direction dir, |
733 | int do_panic) | |
1da177e4 | 734 | { |
fff5d992 GU |
735 | if (swiotlb_force == SWIOTLB_NO_FORCE) |
736 | return; | |
737 | ||
1da177e4 LT |
738 | /* |
739 | * Ran out of IOMMU space for this operation. This is very bad. | |
740 | * Unfortunately the drivers cannot handle this operation properly. | |
17e5ad6c | 741 | * unless they check for dma_mapping_error (most don't) |
1da177e4 LT |
742 | * When the mapping is small enough return a static buffer to limit |
743 | * the damage, or panic when the transfer is too big. | |
744 | */ | |
0d2e1898 GU |
745 | dev_err_ratelimited(dev, "DMA: Out of SW-IOMMU space for %zu bytes\n", |
746 | size); | |
1da177e4 | 747 | |
c7084b35 CD |
748 | if (size <= io_tlb_overflow || !do_panic) |
749 | return; | |
750 | ||
751 | if (dir == DMA_BIDIRECTIONAL) | |
752 | panic("DMA: Random memory could be DMA accessed\n"); | |
753 | if (dir == DMA_FROM_DEVICE) | |
754 | panic("DMA: Random memory could be DMA written\n"); | |
755 | if (dir == DMA_TO_DEVICE) | |
756 | panic("DMA: Random memory could be DMA read\n"); | |
1da177e4 LT |
757 | } |
758 | ||
759 | /* | |
760 | * Map a single buffer of the indicated size for DMA in streaming mode. The | |
17e5ad6c | 761 | * physical address to use is returned. |
1da177e4 LT |
762 | * |
763 | * Once the device is given the dma address, the device owns this memory until | |
ceb5ac32 | 764 | * either swiotlb_unmap_page or swiotlb_dma_sync_single is performed. |
1da177e4 | 765 | */ |
f98eee8e FT |
766 | dma_addr_t swiotlb_map_page(struct device *dev, struct page *page, |
767 | unsigned long offset, size_t size, | |
768 | enum dma_data_direction dir, | |
00085f1e | 769 | unsigned long attrs) |
1da177e4 | 770 | { |
e05ed4d1 | 771 | phys_addr_t map, phys = page_to_phys(page) + offset; |
862d196b | 772 | dma_addr_t dev_addr = phys_to_dma(dev, phys); |
1da177e4 | 773 | |
34814545 | 774 | BUG_ON(dir == DMA_NONE); |
1da177e4 | 775 | /* |
ceb5ac32 | 776 | * If the address happens to be in the device's DMA window, |
1da177e4 LT |
777 | * we can safely return the device addr and not worry about bounce |
778 | * buffering it. | |
779 | */ | |
ae7871be | 780 | if (dma_capable(dev, dev_addr, size) && swiotlb_force != SWIOTLB_FORCE) |
1da177e4 LT |
781 | return dev_addr; |
782 | ||
2b2b614d ZK |
783 | trace_swiotlb_bounced(dev, dev_addr, size, swiotlb_force); |
784 | ||
e05ed4d1 | 785 | /* Oh well, have to allocate and map a bounce buffer. */ |
0443fa00 | 786 | map = map_single(dev, phys, size, dir, attrs); |
e05ed4d1 | 787 | if (map == SWIOTLB_MAP_ERROR) { |
f98eee8e | 788 | swiotlb_full(dev, size, dir, 1); |
ee3f6ba8 | 789 | return phys_to_dma(dev, io_tlb_overflow_buffer); |
1da177e4 LT |
790 | } |
791 | ||
e05ed4d1 | 792 | dev_addr = phys_to_dma(dev, map); |
1da177e4 | 793 | |
e05ed4d1 | 794 | /* Ensure that the address returned is DMA'ble */ |
0443fa00 AD |
795 | if (dma_capable(dev, dev_addr, size)) |
796 | return dev_addr; | |
797 | ||
d29fa0cb AD |
798 | attrs |= DMA_ATTR_SKIP_CPU_SYNC; |
799 | swiotlb_tbl_unmap_single(dev, map, size, dir, attrs); | |
1da177e4 | 800 | |
0443fa00 | 801 | return phys_to_dma(dev, io_tlb_overflow_buffer); |
1da177e4 | 802 | } |
f98eee8e | 803 | EXPORT_SYMBOL_GPL(swiotlb_map_page); |
1da177e4 | 804 | |
1da177e4 LT |
805 | /* |
806 | * Unmap a single streaming mode DMA translation. The dma_addr and size must | |
ceb5ac32 | 807 | * match what was provided for in a previous swiotlb_map_page call. All |
1da177e4 LT |
808 | * other usages are undefined. |
809 | * | |
810 | * After this call, reads by the cpu to the buffer are guaranteed to see | |
811 | * whatever the device wrote there. | |
812 | */ | |
7fcebbd2 | 813 | static void unmap_single(struct device *hwdev, dma_addr_t dev_addr, |
0443fa00 AD |
814 | size_t size, enum dma_data_direction dir, |
815 | unsigned long attrs) | |
1da177e4 | 816 | { |
862d196b | 817 | phys_addr_t paddr = dma_to_phys(hwdev, dev_addr); |
1da177e4 | 818 | |
34814545 | 819 | BUG_ON(dir == DMA_NONE); |
7fcebbd2 | 820 | |
02ca646e | 821 | if (is_swiotlb_buffer(paddr)) { |
0443fa00 | 822 | swiotlb_tbl_unmap_single(hwdev, paddr, size, dir, attrs); |
7fcebbd2 BB |
823 | return; |
824 | } | |
825 | ||
826 | if (dir != DMA_FROM_DEVICE) | |
827 | return; | |
828 | ||
02ca646e FT |
829 | /* |
830 | * phys_to_virt doesn't work with hihgmem page but we could | |
831 | * call dma_mark_clean() with hihgmem page here. However, we | |
832 | * are fine since dma_mark_clean() is null on POWERPC. We can | |
833 | * make dma_mark_clean() take a physical address if necessary. | |
834 | */ | |
835 | dma_mark_clean(phys_to_virt(paddr), size); | |
7fcebbd2 BB |
836 | } |
837 | ||
838 | void swiotlb_unmap_page(struct device *hwdev, dma_addr_t dev_addr, | |
839 | size_t size, enum dma_data_direction dir, | |
00085f1e | 840 | unsigned long attrs) |
7fcebbd2 | 841 | { |
0443fa00 | 842 | unmap_single(hwdev, dev_addr, size, dir, attrs); |
1da177e4 | 843 | } |
f98eee8e | 844 | EXPORT_SYMBOL_GPL(swiotlb_unmap_page); |
874d6a95 | 845 | |
1da177e4 LT |
846 | /* |
847 | * Make physical memory consistent for a single streaming mode DMA translation | |
848 | * after a transfer. | |
849 | * | |
ceb5ac32 | 850 | * If you perform a swiotlb_map_page() but wish to interrogate the buffer |
17e5ad6c TL |
851 | * using the cpu, yet do not wish to teardown the dma mapping, you must |
852 | * call this function before doing so. At the next point you give the dma | |
1da177e4 LT |
853 | * address back to the card, you must first perform a |
854 | * swiotlb_dma_sync_for_device, and then the device again owns the buffer | |
855 | */ | |
be6b0267 | 856 | static void |
8270f3f1 | 857 | swiotlb_sync_single(struct device *hwdev, dma_addr_t dev_addr, |
d7ef1533 KRW |
858 | size_t size, enum dma_data_direction dir, |
859 | enum dma_sync_target target) | |
1da177e4 | 860 | { |
862d196b | 861 | phys_addr_t paddr = dma_to_phys(hwdev, dev_addr); |
1da177e4 | 862 | |
34814545 | 863 | BUG_ON(dir == DMA_NONE); |
380d6878 | 864 | |
02ca646e | 865 | if (is_swiotlb_buffer(paddr)) { |
fbfda893 | 866 | swiotlb_tbl_sync_single(hwdev, paddr, size, dir, target); |
380d6878 BB |
867 | return; |
868 | } | |
869 | ||
870 | if (dir != DMA_FROM_DEVICE) | |
871 | return; | |
872 | ||
02ca646e | 873 | dma_mark_clean(phys_to_virt(paddr), size); |
1da177e4 LT |
874 | } |
875 | ||
8270f3f1 JL |
876 | void |
877 | swiotlb_sync_single_for_cpu(struct device *hwdev, dma_addr_t dev_addr, | |
160c1d8e | 878 | size_t size, enum dma_data_direction dir) |
8270f3f1 | 879 | { |
de69e0f0 | 880 | swiotlb_sync_single(hwdev, dev_addr, size, dir, SYNC_FOR_CPU); |
8270f3f1 | 881 | } |
874d6a95 | 882 | EXPORT_SYMBOL(swiotlb_sync_single_for_cpu); |
8270f3f1 | 883 | |
1da177e4 LT |
884 | void |
885 | swiotlb_sync_single_for_device(struct device *hwdev, dma_addr_t dev_addr, | |
160c1d8e | 886 | size_t size, enum dma_data_direction dir) |
1da177e4 | 887 | { |
de69e0f0 | 888 | swiotlb_sync_single(hwdev, dev_addr, size, dir, SYNC_FOR_DEVICE); |
1da177e4 | 889 | } |
874d6a95 | 890 | EXPORT_SYMBOL(swiotlb_sync_single_for_device); |
1da177e4 LT |
891 | |
892 | /* | |
893 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
ceb5ac32 | 894 | * This is the scatter-gather version of the above swiotlb_map_page |
1da177e4 LT |
895 | * interface. Here the scatter gather list elements are each tagged with the |
896 | * appropriate dma address and length. They are obtained via | |
897 | * sg_dma_{address,length}(SG). | |
898 | * | |
899 | * NOTE: An implementation may be able to use a smaller number of | |
900 | * DMA address/length pairs than there are SG table elements. | |
901 | * (for example via virtual mapping capabilities) | |
902 | * The routine returns the number of addr/length pairs actually | |
903 | * used, at most nents. | |
904 | * | |
ceb5ac32 | 905 | * Device ownership issues as mentioned above for swiotlb_map_page are the |
1da177e4 LT |
906 | * same here. |
907 | */ | |
908 | int | |
309df0c5 | 909 | swiotlb_map_sg_attrs(struct device *hwdev, struct scatterlist *sgl, int nelems, |
00085f1e | 910 | enum dma_data_direction dir, unsigned long attrs) |
1da177e4 | 911 | { |
dbfd49fe | 912 | struct scatterlist *sg; |
1da177e4 LT |
913 | int i; |
914 | ||
34814545 | 915 | BUG_ON(dir == DMA_NONE); |
1da177e4 | 916 | |
dbfd49fe | 917 | for_each_sg(sgl, sg, nelems, i) { |
961d7d0e | 918 | phys_addr_t paddr = sg_phys(sg); |
862d196b | 919 | dma_addr_t dev_addr = phys_to_dma(hwdev, paddr); |
bc40ac66 | 920 | |
ae7871be | 921 | if (swiotlb_force == SWIOTLB_FORCE || |
b9394647 | 922 | !dma_capable(hwdev, dev_addr, sg->length)) { |
e05ed4d1 | 923 | phys_addr_t map = map_single(hwdev, sg_phys(sg), |
0443fa00 | 924 | sg->length, dir, attrs); |
e05ed4d1 | 925 | if (map == SWIOTLB_MAP_ERROR) { |
1da177e4 LT |
926 | /* Don't panic here, we expect map_sg users |
927 | to do proper error handling. */ | |
928 | swiotlb_full(hwdev, sg->length, dir, 0); | |
d29fa0cb | 929 | attrs |= DMA_ATTR_SKIP_CPU_SYNC; |
309df0c5 AK |
930 | swiotlb_unmap_sg_attrs(hwdev, sgl, i, dir, |
931 | attrs); | |
4d86ec7a | 932 | sg_dma_len(sgl) = 0; |
1da177e4 LT |
933 | return 0; |
934 | } | |
e05ed4d1 | 935 | sg->dma_address = phys_to_dma(hwdev, map); |
1da177e4 LT |
936 | } else |
937 | sg->dma_address = dev_addr; | |
4d86ec7a | 938 | sg_dma_len(sg) = sg->length; |
1da177e4 LT |
939 | } |
940 | return nelems; | |
941 | } | |
309df0c5 AK |
942 | EXPORT_SYMBOL(swiotlb_map_sg_attrs); |
943 | ||
1da177e4 LT |
944 | /* |
945 | * Unmap a set of streaming mode DMA translations. Again, cpu read rules | |
ceb5ac32 | 946 | * concerning calls here are the same as for swiotlb_unmap_page() above. |
1da177e4 LT |
947 | */ |
948 | void | |
309df0c5 | 949 | swiotlb_unmap_sg_attrs(struct device *hwdev, struct scatterlist *sgl, |
00085f1e KK |
950 | int nelems, enum dma_data_direction dir, |
951 | unsigned long attrs) | |
1da177e4 | 952 | { |
dbfd49fe | 953 | struct scatterlist *sg; |
1da177e4 LT |
954 | int i; |
955 | ||
34814545 | 956 | BUG_ON(dir == DMA_NONE); |
1da177e4 | 957 | |
7fcebbd2 | 958 | for_each_sg(sgl, sg, nelems, i) |
0443fa00 AD |
959 | unmap_single(hwdev, sg->dma_address, sg_dma_len(sg), dir, |
960 | attrs); | |
1da177e4 | 961 | } |
309df0c5 AK |
962 | EXPORT_SYMBOL(swiotlb_unmap_sg_attrs); |
963 | ||
1da177e4 LT |
964 | /* |
965 | * Make physical memory consistent for a set of streaming mode DMA translations | |
966 | * after a transfer. | |
967 | * | |
968 | * The same as swiotlb_sync_single_* but for a scatter-gather list, same rules | |
969 | * and usage. | |
970 | */ | |
be6b0267 | 971 | static void |
dbfd49fe | 972 | swiotlb_sync_sg(struct device *hwdev, struct scatterlist *sgl, |
d7ef1533 KRW |
973 | int nelems, enum dma_data_direction dir, |
974 | enum dma_sync_target target) | |
1da177e4 | 975 | { |
dbfd49fe | 976 | struct scatterlist *sg; |
1da177e4 LT |
977 | int i; |
978 | ||
380d6878 BB |
979 | for_each_sg(sgl, sg, nelems, i) |
980 | swiotlb_sync_single(hwdev, sg->dma_address, | |
4d86ec7a | 981 | sg_dma_len(sg), dir, target); |
1da177e4 LT |
982 | } |
983 | ||
8270f3f1 JL |
984 | void |
985 | swiotlb_sync_sg_for_cpu(struct device *hwdev, struct scatterlist *sg, | |
160c1d8e | 986 | int nelems, enum dma_data_direction dir) |
8270f3f1 | 987 | { |
de69e0f0 | 988 | swiotlb_sync_sg(hwdev, sg, nelems, dir, SYNC_FOR_CPU); |
8270f3f1 | 989 | } |
874d6a95 | 990 | EXPORT_SYMBOL(swiotlb_sync_sg_for_cpu); |
8270f3f1 | 991 | |
1da177e4 LT |
992 | void |
993 | swiotlb_sync_sg_for_device(struct device *hwdev, struct scatterlist *sg, | |
160c1d8e | 994 | int nelems, enum dma_data_direction dir) |
1da177e4 | 995 | { |
de69e0f0 | 996 | swiotlb_sync_sg(hwdev, sg, nelems, dir, SYNC_FOR_DEVICE); |
1da177e4 | 997 | } |
874d6a95 | 998 | EXPORT_SYMBOL(swiotlb_sync_sg_for_device); |
1da177e4 LT |
999 | |
1000 | int | |
8d8bb39b | 1001 | swiotlb_dma_mapping_error(struct device *hwdev, dma_addr_t dma_addr) |
1da177e4 | 1002 | { |
ee3f6ba8 | 1003 | return (dma_addr == phys_to_dma(hwdev, io_tlb_overflow_buffer)); |
1da177e4 | 1004 | } |
874d6a95 | 1005 | EXPORT_SYMBOL(swiotlb_dma_mapping_error); |
1da177e4 LT |
1006 | |
1007 | /* | |
17e5ad6c | 1008 | * Return whether the given device DMA address mask can be supported |
1da177e4 | 1009 | * properly. For example, if your device can only drive the low 24-bits |
17e5ad6c | 1010 | * during bus mastering, then you would pass 0x00ffffff as the mask to |
1da177e4 LT |
1011 | * this function. |
1012 | */ | |
1013 | int | |
563aaf06 | 1014 | swiotlb_dma_supported(struct device *hwdev, u64 mask) |
1da177e4 | 1015 | { |
c40dba06 | 1016 | return phys_to_dma(hwdev, io_tlb_end - 1) <= mask; |
1da177e4 | 1017 | } |
1da177e4 | 1018 | EXPORT_SYMBOL(swiotlb_dma_supported); |