x86/bugs: Rename SSBD_NO to SSB_NO

The "336996 Speculative Execution Side Channel Mitigations" from
May defines this as SSB_NO, hence lets sync-up.

Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
CVE-2018-3639 (x86)

(backported from commit 240da953fcc6a9008c92fae5b1f727ee5ed167ab)
Signed-off-by: Tyler Hicks <tyhicks@canonical.com>
Signed-off-by: Stefan Bader <stefan.bader@canonical.com>

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 6acc396bee9c2356aeed09d237d4884949640a6b..50439de62f4e10ce09af4e59807f7471f0d31b98 100644 (file)
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -69,7 +69,7 @@
 #define MSR_IA32_ARCH_CAPABILITIES     0x0000010a
 #define ARCH_CAP_RDCL_NO               (1 << 0)        /* Not susceptible to Meltdown */
 #define ARCH_CAP_IBRS_ALL              (1 << 1)        /* Enhanced IBRS support */
 #define MSR_IA32_ARCH_CAPABILITIES     0x0000010a
 #define ARCH_CAP_RDCL_NO               (1 << 0)        /* Not susceptible to Meltdown */
 #define ARCH_CAP_IBRS_ALL              (1 << 1)        /* Enhanced IBRS support */

-#define ARCH_CAP_SSBD_NO               (1 << 4)        /*
+#define ARCH_CAP_SSB_NO                        (1 << 4)        /*

                                                         * Not susceptible to Speculative Store Bypass
                                                         * attack, so no Speculative Store Bypass
                                                         * control required.
                                                         * Not susceptible to Speculative Store Bypass
                                                         * attack, so no Speculative Store Bypass
                                                         * control required.

diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 26097b952ce060d647219016c91654ecae49d4a5..33b333d03435fe663d1abbdd5007a9307ae39a52 100644 (file)
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -904,7 +904,7 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
                rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap);
 
        if (!x86_match_cpu(cpu_no_spec_store_bypass) &&
                rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap);
 
        if (!x86_match_cpu(cpu_no_spec_store_bypass) &&

-          !(ia32_cap & ARCH_CAP_SSBD_NO))
+          !(ia32_cap & ARCH_CAP_SSB_NO))

                setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS);
 
        if (x86_match_cpu(cpu_no_speculation))
                setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS);
 
        if (x86_match_cpu(cpu_no_speculation))