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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1353ebb4 | 2 | /* |
1353ebb4 JF |
3 | * Copyright (C) 1994 Linus Torvalds |
4 | * | |
5 | * Cyrix stuff, June 1998 by: | |
6 | * - Rafael R. Reilova (moved everything from head.S), | |
7 | * <rreilova@ececs.uc.edu> | |
8 | * - Channing Corn (tests & fixes), | |
9 | * - Andrew D. Balsa (code cleanup). | |
10 | */ | |
11 | #include <linux/init.h> | |
12 | #include <linux/utsname.h> | |
61dc0f55 | 13 | #include <linux/cpu.h> |
d280282b | 14 | #include <linux/module.h> |
574dcf89 TG |
15 | #include <linux/nospec.h> |
16 | #include <linux/prctl.h> | |
da285121 | 17 | |
d7a6a163 | 18 | #include <asm/spec-ctrl.h> |
da285121 | 19 | #include <asm/cmdline.h> |
91eb1b79 | 20 | #include <asm/bugs.h> |
1353ebb4 | 21 | #include <asm/processor.h> |
7ebad705 | 22 | #include <asm/processor-flags.h> |
952f07ec | 23 | #include <asm/fpu/internal.h> |
1353ebb4 | 24 | #include <asm/msr.h> |
b9cfedcd | 25 | #include <asm/vmx.h> |
1353ebb4 JF |
26 | #include <asm/paravirt.h> |
27 | #include <asm/alternative.h> | |
62a67e12 | 28 | #include <asm/pgtable.h> |
d1163651 | 29 | #include <asm/set_memory.h> |
c995efd5 | 30 | #include <asm/intel-family.h> |
05516ad8 | 31 | #include <asm/e820/api.h> |
1353ebb4 | 32 | |
da285121 | 33 | static void __init spectre_v2_select_mitigation(void); |
e63490c8 | 34 | static void __init ssb_select_mitigation(void); |
05516ad8 | 35 | static void __init l1tf_select_mitigation(void); |
da285121 | 36 | |
7011f443 JK |
37 | /* The base value of the SPEC_CTRL MSR that always has to be preserved. */ |
38 | u64 x86_spec_ctrl_base; | |
4ac9b1f9 | 39 | EXPORT_SYMBOL_GPL(x86_spec_ctrl_base); |
7011f443 | 40 | static DEFINE_MUTEX(spec_ctrl_mutex); |
296b454a | 41 | |
d0c3bedd KRW |
42 | /* |
43 | * The vendor and possibly platform specific bits which can be modified in | |
44 | * x86_spec_ctrl_base. | |
45 | */ | |
e5f984ed | 46 | static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS; |
d0c3bedd | 47 | |
c37b94dd KRW |
48 | /* |
49 | * AMD specific MSR info for Speculative Store Bypass control. | |
8fe36c9d | 50 | * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu(). |
c37b94dd KRW |
51 | */ |
52 | u64 __ro_after_init x86_amd_ls_cfg_base; | |
8fe36c9d | 53 | u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask; |
c37b94dd | 54 | |
1353ebb4 JF |
55 | void __init check_bugs(void) |
56 | { | |
57 | identify_boot_cpu(); | |
55a36b65 | 58 | |
483ec3c6 TG |
59 | /* |
60 | * identify_boot_cpu() initialized SMT support information, let the | |
61 | * core code know. | |
62 | */ | |
ade31b9e | 63 | cpu_smt_check_topology_early(); |
483ec3c6 | 64 | |
62a67e12 BP |
65 | if (!IS_ENABLED(CONFIG_SMP)) { |
66 | pr_info("CPU: "); | |
67 | print_cpu_info(&boot_cpu_data); | |
68 | } | |
69 | ||
296b454a KRW |
70 | /* |
71 | * Read the SPEC_CTRL MSR to account for reserved bits which may | |
c37b94dd KRW |
72 | * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD |
73 | * init code as it is not enumerated and depends on the family. | |
296b454a | 74 | */ |
50f9b919 | 75 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
296b454a KRW |
76 | rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
77 | ||
e5f984ed TG |
78 | /* Allow STIBP in MSR_SPEC_CTRL if supported */ |
79 | if (boot_cpu_has(X86_FEATURE_STIBP)) | |
80 | x86_spec_ctrl_mask |= SPEC_CTRL_STIBP; | |
81 | ||
da285121 DW |
82 | /* Select the proper spectre mitigation before patching alternatives */ |
83 | spectre_v2_select_mitigation(); | |
84 | ||
e63490c8 KRW |
85 | /* |
86 | * Select proper mitigation for any exposure to the Speculative Store | |
87 | * Bypass vulnerability. | |
88 | */ | |
89 | ssb_select_mitigation(); | |
90 | ||
05516ad8 AK |
91 | l1tf_select_mitigation(); |
92 | ||
62a67e12 | 93 | #ifdef CONFIG_X86_32 |
55a36b65 BP |
94 | /* |
95 | * Check whether we are able to run this kernel safely on SMP. | |
96 | * | |
97 | * - i386 is no longer supported. | |
98 | * - In order to run on anything without a TSC, we need to be | |
99 | * compiled for a i486. | |
100 | */ | |
101 | if (boot_cpu_data.x86 < 4) | |
102 | panic("Kernel requires i486+ for 'invlpg' and other features"); | |
103 | ||
bfe4bb15 MV |
104 | init_utsname()->machine[1] = |
105 | '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); | |
1353ebb4 | 106 | alternative_instructions(); |
304bceda | 107 | |
4d164092 | 108 | fpu__init_check_bugs(); |
62a67e12 BP |
109 | #else /* CONFIG_X86_64 */ |
110 | alternative_instructions(); | |
111 | ||
112 | /* | |
113 | * Make sure the first 2MB area is not mapped by huge pages | |
114 | * There are typically fixed size MTRRs in there and overlapping | |
115 | * MTRRs into large pages causes slow downs. | |
116 | * | |
117 | * Right now we don't do that with gbpages because there seems | |
118 | * very little benefit for that case. | |
119 | */ | |
120 | if (!direct_gbpages) | |
121 | set_memory_4k((unsigned long)__va(0), 1); | |
122 | #endif | |
1353ebb4 | 123 | } |
61dc0f55 | 124 | |
da285121 DW |
125 | /* The kernel command line selection */ |
126 | enum spectre_v2_mitigation_cmd { | |
127 | SPECTRE_V2_CMD_NONE, | |
128 | SPECTRE_V2_CMD_AUTO, | |
129 | SPECTRE_V2_CMD_FORCE, | |
130 | SPECTRE_V2_CMD_RETPOLINE, | |
131 | SPECTRE_V2_CMD_RETPOLINE_GENERIC, | |
132 | SPECTRE_V2_CMD_RETPOLINE_AMD, | |
133 | }; | |
134 | ||
135 | static const char *spectre_v2_strings[] = { | |
136 | [SPECTRE_V2_NONE] = "Vulnerable", | |
da285121 DW |
137 | [SPECTRE_V2_RETPOLINE_GENERIC] = "Mitigation: Full generic retpoline", |
138 | [SPECTRE_V2_RETPOLINE_AMD] = "Mitigation: Full AMD retpoline", | |
1044fde9 | 139 | [SPECTRE_V2_IBRS_ENHANCED] = "Mitigation: Enhanced IBRS", |
da285121 DW |
140 | }; |
141 | ||
142 | #undef pr_fmt | |
bbb5e08b | 143 | #define pr_fmt(fmt) "Spectre V2 : " fmt |
da285121 | 144 | |
b5e6d77d KC |
145 | static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init = |
146 | SPECTRE_V2_NONE; | |
d280282b | 147 | |
12376b62 BP |
148 | void |
149 | x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest) | |
19fff03f | 150 | { |
e5f984ed | 151 | u64 msrval, guestval, hostval = x86_spec_ctrl_base; |
12376b62 | 152 | struct thread_info *ti = current_thread_info(); |
5407b7f8 | 153 | |
50f9b919 | 154 | /* Is MSR_SPEC_CTRL implemented ? */ |
12376b62 | 155 | if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) { |
e5f984ed TG |
156 | /* |
157 | * Restrict guest_spec_ctrl to supported values. Clear the | |
158 | * modifiable bits in the host base value and or the | |
159 | * modifiable bits from the guest value. | |
160 | */ | |
161 | guestval = hostval & ~x86_spec_ctrl_mask; | |
162 | guestval |= guest_spec_ctrl & x86_spec_ctrl_mask; | |
163 | ||
12376b62 | 164 | /* SSBD controlled in MSR_SPEC_CTRL */ |
5005c716 TL |
165 | if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) || |
166 | static_cpu_has(X86_FEATURE_AMD_SSBD)) | |
e5f984ed | 167 | hostval |= ssbd_tif_to_spec_ctrl(ti->flags); |
12376b62 | 168 | |
e5f984ed TG |
169 | if (hostval != guestval) { |
170 | msrval = setguest ? guestval : hostval; | |
171 | wrmsrl(MSR_IA32_SPEC_CTRL, msrval); | |
12376b62 BP |
172 | } |
173 | } | |
1238ed31 TG |
174 | |
175 | /* | |
176 | * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update | |
177 | * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported. | |
178 | */ | |
179 | if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) && | |
180 | !static_cpu_has(X86_FEATURE_VIRT_SSBD)) | |
181 | return; | |
182 | ||
183 | /* | |
184 | * If the host has SSBD mitigation enabled, force it in the host's | |
185 | * virtual MSR value. If its not permanently enabled, evaluate | |
186 | * current's TIF_SSBD thread flag. | |
187 | */ | |
188 | if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE)) | |
189 | hostval = SPEC_CTRL_SSBD; | |
190 | else | |
191 | hostval = ssbd_tif_to_spec_ctrl(ti->flags); | |
192 | ||
193 | /* Sanitize the guest value */ | |
194 | guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD; | |
195 | ||
196 | if (hostval != guestval) { | |
197 | unsigned long tif; | |
198 | ||
199 | tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) : | |
200 | ssbd_spec_ctrl_to_tif(hostval); | |
201 | ||
202 | speculative_store_bypass_update(tif); | |
203 | } | |
19fff03f | 204 | } |
12376b62 | 205 | EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl); |
19fff03f | 206 | |
8fe36c9d | 207 | static void x86_amd_ssb_disable(void) |
c37b94dd | 208 | { |
8fe36c9d | 209 | u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask; |
c37b94dd | 210 | |
65e02bbd TL |
211 | if (boot_cpu_has(X86_FEATURE_VIRT_SSBD)) |
212 | wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD); | |
213 | else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD)) | |
c37b94dd KRW |
214 | wrmsrl(MSR_AMD64_LS_CFG, msrval); |
215 | } | |
216 | ||
d280282b | 217 | #ifdef RETPOLINE |
bb3c2578 TG |
218 | static bool spectre_v2_bad_module; |
219 | ||
d280282b AK |
220 | bool retpoline_module_ok(bool has_retpoline) |
221 | { | |
222 | if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline) | |
223 | return true; | |
224 | ||
c8b8e109 | 225 | pr_err("System may be vulnerable to spectre v2\n"); |
d280282b AK |
226 | spectre_v2_bad_module = true; |
227 | return false; | |
228 | } | |
bb3c2578 TG |
229 | |
230 | static inline const char *spectre_v2_module_string(void) | |
231 | { | |
232 | return spectre_v2_bad_module ? " - vulnerable module loaded" : ""; | |
233 | } | |
234 | #else | |
235 | static inline const char *spectre_v2_module_string(void) { return ""; } | |
d280282b | 236 | #endif |
da285121 DW |
237 | |
238 | static void __init spec2_print_if_insecure(const char *reason) | |
239 | { | |
240 | if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) | |
17c33e7c | 241 | pr_info("%s selected on command line.\n", reason); |
da285121 DW |
242 | } |
243 | ||
244 | static void __init spec2_print_if_secure(const char *reason) | |
245 | { | |
246 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) | |
17c33e7c | 247 | pr_info("%s selected on command line.\n", reason); |
da285121 DW |
248 | } |
249 | ||
da285121 DW |
250 | static inline bool match_option(const char *arg, int arglen, const char *opt) |
251 | { | |
252 | int len = strlen(opt); | |
253 | ||
254 | return len == arglen && !strncmp(arg, opt, len); | |
255 | } | |
256 | ||
17c33e7c KA |
257 | static const struct { |
258 | const char *option; | |
259 | enum spectre_v2_mitigation_cmd cmd; | |
260 | bool secure; | |
261 | } mitigation_options[] = { | |
262 | { "off", SPECTRE_V2_CMD_NONE, false }, | |
263 | { "on", SPECTRE_V2_CMD_FORCE, true }, | |
264 | { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false }, | |
265 | { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD, false }, | |
266 | { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false }, | |
267 | { "auto", SPECTRE_V2_CMD_AUTO, false }, | |
268 | }; | |
269 | ||
da285121 DW |
270 | static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) |
271 | { | |
272 | char arg[20]; | |
17c33e7c KA |
273 | int ret, i; |
274 | enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO; | |
275 | ||
276 | if (cmdline_find_option_bool(boot_command_line, "nospectre_v2")) | |
277 | return SPECTRE_V2_CMD_NONE; | |
17c33e7c | 278 | |
4e8e955a TC |
279 | ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg)); |
280 | if (ret < 0) | |
281 | return SPECTRE_V2_CMD_AUTO; | |
282 | ||
283 | for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) { | |
284 | if (!match_option(arg, ret, mitigation_options[i].option)) | |
285 | continue; | |
286 | cmd = mitigation_options[i].cmd; | |
287 | break; | |
288 | } | |
289 | ||
290 | if (i >= ARRAY_SIZE(mitigation_options)) { | |
291 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); | |
292 | return SPECTRE_V2_CMD_AUTO; | |
da285121 DW |
293 | } |
294 | ||
17c33e7c KA |
295 | if ((cmd == SPECTRE_V2_CMD_RETPOLINE || |
296 | cmd == SPECTRE_V2_CMD_RETPOLINE_AMD || | |
297 | cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) && | |
298 | !IS_ENABLED(CONFIG_RETPOLINE)) { | |
713f1b95 | 299 | pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option); |
da285121 | 300 | return SPECTRE_V2_CMD_AUTO; |
17c33e7c KA |
301 | } |
302 | ||
303 | if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD && | |
304 | boot_cpu_data.x86_vendor != X86_VENDOR_AMD) { | |
305 | pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n"); | |
306 | return SPECTRE_V2_CMD_AUTO; | |
307 | } | |
308 | ||
309 | if (mitigation_options[i].secure) | |
310 | spec2_print_if_secure(mitigation_options[i].option); | |
311 | else | |
312 | spec2_print_if_insecure(mitigation_options[i].option); | |
313 | ||
314 | return cmd; | |
da285121 DW |
315 | } |
316 | ||
7011f443 JK |
317 | static bool stibp_needed(void) |
318 | { | |
319 | if (spectre_v2_enabled == SPECTRE_V2_NONE) | |
320 | return false; | |
321 | ||
322 | if (!boot_cpu_has(X86_FEATURE_STIBP)) | |
323 | return false; | |
324 | ||
325 | return true; | |
326 | } | |
327 | ||
328 | static void update_stibp_msr(void *info) | |
329 | { | |
330 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); | |
331 | } | |
332 | ||
333 | void arch_smt_update(void) | |
334 | { | |
335 | u64 mask; | |
336 | ||
337 | if (!stibp_needed()) | |
338 | return; | |
339 | ||
340 | mutex_lock(&spec_ctrl_mutex); | |
341 | mask = x86_spec_ctrl_base; | |
342 | if (cpu_smt_control == CPU_SMT_ENABLED) | |
343 | mask |= SPEC_CTRL_STIBP; | |
344 | else | |
345 | mask &= ~SPEC_CTRL_STIBP; | |
346 | ||
347 | if (mask != x86_spec_ctrl_base) { | |
348 | pr_info("Spectre v2 cross-process SMT mitigation: %s STIBP\n", | |
349 | cpu_smt_control == CPU_SMT_ENABLED ? | |
350 | "Enabling" : "Disabling"); | |
351 | x86_spec_ctrl_base = mask; | |
352 | on_each_cpu(update_stibp_msr, NULL, 1); | |
353 | } | |
354 | mutex_unlock(&spec_ctrl_mutex); | |
355 | } | |
356 | ||
da285121 DW |
357 | static void __init spectre_v2_select_mitigation(void) |
358 | { | |
359 | enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline(); | |
360 | enum spectre_v2_mitigation mode = SPECTRE_V2_NONE; | |
361 | ||
362 | /* | |
363 | * If the CPU is not affected and the command line mode is NONE or AUTO | |
364 | * then nothing to do. | |
365 | */ | |
366 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) && | |
367 | (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO)) | |
368 | return; | |
369 | ||
370 | switch (cmd) { | |
371 | case SPECTRE_V2_CMD_NONE: | |
372 | return; | |
373 | ||
374 | case SPECTRE_V2_CMD_FORCE: | |
da285121 | 375 | case SPECTRE_V2_CMD_AUTO: |
1044fde9 SP |
376 | if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) { |
377 | mode = SPECTRE_V2_IBRS_ENHANCED; | |
378 | /* Force it so VMEXIT will restore correctly */ | |
379 | x86_spec_ctrl_base |= SPEC_CTRL_IBRS; | |
380 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); | |
381 | goto specv2_set_mode; | |
382 | } | |
d0f293e0 DL |
383 | if (IS_ENABLED(CONFIG_RETPOLINE)) |
384 | goto retpoline_auto; | |
385 | break; | |
da285121 DW |
386 | case SPECTRE_V2_CMD_RETPOLINE_AMD: |
387 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
388 | goto retpoline_amd; | |
389 | break; | |
390 | case SPECTRE_V2_CMD_RETPOLINE_GENERIC: | |
391 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
392 | goto retpoline_generic; | |
393 | break; | |
394 | case SPECTRE_V2_CMD_RETPOLINE: | |
395 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
396 | goto retpoline_auto; | |
397 | break; | |
398 | } | |
713f1b95 | 399 | pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!"); |
da285121 DW |
400 | return; |
401 | ||
402 | retpoline_auto: | |
403 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) { | |
404 | retpoline_amd: | |
405 | if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) { | |
713f1b95 | 406 | pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n"); |
da285121 DW |
407 | goto retpoline_generic; |
408 | } | |
51dd01b5 | 409 | mode = SPECTRE_V2_RETPOLINE_AMD; |
da285121 DW |
410 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD); |
411 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); | |
412 | } else { | |
413 | retpoline_generic: | |
51dd01b5 | 414 | mode = SPECTRE_V2_RETPOLINE_GENERIC; |
da285121 DW |
415 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); |
416 | } | |
417 | ||
1044fde9 | 418 | specv2_set_mode: |
da285121 DW |
419 | spectre_v2_enabled = mode; |
420 | pr_info("%s\n", spectre_v2_strings[mode]); | |
c995efd5 DW |
421 | |
422 | /* | |
14623a43 JK |
423 | * If spectre v2 protection has been enabled, unconditionally fill |
424 | * RSB during a context switch; this protects against two independent | |
425 | * issues: | |
c995efd5 | 426 | * |
14623a43 JK |
427 | * - RSB underflow (and switch to BTB) on Skylake+ |
428 | * - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs | |
c995efd5 | 429 | */ |
14623a43 JK |
430 | setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW); |
431 | pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n"); | |
bd12e896 DW |
432 | |
433 | /* Initialize Indirect Branch Prediction Barrier if supported */ | |
581abf91 DW |
434 | if (boot_cpu_has(X86_FEATURE_IBPB)) { |
435 | setup_force_cpu_cap(X86_FEATURE_USE_IBPB); | |
713f1b95 | 436 | pr_info("Spectre v2 mitigation: Enabling Indirect Branch Prediction Barrier\n"); |
bd12e896 | 437 | } |
390b99c3 DW |
438 | |
439 | /* | |
440 | * Retpoline means the kernel is safe because it has no indirect | |
1044fde9 SP |
441 | * branches. Enhanced IBRS protects firmware too, so, enable restricted |
442 | * speculation around firmware calls only when Enhanced IBRS isn't | |
443 | * supported. | |
444 | * | |
445 | * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because | |
446 | * the user might select retpoline on the kernel command line and if | |
447 | * the CPU supports Enhanced IBRS, kernel might un-intentionally not | |
448 | * enable IBRS around firmware calls. | |
390b99c3 | 449 | */ |
1044fde9 | 450 | if (boot_cpu_has(X86_FEATURE_IBRS) && mode != SPECTRE_V2_IBRS_ENHANCED) { |
390b99c3 DW |
451 | setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW); |
452 | pr_info("Enabling Restricted Speculation for firmware calls\n"); | |
453 | } | |
7011f443 JK |
454 | |
455 | /* Enable STIBP if appropriate */ | |
456 | arch_smt_update(); | |
da285121 DW |
457 | } |
458 | ||
e63490c8 KRW |
459 | #undef pr_fmt |
460 | #define pr_fmt(fmt) "Speculative Store Bypass: " fmt | |
461 | ||
b5e6d77d | 462 | static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE; |
e63490c8 KRW |
463 | |
464 | /* The kernel command line selection */ | |
465 | enum ssb_mitigation_cmd { | |
466 | SPEC_STORE_BYPASS_CMD_NONE, | |
467 | SPEC_STORE_BYPASS_CMD_AUTO, | |
468 | SPEC_STORE_BYPASS_CMD_ON, | |
574dcf89 | 469 | SPEC_STORE_BYPASS_CMD_PRCTL, |
c7416003 | 470 | SPEC_STORE_BYPASS_CMD_SECCOMP, |
e63490c8 KRW |
471 | }; |
472 | ||
473 | static const char *ssb_strings[] = { | |
474 | [SPEC_STORE_BYPASS_NONE] = "Vulnerable", | |
574dcf89 | 475 | [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled", |
c7416003 KC |
476 | [SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl", |
477 | [SPEC_STORE_BYPASS_SECCOMP] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp", | |
e63490c8 KRW |
478 | }; |
479 | ||
480 | static const struct { | |
481 | const char *option; | |
482 | enum ssb_mitigation_cmd cmd; | |
483 | } ssb_mitigation_options[] = { | |
c7416003 KC |
484 | { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */ |
485 | { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */ | |
486 | { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */ | |
487 | { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */ | |
488 | { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */ | |
e63490c8 KRW |
489 | }; |
490 | ||
491 | static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void) | |
492 | { | |
493 | enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO; | |
494 | char arg[20]; | |
495 | int ret, i; | |
496 | ||
497 | if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable")) { | |
498 | return SPEC_STORE_BYPASS_CMD_NONE; | |
499 | } else { | |
500 | ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable", | |
501 | arg, sizeof(arg)); | |
502 | if (ret < 0) | |
503 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
504 | ||
505 | for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) { | |
506 | if (!match_option(arg, ret, ssb_mitigation_options[i].option)) | |
507 | continue; | |
508 | ||
509 | cmd = ssb_mitigation_options[i].cmd; | |
510 | break; | |
511 | } | |
512 | ||
513 | if (i >= ARRAY_SIZE(ssb_mitigation_options)) { | |
514 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); | |
515 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
516 | } | |
517 | } | |
518 | ||
519 | return cmd; | |
520 | } | |
521 | ||
dbe3009d | 522 | static enum ssb_mitigation __init __ssb_select_mitigation(void) |
e63490c8 KRW |
523 | { |
524 | enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE; | |
525 | enum ssb_mitigation_cmd cmd; | |
526 | ||
8fe36c9d | 527 | if (!boot_cpu_has(X86_FEATURE_SSBD)) |
e63490c8 KRW |
528 | return mode; |
529 | ||
530 | cmd = ssb_parse_cmdline(); | |
531 | if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) && | |
532 | (cmd == SPEC_STORE_BYPASS_CMD_NONE || | |
533 | cmd == SPEC_STORE_BYPASS_CMD_AUTO)) | |
534 | return mode; | |
535 | ||
536 | switch (cmd) { | |
537 | case SPEC_STORE_BYPASS_CMD_AUTO: | |
c7416003 KC |
538 | case SPEC_STORE_BYPASS_CMD_SECCOMP: |
539 | /* | |
540 | * Choose prctl+seccomp as the default mode if seccomp is | |
541 | * enabled. | |
542 | */ | |
543 | if (IS_ENABLED(CONFIG_SECCOMP)) | |
544 | mode = SPEC_STORE_BYPASS_SECCOMP; | |
545 | else | |
546 | mode = SPEC_STORE_BYPASS_PRCTL; | |
574dcf89 | 547 | break; |
e63490c8 KRW |
548 | case SPEC_STORE_BYPASS_CMD_ON: |
549 | mode = SPEC_STORE_BYPASS_DISABLE; | |
550 | break; | |
574dcf89 TG |
551 | case SPEC_STORE_BYPASS_CMD_PRCTL: |
552 | mode = SPEC_STORE_BYPASS_PRCTL; | |
553 | break; | |
e63490c8 KRW |
554 | case SPEC_STORE_BYPASS_CMD_NONE: |
555 | break; | |
556 | } | |
557 | ||
23b9eab9 KRW |
558 | /* |
559 | * We have three CPU feature flags that are in play here: | |
560 | * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible. | |
8fe36c9d | 561 | * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass |
23b9eab9 KRW |
562 | * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation |
563 | */ | |
574dcf89 | 564 | if (mode == SPEC_STORE_BYPASS_DISABLE) { |
e63490c8 | 565 | setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE); |
23b9eab9 | 566 | /* |
3b881627 KRW |
567 | * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may |
568 | * use a completely different MSR and bit dependent on family. | |
23b9eab9 | 569 | */ |
5005c716 TL |
570 | if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) && |
571 | !static_cpu_has(X86_FEATURE_AMD_SSBD)) { | |
733c54c9 | 572 | x86_amd_ssb_disable(); |
5005c716 | 573 | } else { |
8fe36c9d | 574 | x86_spec_ctrl_base |= SPEC_CTRL_SSBD; |
e5f984ed | 575 | x86_spec_ctrl_mask |= SPEC_CTRL_SSBD; |
208efa83 | 576 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
23b9eab9 KRW |
577 | } |
578 | } | |
579 | ||
e63490c8 KRW |
580 | return mode; |
581 | } | |
582 | ||
043d480e | 583 | static void ssb_select_mitigation(void) |
e63490c8 KRW |
584 | { |
585 | ssb_mode = __ssb_select_mitigation(); | |
586 | ||
587 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
588 | pr_info("%s\n", ssb_strings[ssb_mode]); | |
589 | } | |
590 | ||
da285121 | 591 | #undef pr_fmt |
c7416003 | 592 | #define pr_fmt(fmt) "Speculation prctl: " fmt |
da285121 | 593 | |
199bfed2 | 594 | static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl) |
574dcf89 | 595 | { |
733f4234 | 596 | bool update; |
574dcf89 | 597 | |
c7416003 KC |
598 | if (ssb_mode != SPEC_STORE_BYPASS_PRCTL && |
599 | ssb_mode != SPEC_STORE_BYPASS_SECCOMP) | |
574dcf89 TG |
600 | return -ENXIO; |
601 | ||
733f4234 TG |
602 | switch (ctrl) { |
603 | case PR_SPEC_ENABLE: | |
604 | /* If speculation is force disabled, enable is not allowed */ | |
605 | if (task_spec_ssb_force_disable(task)) | |
606 | return -EPERM; | |
607 | task_clear_spec_ssb_disable(task); | |
8fe36c9d | 608 | update = test_and_clear_tsk_thread_flag(task, TIF_SSBD); |
733f4234 TG |
609 | break; |
610 | case PR_SPEC_DISABLE: | |
611 | task_set_spec_ssb_disable(task); | |
8fe36c9d | 612 | update = !test_and_set_tsk_thread_flag(task, TIF_SSBD); |
733f4234 TG |
613 | break; |
614 | case PR_SPEC_FORCE_DISABLE: | |
615 | task_set_spec_ssb_disable(task); | |
616 | task_set_spec_ssb_force_disable(task); | |
8fe36c9d | 617 | update = !test_and_set_tsk_thread_flag(task, TIF_SSBD); |
733f4234 TG |
618 | break; |
619 | default: | |
620 | return -ERANGE; | |
621 | } | |
574dcf89 | 622 | |
199bfed2 KC |
623 | /* |
624 | * If being set on non-current task, delay setting the CPU | |
625 | * mitigation until it is next scheduled. | |
626 | */ | |
733f4234 | 627 | if (task == current && update) |
8a3ba093 | 628 | speculative_store_bypass_update_current(); |
574dcf89 TG |
629 | |
630 | return 0; | |
631 | } | |
632 | ||
5b38e244 TG |
633 | int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which, |
634 | unsigned long ctrl) | |
635 | { | |
636 | switch (which) { | |
637 | case PR_SPEC_STORE_BYPASS: | |
638 | return ssb_prctl_set(task, ctrl); | |
639 | default: | |
640 | return -ENODEV; | |
641 | } | |
642 | } | |
643 | ||
644 | #ifdef CONFIG_SECCOMP | |
645 | void arch_seccomp_spec_mitigate(struct task_struct *task) | |
646 | { | |
c7416003 KC |
647 | if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP) |
648 | ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE); | |
5b38e244 TG |
649 | } |
650 | #endif | |
651 | ||
199bfed2 | 652 | static int ssb_prctl_get(struct task_struct *task) |
574dcf89 TG |
653 | { |
654 | switch (ssb_mode) { | |
655 | case SPEC_STORE_BYPASS_DISABLE: | |
656 | return PR_SPEC_DISABLE; | |
c7416003 | 657 | case SPEC_STORE_BYPASS_SECCOMP: |
574dcf89 | 658 | case SPEC_STORE_BYPASS_PRCTL: |
733f4234 TG |
659 | if (task_spec_ssb_force_disable(task)) |
660 | return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; | |
661 | if (task_spec_ssb_disable(task)) | |
574dcf89 TG |
662 | return PR_SPEC_PRCTL | PR_SPEC_DISABLE; |
663 | return PR_SPEC_PRCTL | PR_SPEC_ENABLE; | |
664 | default: | |
665 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
666 | return PR_SPEC_ENABLE; | |
667 | return PR_SPEC_NOT_AFFECTED; | |
668 | } | |
669 | } | |
670 | ||
199bfed2 | 671 | int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which) |
574dcf89 TG |
672 | { |
673 | switch (which) { | |
674 | case PR_SPEC_STORE_BYPASS: | |
199bfed2 | 675 | return ssb_prctl_get(task); |
574dcf89 TG |
676 | default: |
677 | return -ENODEV; | |
678 | } | |
679 | } | |
680 | ||
23b9eab9 KRW |
681 | void x86_spec_ctrl_setup_ap(void) |
682 | { | |
50f9b919 | 683 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
208efa83 | 684 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
c37b94dd KRW |
685 | |
686 | if (ssb_mode == SPEC_STORE_BYPASS_DISABLE) | |
8fe36c9d | 687 | x86_amd_ssb_disable(); |
23b9eab9 KRW |
688 | } |
689 | ||
73ca9f47 KRW |
690 | #undef pr_fmt |
691 | #define pr_fmt(fmt) "L1TF: " fmt | |
b9cfedcd | 692 | |
24fcb53c JK |
693 | /* Default mitigation for L1TF-affected CPUs */ |
694 | enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH; | |
b9cfedcd | 695 | #if IS_ENABLED(CONFIG_KVM_INTEL) |
24fcb53c JK |
696 | EXPORT_SYMBOL_GPL(l1tf_mitigation); |
697 | ||
522c7bed | 698 | enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO; |
b9cfedcd TG |
699 | EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation); |
700 | #endif | |
701 | ||
f1f016ed AK |
702 | /* |
703 | * These CPUs all support 44bits physical address space internally in the | |
704 | * cache but CPUID can report a smaller number of physical address bits. | |
705 | * | |
706 | * The L1TF mitigation uses the top most address bit for the inversion of | |
707 | * non present PTEs. When the installed memory reaches into the top most | |
708 | * address bit due to memory holes, which has been observed on machines | |
709 | * which report 36bits physical address bits and have 32G RAM installed, | |
710 | * then the mitigation range check in l1tf_select_mitigation() triggers. | |
711 | * This is a false positive because the mitigation is still possible due to | |
712 | * the fact that the cache uses 44bit internally. Use the cache bits | |
713 | * instead of the reported physical bits and adjust them on the affected | |
714 | * machines to 44bit if the reported bits are less than 44. | |
715 | */ | |
716 | static void override_cache_bits(struct cpuinfo_x86 *c) | |
717 | { | |
718 | if (c->x86 != 6) | |
719 | return; | |
720 | ||
721 | switch (c->x86_model) { | |
722 | case INTEL_FAM6_NEHALEM: | |
723 | case INTEL_FAM6_WESTMERE: | |
724 | case INTEL_FAM6_SANDYBRIDGE: | |
725 | case INTEL_FAM6_IVYBRIDGE: | |
726 | case INTEL_FAM6_HASWELL_CORE: | |
727 | case INTEL_FAM6_HASWELL_ULT: | |
728 | case INTEL_FAM6_HASWELL_GT3E: | |
729 | case INTEL_FAM6_BROADWELL_CORE: | |
730 | case INTEL_FAM6_BROADWELL_GT3E: | |
731 | case INTEL_FAM6_SKYLAKE_MOBILE: | |
732 | case INTEL_FAM6_SKYLAKE_DESKTOP: | |
733 | case INTEL_FAM6_KABYLAKE_MOBILE: | |
734 | case INTEL_FAM6_KABYLAKE_DESKTOP: | |
735 | if (c->x86_cache_bits < 44) | |
736 | c->x86_cache_bits = 44; | |
737 | break; | |
738 | } | |
739 | } | |
740 | ||
73ca9f47 KRW |
741 | static void __init l1tf_select_mitigation(void) |
742 | { | |
743 | u64 half_pa; | |
744 | ||
745 | if (!boot_cpu_has_bug(X86_BUG_L1TF)) | |
746 | return; | |
747 | ||
f1f016ed AK |
748 | override_cache_bits(&boot_cpu_data); |
749 | ||
24fcb53c JK |
750 | switch (l1tf_mitigation) { |
751 | case L1TF_MITIGATION_OFF: | |
752 | case L1TF_MITIGATION_FLUSH_NOWARN: | |
753 | case L1TF_MITIGATION_FLUSH: | |
754 | break; | |
755 | case L1TF_MITIGATION_FLUSH_NOSMT: | |
756 | case L1TF_MITIGATION_FULL: | |
757 | cpu_smt_disable(false); | |
758 | break; | |
759 | case L1TF_MITIGATION_FULL_FORCE: | |
760 | cpu_smt_disable(true); | |
761 | break; | |
762 | } | |
763 | ||
73ca9f47 KRW |
764 | #if CONFIG_PGTABLE_LEVELS == 2 |
765 | pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n"); | |
766 | return; | |
767 | #endif | |
768 | ||
73ca9f47 KRW |
769 | half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT; |
770 | if (e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) { | |
771 | pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n"); | |
772 | return; | |
773 | } | |
774 | ||
775 | setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV); | |
776 | } | |
24fcb53c JK |
777 | |
778 | static int __init l1tf_cmdline(char *str) | |
779 | { | |
780 | if (!boot_cpu_has_bug(X86_BUG_L1TF)) | |
781 | return 0; | |
782 | ||
783 | if (!str) | |
784 | return -EINVAL; | |
785 | ||
786 | if (!strcmp(str, "off")) | |
787 | l1tf_mitigation = L1TF_MITIGATION_OFF; | |
788 | else if (!strcmp(str, "flush,nowarn")) | |
789 | l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN; | |
790 | else if (!strcmp(str, "flush")) | |
791 | l1tf_mitigation = L1TF_MITIGATION_FLUSH; | |
792 | else if (!strcmp(str, "flush,nosmt")) | |
793 | l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT; | |
794 | else if (!strcmp(str, "full")) | |
795 | l1tf_mitigation = L1TF_MITIGATION_FULL; | |
796 | else if (!strcmp(str, "full,force")) | |
797 | l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE; | |
798 | ||
799 | return 0; | |
800 | } | |
801 | early_param("l1tf", l1tf_cmdline); | |
802 | ||
73ca9f47 KRW |
803 | #undef pr_fmt |
804 | ||
61dc0f55 | 805 | #ifdef CONFIG_SYSFS |
d2b8fc2d | 806 | |
b9cfedcd TG |
807 | #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion" |
808 | ||
809 | #if IS_ENABLED(CONFIG_KVM_INTEL) | |
810 | static const char *l1tf_vmx_states[] = { | |
1ead4979 TG |
811 | [VMENTER_L1D_FLUSH_AUTO] = "auto", |
812 | [VMENTER_L1D_FLUSH_NEVER] = "vulnerable", | |
813 | [VMENTER_L1D_FLUSH_COND] = "conditional cache flushes", | |
814 | [VMENTER_L1D_FLUSH_ALWAYS] = "cache flushes", | |
815 | [VMENTER_L1D_FLUSH_EPT_DISABLED] = "EPT disabled", | |
364a4311 | 816 | [VMENTER_L1D_FLUSH_NOT_REQUIRED] = "flush not necessary" |
b9cfedcd TG |
817 | }; |
818 | ||
819 | static ssize_t l1tf_show_state(char *buf) | |
820 | { | |
821 | if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) | |
822 | return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG); | |
823 | ||
3899f7b1 PB |
824 | if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED || |
825 | (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER && | |
826 | cpu_smt_control == CPU_SMT_ENABLED)) | |
827 | return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG, | |
828 | l1tf_vmx_states[l1tf_vmx_mitigation]); | |
829 | ||
830 | return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG, | |
831 | l1tf_vmx_states[l1tf_vmx_mitigation], | |
832 | cpu_smt_control == CPU_SMT_ENABLED ? "vulnerable" : "disabled"); | |
b9cfedcd TG |
833 | } |
834 | #else | |
835 | static ssize_t l1tf_show_state(char *buf) | |
836 | { | |
837 | return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG); | |
838 | } | |
839 | #endif | |
840 | ||
ace051d5 | 841 | static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr, |
043d480e | 842 | char *buf, unsigned int bug) |
61dc0f55 | 843 | { |
d2b8fc2d | 844 | if (!boot_cpu_has_bug(bug)) |
61dc0f55 | 845 | return sprintf(buf, "Not affected\n"); |
d2b8fc2d KRW |
846 | |
847 | switch (bug) { | |
848 | case X86_BUG_CPU_MELTDOWN: | |
849 | if (boot_cpu_has(X86_FEATURE_PTI)) | |
850 | return sprintf(buf, "Mitigation: PTI\n"); | |
851 | ||
852 | break; | |
853 | ||
854 | case X86_BUG_SPECTRE_V1: | |
855 | return sprintf(buf, "Mitigation: __user pointer sanitization\n"); | |
856 | ||
857 | case X86_BUG_SPECTRE_V2: | |
0b96b80d | 858 | return sprintf(buf, "%s%s%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled], |
d2b8fc2d KRW |
859 | boot_cpu_has(X86_FEATURE_USE_IBPB) ? ", IBPB" : "", |
860 | boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "", | |
7011f443 | 861 | (x86_spec_ctrl_base & SPEC_CTRL_STIBP) ? ", STIBP" : "", |
5e2fafd5 | 862 | boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? ", RSB filling" : "", |
d2b8fc2d KRW |
863 | spectre_v2_module_string()); |
864 | ||
e63490c8 KRW |
865 | case X86_BUG_SPEC_STORE_BYPASS: |
866 | return sprintf(buf, "%s\n", ssb_strings[ssb_mode]); | |
867 | ||
05516ad8 AK |
868 | case X86_BUG_L1TF: |
869 | if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV)) | |
b9cfedcd | 870 | return l1tf_show_state(buf); |
05516ad8 | 871 | break; |
d2b8fc2d KRW |
872 | default: |
873 | break; | |
874 | } | |
875 | ||
61dc0f55 TG |
876 | return sprintf(buf, "Vulnerable\n"); |
877 | } | |
878 | ||
d2b8fc2d KRW |
879 | ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf) |
880 | { | |
881 | return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN); | |
882 | } | |
883 | ||
713f1b95 | 884 | ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 885 | { |
d2b8fc2d | 886 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1); |
61dc0f55 TG |
887 | } |
888 | ||
713f1b95 | 889 | ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 890 | { |
d2b8fc2d | 891 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2); |
61dc0f55 | 892 | } |
d7de9182 KRW |
893 | |
894 | ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf) | |
895 | { | |
896 | return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS); | |
897 | } | |
05516ad8 AK |
898 | |
899 | ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf) | |
900 | { | |
901 | return cpu_show_common(dev, attr, buf, X86_BUG_L1TF); | |
902 | } | |
61dc0f55 | 903 | #endif |