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KVM: Avoid checking huge page mappings in get_dirty_log()
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
aec51dc4 49#include <trace/events/kvm.h>
2ed152af 50
229456fc
MT		 51#define CREATE_TRACE_POINTS
52#include "trace.h"
043405e1 53
24f1e32c 54#include <asm/debugreg.h>
d825ed0a 55#include <asm/msr.h>
a5f61300 56#include <asm/desc.h>
0bed3b56 57#include <asm/mtrr.h>
890ca9ae 58#include <asm/mce.h>
7cf30855 59#include <asm/i387.h>
1361b83a 60#include <asm/fpu-internal.h> /* Ugh! */
98918833 61#include <asm/xcr.h>
1d5f066e 62#include <asm/pvclock.h>
217fc9cf 63#include <asm/div64.h>
043405e1 64
313a3dc7 65#define MAX_IO_MSRS 256
890ca9ae 66#define KVM_MAX_MCE_BANKS 32
5854dbca 67#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 68
0f65dd70
AK		 69#define emul_to_vcpu(ctxt) \
70 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
71
50a37eb4
JR		 72/* EFER defaults:
73 * - enable syscall per default because its emulated by KVM
74 * - enable LME and LMA per default on 64 bit KVM
75 */
76#ifdef CONFIG_X86_64
1260edbe
LJ		 77static
78u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 79#else
1260edbe 80static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 81#endif
313a3dc7 82
ba1389b7
AK		 83#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
84#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 85
cb142eb7 86static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 87static void process_nmi(struct kvm_vcpu *vcpu);
674eea0f 88
97896d04 89struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 90EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 91
476bc001
RR		 92static bool ignore_msrs = 0;
93module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 94
92a1f12d
JR		 95bool kvm_has_tsc_control;
96EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
97u32 kvm_max_guest_tsc_khz;
98EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
99
cc578287
ZA		 100/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
101static u32 tsc_tolerance_ppm = 250;
102module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
103
18863bdd
AK		 104#define KVM_NR_SHARED_MSRS 16
105
106struct kvm_shared_msrs_global {
107 int nr;
2bf78fa7 108 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 109};
110
111struct kvm_shared_msrs {
112 struct user_return_notifier urn;
113 bool registered;
2bf78fa7
SY		 114 struct kvm_shared_msr_values {
115 u64 host;
116 u64 curr;
117 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 118};
119
120static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
121static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
122
417bc304 123struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 124 { "pf_fixed", VCPU_STAT(pf_fixed) },
125 { "pf_guest", VCPU_STAT(pf_guest) },
126 { "tlb_flush", VCPU_STAT(tlb_flush) },
127 { "invlpg", VCPU_STAT(invlpg) },
128 { "exits", VCPU_STAT(exits) },
129 { "io_exits", VCPU_STAT(io_exits) },
130 { "mmio_exits", VCPU_STAT(mmio_exits) },
131 { "signal_exits", VCPU_STAT(signal_exits) },
132 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 133 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 134 { "halt_exits", VCPU_STAT(halt_exits) },
135 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 136 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 137 { "request_irq", VCPU_STAT(request_irq_exits) },
138 { "irq_exits", VCPU_STAT(irq_exits) },
139 { "host_state_reload", VCPU_STAT(host_state_reload) },
140 { "efer_reload", VCPU_STAT(efer_reload) },
141 { "fpu_reload", VCPU_STAT(fpu_reload) },
142 { "insn_emulation", VCPU_STAT(insn_emulation) },
143 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 144 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 145 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 146 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
147 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
148 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
149 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
150 { "mmu_flooded", VM_STAT(mmu_flooded) },
151 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 152 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 153 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 154 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 155 { "largepages", VM_STAT(lpages) },
417bc304
HB		 156 { NULL }
157};
158
2acf923e
DC		 159u64 __read_mostly host_xcr0;
160
d6aa1000
AK		 161int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
162
af585b92
GN		 163static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
164{
165 int i;
166 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
167 vcpu->arch.apf.gfns[i] = ~0;
168}
169
18863bdd
AK		 170static void kvm_on_user_return(struct user_return_notifier *urn)
171{
172 unsigned slot;
18863bdd
AK		 173 struct kvm_shared_msrs *locals
174 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 175 struct kvm_shared_msr_values *values;
18863bdd
AK		 176
177 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 178 values = &locals->values[slot];
179 if (values->host != values->curr) {
180 wrmsrl(shared_msrs_global.msrs[slot], values->host);
181 values->curr = values->host;
18863bdd
AK		 182 }
183 }
184 locals->registered = false;
185 user_return_notifier_unregister(urn);
186}
187
2bf78fa7 188static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 189{
2bf78fa7 190 struct kvm_shared_msrs *smsr;
18863bdd
AK		 191 u64 value;
192
2bf78fa7
SY		 193 smsr = &__get_cpu_var(shared_msrs);
194 /* only read, and nobody should modify it at this time,
195 * so don't need lock */
196 if (slot >= shared_msrs_global.nr) {
197 printk(KERN_ERR "kvm: invalid MSR slot!");
198 return;
199 }
200 rdmsrl_safe(msr, &value);
201 smsr->values[slot].host = value;
202 smsr->values[slot].curr = value;
203}
204
205void kvm_define_shared_msr(unsigned slot, u32 msr)
206{
18863bdd
AK		 207 if (slot >= shared_msrs_global.nr)
208 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 209 shared_msrs_global.msrs[slot] = msr;
210 /* we need ensured the shared_msr_global have been updated */
211 smp_wmb();
18863bdd
AK		 212}
213EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
214
215static void kvm_shared_msr_cpu_online(void)
216{
217 unsigned i;
18863bdd
AK		 218
219 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 220 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 221}
222
d5696725 223void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 224{
225 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
226
2bf78fa7 227 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 228 return;
2bf78fa7
SY		 229 smsr->values[slot].curr = value;
230 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 231 if (!smsr->registered) {
232 smsr->urn.on_user_return = kvm_on_user_return;
233 user_return_notifier_register(&smsr->urn);
234 smsr->registered = true;
235 }
236}
237EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
238
3548bab5
AK		 239static void drop_user_return_notifiers(void *ignore)
240{
241 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
242
243 if (smsr->registered)
244 kvm_on_user_return(&smsr->urn);
245}
246
6866b83e
CO		 247u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
248{
249 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 250 return vcpu->arch.apic_base;
6866b83e 251 else
ad312c7c 252 return vcpu->arch.apic_base;
6866b83e
CO		 253}
254EXPORT_SYMBOL_GPL(kvm_get_apic_base);
255
256void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
257{
258 /* TODO: reserve bits check */
259 if (irqchip_in_kernel(vcpu->kvm))
260 kvm_lapic_set_base(vcpu, data);
261 else
ad312c7c 262 vcpu->arch.apic_base = data;
6866b83e
CO		 263}
264EXPORT_SYMBOL_GPL(kvm_set_apic_base);
265
3fd28fce
ED		 266#define EXCPT_BENIGN 0
267#define EXCPT_CONTRIBUTORY 1
268#define EXCPT_PF 2
269
270static int exception_class(int vector)
271{
272 switch (vector) {
273 case PF_VECTOR:
274 return EXCPT_PF;
275 case DE_VECTOR:
276 case TS_VECTOR:
277 case NP_VECTOR:
278 case SS_VECTOR:
279 case GP_VECTOR:
280 return EXCPT_CONTRIBUTORY;
281 default:
282 break;
283 }
284 return EXCPT_BENIGN;
285}
286
287static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 288 unsigned nr, bool has_error, u32 error_code,
289 bool reinject)
3fd28fce
ED		 290{
291 u32 prev_nr;
292 int class1, class2;
293
3842d135
AK		 294 kvm_make_request(KVM_REQ_EVENT, vcpu);
295
3fd28fce
ED		 296 if (!vcpu->arch.exception.pending) {
297 queue:
298 vcpu->arch.exception.pending = true;
299 vcpu->arch.exception.has_error_code = has_error;
300 vcpu->arch.exception.nr = nr;
301 vcpu->arch.exception.error_code = error_code;
3f0fd292 302 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 303 return;
304 }
305
306 /* to check exception */
307 prev_nr = vcpu->arch.exception.nr;
308 if (prev_nr == DF_VECTOR) {
309 /* triple fault -> shutdown */
a8eeb04a 310 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 311 return;
312 }
313 class1 = exception_class(prev_nr);
314 class2 = exception_class(nr);
315 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
316 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
317 /* generate double fault per SDM Table 5-5 */
318 vcpu->arch.exception.pending = true;
319 vcpu->arch.exception.has_error_code = true;
320 vcpu->arch.exception.nr = DF_VECTOR;
321 vcpu->arch.exception.error_code = 0;
322 } else
323 /* replace previous exception with a new one in a hope
324 that instruction re-execution will regenerate lost
325 exception */
326 goto queue;
327}
328
298101da
AK		 329void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
330{
ce7ddec4 331 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 332}
333EXPORT_SYMBOL_GPL(kvm_queue_exception);
334
ce7ddec4
JR		 335void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
336{
337 kvm_multiple_exception(vcpu, nr, false, 0, true);
338}
339EXPORT_SYMBOL_GPL(kvm_requeue_exception);
340
db8fcefa 341void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 342{
db8fcefa
AP		 343 if (err)
344 kvm_inject_gp(vcpu, 0);
345 else
346 kvm_x86_ops->skip_emulated_instruction(vcpu);
347}
348EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 349
6389ee94 350void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 351{
352 ++vcpu->stat.pf_guest;
6389ee94
AK		 353 vcpu->arch.cr2 = fault->address;
354 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 355}
27d6c865 356EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 357
6389ee94 358void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 359{
6389ee94
AK		 360 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
361 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 362 else
6389ee94 363 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 364}
365
3419ffc8
SY		 366void kvm_inject_nmi(struct kvm_vcpu *vcpu)
367{
7460fb4a
AK		 368 atomic_inc(&vcpu->arch.nmi_queued);
369 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 370}
371EXPORT_SYMBOL_GPL(kvm_inject_nmi);
372
298101da
AK		 373void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
374{
ce7ddec4 375 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 376}
377EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
378
ce7ddec4
JR		 379void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
380{
381 kvm_multiple_exception(vcpu, nr, true, error_code, true);
382}
383EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
384
0a79b009
AK		 385/*
386 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
387 * a #GP and return false.
388 */
389bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 390{
0a79b009
AK		 391 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
392 return true;
393 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
394 return false;
298101da 395}
0a79b009 396EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 397
ec92fe44
JR		 398/*
399 * This function will be used to read from the physical memory of the currently
400 * running guest. The difference to kvm_read_guest_page is that this function
401 * can read from guest physical or from the guest's guest physical memory.
402 */
403int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
404 gfn_t ngfn, void *data, int offset, int len,
405 u32 access)
406{
407 gfn_t real_gfn;
408 gpa_t ngpa;
409
410 ngpa = gfn_to_gpa(ngfn);
411 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
412 if (real_gfn == UNMAPPED_GVA)
413 return -EFAULT;
414
415 real_gfn = gpa_to_gfn(real_gfn);
416
417 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
418}
419EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
420
3d06b8bf
JR		 421int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
422 void *data, int offset, int len, u32 access)
423{
424 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
425 data, offset, len, access);
426}
427
a03490ed
CO		 428/*
429 * Load the pae pdptrs. Return true is they are all valid.
430 */
ff03a073 431int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 432{
433 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
434 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
435 int i;
436 int ret;
ff03a073 437 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 438
ff03a073
JR		 439 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
440 offset * sizeof(u64), sizeof(pdpte),
441 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 442 if (ret < 0) {
443 ret = 0;
444 goto out;
445 }
446 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 447 if (is_present_gpte(pdpte[i]) &&
20c466b5 448 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 449 ret = 0;
450 goto out;
451 }
452 }
453 ret = 1;
454
ff03a073 455 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 456 __set_bit(VCPU_EXREG_PDPTR,
457 (unsigned long *)&vcpu->arch.regs_avail);
458 __set_bit(VCPU_EXREG_PDPTR,
459 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 460out:
a03490ed
CO		 461
462 return ret;
463}
cc4b6871 464EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 465
d835dfec
AK		 466static bool pdptrs_changed(struct kvm_vcpu *vcpu)
467{
ff03a073 468 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 469 bool changed = true;
3d06b8bf
JR		 470 int offset;
471 gfn_t gfn;
d835dfec
AK		 472 int r;
473
474 if (is_long_mode(vcpu) || !is_pae(vcpu))
475 return false;
476
6de4f3ad
AK		 477 if (!test_bit(VCPU_EXREG_PDPTR,
478 (unsigned long *)&vcpu->arch.regs_avail))
479 return true;
480
9f8fe504
AK		 481 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
482 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 483 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
484 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 485 if (r < 0)
486 goto out;
ff03a073 487 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 488out:
d835dfec
AK		 489
490 return changed;
491}
492
49a9b07e 493int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 494{
aad82703
SY		 495 unsigned long old_cr0 = kvm_read_cr0(vcpu);
496 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
497 X86_CR0_CD | X86_CR0_NW;
498
f9a48e6a
AK		 499 cr0 |= X86_CR0_ET;
500
ab344828 501#ifdef CONFIG_X86_64
0f12244f
GN		 502 if (cr0 & 0xffffffff00000000UL)
503 return 1;
ab344828
GN		 504#endif
505
506 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 507
0f12244f
GN		 508 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
509 return 1;
a03490ed 510
0f12244f
GN		 511 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
512 return 1;
a03490ed
CO		 513
514 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
515#ifdef CONFIG_X86_64
f6801dff 516 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 517 int cs_db, cs_l;
518
0f12244f
GN		 519 if (!is_pae(vcpu))
520 return 1;
a03490ed 521 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 522 if (cs_l)
523 return 1;
a03490ed
CO		 524 } else
525#endif
ff03a073 526 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 527 kvm_read_cr3(vcpu)))
0f12244f 528 return 1;
a03490ed
CO		 529 }
530
531 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 532
d170c419 533 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 534 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 535 kvm_async_pf_hash_reset(vcpu);
536 }
e5f3f027 537
aad82703
SY		 538 if ((cr0 ^ old_cr0) & update_bits)
539 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 540 return 0;
541}
2d3ad1f4 542EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 543
2d3ad1f4 544void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 545{
49a9b07e 546 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 547}
2d3ad1f4 548EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 549
2acf923e
DC		 550int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
551{
552 u64 xcr0;
553
554 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
555 if (index != XCR_XFEATURE_ENABLED_MASK)
556 return 1;
557 xcr0 = xcr;
558 if (kvm_x86_ops->get_cpl(vcpu) != 0)
559 return 1;
560 if (!(xcr0 & XSTATE_FP))
561 return 1;
562 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
563 return 1;
564 if (xcr0 & ~host_xcr0)
565 return 1;
566 vcpu->arch.xcr0 = xcr0;
567 vcpu->guest_xcr0_loaded = 0;
568 return 0;
569}
570
571int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
572{
573 if (__kvm_set_xcr(vcpu, index, xcr)) {
574 kvm_inject_gp(vcpu, 0);
575 return 1;
576 }
577 return 0;
578}
579EXPORT_SYMBOL_GPL(kvm_set_xcr);
580
a83b29c6 581int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 582{
fc78f519 583 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 584 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
585 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 586 if (cr4 & CR4_RESERVED_BITS)
587 return 1;
a03490ed 588
2acf923e
DC		 589 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
590 return 1;
591
c68b734f
YW		 592 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
593 return 1;
594
74dc2b4f
YW		 595 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
596 return 1;
597
a03490ed 598 if (is_long_mode(vcpu)) {
0f12244f
GN		 599 if (!(cr4 & X86_CR4_PAE))
600 return 1;
a2edf57f
AK		 601 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
602 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 603 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
604 kvm_read_cr3(vcpu)))
0f12244f
GN		 605 return 1;
606
5e1746d6 607 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 608 return 1;
a03490ed 609
aad82703
SY		 610 if ((cr4 ^ old_cr4) & pdptr_bits)
611 kvm_mmu_reset_context(vcpu);
0f12244f 612
2acf923e 613 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 614 kvm_update_cpuid(vcpu);
2acf923e 615
0f12244f
GN		 616 return 0;
617}
2d3ad1f4 618EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 619
2390218b 620int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 621{
9f8fe504 622 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 623 kvm_mmu_sync_roots(vcpu);
d835dfec 624 kvm_mmu_flush_tlb(vcpu);
0f12244f 625 return 0;
d835dfec
AK		 626 }
627
a03490ed 628 if (is_long_mode(vcpu)) {
0f12244f
GN		 629 if (cr3 & CR3_L_MODE_RESERVED_BITS)
630 return 1;
a03490ed
CO		 631 } else {
632 if (is_pae(vcpu)) {
0f12244f
GN		 633 if (cr3 & CR3_PAE_RESERVED_BITS)
634 return 1;
ff03a073
JR		 635 if (is_paging(vcpu) &&
636 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 637 return 1;
a03490ed
CO		 638 }
639 /*
640 * We don't check reserved bits in nonpae mode, because
641 * this isn't enforced, and VMware depends on this.
642 */
643 }
644
a03490ed
CO		 645 /*
646 * Does the new cr3 value map to physical memory? (Note, we
647 * catch an invalid cr3 even in real-mode, because it would
648 * cause trouble later on when we turn on paging anyway.)
649 *
650 * A real CPU would silently accept an invalid cr3 and would
651 * attempt to use it - with largely undefined (and often hard
652 * to debug) behavior on the guest side.
653 */
654 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 655 return 1;
656 vcpu->arch.cr3 = cr3;
aff48baa 657 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
0f12244f
GN		 658 vcpu->arch.mmu.new_cr3(vcpu);
659 return 0;
660}
2d3ad1f4 661EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 662
eea1cff9 663int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 664{
0f12244f
GN		 665 if (cr8 & CR8_RESERVED_BITS)
666 return 1;
a03490ed
CO		 667 if (irqchip_in_kernel(vcpu->kvm))
668 kvm_lapic_set_tpr(vcpu, cr8);
669 else
ad312c7c 670 vcpu->arch.cr8 = cr8;
0f12244f
GN		 671 return 0;
672}
2d3ad1f4 673EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 674
2d3ad1f4 675unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 676{
677 if (irqchip_in_kernel(vcpu->kvm))
678 return kvm_lapic_get_cr8(vcpu);
679 else
ad312c7c 680 return vcpu->arch.cr8;
a03490ed 681}
2d3ad1f4 682EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 683
338dbc97 684static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 685{
686 switch (dr) {
687 case 0 ... 3:
688 vcpu->arch.db[dr] = val;
689 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
690 vcpu->arch.eff_db[dr] = val;
691 break;
692 case 4:
338dbc97
GN		 693 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
694 return 1; /* #UD */
020df079
GN		 695 /* fall through */
696 case 6:
338dbc97
GN		 697 if (val & 0xffffffff00000000ULL)
698 return -1; /* #GP */
020df079
GN		 699 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
700 break;
701 case 5:
338dbc97
GN		 702 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
703 return 1; /* #UD */
020df079
GN		 704 /* fall through */
705 default: /* 7 */
338dbc97
GN		 706 if (val & 0xffffffff00000000ULL)
707 return -1; /* #GP */
020df079
GN		 708 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
709 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
710 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
711 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
712 }
713 break;
714 }
715
716 return 0;
717}
338dbc97
GN		 718
719int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
720{
721 int res;
722
723 res = __kvm_set_dr(vcpu, dr, val);
724 if (res > 0)
725 kvm_queue_exception(vcpu, UD_VECTOR);
726 else if (res < 0)
727 kvm_inject_gp(vcpu, 0);
728
729 return res;
730}
020df079
GN		 731EXPORT_SYMBOL_GPL(kvm_set_dr);
732
338dbc97 733static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 734{
735 switch (dr) {
736 case 0 ... 3:
737 *val = vcpu->arch.db[dr];
738 break;
739 case 4:
338dbc97 740 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 741 return 1;
020df079
GN		 742 /* fall through */
743 case 6:
744 *val = vcpu->arch.dr6;
745 break;
746 case 5:
338dbc97 747 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 748 return 1;
020df079
GN		 749 /* fall through */
750 default: /* 7 */
751 *val = vcpu->arch.dr7;
752 break;
753 }
754
755 return 0;
756}
338dbc97
GN		 757
758int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
759{
760 if (_kvm_get_dr(vcpu, dr, val)) {
761 kvm_queue_exception(vcpu, UD_VECTOR);
762 return 1;
763 }
764 return 0;
765}
020df079
GN		 766EXPORT_SYMBOL_GPL(kvm_get_dr);
767
022cd0e8
AK		 768bool kvm_rdpmc(struct kvm_vcpu *vcpu)
769{
770 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
771 u64 data;
772 int err;
773
774 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
775 if (err)
776 return err;
777 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
778 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
779 return err;
780}
781EXPORT_SYMBOL_GPL(kvm_rdpmc);
782
043405e1
CO		 783/*
784 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
785 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
786 *
787 * This list is modified at module load time to reflect the
e3267cbb
GC		 788 * capabilities of the host cpu. This capabilities test skips MSRs that are
789 * kvm-specific. Those are put in the beginning of the list.
043405e1 790 */
e3267cbb 791
c9aaa895 792#define KVM_SAVE_MSRS_BEGIN 9
043405e1 793static u32 msrs_to_save[] = {
e3267cbb 794 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 795 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 796 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
c9aaa895 797 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
043405e1 798 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 799 MSR_STAR,
043405e1
CO		 800#ifdef CONFIG_X86_64
801 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
802#endif
e90aa41e 803 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 804};
805
806static unsigned num_msrs_to_save;
807
808static u32 emulated_msrs[] = {
a3e06bbe 809 MSR_IA32_TSCDEADLINE,
043405e1 810 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 811 MSR_IA32_MCG_STATUS,
812 MSR_IA32_MCG_CTL,
043405e1
CO		 813};
814
b69e8cae 815static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 816{
aad82703
SY		 817 u64 old_efer = vcpu->arch.efer;
818
b69e8cae
RJ		 819 if (efer & efer_reserved_bits)
820 return 1;
15c4a640
CO		 821
822 if (is_paging(vcpu)
b69e8cae
RJ		 823 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
824 return 1;
15c4a640 825
1b2fd70c
AG		 826 if (efer & EFER_FFXSR) {
827 struct kvm_cpuid_entry2 *feat;
828
829 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 830 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
831 return 1;
1b2fd70c
AG		 832 }
833
d8017474
AG		 834 if (efer & EFER_SVME) {
835 struct kvm_cpuid_entry2 *feat;
836
837 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 838 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
839 return 1;
d8017474
AG		 840 }
841
15c4a640 842 efer &= ~EFER_LMA;
f6801dff 843 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 844
a3d204e2
SY		 845 kvm_x86_ops->set_efer(vcpu, efer);
846
9645bb56 847 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
b69e8cae 848
aad82703
SY		 849 /* Update reserved bits */
850 if ((efer ^ old_efer) & EFER_NX)
851 kvm_mmu_reset_context(vcpu);
852
b69e8cae 853 return 0;
15c4a640
CO		 854}
855
f2b4b7dd
JR		 856void kvm_enable_efer_bits(u64 mask)
857{
858 efer_reserved_bits &= ~mask;
859}
860EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
861
862
15c4a640
CO		 863/*
864 * Writes msr value into into the appropriate "register".
865 * Returns 0 on success, non-0 otherwise.
866 * Assumes vcpu_load() was already called.
867 */
868int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
869{
870 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
871}
872
313a3dc7
CO		 873/*
874 * Adapt set_msr() to msr_io()'s calling convention
875 */
876static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
877{
878 return kvm_set_msr(vcpu, index, *data);
879}
880
18068523
GOC		 881static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
882{
9ed3c444
AK		 883 int version;
884 int r;
50d0a0f9 885 struct pvclock_wall_clock wc;
923de3cf 886 struct timespec boot;
18068523
GOC		 887
888 if (!wall_clock)
889 return;
890
9ed3c444
AK		 891 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
892 if (r)
893 return;
894
895 if (version & 1)
896 ++version; /* first time write, random junk */
897
898 ++version;
18068523 899
18068523
GOC		 900 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
901
50d0a0f9
GH		 902 /*
903 * The guest calculates current wall clock time by adding
34c238a1 904 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 905 * wall clock specified here. guest system time equals host
906 * system time for us, thus we must fill in host boot time here.
907 */
923de3cf 908 getboottime(&boot);
50d0a0f9
GH		 909
910 wc.sec = boot.tv_sec;
911 wc.nsec = boot.tv_nsec;
912 wc.version = version;
18068523
GOC		 913
914 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
915
916 version++;
917 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 918}
919
50d0a0f9
GH		 920static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
921{
922 uint32_t quotient, remainder;
923
924 /* Don't try to replace with do_div(), this one calculates
925 * "(dividend << 32) / divisor" */
926 __asm__ ( "divl %4"
927 : "=a" (quotient), "=d" (remainder)
928 : "0" (0), "1" (dividend), "r" (divisor) );
929 return quotient;
930}
931
5f4e3f88
ZA		 932static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
933 s8 *pshift, u32 *pmultiplier)
50d0a0f9 934{
5f4e3f88 935 uint64_t scaled64;
50d0a0f9
GH		 936 int32_t shift = 0;
937 uint64_t tps64;
938 uint32_t tps32;
939
5f4e3f88
ZA		 940 tps64 = base_khz * 1000LL;
941 scaled64 = scaled_khz * 1000LL;
50933623 942 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 943 tps64 >>= 1;
944 shift--;
945 }
946
947 tps32 = (uint32_t)tps64;
50933623
JK		 948 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
949 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 950 scaled64 >>= 1;
951 else
952 tps32 <<= 1;
50d0a0f9
GH		 953 shift++;
954 }
955
5f4e3f88
ZA		 956 *pshift = shift;
957 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 958
5f4e3f88
ZA		 959 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
960 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 961}
962
759379dd
ZA		 963static inline u64 get_kernel_ns(void)
964{
965 struct timespec ts;
966
967 WARN_ON(preemptible());
968 ktime_get_ts(&ts);
969 monotonic_to_bootbased(&ts);
970 return timespec_to_ns(&ts);
50d0a0f9
GH		 971}
972
c8076604 973static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 974unsigned long max_tsc_khz;
c8076604 975
cc578287 976static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 977{
cc578287
ZA		 978 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
979 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 980}
981
cc578287 982static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 983{
cc578287
ZA		 984 u64 v = (u64)khz * (1000000 + ppm);
985 do_div(v, 1000000);
986 return v;
1e993611
JR		 987}
988
cc578287 989static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 990{
cc578287
ZA		 991 u32 thresh_lo, thresh_hi;
992 int use_scaling = 0;
217fc9cf 993
c285545f
ZA		 994 /* Compute a scale to convert nanoseconds in TSC cycles */
995 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 996 &vcpu->arch.virtual_tsc_shift,
997 &vcpu->arch.virtual_tsc_mult);
998 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
999
1000 /*
1001 * Compute the variation in TSC rate which is acceptable
1002 * within the range of tolerance and decide if the
1003 * rate being applied is within that bounds of the hardware
1004 * rate. If so, no scaling or compensation need be done.
1005 */
1006 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1007 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1008 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1009 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1010 use_scaling = 1;
1011 }
1012 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1013}
1014
1015static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1016{
e26101b1 1017 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1018 vcpu->arch.virtual_tsc_mult,
1019 vcpu->arch.virtual_tsc_shift);
e26101b1 1020 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1021 return tsc;
1022}
1023
99e3e30a
ZA		 1024void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1025{
1026 struct kvm *kvm = vcpu->kvm;
f38e098f 1027 u64 offset, ns, elapsed;
99e3e30a 1028 unsigned long flags;
02626b6a 1029 s64 usdiff;
99e3e30a 1030
038f8c11 1031 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1032 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1033 ns = get_kernel_ns();
f38e098f 1034 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6
ZA		 1035
1036 /* n.b - signed multiplication and division required */
02626b6a 1037 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1038#ifdef CONFIG_X86_64
02626b6a 1039 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6
ZA		 1040#else
1041 /* do_div() only does unsigned */
1042 asm("idivl %2; xor %%edx, %%edx"
02626b6a
MT		 1043 : "=A"(usdiff)
1044 : "A"(usdiff * 1000), "rm"(vcpu->arch.virtual_tsc_khz));
5d3cb0f6 1045#endif
02626b6a
MT		 1046 do_div(elapsed, 1000);
1047 usdiff -= elapsed;
1048 if (usdiff < 0)
1049 usdiff = -usdiff;
f38e098f
ZA		 1050
1051 /*
5d3cb0f6
ZA		 1052 * Special case: TSC write with a small delta (1 second) of virtual
1053 * cycle time against real time is interpreted as an attempt to
1054 * synchronize the CPU.
1055 *
1056 * For a reliable TSC, we can match TSC offsets, and for an unstable
1057 * TSC, we add elapsed time in this computation. We could let the
1058 * compensation code attempt to catch up if we fall behind, but
1059 * it's better to try to match offsets from the beginning.
1060 */
02626b6a 1061 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1062 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1063 if (!check_tsc_unstable()) {
e26101b1 1064 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1065 pr_debug("kvm: matched tsc offset for %llu\n", data);
1066 } else {
857e4099 1067 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1068 data += delta;
1069 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1070 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1071 }
e26101b1
ZA		 1072 } else {
1073 /*
1074 * We split periods of matched TSC writes into generations.
1075 * For each generation, we track the original measured
1076 * nanosecond time, offset, and write, so if TSCs are in
1077 * sync, we can match exact offset, and if not, we can match
1078 * exact software computaion in compute_guest_tsc()
1079 *
1080 * These values are tracked in kvm->arch.cur_xxx variables.
1081 */
1082 kvm->arch.cur_tsc_generation++;
1083 kvm->arch.cur_tsc_nsec = ns;
1084 kvm->arch.cur_tsc_write = data;
1085 kvm->arch.cur_tsc_offset = offset;
1086 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1087 kvm->arch.cur_tsc_generation, data);
f38e098f 1088 }
e26101b1
ZA		 1089
1090 /*
1091 * We also track th most recent recorded KHZ, write and time to
1092 * allow the matching interval to be extended at each write.
1093 */
f38e098f
ZA		 1094 kvm->arch.last_tsc_nsec = ns;
1095 kvm->arch.last_tsc_write = data;
5d3cb0f6 1096 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a
ZA		 1097
1098 /* Reset of TSC must disable overshoot protection below */
1099 vcpu->arch.hv_clock.tsc_timestamp = 0;
b183aa58 1100 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1101
1102 /* Keep track of which generation this VCPU has synchronized to */
1103 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1104 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1105 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1106
1107 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1108 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
99e3e30a 1109}
e26101b1 1110
99e3e30a
ZA		 1111EXPORT_SYMBOL_GPL(kvm_write_tsc);
1112
34c238a1 1113static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1114{
18068523
GOC		 1115 unsigned long flags;
1116 struct kvm_vcpu_arch *vcpu = &v->arch;
1117 void *shared_kaddr;
463656c0 1118 unsigned long this_tsc_khz;
1d5f066e
ZA		 1119 s64 kernel_ns, max_kernel_ns;
1120 u64 tsc_timestamp;
18068523 1121
18068523
GOC		 1122 /* Keep irq disabled to prevent changes to the clock */
1123 local_irq_save(flags);
d5c1785d 1124 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v);
759379dd 1125 kernel_ns = get_kernel_ns();
cc578287 1126 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
8cfdc000 1127 if (unlikely(this_tsc_khz == 0)) {
c285545f 1128 local_irq_restore(flags);
34c238a1 1129 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
8cfdc000
ZA		 1130 return 1;
1131 }
18068523 1132
c285545f
ZA		 1133 /*
1134 * We may have to catch up the TSC to match elapsed wall clock
1135 * time for two reasons, even if kvmclock is used.
1136 * 1) CPU could have been running below the maximum TSC rate
1137 * 2) Broken TSC compensation resets the base at each VCPU
1138 * entry to avoid unknown leaps of TSC even when running
1139 * again on the same CPU. This may cause apparent elapsed
1140 * time to disappear, and the guest to stand still or run
1141 * very slowly.
1142 */
1143 if (vcpu->tsc_catchup) {
1144 u64 tsc = compute_guest_tsc(v, kernel_ns);
1145 if (tsc > tsc_timestamp) {
f1e2b260 1146 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1147 tsc_timestamp = tsc;
1148 }
50d0a0f9
GH		 1149 }
1150
18068523
GOC		 1151 local_irq_restore(flags);
1152
c285545f
ZA		 1153 if (!vcpu->time_page)
1154 return 0;
18068523 1155
1d5f066e
ZA		 1156 /*
1157 * Time as measured by the TSC may go backwards when resetting the base
1158 * tsc_timestamp. The reason for this is that the TSC resolution is
1159 * higher than the resolution of the other clock scales. Thus, many
1160 * possible measurments of the TSC correspond to one measurement of any
1161 * other clock, and so a spread of values is possible. This is not a
1162 * problem for the computation of the nanosecond clock; with TSC rates
1163 * around 1GHZ, there can only be a few cycles which correspond to one
1164 * nanosecond value, and any path through this code will inevitably
1165 * take longer than that. However, with the kernel_ns value itself,
1166 * the precision may be much lower, down to HZ granularity. If the
1167 * first sampling of TSC against kernel_ns ends in the low part of the
1168 * range, and the second in the high end of the range, we can get:
1169 *
1170 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1171 *
1172 * As the sampling errors potentially range in the thousands of cycles,
1173 * it is possible such a time value has already been observed by the
1174 * guest. To protect against this, we must compute the system time as
1175 * observed by the guest and ensure the new system time is greater.
1176 */
1177 max_kernel_ns = 0;
b183aa58 1178 if (vcpu->hv_clock.tsc_timestamp) {
1d5f066e
ZA		 1179 max_kernel_ns = vcpu->last_guest_tsc -
1180 vcpu->hv_clock.tsc_timestamp;
1181 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1182 vcpu->hv_clock.tsc_to_system_mul,
1183 vcpu->hv_clock.tsc_shift);
1184 max_kernel_ns += vcpu->last_kernel_ns;
1185 }
afbcf7ab 1186
e48672fa 1187 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1188 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1189 &vcpu->hv_clock.tsc_shift,
1190 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1191 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1192 }
1193
1d5f066e
ZA		 1194 if (max_kernel_ns > kernel_ns)
1195 kernel_ns = max_kernel_ns;
1196
8cfdc000 1197 /* With all the info we got, fill in the values */
1d5f066e 1198 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1199 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1200 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1201 vcpu->last_guest_tsc = tsc_timestamp;
371bcf64
GC		 1202 vcpu->hv_clock.flags = 0;
1203
18068523
GOC		 1204 /*
1205 * The interface expects us to write an even number signaling that the
1206 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1207 * state, we just increase by 2 at the end.
18068523 1208 */
50d0a0f9 1209 vcpu->hv_clock.version += 2;
18068523 1210
8fd75e12 1211 shared_kaddr = kmap_atomic(vcpu->time_page);
18068523
GOC		 1212
1213 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1214 sizeof(vcpu->hv_clock));
18068523 1215
8fd75e12 1216 kunmap_atomic(shared_kaddr);
18068523
GOC		 1217
1218 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1219 return 0;
c8076604
GH		 1220}
1221
9ba075a6
AK		 1222static bool msr_mtrr_valid(unsigned msr)
1223{
1224 switch (msr) {
1225 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1226 case MSR_MTRRfix64K_00000:
1227 case MSR_MTRRfix16K_80000:
1228 case MSR_MTRRfix16K_A0000:
1229 case MSR_MTRRfix4K_C0000:
1230 case MSR_MTRRfix4K_C8000:
1231 case MSR_MTRRfix4K_D0000:
1232 case MSR_MTRRfix4K_D8000:
1233 case MSR_MTRRfix4K_E0000:
1234 case MSR_MTRRfix4K_E8000:
1235 case MSR_MTRRfix4K_F0000:
1236 case MSR_MTRRfix4K_F8000:
1237 case MSR_MTRRdefType:
1238 case MSR_IA32_CR_PAT:
1239 return true;
1240 case 0x2f8:
1241 return true;
1242 }
1243 return false;
1244}
1245
d6289b93
MT		 1246static bool valid_pat_type(unsigned t)
1247{
1248 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1249}
1250
1251static bool valid_mtrr_type(unsigned t)
1252{
1253 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1254}
1255
1256static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1257{
1258 int i;
1259
1260 if (!msr_mtrr_valid(msr))
1261 return false;
1262
1263 if (msr == MSR_IA32_CR_PAT) {
1264 for (i = 0; i < 8; i++)
1265 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1266 return false;
1267 return true;
1268 } else if (msr == MSR_MTRRdefType) {
1269 if (data & ~0xcff)
1270 return false;
1271 return valid_mtrr_type(data & 0xff);
1272 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1273 for (i = 0; i < 8 ; i++)
1274 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1275 return false;
1276 return true;
1277 }
1278
1279 /* variable MTRRs */
1280 return valid_mtrr_type(data & 0xff);
1281}
1282
9ba075a6
AK		 1283static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1284{
0bed3b56
SY		 1285 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1286
d6289b93 1287 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1288 return 1;
1289
0bed3b56
SY		 1290 if (msr == MSR_MTRRdefType) {
1291 vcpu->arch.mtrr_state.def_type = data;
1292 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1293 } else if (msr == MSR_MTRRfix64K_00000)
1294 p[0] = data;
1295 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1296 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1297 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1298 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1299 else if (msr == MSR_IA32_CR_PAT)
1300 vcpu->arch.pat = data;
1301 else { /* Variable MTRRs */
1302 int idx, is_mtrr_mask;
1303 u64 *pt;
1304
1305 idx = (msr - 0x200) / 2;
1306 is_mtrr_mask = msr - 0x200 - 2 * idx;
1307 if (!is_mtrr_mask)
1308 pt =
1309 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1310 else
1311 pt =
1312 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1313 *pt = data;
1314 }
1315
1316 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1317 return 0;
1318}
15c4a640 1319
890ca9ae 1320static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1321{
890ca9ae
HY		 1322 u64 mcg_cap = vcpu->arch.mcg_cap;
1323 unsigned bank_num = mcg_cap & 0xff;
1324
15c4a640 1325 switch (msr) {
15c4a640 1326 case MSR_IA32_MCG_STATUS:
890ca9ae 1327 vcpu->arch.mcg_status = data;
15c4a640 1328 break;
c7ac679c 1329 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1330 if (!(mcg_cap & MCG_CTL_P))
1331 return 1;
1332 if (data != 0 && data != ~(u64)0)
1333 return -1;
1334 vcpu->arch.mcg_ctl = data;
1335 break;
1336 default:
1337 if (msr >= MSR_IA32_MC0_CTL &&
1338 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1339 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1340 /* only 0 or all 1s can be written to IA32_MCi_CTL
1341 * some Linux kernels though clear bit 10 in bank 4 to
1342 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1343 * this to avoid an uncatched #GP in the guest
1344 */
890ca9ae 1345 if ((offset & 0x3) == 0 &&
114be429 1346 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1347 return -1;
1348 vcpu->arch.mce_banks[offset] = data;
1349 break;
1350 }
1351 return 1;
1352 }
1353 return 0;
1354}
1355
ffde22ac
ES		 1356static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1357{
1358 struct kvm *kvm = vcpu->kvm;
1359 int lm = is_long_mode(vcpu);
1360 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1361 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1362 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1363 : kvm->arch.xen_hvm_config.blob_size_32;
1364 u32 page_num = data & ~PAGE_MASK;
1365 u64 page_addr = data & PAGE_MASK;
1366 u8 *page;
1367 int r;
1368
1369 r = -E2BIG;
1370 if (page_num >= blob_size)
1371 goto out;
1372 r = -ENOMEM;
ff5c2c03
SL		 1373 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1374 if (IS_ERR(page)) {
1375 r = PTR_ERR(page);
ffde22ac 1376 goto out;
ff5c2c03 1377 }
ffde22ac
ES		 1378 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1379 goto out_free;
1380 r = 0;
1381out_free:
1382 kfree(page);
1383out:
1384 return r;
1385}
1386
55cd8e5a
GN		 1387static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1388{
1389 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1390}
1391
1392static bool kvm_hv_msr_partition_wide(u32 msr)
1393{
1394 bool r = false;
1395 switch (msr) {
1396 case HV_X64_MSR_GUEST_OS_ID:
1397 case HV_X64_MSR_HYPERCALL:
1398 r = true;
1399 break;
1400 }
1401
1402 return r;
1403}
1404
1405static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1406{
1407 struct kvm *kvm = vcpu->kvm;
1408
1409 switch (msr) {
1410 case HV_X64_MSR_GUEST_OS_ID:
1411 kvm->arch.hv_guest_os_id = data;
1412 /* setting guest os id to zero disables hypercall page */
1413 if (!kvm->arch.hv_guest_os_id)
1414 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1415 break;
1416 case HV_X64_MSR_HYPERCALL: {
1417 u64 gfn;
1418 unsigned long addr;
1419 u8 instructions[4];
1420
1421 /* if guest os id is not set hypercall should remain disabled */
1422 if (!kvm->arch.hv_guest_os_id)
1423 break;
1424 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1425 kvm->arch.hv_hypercall = data;
1426 break;
1427 }
1428 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1429 addr = gfn_to_hva(kvm, gfn);
1430 if (kvm_is_error_hva(addr))
1431 return 1;
1432 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1433 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1434 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1435 return 1;
1436 kvm->arch.hv_hypercall = data;
1437 break;
1438 }
1439 default:
1440 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1441 "data 0x%llx\n", msr, data);
1442 return 1;
1443 }
1444 return 0;
1445}
1446
1447static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1448{
10388a07
GN		 1449 switch (msr) {
1450 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1451 unsigned long addr;
55cd8e5a 1452
10388a07
GN		 1453 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1454 vcpu->arch.hv_vapic = data;
1455 break;
1456 }
1457 addr = gfn_to_hva(vcpu->kvm, data >>
1458 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1459 if (kvm_is_error_hva(addr))
1460 return 1;
8b0cedff 1461 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1462 return 1;
1463 vcpu->arch.hv_vapic = data;
1464 break;
1465 }
1466 case HV_X64_MSR_EOI:
1467 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1468 case HV_X64_MSR_ICR:
1469 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1470 case HV_X64_MSR_TPR:
1471 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1472 default:
1473 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1474 "data 0x%llx\n", msr, data);
1475 return 1;
1476 }
1477
1478 return 0;
55cd8e5a
GN		 1479}
1480
344d9588
GN		 1481static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1482{
1483 gpa_t gpa = data & ~0x3f;
1484
6adba527
GN		 1485 /* Bits 2:5 are resrved, Should be zero */
1486 if (data & 0x3c)
344d9588
GN		 1487 return 1;
1488
1489 vcpu->arch.apf.msr_val = data;
1490
1491 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1492 kvm_clear_async_pf_completion_queue(vcpu);
1493 kvm_async_pf_hash_reset(vcpu);
1494 return 0;
1495 }
1496
1497 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1498 return 1;
1499
6adba527 1500 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1501 kvm_async_pf_wakeup_all(vcpu);
1502 return 0;
1503}
1504
12f9a48f
GC		 1505static void kvmclock_reset(struct kvm_vcpu *vcpu)
1506{
1507 if (vcpu->arch.time_page) {
1508 kvm_release_page_dirty(vcpu->arch.time_page);
1509 vcpu->arch.time_page = NULL;
1510 }
1511}
1512
c9aaa895
GC		 1513static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1514{
1515 u64 delta;
1516
1517 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1518 return;
1519
1520 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1521 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1522 vcpu->arch.st.accum_steal = delta;
1523}
1524
1525static void record_steal_time(struct kvm_vcpu *vcpu)
1526{
1527 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1528 return;
1529
1530 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1531 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1532 return;
1533
1534 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1535 vcpu->arch.st.steal.version += 2;
1536 vcpu->arch.st.accum_steal = 0;
1537
1538 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1539 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1540}
1541
15c4a640
CO		 1542int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1543{
5753785f
GN		 1544 bool pr = false;
1545
15c4a640 1546 switch (msr) {
15c4a640 1547 case MSR_EFER:
b69e8cae 1548 return set_efer(vcpu, data);
8f1589d9
AP		 1549 case MSR_K7_HWCR:
1550 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1551 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 1552 data &= ~(u64)0x8; /* ignore TLB cache disable */
8f1589d9
AP		 1553 if (data != 0) {
1554 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1555 data);
1556 return 1;
1557 }
15c4a640 1558 break;
f7c6d140
AP		 1559 case MSR_FAM10H_MMIO_CONF_BASE:
1560 if (data != 0) {
1561 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1562 "0x%llx\n", data);
1563 return 1;
1564 }
15c4a640 1565 break;
c323c0e5 1566 case MSR_AMD64_NB_CFG:
c7ac679c 1567 break;
b5e2fec0
AG		 1568 case MSR_IA32_DEBUGCTLMSR:
1569 if (!data) {
1570 /* We support the non-activated case already */
1571 break;
1572 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1573 /* Values other than LBR and BTF are vendor-specific,
1574 thus reserved and should throw a #GP */
1575 return 1;
1576 }
1577 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1578 __func__, data);
1579 break;
15c4a640
CO		 1580 case MSR_IA32_UCODE_REV:
1581 case MSR_IA32_UCODE_WRITE:
61a6bd67 1582 case MSR_VM_HSAVE_PA:
6098ca93 1583 case MSR_AMD64_PATCH_LOADER:
15c4a640 1584 break;
9ba075a6
AK		 1585 case 0x200 ... 0x2ff:
1586 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1587 case MSR_IA32_APICBASE:
1588 kvm_set_apic_base(vcpu, data);
1589 break;
0105d1a5
GN		 1590 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1591 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 1592 case MSR_IA32_TSCDEADLINE:
1593 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1594 break;
15c4a640 1595 case MSR_IA32_MISC_ENABLE:
ad312c7c 1596 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1597 break;
11c6bffa 1598 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1599 case MSR_KVM_WALL_CLOCK:
1600 vcpu->kvm->arch.wall_clock = data;
1601 kvm_write_wall_clock(vcpu->kvm, data);
1602 break;
11c6bffa 1603 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 1604 case MSR_KVM_SYSTEM_TIME: {
12f9a48f 1605 kvmclock_reset(vcpu);
18068523
GOC		 1606
1607 vcpu->arch.time = data;
c285545f 1608 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1609
1610 /* we verify if the enable bit is set... */
1611 if (!(data & 1))
1612 break;
1613
1614 /* ...but clean it before doing the actual write */
1615 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1616
18068523
GOC		 1617 vcpu->arch.time_page =
1618 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1619
1620 if (is_error_page(vcpu->arch.time_page)) {
1621 kvm_release_page_clean(vcpu->arch.time_page);
1622 vcpu->arch.time_page = NULL;
1623 }
18068523
GOC		 1624 break;
1625 }
344d9588
GN		 1626 case MSR_KVM_ASYNC_PF_EN:
1627 if (kvm_pv_enable_async_pf(vcpu, data))
1628 return 1;
1629 break;
c9aaa895
GC		 1630 case MSR_KVM_STEAL_TIME:
1631
1632 if (unlikely(!sched_info_on()))
1633 return 1;
1634
1635 if (data & KVM_STEAL_RESERVED_MASK)
1636 return 1;
1637
1638 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
1639 data & KVM_STEAL_VALID_BITS))
1640 return 1;
1641
1642 vcpu->arch.st.msr_val = data;
1643
1644 if (!(data & KVM_MSR_ENABLED))
1645 break;
1646
1647 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1648
1649 preempt_disable();
1650 accumulate_steal_time(vcpu);
1651 preempt_enable();
1652
1653 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
1654
1655 break;
1656
890ca9ae
HY		 1657 case MSR_IA32_MCG_CTL:
1658 case MSR_IA32_MCG_STATUS:
1659 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1660 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1661
1662 /* Performance counters are not protected by a CPUID bit,
1663 * so we should check all of them in the generic path for the sake of
1664 * cross vendor migration.
1665 * Writing a zero into the event select MSRs disables them,
1666 * which we perfectly emulate ;-). Any other value should be at least
1667 * reported, some guests depend on them.
1668 */
71db6023
AP		 1669 case MSR_K7_EVNTSEL0:
1670 case MSR_K7_EVNTSEL1:
1671 case MSR_K7_EVNTSEL2:
1672 case MSR_K7_EVNTSEL3:
1673 if (data != 0)
1674 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1675 "0x%x data 0x%llx\n", msr, data);
1676 break;
1677 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1678 * so we ignore writes to make it happy.
1679 */
71db6023
AP		 1680 case MSR_K7_PERFCTR0:
1681 case MSR_K7_PERFCTR1:
1682 case MSR_K7_PERFCTR2:
1683 case MSR_K7_PERFCTR3:
1684 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1685 "0x%x data 0x%llx\n", msr, data);
1686 break;
5753785f
GN		 1687 case MSR_P6_PERFCTR0:
1688 case MSR_P6_PERFCTR1:
1689 pr = true;
1690 case MSR_P6_EVNTSEL0:
1691 case MSR_P6_EVNTSEL1:
1692 if (kvm_pmu_msr(vcpu, msr))
1693 return kvm_pmu_set_msr(vcpu, msr, data);
1694
1695 if (pr || data != 0)
1696 pr_unimpl(vcpu, "disabled perfctr wrmsr: "
1697 "0x%x data 0x%llx\n", msr, data);
1698 break;
84e0cefa
JS		 1699 case MSR_K7_CLK_CTL:
1700 /*
1701 * Ignore all writes to this no longer documented MSR.
1702 * Writes are only relevant for old K7 processors,
1703 * all pre-dating SVM, but a recommended workaround from
1704 * AMD for these chips. It is possible to speicify the
1705 * affected processor models on the command line, hence
1706 * the need to ignore the workaround.
1707 */
1708 break;
55cd8e5a
GN		 1709 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1710 if (kvm_hv_msr_partition_wide(msr)) {
1711 int r;
1712 mutex_lock(&vcpu->kvm->lock);
1713 r = set_msr_hyperv_pw(vcpu, msr, data);
1714 mutex_unlock(&vcpu->kvm->lock);
1715 return r;
1716 } else
1717 return set_msr_hyperv(vcpu, msr, data);
1718 break;
91c9c3ed 1719 case MSR_IA32_BBL_CR_CTL3:
1720 /* Drop writes to this legacy MSR -- see rdmsr
1721 * counterpart for further detail.
1722 */
1723 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
1724 break;
2b036c6b
BO		 1725 case MSR_AMD64_OSVW_ID_LENGTH:
1726 if (!guest_cpuid_has_osvw(vcpu))
1727 return 1;
1728 vcpu->arch.osvw.length = data;
1729 break;
1730 case MSR_AMD64_OSVW_STATUS:
1731 if (!guest_cpuid_has_osvw(vcpu))
1732 return 1;
1733 vcpu->arch.osvw.status = data;
1734 break;
15c4a640 1735 default:
ffde22ac
ES		 1736 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1737 return xen_hvm_config(vcpu, data);
f5132b01
GN		 1738 if (kvm_pmu_msr(vcpu, msr))
1739 return kvm_pmu_set_msr(vcpu, msr, data);
ed85c068
AP		 1740 if (!ignore_msrs) {
1741 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1742 msr, data);
1743 return 1;
1744 } else {
1745 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1746 msr, data);
1747 break;
1748 }
15c4a640
CO		 1749 }
1750 return 0;
1751}
1752EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1753
1754
1755/*
1756 * Reads an msr value (of 'msr_index') into 'pdata'.
1757 * Returns 0 on success, non-0 otherwise.
1758 * Assumes vcpu_load() was already called.
1759 */
1760int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1761{
1762 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1763}
1764
9ba075a6
AK		 1765static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1766{
0bed3b56
SY		 1767 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1768
9ba075a6
AK		 1769 if (!msr_mtrr_valid(msr))
1770 return 1;
1771
0bed3b56
SY		 1772 if (msr == MSR_MTRRdefType)
1773 *pdata = vcpu->arch.mtrr_state.def_type +
1774 (vcpu->arch.mtrr_state.enabled << 10);
1775 else if (msr == MSR_MTRRfix64K_00000)
1776 *pdata = p[0];
1777 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1778 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1779 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1780 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1781 else if (msr == MSR_IA32_CR_PAT)
1782 *pdata = vcpu->arch.pat;
1783 else { /* Variable MTRRs */
1784 int idx, is_mtrr_mask;
1785 u64 *pt;
1786
1787 idx = (msr - 0x200) / 2;
1788 is_mtrr_mask = msr - 0x200 - 2 * idx;
1789 if (!is_mtrr_mask)
1790 pt =
1791 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1792 else
1793 pt =
1794 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1795 *pdata = *pt;
1796 }
1797
9ba075a6
AK		 1798 return 0;
1799}
1800
890ca9ae 1801static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1802{
1803 u64 data;
890ca9ae
HY		 1804 u64 mcg_cap = vcpu->arch.mcg_cap;
1805 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1806
1807 switch (msr) {
15c4a640
CO		 1808 case MSR_IA32_P5_MC_ADDR:
1809 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1810 data = 0;
1811 break;
15c4a640 1812 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1813 data = vcpu->arch.mcg_cap;
1814 break;
c7ac679c 1815 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1816 if (!(mcg_cap & MCG_CTL_P))
1817 return 1;
1818 data = vcpu->arch.mcg_ctl;
1819 break;
1820 case MSR_IA32_MCG_STATUS:
1821 data = vcpu->arch.mcg_status;
1822 break;
1823 default:
1824 if (msr >= MSR_IA32_MC0_CTL &&
1825 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1826 u32 offset = msr - MSR_IA32_MC0_CTL;
1827 data = vcpu->arch.mce_banks[offset];
1828 break;
1829 }
1830 return 1;
1831 }
1832 *pdata = data;
1833 return 0;
1834}
1835
55cd8e5a
GN		 1836static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1837{
1838 u64 data = 0;
1839 struct kvm *kvm = vcpu->kvm;
1840
1841 switch (msr) {
1842 case HV_X64_MSR_GUEST_OS_ID:
1843 data = kvm->arch.hv_guest_os_id;
1844 break;
1845 case HV_X64_MSR_HYPERCALL:
1846 data = kvm->arch.hv_hypercall;
1847 break;
1848 default:
1849 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1850 return 1;
1851 }
1852
1853 *pdata = data;
1854 return 0;
1855}
1856
1857static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1858{
1859 u64 data = 0;
1860
1861 switch (msr) {
1862 case HV_X64_MSR_VP_INDEX: {
1863 int r;
1864 struct kvm_vcpu *v;
1865 kvm_for_each_vcpu(r, v, vcpu->kvm)
1866 if (v == vcpu)
1867 data = r;
1868 break;
1869 }
10388a07
GN		 1870 case HV_X64_MSR_EOI:
1871 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1872 case HV_X64_MSR_ICR:
1873 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1874 case HV_X64_MSR_TPR:
1875 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 1876 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 1877 data = vcpu->arch.hv_vapic;
1878 break;
55cd8e5a
GN		 1879 default:
1880 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1881 return 1;
1882 }
1883 *pdata = data;
1884 return 0;
1885}
1886
890ca9ae
HY		 1887int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1888{
1889 u64 data;
1890
1891 switch (msr) {
890ca9ae 1892 case MSR_IA32_PLATFORM_ID:
15c4a640 1893 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1894 case MSR_IA32_DEBUGCTLMSR:
1895 case MSR_IA32_LASTBRANCHFROMIP:
1896 case MSR_IA32_LASTBRANCHTOIP:
1897 case MSR_IA32_LASTINTFROMIP:
1898 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1899 case MSR_K8_SYSCFG:
1900 case MSR_K7_HWCR:
61a6bd67 1901 case MSR_VM_HSAVE_PA:
9e699624 1902 case MSR_K7_EVNTSEL0:
1f3ee616 1903 case MSR_K7_PERFCTR0:
1fdbd48c 1904 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1905 case MSR_AMD64_NB_CFG:
f7c6d140 1906 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1907 data = 0;
1908 break;
5753785f
GN		 1909 case MSR_P6_PERFCTR0:
1910 case MSR_P6_PERFCTR1:
1911 case MSR_P6_EVNTSEL0:
1912 case MSR_P6_EVNTSEL1:
1913 if (kvm_pmu_msr(vcpu, msr))
1914 return kvm_pmu_get_msr(vcpu, msr, pdata);
1915 data = 0;
1916 break;
742bc670
MT		 1917 case MSR_IA32_UCODE_REV:
1918 data = 0x100000000ULL;
1919 break;
9ba075a6
AK		 1920 case MSR_MTRRcap:
1921 data = 0x500 | KVM_NR_VAR_MTRR;
1922 break;
1923 case 0x200 ... 0x2ff:
1924 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1925 case 0xcd: /* fsb frequency */
1926 data = 3;
1927 break;
7b914098
JS		 1928 /*
1929 * MSR_EBC_FREQUENCY_ID
1930 * Conservative value valid for even the basic CPU models.
1931 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1932 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1933 * and 266MHz for model 3, or 4. Set Core Clock
1934 * Frequency to System Bus Frequency Ratio to 1 (bits
1935 * 31:24) even though these are only valid for CPU
1936 * models > 2, however guests may end up dividing or
1937 * multiplying by zero otherwise.
1938 */
1939 case MSR_EBC_FREQUENCY_ID:
1940 data = 1 << 24;
1941 break;
15c4a640
CO		 1942 case MSR_IA32_APICBASE:
1943 data = kvm_get_apic_base(vcpu);
1944 break;
0105d1a5
GN		 1945 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1946 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1947 break;
a3e06bbe
LJ		 1948 case MSR_IA32_TSCDEADLINE:
1949 data = kvm_get_lapic_tscdeadline_msr(vcpu);
1950 break;
15c4a640 1951 case MSR_IA32_MISC_ENABLE:
ad312c7c 1952 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1953 break;
847f0ad8
AG		 1954 case MSR_IA32_PERF_STATUS:
1955 /* TSC increment by tick */
1956 data = 1000ULL;
1957 /* CPU multiplier */
1958 data |= (((uint64_t)4ULL) << 40);
1959 break;
15c4a640 1960 case MSR_EFER:
f6801dff 1961 data = vcpu->arch.efer;
15c4a640 1962 break;
18068523 1963 case MSR_KVM_WALL_CLOCK:
11c6bffa 1964 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1965 data = vcpu->kvm->arch.wall_clock;
1966 break;
1967 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1968 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1969 data = vcpu->arch.time;
1970 break;
344d9588
GN		 1971 case MSR_KVM_ASYNC_PF_EN:
1972 data = vcpu->arch.apf.msr_val;
1973 break;
c9aaa895
GC		 1974 case MSR_KVM_STEAL_TIME:
1975 data = vcpu->arch.st.msr_val;
1976 break;
890ca9ae
HY		 1977 case MSR_IA32_P5_MC_ADDR:
1978 case MSR_IA32_P5_MC_TYPE:
1979 case MSR_IA32_MCG_CAP:
1980 case MSR_IA32_MCG_CTL:
1981 case MSR_IA32_MCG_STATUS:
1982 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1983 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 1984 case MSR_K7_CLK_CTL:
1985 /*
1986 * Provide expected ramp-up count for K7. All other
1987 * are set to zero, indicating minimum divisors for
1988 * every field.
1989 *
1990 * This prevents guest kernels on AMD host with CPU
1991 * type 6, model 8 and higher from exploding due to
1992 * the rdmsr failing.
1993 */
1994 data = 0x20000000;
1995 break;
55cd8e5a
GN		 1996 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1997 if (kvm_hv_msr_partition_wide(msr)) {
1998 int r;
1999 mutex_lock(&vcpu->kvm->lock);
2000 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2001 mutex_unlock(&vcpu->kvm->lock);
2002 return r;
2003 } else
2004 return get_msr_hyperv(vcpu, msr, pdata);
2005 break;
91c9c3ed 2006 case MSR_IA32_BBL_CR_CTL3:
2007 /* This legacy MSR exists but isn't fully documented in current
2008 * silicon. It is however accessed by winxp in very narrow
2009 * scenarios where it sets bit #19, itself documented as
2010 * a "reserved" bit. Best effort attempt to source coherent
2011 * read data here should the balance of the register be
2012 * interpreted by the guest:
2013 *
2014 * L2 cache control register 3: 64GB range, 256KB size,
2015 * enabled, latency 0x1, configured
2016 */
2017 data = 0xbe702111;
2018 break;
2b036c6b
BO		 2019 case MSR_AMD64_OSVW_ID_LENGTH:
2020 if (!guest_cpuid_has_osvw(vcpu))
2021 return 1;
2022 data = vcpu->arch.osvw.length;
2023 break;
2024 case MSR_AMD64_OSVW_STATUS:
2025 if (!guest_cpuid_has_osvw(vcpu))
2026 return 1;
2027 data = vcpu->arch.osvw.status;
2028 break;
15c4a640 2029 default:
f5132b01
GN		 2030 if (kvm_pmu_msr(vcpu, msr))
2031 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068
AP		 2032 if (!ignore_msrs) {
2033 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2034 return 1;
2035 } else {
2036 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2037 data = 0;
2038 }
2039 break;
15c4a640
CO		 2040 }
2041 *pdata = data;
2042 return 0;
2043}
2044EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2045
313a3dc7
CO		 2046/*
2047 * Read or write a bunch of msrs. All parameters are kernel addresses.
2048 *
2049 * @return number of msrs set successfully.
2050 */
2051static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2052 struct kvm_msr_entry *entries,
2053 int (*do_msr)(struct kvm_vcpu *vcpu,
2054 unsigned index, u64 *data))
2055{
f656ce01 2056 int i, idx;
313a3dc7 2057
f656ce01 2058 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2059 for (i = 0; i < msrs->nmsrs; ++i)
2060 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2061 break;
f656ce01 2062 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2063
313a3dc7
CO		 2064 return i;
2065}
2066
2067/*
2068 * Read or write a bunch of msrs. Parameters are user addresses.
2069 *
2070 * @return number of msrs set successfully.
2071 */
2072static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2073 int (*do_msr)(struct kvm_vcpu *vcpu,
2074 unsigned index, u64 *data),
2075 int writeback)
2076{
2077 struct kvm_msrs msrs;
2078 struct kvm_msr_entry *entries;
2079 int r, n;
2080 unsigned size;
2081
2082 r = -EFAULT;
2083 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2084 goto out;
2085
2086 r = -E2BIG;
2087 if (msrs.nmsrs >= MAX_IO_MSRS)
2088 goto out;
2089
313a3dc7 2090 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2091 entries = memdup_user(user_msrs->entries, size);
2092 if (IS_ERR(entries)) {
2093 r = PTR_ERR(entries);
313a3dc7 2094 goto out;
ff5c2c03 2095 }
313a3dc7
CO		 2096
2097 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2098 if (r < 0)
2099 goto out_free;
2100
2101 r = -EFAULT;
2102 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2103 goto out_free;
2104
2105 r = n;
2106
2107out_free:
7a73c028 2108 kfree(entries);
313a3dc7
CO		 2109out:
2110 return r;
2111}
2112
018d00d2
ZX		 2113int kvm_dev_ioctl_check_extension(long ext)
2114{
2115 int r;
2116
2117 switch (ext) {
2118 case KVM_CAP_IRQCHIP:
2119 case KVM_CAP_HLT:
2120 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2121 case KVM_CAP_SET_TSS_ADDR:
07716717 2122 case KVM_CAP_EXT_CPUID:
c8076604 2123 case KVM_CAP_CLOCKSOURCE:
7837699f 2124 case KVM_CAP_PIT:
a28e4f5a 2125 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2126 case KVM_CAP_MP_STATE:
ed848624 2127 case KVM_CAP_SYNC_MMU:
a355c85c 2128 case KVM_CAP_USER_NMI:
52d939a0 2129 case KVM_CAP_REINJECT_CONTROL:
4925663a 2130 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 2131 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 2132 case KVM_CAP_IRQFD:
d34e6b17 2133 case KVM_CAP_IOEVENTFD:
c5ff41ce 2134 case KVM_CAP_PIT2:
e9f42757 2135 case KVM_CAP_PIT_STATE2:
b927a3ce 2136 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2137 case KVM_CAP_XEN_HVM:
afbcf7ab 2138 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2139 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2140 case KVM_CAP_HYPERV:
10388a07 2141 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2142 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2143 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2144 case KVM_CAP_DEBUGREGS:
d2be1651 2145 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2146 case KVM_CAP_XSAVE:
344d9588 2147 case KVM_CAP_ASYNC_PF:
92a1f12d 2148 case KVM_CAP_GET_TSC_KHZ:
07700a94 2149 case KVM_CAP_PCI_2_3:
1c0b28c2 2150 case KVM_CAP_KVMCLOCK_CTRL:
018d00d2
ZX		 2151 r = 1;
2152 break;
542472b5
LV		 2153 case KVM_CAP_COALESCED_MMIO:
2154 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2155 break;
774ead3a
AK		 2156 case KVM_CAP_VAPIC:
2157 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2158 break;
f725230a 2159 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2160 r = KVM_SOFT_MAX_VCPUS;
2161 break;
2162 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2163 r = KVM_MAX_VCPUS;
2164 break;
a988b910
AK		 2165 case KVM_CAP_NR_MEMSLOTS:
2166 r = KVM_MEMORY_SLOTS;
2167 break;
a68a6a72
MT		 2168 case KVM_CAP_PV_MMU: /* obsolete */
2169 r = 0;
2f333bcb 2170 break;
62c476c7 2171 case KVM_CAP_IOMMU:
a1b60c1c 2172 r = iommu_present(&pci_bus_type);
62c476c7 2173 break;
890ca9ae
HY		 2174 case KVM_CAP_MCE:
2175 r = KVM_MAX_MCE_BANKS;
2176 break;
2d5b5a66
SY		 2177 case KVM_CAP_XCRS:
2178 r = cpu_has_xsave;
2179 break;
92a1f12d
JR		 2180 case KVM_CAP_TSC_CONTROL:
2181 r = kvm_has_tsc_control;
2182 break;
4d25a066
JK		 2183 case KVM_CAP_TSC_DEADLINE_TIMER:
2184 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2185 break;
018d00d2
ZX		 2186 default:
2187 r = 0;
2188 break;
2189 }
2190 return r;
2191
2192}
2193
043405e1
CO		 2194long kvm_arch_dev_ioctl(struct file *filp,
2195 unsigned int ioctl, unsigned long arg)
2196{
2197 void __user *argp = (void __user *)arg;
2198 long r;
2199
2200 switch (ioctl) {
2201 case KVM_GET_MSR_INDEX_LIST: {
2202 struct kvm_msr_list __user *user_msr_list = argp;
2203 struct kvm_msr_list msr_list;
2204 unsigned n;
2205
2206 r = -EFAULT;
2207 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2208 goto out;
2209 n = msr_list.nmsrs;
2210 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2211 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2212 goto out;
2213 r = -E2BIG;
e125e7b6 2214 if (n < msr_list.nmsrs)
043405e1
CO		 2215 goto out;
2216 r = -EFAULT;
2217 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2218 num_msrs_to_save * sizeof(u32)))
2219 goto out;
e125e7b6 2220 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2221 &emulated_msrs,
2222 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2223 goto out;
2224 r = 0;
2225 break;
2226 }
674eea0f
AK		 2227 case KVM_GET_SUPPORTED_CPUID: {
2228 struct kvm_cpuid2 __user *cpuid_arg = argp;
2229 struct kvm_cpuid2 cpuid;
2230
2231 r = -EFAULT;
2232 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2233 goto out;
2234 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2235 cpuid_arg->entries);
674eea0f
AK		 2236 if (r)
2237 goto out;
2238
2239 r = -EFAULT;
2240 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2241 goto out;
2242 r = 0;
2243 break;
2244 }
890ca9ae
HY		 2245 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2246 u64 mce_cap;
2247
2248 mce_cap = KVM_MCE_CAP_SUPPORTED;
2249 r = -EFAULT;
2250 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2251 goto out;
2252 r = 0;
2253 break;
2254 }
043405e1
CO		 2255 default:
2256 r = -EINVAL;
2257 }
2258out:
2259 return r;
2260}
2261
f5f48ee1
SY		 2262static void wbinvd_ipi(void *garbage)
2263{
2264 wbinvd();
2265}
2266
2267static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2268{
2269 return vcpu->kvm->arch.iommu_domain &&
2270 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2271}
2272
313a3dc7
CO		 2273void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2274{
f5f48ee1
SY		 2275 /* Address WBINVD may be executed by guest */
2276 if (need_emulate_wbinvd(vcpu)) {
2277 if (kvm_x86_ops->has_wbinvd_exit())
2278 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2279 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2280 smp_call_function_single(vcpu->cpu,
2281 wbinvd_ipi, NULL, 1);
2282 }
2283
313a3dc7 2284 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2285
0dd6a6ed
ZA		 2286 /* Apply any externally detected TSC adjustments (due to suspend) */
2287 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2288 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2289 vcpu->arch.tsc_offset_adjustment = 0;
2290 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2291 }
8f6055cb 2292
48434c20 2293 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2294 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2295 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2296 if (tsc_delta < 0)
2297 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2298 if (check_tsc_unstable()) {
b183aa58
ZA		 2299 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2300 vcpu->arch.last_guest_tsc);
2301 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2302 vcpu->arch.tsc_catchup = 1;
c285545f 2303 }
1aa8ceef 2304 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2305 if (vcpu->cpu != cpu)
2306 kvm_migrate_timers(vcpu);
e48672fa 2307 vcpu->cpu = cpu;
6b7d7e76 2308 }
c9aaa895
GC		 2309
2310 accumulate_steal_time(vcpu);
2311 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2312}
2313
2314void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2315{
02daab21 2316 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2317 kvm_put_guest_fpu(vcpu);
6f526ec5 2318 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2319}
2320
313a3dc7
CO		 2321static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2322 struct kvm_lapic_state *s)
2323{
ad312c7c 2324 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2325
2326 return 0;
2327}
2328
2329static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2330 struct kvm_lapic_state *s)
2331{
ad312c7c 2332 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2333 kvm_apic_post_state_restore(vcpu);
cb142eb7 2334 update_cr8_intercept(vcpu);
313a3dc7
CO		 2335
2336 return 0;
2337}
2338
f77bc6a4
ZX		 2339static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2340 struct kvm_interrupt *irq)
2341{
2342 if (irq->irq < 0 || irq->irq >= 256)
2343 return -EINVAL;
2344 if (irqchip_in_kernel(vcpu->kvm))
2345 return -ENXIO;
f77bc6a4 2346
66fd3f7f 2347 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2348 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2349
f77bc6a4
ZX		 2350 return 0;
2351}
2352
c4abb7c9
JK		 2353static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2354{
c4abb7c9 2355 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2356
2357 return 0;
2358}
2359
b209749f
AK		 2360static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2361 struct kvm_tpr_access_ctl *tac)
2362{
2363 if (tac->flags)
2364 return -EINVAL;
2365 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2366 return 0;
2367}
2368
890ca9ae
HY		 2369static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2370 u64 mcg_cap)
2371{
2372 int r;
2373 unsigned bank_num = mcg_cap & 0xff, bank;
2374
2375 r = -EINVAL;
a9e38c3e 2376 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2377 goto out;
2378 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2379 goto out;
2380 r = 0;
2381 vcpu->arch.mcg_cap = mcg_cap;
2382 /* Init IA32_MCG_CTL to all 1s */
2383 if (mcg_cap & MCG_CTL_P)
2384 vcpu->arch.mcg_ctl = ~(u64)0;
2385 /* Init IA32_MCi_CTL to all 1s */
2386 for (bank = 0; bank < bank_num; bank++)
2387 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2388out:
2389 return r;
2390}
2391
2392static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2393 struct kvm_x86_mce *mce)
2394{
2395 u64 mcg_cap = vcpu->arch.mcg_cap;
2396 unsigned bank_num = mcg_cap & 0xff;
2397 u64 *banks = vcpu->arch.mce_banks;
2398
2399 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2400 return -EINVAL;
2401 /*
2402 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2403 * reporting is disabled
2404 */
2405 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2406 vcpu->arch.mcg_ctl != ~(u64)0)
2407 return 0;
2408 banks += 4 * mce->bank;
2409 /*
2410 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2411 * reporting is disabled for the bank
2412 */
2413 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2414 return 0;
2415 if (mce->status & MCI_STATUS_UC) {
2416 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2417 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2418 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2419 return 0;
2420 }
2421 if (banks[1] & MCI_STATUS_VAL)
2422 mce->status |= MCI_STATUS_OVER;
2423 banks[2] = mce->addr;
2424 banks[3] = mce->misc;
2425 vcpu->arch.mcg_status = mce->mcg_status;
2426 banks[1] = mce->status;
2427 kvm_queue_exception(vcpu, MC_VECTOR);
2428 } else if (!(banks[1] & MCI_STATUS_VAL)
2429 || !(banks[1] & MCI_STATUS_UC)) {
2430 if (banks[1] & MCI_STATUS_VAL)
2431 mce->status |= MCI_STATUS_OVER;
2432 banks[2] = mce->addr;
2433 banks[3] = mce->misc;
2434 banks[1] = mce->status;
2435 } else
2436 banks[1] |= MCI_STATUS_OVER;
2437 return 0;
2438}
2439
3cfc3092
JK		 2440static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2441 struct kvm_vcpu_events *events)
2442{
7460fb4a 2443 process_nmi(vcpu);
03b82a30
JK		 2444 events->exception.injected =
2445 vcpu->arch.exception.pending &&
2446 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2447 events->exception.nr = vcpu->arch.exception.nr;
2448 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2449 events->exception.pad = 0;
3cfc3092
JK		 2450 events->exception.error_code = vcpu->arch.exception.error_code;
2451
03b82a30
JK		 2452 events->interrupt.injected =
2453 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2454 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2455 events->interrupt.soft = 0;
48005f64
JK		 2456 events->interrupt.shadow =
2457 kvm_x86_ops->get_interrupt_shadow(vcpu,
2458 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2459
2460 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2461 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2462 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2463 events->nmi.pad = 0;
3cfc3092
JK		 2464
2465 events->sipi_vector = vcpu->arch.sipi_vector;
2466
dab4b911 2467 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2468 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2469 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2470 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2471}
2472
2473static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2474 struct kvm_vcpu_events *events)
2475{
dab4b911 2476 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2477 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2478 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2479 return -EINVAL;
2480
7460fb4a 2481 process_nmi(vcpu);
3cfc3092
JK		 2482 vcpu->arch.exception.pending = events->exception.injected;
2483 vcpu->arch.exception.nr = events->exception.nr;
2484 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2485 vcpu->arch.exception.error_code = events->exception.error_code;
2486
2487 vcpu->arch.interrupt.pending = events->interrupt.injected;
2488 vcpu->arch.interrupt.nr = events->interrupt.nr;
2489 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2490 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2491 kvm_x86_ops->set_interrupt_shadow(vcpu,
2492 events->interrupt.shadow);
3cfc3092
JK		 2493
2494 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2495 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2496 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2497 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2498
dab4b911
JK		 2499 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2500 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2501
3842d135
AK		 2502 kvm_make_request(KVM_REQ_EVENT, vcpu);
2503
3cfc3092
JK		 2504 return 0;
2505}
2506
a1efbe77
JK		 2507static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2508 struct kvm_debugregs *dbgregs)
2509{
a1efbe77
JK		 2510 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2511 dbgregs->dr6 = vcpu->arch.dr6;
2512 dbgregs->dr7 = vcpu->arch.dr7;
2513 dbgregs->flags = 0;
97e69aa6 2514 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2515}
2516
2517static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2518 struct kvm_debugregs *dbgregs)
2519{
2520 if (dbgregs->flags)
2521 return -EINVAL;
2522
a1efbe77
JK		 2523 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2524 vcpu->arch.dr6 = dbgregs->dr6;
2525 vcpu->arch.dr7 = dbgregs->dr7;
2526
a1efbe77
JK		 2527 return 0;
2528}
2529
2d5b5a66
SY		 2530static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2531 struct kvm_xsave *guest_xsave)
2532{
2533 if (cpu_has_xsave)
2534 memcpy(guest_xsave->region,
2535 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2536 xstate_size);
2d5b5a66
SY		 2537 else {
2538 memcpy(guest_xsave->region,
2539 &vcpu->arch.guest_fpu.state->fxsave,
2540 sizeof(struct i387_fxsave_struct));
2541 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2542 XSTATE_FPSSE;
2543 }
2544}
2545
2546static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2547 struct kvm_xsave *guest_xsave)
2548{
2549 u64 xstate_bv =
2550 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2551
2552 if (cpu_has_xsave)
2553 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2554 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2555 else {
2556 if (xstate_bv & ~XSTATE_FPSSE)
2557 return -EINVAL;
2558 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2559 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2560 }
2561 return 0;
2562}
2563
2564static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2565 struct kvm_xcrs *guest_xcrs)
2566{
2567 if (!cpu_has_xsave) {
2568 guest_xcrs->nr_xcrs = 0;
2569 return;
2570 }
2571
2572 guest_xcrs->nr_xcrs = 1;
2573 guest_xcrs->flags = 0;
2574 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2575 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2576}
2577
2578static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2579 struct kvm_xcrs *guest_xcrs)
2580{
2581 int i, r = 0;
2582
2583 if (!cpu_has_xsave)
2584 return -EINVAL;
2585
2586 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2587 return -EINVAL;
2588
2589 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2590 /* Only support XCR0 currently */
2591 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2592 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2593 guest_xcrs->xcrs[0].value);
2594 break;
2595 }
2596 if (r)
2597 r = -EINVAL;
2598 return r;
2599}
2600
1c0b28c2
EM		 2601/*
2602 * kvm_set_guest_paused() indicates to the guest kernel that it has been
2603 * stopped by the hypervisor. This function will be called from the host only.
2604 * EINVAL is returned when the host attempts to set the flag for a guest that
2605 * does not support pv clocks.
2606 */
2607static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
2608{
2609 struct pvclock_vcpu_time_info *src = &vcpu->arch.hv_clock;
2610 if (!vcpu->arch.time_page)
2611 return -EINVAL;
2612 src->flags |= PVCLOCK_GUEST_STOPPED;
2613 mark_page_dirty(vcpu->kvm, vcpu->arch.time >> PAGE_SHIFT);
2614 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2615 return 0;
2616}
2617
313a3dc7
CO		 2618long kvm_arch_vcpu_ioctl(struct file *filp,
2619 unsigned int ioctl, unsigned long arg)
2620{
2621 struct kvm_vcpu *vcpu = filp->private_data;
2622 void __user *argp = (void __user *)arg;
2623 int r;
d1ac91d8
AK		 2624 union {
2625 struct kvm_lapic_state *lapic;
2626 struct kvm_xsave *xsave;
2627 struct kvm_xcrs *xcrs;
2628 void *buffer;
2629 } u;
2630
2631 u.buffer = NULL;
313a3dc7
CO		 2632 switch (ioctl) {
2633 case KVM_GET_LAPIC: {
2204ae3c
MT		 2634 r = -EINVAL;
2635 if (!vcpu->arch.apic)
2636 goto out;
d1ac91d8 2637 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2638
b772ff36 2639 r = -ENOMEM;
d1ac91d8 2640 if (!u.lapic)
b772ff36 2641 goto out;
d1ac91d8 2642 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2643 if (r)
2644 goto out;
2645 r = -EFAULT;
d1ac91d8 2646 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2647 goto out;
2648 r = 0;
2649 break;
2650 }
2651 case KVM_SET_LAPIC: {
2204ae3c
MT		 2652 r = -EINVAL;
2653 if (!vcpu->arch.apic)
2654 goto out;
ff5c2c03
SL		 2655 u.lapic = memdup_user(argp, sizeof(*u.lapic));
2656 if (IS_ERR(u.lapic)) {
2657 r = PTR_ERR(u.lapic);
313a3dc7 2658 goto out;
ff5c2c03
SL		 2659 }
2660
d1ac91d8 2661 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2662 if (r)
2663 goto out;
2664 r = 0;
2665 break;
2666 }
f77bc6a4
ZX		 2667 case KVM_INTERRUPT: {
2668 struct kvm_interrupt irq;
2669
2670 r = -EFAULT;
2671 if (copy_from_user(&irq, argp, sizeof irq))
2672 goto out;
2673 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2674 if (r)
2675 goto out;
2676 r = 0;
2677 break;
2678 }
c4abb7c9
JK		 2679 case KVM_NMI: {
2680 r = kvm_vcpu_ioctl_nmi(vcpu);
2681 if (r)
2682 goto out;
2683 r = 0;
2684 break;
2685 }
313a3dc7
CO		 2686 case KVM_SET_CPUID: {
2687 struct kvm_cpuid __user *cpuid_arg = argp;
2688 struct kvm_cpuid cpuid;
2689
2690 r = -EFAULT;
2691 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2692 goto out;
2693 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2694 if (r)
2695 goto out;
2696 break;
2697 }
07716717
DK		 2698 case KVM_SET_CPUID2: {
2699 struct kvm_cpuid2 __user *cpuid_arg = argp;
2700 struct kvm_cpuid2 cpuid;
2701
2702 r = -EFAULT;
2703 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2704 goto out;
2705 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2706 cpuid_arg->entries);
07716717
DK		 2707 if (r)
2708 goto out;
2709 break;
2710 }
2711 case KVM_GET_CPUID2: {
2712 struct kvm_cpuid2 __user *cpuid_arg = argp;
2713 struct kvm_cpuid2 cpuid;
2714
2715 r = -EFAULT;
2716 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2717 goto out;
2718 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2719 cpuid_arg->entries);
07716717
DK		 2720 if (r)
2721 goto out;
2722 r = -EFAULT;
2723 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2724 goto out;
2725 r = 0;
2726 break;
2727 }
313a3dc7
CO		 2728 case KVM_GET_MSRS:
2729 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2730 break;
2731 case KVM_SET_MSRS:
2732 r = msr_io(vcpu, argp, do_set_msr, 0);
2733 break;
b209749f
AK		 2734 case KVM_TPR_ACCESS_REPORTING: {
2735 struct kvm_tpr_access_ctl tac;
2736
2737 r = -EFAULT;
2738 if (copy_from_user(&tac, argp, sizeof tac))
2739 goto out;
2740 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2741 if (r)
2742 goto out;
2743 r = -EFAULT;
2744 if (copy_to_user(argp, &tac, sizeof tac))
2745 goto out;
2746 r = 0;
2747 break;
2748 };
b93463aa
AK		 2749 case KVM_SET_VAPIC_ADDR: {
2750 struct kvm_vapic_addr va;
2751
2752 r = -EINVAL;
2753 if (!irqchip_in_kernel(vcpu->kvm))
2754 goto out;
2755 r = -EFAULT;
2756 if (copy_from_user(&va, argp, sizeof va))
2757 goto out;
2758 r = 0;
2759 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2760 break;
2761 }
890ca9ae
HY		 2762 case KVM_X86_SETUP_MCE: {
2763 u64 mcg_cap;
2764
2765 r = -EFAULT;
2766 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2767 goto out;
2768 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2769 break;
2770 }
2771 case KVM_X86_SET_MCE: {
2772 struct kvm_x86_mce mce;
2773
2774 r = -EFAULT;
2775 if (copy_from_user(&mce, argp, sizeof mce))
2776 goto out;
2777 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2778 break;
2779 }
3cfc3092
JK		 2780 case KVM_GET_VCPU_EVENTS: {
2781 struct kvm_vcpu_events events;
2782
2783 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2784
2785 r = -EFAULT;
2786 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2787 break;
2788 r = 0;
2789 break;
2790 }
2791 case KVM_SET_VCPU_EVENTS: {
2792 struct kvm_vcpu_events events;
2793
2794 r = -EFAULT;
2795 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2796 break;
2797
2798 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2799 break;
2800 }
a1efbe77
JK		 2801 case KVM_GET_DEBUGREGS: {
2802 struct kvm_debugregs dbgregs;
2803
2804 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2805
2806 r = -EFAULT;
2807 if (copy_to_user(argp, &dbgregs,
2808 sizeof(struct kvm_debugregs)))
2809 break;
2810 r = 0;
2811 break;
2812 }
2813 case KVM_SET_DEBUGREGS: {
2814 struct kvm_debugregs dbgregs;
2815
2816 r = -EFAULT;
2817 if (copy_from_user(&dbgregs, argp,
2818 sizeof(struct kvm_debugregs)))
2819 break;
2820
2821 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2822 break;
2823 }
2d5b5a66 2824 case KVM_GET_XSAVE: {
d1ac91d8 2825 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2826 r = -ENOMEM;
d1ac91d8 2827 if (!u.xsave)
2d5b5a66
SY		 2828 break;
2829
d1ac91d8 2830 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2831
2832 r = -EFAULT;
d1ac91d8 2833 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2834 break;
2835 r = 0;
2836 break;
2837 }
2838 case KVM_SET_XSAVE: {
ff5c2c03
SL		 2839 u.xsave = memdup_user(argp, sizeof(*u.xsave));
2840 if (IS_ERR(u.xsave)) {
2841 r = PTR_ERR(u.xsave);
2842 goto out;
2843 }
2d5b5a66 2844
d1ac91d8 2845 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2846 break;
2847 }
2848 case KVM_GET_XCRS: {
d1ac91d8 2849 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2850 r = -ENOMEM;
d1ac91d8 2851 if (!u.xcrs)
2d5b5a66
SY		 2852 break;
2853
d1ac91d8 2854 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2855
2856 r = -EFAULT;
d1ac91d8 2857 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 2858 sizeof(struct kvm_xcrs)))
2859 break;
2860 r = 0;
2861 break;
2862 }
2863 case KVM_SET_XCRS: {
ff5c2c03
SL		 2864 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
2865 if (IS_ERR(u.xcrs)) {
2866 r = PTR_ERR(u.xcrs);
2867 goto out;
2868 }
2d5b5a66 2869
d1ac91d8 2870 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2871 break;
2872 }
92a1f12d
JR		 2873 case KVM_SET_TSC_KHZ: {
2874 u32 user_tsc_khz;
2875
2876 r = -EINVAL;
92a1f12d
JR		 2877 user_tsc_khz = (u32)arg;
2878
2879 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
2880 goto out;
2881
cc578287
ZA		 2882 if (user_tsc_khz == 0)
2883 user_tsc_khz = tsc_khz;
2884
2885 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 2886
2887 r = 0;
2888 goto out;
2889 }
2890 case KVM_GET_TSC_KHZ: {
cc578287 2891 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 2892 goto out;
2893 }
1c0b28c2
EM		 2894 case KVM_KVMCLOCK_CTRL: {
2895 r = kvm_set_guest_paused(vcpu);
2896 goto out;
2897 }
313a3dc7
CO		 2898 default:
2899 r = -EINVAL;
2900 }
2901out:
d1ac91d8 2902 kfree(u.buffer);
313a3dc7
CO		 2903 return r;
2904}
2905
5b1c1493
CO		 2906int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
2907{
2908 return VM_FAULT_SIGBUS;
2909}
2910
1fe779f8
CO		 2911static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2912{
2913 int ret;
2914
2915 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2916 return -1;
2917 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2918 return ret;
2919}
2920
b927a3ce
SY		 2921static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2922 u64 ident_addr)
2923{
2924 kvm->arch.ept_identity_map_addr = ident_addr;
2925 return 0;
2926}
2927
1fe779f8
CO		 2928static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2929 u32 kvm_nr_mmu_pages)
2930{
2931 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2932 return -EINVAL;
2933
79fac95e 2934 mutex_lock(&kvm->slots_lock);
7c8a83b7 2935 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2936
2937 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2938 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2939
7c8a83b7 2940 spin_unlock(&kvm->mmu_lock);
79fac95e 2941 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2942 return 0;
2943}
2944
2945static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2946{
39de71ec 2947 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 2948}
2949
1fe779f8
CO		 2950static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2951{
2952 int r;
2953
2954 r = 0;
2955 switch (chip->chip_id) {
2956 case KVM_IRQCHIP_PIC_MASTER:
2957 memcpy(&chip->chip.pic,
2958 &pic_irqchip(kvm)->pics[0],
2959 sizeof(struct kvm_pic_state));
2960 break;
2961 case KVM_IRQCHIP_PIC_SLAVE:
2962 memcpy(&chip->chip.pic,
2963 &pic_irqchip(kvm)->pics[1],
2964 sizeof(struct kvm_pic_state));
2965 break;
2966 case KVM_IRQCHIP_IOAPIC:
eba0226b 2967 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2968 break;
2969 default:
2970 r = -EINVAL;
2971 break;
2972 }
2973 return r;
2974}
2975
2976static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2977{
2978 int r;
2979
2980 r = 0;
2981 switch (chip->chip_id) {
2982 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 2983 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2984 memcpy(&pic_irqchip(kvm)->pics[0],
2985 &chip->chip.pic,
2986 sizeof(struct kvm_pic_state));
f4f51050 2987 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2988 break;
2989 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 2990 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2991 memcpy(&pic_irqchip(kvm)->pics[1],
2992 &chip->chip.pic,
2993 sizeof(struct kvm_pic_state));
f4f51050 2994 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2995 break;
2996 case KVM_IRQCHIP_IOAPIC:
eba0226b 2997 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2998 break;
2999 default:
3000 r = -EINVAL;
3001 break;
3002 }
3003 kvm_pic_update_irq(pic_irqchip(kvm));
3004 return r;
3005}
3006
e0f63cb9
SY		 3007static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3008{
3009 int r = 0;
3010
894a9c55 3011 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3012 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3013 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3014 return r;
3015}
3016
3017static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3018{
3019 int r = 0;
3020
894a9c55 3021 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3022 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3023 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3024 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3025 return r;
3026}
3027
3028static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3029{
3030 int r = 0;
3031
3032 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3033 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3034 sizeof(ps->channels));
3035 ps->flags = kvm->arch.vpit->pit_state.flags;
3036 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3037 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3038 return r;
3039}
3040
3041static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3042{
3043 int r = 0, start = 0;
3044 u32 prev_legacy, cur_legacy;
3045 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3046 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3047 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3048 if (!prev_legacy && cur_legacy)
3049 start = 1;
3050 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3051 sizeof(kvm->arch.vpit->pit_state.channels));
3052 kvm->arch.vpit->pit_state.flags = ps->flags;
3053 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3054 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3055 return r;
3056}
3057
52d939a0
MT		 3058static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3059 struct kvm_reinject_control *control)
3060{
3061 if (!kvm->arch.vpit)
3062 return -ENXIO;
894a9c55 3063 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 3064 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 3065 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3066 return 0;
3067}
3068
95d4c16c
TY		 3069/**
3070 * write_protect_slot - write protect a slot for dirty logging
3071 * @kvm: the kvm instance
3072 * @memslot: the slot we protect
3073 * @dirty_bitmap: the bitmap indicating which pages are dirty
3074 * @nr_dirty_pages: the number of dirty pages
3075 *
3076 * We have two ways to find all sptes to protect:
3077 * 1. Use kvm_mmu_slot_remove_write_access() which walks all shadow pages and
3078 * checks ones that have a spte mapping a page in the slot.
3079 * 2. Use kvm_mmu_rmap_write_protect() for each gfn found in the bitmap.
3080 *
3081 * Generally speaking, if there are not so many dirty pages compared to the
3082 * number of shadow pages, we should use the latter.
3083 *
3084 * Note that letting others write into a page marked dirty in the old bitmap
3085 * by using the remaining tlb entry is not a problem. That page will become
3086 * write protected again when we flush the tlb and then be reported dirty to
3087 * the user space by copying the old bitmap.
3088 */
3089static void write_protect_slot(struct kvm *kvm,
3090 struct kvm_memory_slot *memslot,
3091 unsigned long *dirty_bitmap,
3092 unsigned long nr_dirty_pages)
3093{
6dbf79e7
TY		 3094 spin_lock(&kvm->mmu_lock);
3095
95d4c16c
TY		 3096 /* Not many dirty pages compared to # of shadow pages. */
3097 if (nr_dirty_pages < kvm->arch.n_used_mmu_pages) {
5dc99b23 3098 gfn_t offset;
95d4c16c 3099
5dc99b23
TY		 3100 for_each_set_bit(offset, dirty_bitmap, memslot->npages)
3101 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, 1);
95d4c16c 3102
95d4c16c 3103 kvm_flush_remote_tlbs(kvm);
6dbf79e7 3104 } else
95d4c16c 3105 kvm_mmu_slot_remove_write_access(kvm, memslot->id);
6dbf79e7
TY		 3106
3107 spin_unlock(&kvm->mmu_lock);
95d4c16c
TY		 3108}
3109
5bb064dc
ZX		 3110/*
3111 * Get (and clear) the dirty memory log for a memory slot.
3112 */
3113int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3114 struct kvm_dirty_log *log)
3115{
7850ac54 3116 int r;
5bb064dc 3117 struct kvm_memory_slot *memslot;
95d4c16c 3118 unsigned long n, nr_dirty_pages;
5bb064dc 3119
79fac95e 3120 mutex_lock(&kvm->slots_lock);
5bb064dc 3121
b050b015
MT		 3122 r = -EINVAL;
3123 if (log->slot >= KVM_MEMORY_SLOTS)
3124 goto out;
3125
28a37544 3126 memslot = id_to_memslot(kvm->memslots, log->slot);
b050b015
MT		 3127 r = -ENOENT;
3128 if (!memslot->dirty_bitmap)
3129 goto out;
3130
87bf6e7d 3131 n = kvm_dirty_bitmap_bytes(memslot);
95d4c16c 3132 nr_dirty_pages = memslot->nr_dirty_pages;
b050b015 3133
5bb064dc 3134 /* If nothing is dirty, don't bother messing with page tables. */
95d4c16c 3135 if (nr_dirty_pages) {
b050b015 3136 struct kvm_memslots *slots, *old_slots;
28a37544 3137 unsigned long *dirty_bitmap, *dirty_bitmap_head;
b050b015 3138
28a37544
XG		 3139 dirty_bitmap = memslot->dirty_bitmap;
3140 dirty_bitmap_head = memslot->dirty_bitmap_head;
3141 if (dirty_bitmap == dirty_bitmap_head)
3142 dirty_bitmap_head += n / sizeof(long);
3143 memset(dirty_bitmap_head, 0, n);
b050b015 3144
914ebccd 3145 r = -ENOMEM;
cdfca7b3 3146 slots = kmemdup(kvm->memslots, sizeof(*kvm->memslots), GFP_KERNEL);
515a0127 3147 if (!slots)
914ebccd 3148 goto out;
cdfca7b3 3149
28a37544 3150 memslot = id_to_memslot(slots, log->slot);
95d4c16c 3151 memslot->nr_dirty_pages = 0;
28a37544 3152 memslot->dirty_bitmap = dirty_bitmap_head;
be593d62 3153 update_memslots(slots, NULL);
b050b015
MT		 3154
3155 old_slots = kvm->memslots;
3156 rcu_assign_pointer(kvm->memslots, slots);
3157 synchronize_srcu_expedited(&kvm->srcu);
b050b015 3158 kfree(old_slots);
914ebccd 3159
95d4c16c 3160 write_protect_slot(kvm, memslot, dirty_bitmap, nr_dirty_pages);
edde99ce 3161
914ebccd 3162 r = -EFAULT;
515a0127 3163 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
914ebccd 3164 goto out;
914ebccd
TY		 3165 } else {
3166 r = -EFAULT;
3167 if (clear_user(log->dirty_bitmap, n))
3168 goto out;
5bb064dc 3169 }
b050b015 3170
5bb064dc
ZX		 3171 r = 0;
3172out:
79fac95e 3173 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3174 return r;
3175}
3176
1fe779f8
CO		 3177long kvm_arch_vm_ioctl(struct file *filp,
3178 unsigned int ioctl, unsigned long arg)
3179{
3180 struct kvm *kvm = filp->private_data;
3181 void __user *argp = (void __user *)arg;
367e1319 3182 int r = -ENOTTY;
f0d66275
DH		 3183 /*
3184 * This union makes it completely explicit to gcc-3.x
3185 * that these two variables' stack usage should be
3186 * combined, not added together.
3187 */
3188 union {
3189 struct kvm_pit_state ps;
e9f42757 3190 struct kvm_pit_state2 ps2;
c5ff41ce 3191 struct kvm_pit_config pit_config;
f0d66275 3192 } u;
1fe779f8
CO		 3193
3194 switch (ioctl) {
3195 case KVM_SET_TSS_ADDR:
3196 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3197 if (r < 0)
3198 goto out;
3199 break;
b927a3ce
SY		 3200 case KVM_SET_IDENTITY_MAP_ADDR: {
3201 u64 ident_addr;
3202
3203 r = -EFAULT;
3204 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3205 goto out;
3206 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3207 if (r < 0)
3208 goto out;
3209 break;
3210 }
1fe779f8
CO		 3211 case KVM_SET_NR_MMU_PAGES:
3212 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3213 if (r)
3214 goto out;
3215 break;
3216 case KVM_GET_NR_MMU_PAGES:
3217 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3218 break;
3ddea128
MT		 3219 case KVM_CREATE_IRQCHIP: {
3220 struct kvm_pic *vpic;
3221
3222 mutex_lock(&kvm->lock);
3223 r = -EEXIST;
3224 if (kvm->arch.vpic)
3225 goto create_irqchip_unlock;
3e515705
AK		 3226 r = -EINVAL;
3227 if (atomic_read(&kvm->online_vcpus))
3228 goto create_irqchip_unlock;
1fe779f8 3229 r = -ENOMEM;
3ddea128
MT		 3230 vpic = kvm_create_pic(kvm);
3231 if (vpic) {
1fe779f8
CO		 3232 r = kvm_ioapic_init(kvm);
3233 if (r) {
175504cd 3234 mutex_lock(&kvm->slots_lock);
72bb2fcd 3235 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3236 &vpic->dev_master);
3237 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3238 &vpic->dev_slave);
3239 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3240 &vpic->dev_eclr);
175504cd 3241 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3242 kfree(vpic);
3243 goto create_irqchip_unlock;
1fe779f8
CO		 3244 }
3245 } else
3ddea128
MT		 3246 goto create_irqchip_unlock;
3247 smp_wmb();
3248 kvm->arch.vpic = vpic;
3249 smp_wmb();
399ec807
AK		 3250 r = kvm_setup_default_irq_routing(kvm);
3251 if (r) {
175504cd 3252 mutex_lock(&kvm->slots_lock);
3ddea128 3253 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3254 kvm_ioapic_destroy(kvm);
3255 kvm_destroy_pic(kvm);
3ddea128 3256 mutex_unlock(&kvm->irq_lock);
175504cd 3257 mutex_unlock(&kvm->slots_lock);
399ec807 3258 }
3ddea128
MT		 3259 create_irqchip_unlock:
3260 mutex_unlock(&kvm->lock);
1fe779f8 3261 break;
3ddea128 3262 }
7837699f 3263 case KVM_CREATE_PIT:
c5ff41ce
JK		 3264 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3265 goto create_pit;
3266 case KVM_CREATE_PIT2:
3267 r = -EFAULT;
3268 if (copy_from_user(&u.pit_config, argp,
3269 sizeof(struct kvm_pit_config)))
3270 goto out;
3271 create_pit:
79fac95e 3272 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3273 r = -EEXIST;
3274 if (kvm->arch.vpit)
3275 goto create_pit_unlock;
7837699f 3276 r = -ENOMEM;
c5ff41ce 3277 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3278 if (kvm->arch.vpit)
3279 r = 0;
269e05e4 3280 create_pit_unlock:
79fac95e 3281 mutex_unlock(&kvm->slots_lock);
7837699f 3282 break;
4925663a 3283 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3284 case KVM_IRQ_LINE: {
3285 struct kvm_irq_level irq_event;
3286
3287 r = -EFAULT;
3288 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3289 goto out;
160d2f6c 3290 r = -ENXIO;
1fe779f8 3291 if (irqchip_in_kernel(kvm)) {
4925663a 3292 __s32 status;
4925663a
GN		 3293 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3294 irq_event.irq, irq_event.level);
4925663a 3295 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3296 r = -EFAULT;
4925663a
GN		 3297 irq_event.status = status;
3298 if (copy_to_user(argp, &irq_event,
3299 sizeof irq_event))
3300 goto out;
3301 }
1fe779f8
CO		 3302 r = 0;
3303 }
3304 break;
3305 }
3306 case KVM_GET_IRQCHIP: {
3307 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3308 struct kvm_irqchip *chip;
1fe779f8 3309
ff5c2c03
SL		 3310 chip = memdup_user(argp, sizeof(*chip));
3311 if (IS_ERR(chip)) {
3312 r = PTR_ERR(chip);
1fe779f8 3313 goto out;
ff5c2c03
SL		 3314 }
3315
1fe779f8
CO		 3316 r = -ENXIO;
3317 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3318 goto get_irqchip_out;
3319 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3320 if (r)
f0d66275 3321 goto get_irqchip_out;
1fe779f8 3322 r = -EFAULT;
f0d66275
DH		 3323 if (copy_to_user(argp, chip, sizeof *chip))
3324 goto get_irqchip_out;
1fe779f8 3325 r = 0;
f0d66275
DH		 3326 get_irqchip_out:
3327 kfree(chip);
3328 if (r)
3329 goto out;
1fe779f8
CO		 3330 break;
3331 }
3332 case KVM_SET_IRQCHIP: {
3333 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3334 struct kvm_irqchip *chip;
1fe779f8 3335
ff5c2c03
SL		 3336 chip = memdup_user(argp, sizeof(*chip));
3337 if (IS_ERR(chip)) {
3338 r = PTR_ERR(chip);
1fe779f8 3339 goto out;
ff5c2c03
SL		 3340 }
3341
1fe779f8
CO		 3342 r = -ENXIO;
3343 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3344 goto set_irqchip_out;
3345 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3346 if (r)
f0d66275 3347 goto set_irqchip_out;
1fe779f8 3348 r = 0;
f0d66275
DH		 3349 set_irqchip_out:
3350 kfree(chip);
3351 if (r)
3352 goto out;
1fe779f8
CO		 3353 break;
3354 }
e0f63cb9 3355 case KVM_GET_PIT: {
e0f63cb9 3356 r = -EFAULT;
f0d66275 3357 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3358 goto out;
3359 r = -ENXIO;
3360 if (!kvm->arch.vpit)
3361 goto out;
f0d66275 3362 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3363 if (r)
3364 goto out;
3365 r = -EFAULT;
f0d66275 3366 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3367 goto out;
3368 r = 0;
3369 break;
3370 }
3371 case KVM_SET_PIT: {
e0f63cb9 3372 r = -EFAULT;
f0d66275 3373 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3374 goto out;
3375 r = -ENXIO;
3376 if (!kvm->arch.vpit)
3377 goto out;
f0d66275 3378 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3379 if (r)
3380 goto out;
3381 r = 0;
3382 break;
3383 }
e9f42757
BK		 3384 case KVM_GET_PIT2: {
3385 r = -ENXIO;
3386 if (!kvm->arch.vpit)
3387 goto out;
3388 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3389 if (r)
3390 goto out;
3391 r = -EFAULT;
3392 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3393 goto out;
3394 r = 0;
3395 break;
3396 }
3397 case KVM_SET_PIT2: {
3398 r = -EFAULT;
3399 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3400 goto out;
3401 r = -ENXIO;
3402 if (!kvm->arch.vpit)
3403 goto out;
3404 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3405 if (r)
3406 goto out;
3407 r = 0;
3408 break;
3409 }
52d939a0
MT		 3410 case KVM_REINJECT_CONTROL: {
3411 struct kvm_reinject_control control;
3412 r = -EFAULT;
3413 if (copy_from_user(&control, argp, sizeof(control)))
3414 goto out;
3415 r = kvm_vm_ioctl_reinject(kvm, &control);
3416 if (r)
3417 goto out;
3418 r = 0;
3419 break;
3420 }
ffde22ac
ES		 3421 case KVM_XEN_HVM_CONFIG: {
3422 r = -EFAULT;
3423 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3424 sizeof(struct kvm_xen_hvm_config)))
3425 goto out;
3426 r = -EINVAL;
3427 if (kvm->arch.xen_hvm_config.flags)
3428 goto out;
3429 r = 0;
3430 break;
3431 }
afbcf7ab 3432 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3433 struct kvm_clock_data user_ns;
3434 u64 now_ns;
3435 s64 delta;
3436
3437 r = -EFAULT;
3438 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3439 goto out;
3440
3441 r = -EINVAL;
3442 if (user_ns.flags)
3443 goto out;
3444
3445 r = 0;
395c6b0a 3446 local_irq_disable();
759379dd 3447 now_ns = get_kernel_ns();
afbcf7ab 3448 delta = user_ns.clock - now_ns;
395c6b0a 3449 local_irq_enable();
afbcf7ab
GC		 3450 kvm->arch.kvmclock_offset = delta;
3451 break;
3452 }
3453 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3454 struct kvm_clock_data user_ns;
3455 u64 now_ns;
3456
395c6b0a 3457 local_irq_disable();
759379dd 3458 now_ns = get_kernel_ns();
afbcf7ab 3459 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3460 local_irq_enable();
afbcf7ab 3461 user_ns.flags = 0;
97e69aa6 3462 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3463
3464 r = -EFAULT;
3465 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3466 goto out;
3467 r = 0;
3468 break;
3469 }
3470
1fe779f8
CO		 3471 default:
3472 ;
3473 }
3474out:
3475 return r;
3476}
3477
a16b043c 3478static void kvm_init_msr_list(void)
043405e1
CO		 3479{
3480 u32 dummy[2];
3481 unsigned i, j;
3482
e3267cbb
GC		 3483 /* skip the first msrs in the list. KVM-specific */
3484 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3485 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3486 continue;
3487 if (j < i)
3488 msrs_to_save[j] = msrs_to_save[i];
3489 j++;
3490 }
3491 num_msrs_to_save = j;
3492}
3493
bda9020e
MT		 3494static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3495 const void *v)
bbd9b64e 3496{
70252a10
AK		 3497 int handled = 0;
3498 int n;
3499
3500 do {
3501 n = min(len, 8);
3502 if (!(vcpu->arch.apic &&
3503 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3504 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3505 break;
3506 handled += n;
3507 addr += n;
3508 len -= n;
3509 v += n;
3510 } while (len);
bbd9b64e 3511
70252a10 3512 return handled;
bbd9b64e
CO		 3513}
3514
bda9020e 3515static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3516{
70252a10
AK		 3517 int handled = 0;
3518 int n;
3519
3520 do {
3521 n = min(len, 8);
3522 if (!(vcpu->arch.apic &&
3523 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3524 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3525 break;
3526 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3527 handled += n;
3528 addr += n;
3529 len -= n;
3530 v += n;
3531 } while (len);
bbd9b64e 3532
70252a10 3533 return handled;
bbd9b64e
CO		 3534}
3535
2dafc6c2
GN		 3536static void kvm_set_segment(struct kvm_vcpu *vcpu,
3537 struct kvm_segment *var, int seg)
3538{
3539 kvm_x86_ops->set_segment(vcpu, var, seg);
3540}
3541
3542void kvm_get_segment(struct kvm_vcpu *vcpu,
3543 struct kvm_segment *var, int seg)
3544{
3545 kvm_x86_ops->get_segment(vcpu, var, seg);
3546}
3547
e459e322 3548gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 3549{
3550 gpa_t t_gpa;
ab9ae313 3551 struct x86_exception exception;
02f59dc9
JR		 3552
3553 BUG_ON(!mmu_is_nested(vcpu));
3554
3555 /* NPT walks are always user-walks */
3556 access |= PFERR_USER_MASK;
ab9ae313 3557 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3558
3559 return t_gpa;
3560}
3561
ab9ae313
AK		 3562gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3563 struct x86_exception *exception)
1871c602
GN		 3564{
3565 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3566 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3567}
3568
ab9ae313
AK		 3569 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3570 struct x86_exception *exception)
1871c602
GN		 3571{
3572 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3573 access |= PFERR_FETCH_MASK;
ab9ae313 3574 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3575}
3576
ab9ae313
AK		 3577gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3578 struct x86_exception *exception)
1871c602
GN		 3579{
3580 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3581 access |= PFERR_WRITE_MASK;
ab9ae313 3582 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3583}
3584
3585/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3586gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3587 struct x86_exception *exception)
1871c602 3588{
ab9ae313 3589 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3590}
3591
3592static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3593 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3594 struct x86_exception *exception)
bbd9b64e
CO		 3595{
3596 void *data = val;
10589a46 3597 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3598
3599 while (bytes) {
14dfe855 3600 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3601 exception);
bbd9b64e 3602 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3603 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3604 int ret;
3605
bcc55cba 3606 if (gpa == UNMAPPED_GVA)
ab9ae313 3607 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3608 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3609 if (ret < 0) {
c3cd7ffa 3610 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3611 goto out;
3612 }
bbd9b64e 3613
77c2002e
IE		 3614 bytes -= toread;
3615 data += toread;
3616 addr += toread;
bbd9b64e 3617 }
10589a46 3618out:
10589a46 3619 return r;
bbd9b64e 3620}
77c2002e 3621
1871c602 3622/* used for instruction fetching */
0f65dd70
AK		 3623static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3624 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3625 struct x86_exception *exception)
1871c602 3626{
0f65dd70 3627 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3628 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3629
1871c602 3630 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 3631 access | PFERR_FETCH_MASK,
3632 exception);
1871c602
GN		 3633}
3634
064aea77 3635int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 3636 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3637 struct x86_exception *exception)
1871c602 3638{
0f65dd70 3639 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3640 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3641
1871c602 3642 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 3643 exception);
1871c602 3644}
064aea77 3645EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 3646
0f65dd70
AK		 3647static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3648 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3649 struct x86_exception *exception)
1871c602 3650{
0f65dd70 3651 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 3652 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 3653}
3654
6a4d7550 3655int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 3656 gva_t addr, void *val,
2dafc6c2 3657 unsigned int bytes,
bcc55cba 3658 struct x86_exception *exception)
77c2002e 3659{
0f65dd70 3660 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 3661 void *data = val;
3662 int r = X86EMUL_CONTINUE;
3663
3664 while (bytes) {
14dfe855
JR		 3665 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3666 PFERR_WRITE_MASK,
ab9ae313 3667 exception);
77c2002e
IE		 3668 unsigned offset = addr & (PAGE_SIZE-1);
3669 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3670 int ret;
3671
bcc55cba 3672 if (gpa == UNMAPPED_GVA)
ab9ae313 3673 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 3674 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3675 if (ret < 0) {
c3cd7ffa 3676 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3677 goto out;
3678 }
3679
3680 bytes -= towrite;
3681 data += towrite;
3682 addr += towrite;
3683 }
3684out:
3685 return r;
3686}
6a4d7550 3687EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 3688
af7cc7d1
XG		 3689static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
3690 gpa_t *gpa, struct x86_exception *exception,
3691 bool write)
3692{
3693 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3694
bebb106a
XG		 3695 if (vcpu_match_mmio_gva(vcpu, gva) &&
3696 check_write_user_access(vcpu, write, access,
3697 vcpu->arch.access)) {
3698 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
3699 (gva & (PAGE_SIZE - 1));
4f022648 3700 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 3701 return 1;
3702 }
3703
af7cc7d1
XG		 3704 if (write)
3705 access |= PFERR_WRITE_MASK;
3706
3707 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3708
3709 if (*gpa == UNMAPPED_GVA)
3710 return -1;
3711
3712 /* For APIC access vmexit */
3713 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3714 return 1;
3715
4f022648
XG		 3716 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
3717 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 3718 return 1;
4f022648 3719 }
bebb106a 3720
af7cc7d1
XG		 3721 return 0;
3722}
3723
3200f405 3724int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 3725 const void *val, int bytes)
bbd9b64e
CO		 3726{
3727 int ret;
3728
3729 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3730 if (ret < 0)
bbd9b64e 3731 return 0;
f57f2ef5 3732 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 3733 return 1;
3734}
3735
77d197b2
XG		 3736struct read_write_emulator_ops {
3737 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
3738 int bytes);
3739 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
3740 void *val, int bytes);
3741 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3742 int bytes, void *val);
3743 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3744 void *val, int bytes);
3745 bool write;
3746};
3747
3748static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
3749{
3750 if (vcpu->mmio_read_completed) {
3751 memcpy(val, vcpu->mmio_data, bytes);
3752 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3753 vcpu->mmio_phys_addr, *(u64 *)val);
3754 vcpu->mmio_read_completed = 0;
3755 return 1;
3756 }
3757
3758 return 0;
3759}
3760
3761static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3762 void *val, int bytes)
3763{
3764 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
3765}
3766
3767static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3768 void *val, int bytes)
3769{
3770 return emulator_write_phys(vcpu, gpa, val, bytes);
3771}
3772
3773static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
3774{
3775 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
3776 return vcpu_mmio_write(vcpu, gpa, bytes, val);
3777}
3778
3779static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3780 void *val, int bytes)
3781{
3782 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
3783 return X86EMUL_IO_NEEDED;
3784}
3785
3786static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3787 void *val, int bytes)
3788{
3789 memcpy(vcpu->mmio_data, val, bytes);
3790 memcpy(vcpu->run->mmio.data, vcpu->mmio_data, 8);
3791 return X86EMUL_CONTINUE;
3792}
3793
3794static struct read_write_emulator_ops read_emultor = {
3795 .read_write_prepare = read_prepare,
3796 .read_write_emulate = read_emulate,
3797 .read_write_mmio = vcpu_mmio_read,
3798 .read_write_exit_mmio = read_exit_mmio,
3799};
3800
3801static struct read_write_emulator_ops write_emultor = {
3802 .read_write_emulate = write_emulate,
3803 .read_write_mmio = write_mmio,
3804 .read_write_exit_mmio = write_exit_mmio,
3805 .write = true,
3806};
3807
22388a3c
XG		 3808static int emulator_read_write_onepage(unsigned long addr, void *val,
3809 unsigned int bytes,
3810 struct x86_exception *exception,
3811 struct kvm_vcpu *vcpu,
3812 struct read_write_emulator_ops *ops)
bbd9b64e 3813{
af7cc7d1
XG		 3814 gpa_t gpa;
3815 int handled, ret;
22388a3c
XG		 3816 bool write = ops->write;
3817
3818 if (ops->read_write_prepare &&
3819 ops->read_write_prepare(vcpu, val, bytes))
3820 return X86EMUL_CONTINUE;
10589a46 3821
22388a3c 3822 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 3823
af7cc7d1 3824 if (ret < 0)
bbd9b64e 3825 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3826
3827 /* For APIC access vmexit */
af7cc7d1 3828 if (ret)
bbd9b64e
CO		 3829 goto mmio;
3830
22388a3c 3831 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 3832 return X86EMUL_CONTINUE;
3833
3834mmio:
3835 /*
3836 * Is this MMIO handled locally?
3837 */
22388a3c 3838 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 3839 if (handled == bytes)
bbd9b64e 3840 return X86EMUL_CONTINUE;
bbd9b64e 3841
70252a10
AK		 3842 gpa += handled;
3843 bytes -= handled;
3844 val += handled;
3845
bbd9b64e 3846 vcpu->mmio_needed = 1;
411c35b7
GN		 3847 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3848 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
cef4dea0
AK		 3849 vcpu->mmio_size = bytes;
3850 vcpu->run->mmio.len = min(vcpu->mmio_size, 8);
22388a3c 3851 vcpu->run->mmio.is_write = vcpu->mmio_is_write = write;
cef4dea0 3852 vcpu->mmio_index = 0;
bbd9b64e 3853
22388a3c 3854 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
bbd9b64e
CO		 3855}
3856
22388a3c
XG		 3857int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
3858 void *val, unsigned int bytes,
3859 struct x86_exception *exception,
3860 struct read_write_emulator_ops *ops)
bbd9b64e 3861{
0f65dd70
AK		 3862 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3863
bbd9b64e
CO		 3864 /* Crossing a page boundary? */
3865 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3866 int rc, now;
3867
3868 now = -addr & ~PAGE_MASK;
22388a3c
XG		 3869 rc = emulator_read_write_onepage(addr, val, now, exception,
3870 vcpu, ops);
3871
bbd9b64e
CO		 3872 if (rc != X86EMUL_CONTINUE)
3873 return rc;
3874 addr += now;
3875 val += now;
3876 bytes -= now;
3877 }
22388a3c
XG		 3878
3879 return emulator_read_write_onepage(addr, val, bytes, exception,
3880 vcpu, ops);
3881}
3882
3883static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
3884 unsigned long addr,
3885 void *val,
3886 unsigned int bytes,
3887 struct x86_exception *exception)
3888{
3889 return emulator_read_write(ctxt, addr, val, bytes,
3890 exception, &read_emultor);
3891}
3892
3893int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
3894 unsigned long addr,
3895 const void *val,
3896 unsigned int bytes,
3897 struct x86_exception *exception)
3898{
3899 return emulator_read_write(ctxt, addr, (void *)val, bytes,
3900 exception, &write_emultor);
bbd9b64e 3901}
bbd9b64e 3902
daea3e73
AK		 3903#define CMPXCHG_TYPE(t, ptr, old, new) \
3904 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3905
3906#ifdef CONFIG_X86_64
3907# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3908#else
3909# define CMPXCHG64(ptr, old, new) \
9749a6c0 3910 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3911#endif
3912
0f65dd70
AK		 3913static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
3914 unsigned long addr,
bbd9b64e
CO		 3915 const void *old,
3916 const void *new,
3917 unsigned int bytes,
0f65dd70 3918 struct x86_exception *exception)
bbd9b64e 3919{
0f65dd70 3920 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 3921 gpa_t gpa;
3922 struct page *page;
3923 char *kaddr;
3924 bool exchanged;
2bacc55c 3925
daea3e73
AK		 3926 /* guests cmpxchg8b have to be emulated atomically */
3927 if (bytes > 8 || (bytes & (bytes - 1)))
3928 goto emul_write;
10589a46 3929
daea3e73 3930 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3931
daea3e73
AK		 3932 if (gpa == UNMAPPED_GVA ||
3933 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3934 goto emul_write;
2bacc55c 3935
daea3e73
AK		 3936 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3937 goto emul_write;
72dc67a6 3938
daea3e73 3939 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
c19b8bd6
WY		 3940 if (is_error_page(page)) {
3941 kvm_release_page_clean(page);
3942 goto emul_write;
3943 }
72dc67a6 3944
8fd75e12 3945 kaddr = kmap_atomic(page);
daea3e73
AK		 3946 kaddr += offset_in_page(gpa);
3947 switch (bytes) {
3948 case 1:
3949 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3950 break;
3951 case 2:
3952 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3953 break;
3954 case 4:
3955 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3956 break;
3957 case 8:
3958 exchanged = CMPXCHG64(kaddr, old, new);
3959 break;
3960 default:
3961 BUG();
2bacc55c 3962 }
8fd75e12 3963 kunmap_atomic(kaddr);
daea3e73
AK		 3964 kvm_release_page_dirty(page);
3965
3966 if (!exchanged)
3967 return X86EMUL_CMPXCHG_FAILED;
3968
f57f2ef5 3969 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 3970
3971 return X86EMUL_CONTINUE;
4a5f48f6 3972
3200f405 3973emul_write:
daea3e73 3974 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3975
0f65dd70 3976 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 3977}
3978
cf8f70bf
GN		 3979static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3980{
3981 /* TODO: String I/O for in kernel device */
3982 int r;
3983
3984 if (vcpu->arch.pio.in)
3985 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3986 vcpu->arch.pio.size, pd);
3987 else
3988 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3989 vcpu->arch.pio.port, vcpu->arch.pio.size,
3990 pd);
3991 return r;
3992}
3993
6f6fbe98
XG		 3994static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
3995 unsigned short port, void *val,
3996 unsigned int count, bool in)
cf8f70bf 3997{
6f6fbe98 3998 trace_kvm_pio(!in, port, size, count);
cf8f70bf
GN		 3999
4000 vcpu->arch.pio.port = port;
6f6fbe98 4001 vcpu->arch.pio.in = in;
7972995b 4002 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4003 vcpu->arch.pio.size = size;
4004
4005 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4006 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4007 return 1;
4008 }
4009
4010 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4011 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4012 vcpu->run->io.size = size;
4013 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4014 vcpu->run->io.count = count;
4015 vcpu->run->io.port = port;
4016
4017 return 0;
4018}
4019
6f6fbe98
XG		 4020static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4021 int size, unsigned short port, void *val,
4022 unsigned int count)
cf8f70bf 4023{
ca1d4a9e 4024 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4025 int ret;
ca1d4a9e 4026
6f6fbe98
XG		 4027 if (vcpu->arch.pio.count)
4028 goto data_avail;
cf8f70bf 4029
6f6fbe98
XG		 4030 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4031 if (ret) {
4032data_avail:
4033 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4034 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4035 return 1;
4036 }
4037
cf8f70bf
GN		 4038 return 0;
4039}
4040
6f6fbe98
XG		 4041static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4042 int size, unsigned short port,
4043 const void *val, unsigned int count)
4044{
4045 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4046
4047 memcpy(vcpu->arch.pio_data, val, size * count);
4048 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4049}
4050
bbd9b64e
CO		 4051static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4052{
4053 return kvm_x86_ops->get_segment_base(vcpu, seg);
4054}
4055
3cb16fe7 4056static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4057{
3cb16fe7 4058 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4059}
4060
f5f48ee1
SY		 4061int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4062{
4063 if (!need_emulate_wbinvd(vcpu))
4064 return X86EMUL_CONTINUE;
4065
4066 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4067 int cpu = get_cpu();
4068
4069 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4070 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4071 wbinvd_ipi, NULL, 1);
2eec7343 4072 put_cpu();
f5f48ee1 4073 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4074 } else
4075 wbinvd();
f5f48ee1
SY		 4076 return X86EMUL_CONTINUE;
4077}
4078EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4079
bcaf5cc5
AK		 4080static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4081{
4082 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4083}
4084
717746e3 4085int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4086{
717746e3 4087 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4088}
4089
717746e3 4090int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4091{
338dbc97 4092
717746e3 4093 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4094}
4095
52a46617 4096static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4097{
52a46617 4098 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4099}
4100
717746e3 4101static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4102{
717746e3 4103 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4104 unsigned long value;
4105
4106 switch (cr) {
4107 case 0:
4108 value = kvm_read_cr0(vcpu);
4109 break;
4110 case 2:
4111 value = vcpu->arch.cr2;
4112 break;
4113 case 3:
9f8fe504 4114 value = kvm_read_cr3(vcpu);
52a46617
GN		 4115 break;
4116 case 4:
4117 value = kvm_read_cr4(vcpu);
4118 break;
4119 case 8:
4120 value = kvm_get_cr8(vcpu);
4121 break;
4122 default:
4123 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4124 return 0;
4125 }
4126
4127 return value;
4128}
4129
717746e3 4130static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4131{
717746e3 4132 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4133 int res = 0;
4134
52a46617
GN		 4135 switch (cr) {
4136 case 0:
49a9b07e 4137 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4138 break;
4139 case 2:
4140 vcpu->arch.cr2 = val;
4141 break;
4142 case 3:
2390218b 4143 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4144 break;
4145 case 4:
a83b29c6 4146 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4147 break;
4148 case 8:
eea1cff9 4149 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4150 break;
4151 default:
4152 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 4153 res = -1;
52a46617 4154 }
0f12244f
GN		 4155
4156 return res;
52a46617
GN		 4157}
4158
4cee4798
KW		 4159static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4160{
4161 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4162}
4163
717746e3 4164static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4165{
717746e3 4166 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4167}
4168
4bff1e86 4169static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4170{
4bff1e86 4171 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4172}
4173
4bff1e86 4174static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4175{
4bff1e86 4176 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4177}
4178
1ac9d0cf
AK		 4179static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4180{
4181 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4182}
4183
4184static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4185{
4186 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4187}
4188
4bff1e86
AK		 4189static unsigned long emulator_get_cached_segment_base(
4190 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4191{
4bff1e86 4192 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4193}
4194
1aa36616
AK		 4195static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4196 struct desc_struct *desc, u32 *base3,
4197 int seg)
2dafc6c2
GN		 4198{
4199 struct kvm_segment var;
4200
4bff1e86 4201 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4202 *selector = var.selector;
2dafc6c2
GN		 4203
4204 if (var.unusable)
4205 return false;
4206
4207 if (var.g)
4208 var.limit >>= 12;
4209 set_desc_limit(desc, var.limit);
4210 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4211#ifdef CONFIG_X86_64
4212 if (base3)
4213 *base3 = var.base >> 32;
4214#endif
2dafc6c2
GN		 4215 desc->type = var.type;
4216 desc->s = var.s;
4217 desc->dpl = var.dpl;
4218 desc->p = var.present;
4219 desc->avl = var.avl;
4220 desc->l = var.l;
4221 desc->d = var.db;
4222 desc->g = var.g;
4223
4224 return true;
4225}
4226
1aa36616
AK		 4227static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4228 struct desc_struct *desc, u32 base3,
4229 int seg)
2dafc6c2 4230{
4bff1e86 4231 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4232 struct kvm_segment var;
4233
1aa36616 4234 var.selector = selector;
2dafc6c2 4235 var.base = get_desc_base(desc);
5601d05b
GN		 4236#ifdef CONFIG_X86_64
4237 var.base |= ((u64)base3) << 32;
4238#endif
2dafc6c2
GN		 4239 var.limit = get_desc_limit(desc);
4240 if (desc->g)
4241 var.limit = (var.limit << 12) | 0xfff;
4242 var.type = desc->type;
4243 var.present = desc->p;
4244 var.dpl = desc->dpl;
4245 var.db = desc->d;
4246 var.s = desc->s;
4247 var.l = desc->l;
4248 var.g = desc->g;
4249 var.avl = desc->avl;
4250 var.present = desc->p;
4251 var.unusable = !var.present;
4252 var.padding = 0;
4253
4254 kvm_set_segment(vcpu, &var, seg);
4255 return;
4256}
4257
717746e3
AK		 4258static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4259 u32 msr_index, u64 *pdata)
4260{
4261 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4262}
4263
4264static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4265 u32 msr_index, u64 data)
4266{
4267 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
4268}
4269
222d21aa
AK		 4270static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4271 u32 pmc, u64 *pdata)
4272{
4273 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4274}
4275
6c3287f7
AK		 4276static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4277{
4278 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4279}
4280
5037f6f3
AK		 4281static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4282{
4283 preempt_disable();
5197b808 4284 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4285 /*
4286 * CR0.TS may reference the host fpu state, not the guest fpu state,
4287 * so it may be clear at this point.
4288 */
4289 clts();
4290}
4291
4292static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4293{
4294 preempt_enable();
4295}
4296
2953538e 4297static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4298 struct x86_instruction_info *info,
c4f035c6
AK		 4299 enum x86_intercept_stage stage)
4300{
2953538e 4301 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4302}
4303
bdb42f5a
SB		 4304static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4305 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4306{
4307 struct kvm_cpuid_entry2 *cpuid = NULL;
4308
4309 if (eax && ecx)
4310 cpuid = kvm_find_cpuid_entry(emul_to_vcpu(ctxt),
4311 *eax, *ecx);
4312
4313 if (cpuid) {
4314 *eax = cpuid->eax;
4315 *ecx = cpuid->ecx;
4316 if (ebx)
4317 *ebx = cpuid->ebx;
4318 if (edx)
4319 *edx = cpuid->edx;
4320 return true;
4321 }
4322
4323 return false;
4324}
4325
14af3f3c 4326static struct x86_emulate_ops emulate_ops = {
1871c602 4327 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4328 .write_std = kvm_write_guest_virt_system,
1871c602 4329 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4330 .read_emulated = emulator_read_emulated,
4331 .write_emulated = emulator_write_emulated,
4332 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4333 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4334 .pio_in_emulated = emulator_pio_in_emulated,
4335 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4336 .get_segment = emulator_get_segment,
4337 .set_segment = emulator_set_segment,
5951c442 4338 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4339 .get_gdt = emulator_get_gdt,
160ce1f1 4340 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4341 .set_gdt = emulator_set_gdt,
4342 .set_idt = emulator_set_idt,
52a46617
GN		 4343 .get_cr = emulator_get_cr,
4344 .set_cr = emulator_set_cr,
4cee4798 4345 .set_rflags = emulator_set_rflags,
9c537244 4346 .cpl = emulator_get_cpl,
35aa5375
GN		 4347 .get_dr = emulator_get_dr,
4348 .set_dr = emulator_set_dr,
717746e3
AK		 4349 .set_msr = emulator_set_msr,
4350 .get_msr = emulator_get_msr,
222d21aa 4351 .read_pmc = emulator_read_pmc,
6c3287f7 4352 .halt = emulator_halt,
bcaf5cc5 4353 .wbinvd = emulator_wbinvd,
d6aa1000 4354 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4355 .get_fpu = emulator_get_fpu,
4356 .put_fpu = emulator_put_fpu,
c4f035c6 4357 .intercept = emulator_intercept,
bdb42f5a 4358 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4359};
4360
5fdbf976
MT		 4361static void cache_all_regs(struct kvm_vcpu *vcpu)
4362{
4363 kvm_register_read(vcpu, VCPU_REGS_RAX);
4364 kvm_register_read(vcpu, VCPU_REGS_RSP);
4365 kvm_register_read(vcpu, VCPU_REGS_RIP);
4366 vcpu->arch.regs_dirty = ~0;
4367}
4368
95cb2295
GN		 4369static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4370{
4371 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4372 /*
4373 * an sti; sti; sequence only disable interrupts for the first
4374 * instruction. So, if the last instruction, be it emulated or
4375 * not, left the system with the INT_STI flag enabled, it
4376 * means that the last instruction is an sti. We should not
4377 * leave the flag on in this case. The same goes for mov ss
4378 */
4379 if (!(int_shadow & mask))
4380 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4381}
4382
54b8486f
GN		 4383static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4384{
4385 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4386 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4387 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4388 else if (ctxt->exception.error_code_valid)
4389 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4390 ctxt->exception.error_code);
54b8486f 4391 else
da9cb575 4392 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4393}
4394
9dac77fa 4395static void init_decode_cache(struct x86_emulate_ctxt *ctxt,
b5c9ff73
TY		 4396 const unsigned long *regs)
4397{
9dac77fa
AK		 4398 memset(&ctxt->twobyte, 0,
4399 (void *)&ctxt->regs - (void *)&ctxt->twobyte);
4400 memcpy(ctxt->regs, regs, sizeof(ctxt->regs));
b5c9ff73 4401
9dac77fa
AK		 4402 ctxt->fetch.start = 0;
4403 ctxt->fetch.end = 0;
4404 ctxt->io_read.pos = 0;
4405 ctxt->io_read.end = 0;
4406 ctxt->mem_read.pos = 0;
4407 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4408}
4409
8ec4722d
MG		 4410static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4411{
adf52235 4412 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4413 int cs_db, cs_l;
4414
2aab2c5b
GN		 4415 /*
4416 * TODO: fix emulate.c to use guest_read/write_register
4417 * instead of direct ->regs accesses, can save hundred cycles
4418 * on Intel for instructions that don't read/change RSP, for
4419 * for example.
4420 */
8ec4722d
MG		 4421 cache_all_regs(vcpu);
4422
4423 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4424
adf52235
TY		 4425 ctxt->eflags = kvm_get_rflags(vcpu);
4426 ctxt->eip = kvm_rip_read(vcpu);
4427 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4428 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4429 cs_l ? X86EMUL_MODE_PROT64 :
4430 cs_db ? X86EMUL_MODE_PROT32 :
4431 X86EMUL_MODE_PROT16;
4432 ctxt->guest_mode = is_guest_mode(vcpu);
4433
9dac77fa 4434 init_decode_cache(ctxt, vcpu->arch.regs);
7ae441ea 4435 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4436}
4437
71f9833b 4438int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4439{
9d74191a 4440 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4441 int ret;
4442
4443 init_emulate_ctxt(vcpu);
4444
9dac77fa
AK		 4445 ctxt->op_bytes = 2;
4446 ctxt->ad_bytes = 2;
4447 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4448 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4449
4450 if (ret != X86EMUL_CONTINUE)
4451 return EMULATE_FAIL;
4452
9dac77fa
AK		 4453 ctxt->eip = ctxt->_eip;
4454 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
9d74191a
TY		 4455 kvm_rip_write(vcpu, ctxt->eip);
4456 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4457
4458 if (irq == NMI_VECTOR)
7460fb4a 4459 vcpu->arch.nmi_pending = 0;
63995653
MG		 4460 else
4461 vcpu->arch.interrupt.pending = false;
4462
4463 return EMULATE_DONE;
4464}
4465EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4466
6d77dbfc
GN		 4467static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4468{
fc3a9157
JR		 4469 int r = EMULATE_DONE;
4470
6d77dbfc
GN		 4471 ++vcpu->stat.insn_emulation_fail;
4472 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4473 if (!is_guest_mode(vcpu)) {
4474 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4475 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4476 vcpu->run->internal.ndata = 0;
4477 r = EMULATE_FAIL;
4478 }
6d77dbfc 4479 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4480
4481 return r;
6d77dbfc
GN		 4482}
4483
a6f177ef
GN		 4484static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4485{
4486 gpa_t gpa;
4487
68be0803
GN		 4488 if (tdp_enabled)
4489 return false;
4490
a6f177ef
GN		 4491 /*
4492 * if emulation was due to access to shadowed page table
4493 * and it failed try to unshadow page and re-entetr the
4494 * guest to let CPU execute the instruction.
4495 */
4496 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4497 return true;
4498
4499 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4500
4501 if (gpa == UNMAPPED_GVA)
4502 return true; /* let cpu generate fault */
4503
4504 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4505 return true;
4506
4507 return false;
4508}
4509
1cb3f3ae
XG		 4510static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4511 unsigned long cr2, int emulation_type)
4512{
4513 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4514 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4515
4516 last_retry_eip = vcpu->arch.last_retry_eip;
4517 last_retry_addr = vcpu->arch.last_retry_addr;
4518
4519 /*
4520 * If the emulation is caused by #PF and it is non-page_table
4521 * writing instruction, it means the VM-EXIT is caused by shadow
4522 * page protected, we can zap the shadow page and retry this
4523 * instruction directly.
4524 *
4525 * Note: if the guest uses a non-page-table modifying instruction
4526 * on the PDE that points to the instruction, then we will unmap
4527 * the instruction and go to an infinite loop. So, we cache the
4528 * last retried eip and the last fault address, if we meet the eip
4529 * and the address again, we can break out of the potential infinite
4530 * loop.
4531 */
4532 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4533
4534 if (!(emulation_type & EMULTYPE_RETRY))
4535 return false;
4536
4537 if (x86_page_table_writing_insn(ctxt))
4538 return false;
4539
4540 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4541 return false;
4542
4543 vcpu->arch.last_retry_eip = ctxt->eip;
4544 vcpu->arch.last_retry_addr = cr2;
4545
4546 if (!vcpu->arch.mmu.direct_map)
4547 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4548
4549 kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4550
4551 return true;
4552}
4553
51d8b661
AP		 4554int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4555 unsigned long cr2,
dc25e89e
AP		 4556 int emulation_type,
4557 void *insn,
4558 int insn_len)
bbd9b64e 4559{
95cb2295 4560 int r;
9d74191a 4561 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 4562 bool writeback = true;
bbd9b64e 4563
26eef70c 4564 kvm_clear_exception_queue(vcpu);
8d7d8102 4565
571008da 4566 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4567 init_emulate_ctxt(vcpu);
9d74191a
TY		 4568 ctxt->interruptibility = 0;
4569 ctxt->have_exception = false;
4570 ctxt->perm_ok = false;
bbd9b64e 4571
9d74191a 4572 ctxt->only_vendor_specific_insn
4005996e
AK		 4573 = emulation_type & EMULTYPE_TRAP_UD;
4574
9d74191a 4575 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 4576
e46479f8 4577 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 4578 ++vcpu->stat.insn_emulation;
1d2887e2 4579 if (r != EMULATION_OK) {
4005996e
AK		 4580 if (emulation_type & EMULTYPE_TRAP_UD)
4581 return EMULATE_FAIL;
a6f177ef 4582 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4583 return EMULATE_DONE;
6d77dbfc
GN		 4584 if (emulation_type & EMULTYPE_SKIP)
4585 return EMULATE_FAIL;
4586 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4587 }
4588 }
4589
ba8afb6b 4590 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 4591 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 4592 return EMULATE_DONE;
4593 }
4594
1cb3f3ae
XG		 4595 if (retry_instruction(ctxt, cr2, emulation_type))
4596 return EMULATE_DONE;
4597
7ae441ea 4598 /* this is needed for vmware backdoor interface to work since it
4d2179e1 4599 changes registers values during IO operation */
7ae441ea
GN		 4600 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4601 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
9dac77fa 4602 memcpy(ctxt->regs, vcpu->arch.regs, sizeof ctxt->regs);
7ae441ea 4603 }
4d2179e1 4604
5cd21917 4605restart:
9d74191a 4606 r = x86_emulate_insn(ctxt);
bbd9b64e 4607
775fde86
JR		 4608 if (r == EMULATION_INTERCEPTED)
4609 return EMULATE_DONE;
4610
d2ddd1c4 4611 if (r == EMULATION_FAILED) {
a6f177ef 4612 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4613 return EMULATE_DONE;
4614
6d77dbfc 4615 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4616 }
4617
9d74191a 4618 if (ctxt->have_exception) {
54b8486f 4619 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4620 r = EMULATE_DONE;
4621 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4622 if (!vcpu->arch.pio.in)
4623 vcpu->arch.pio.count = 0;
7ae441ea
GN		 4624 else
4625 writeback = false;
e85d28f8 4626 r = EMULATE_DO_MMIO;
7ae441ea
GN		 4627 } else if (vcpu->mmio_needed) {
4628 if (!vcpu->mmio_is_write)
4629 writeback = false;
e85d28f8 4630 r = EMULATE_DO_MMIO;
7ae441ea 4631 } else if (r == EMULATION_RESTART)
5cd21917 4632 goto restart;
d2ddd1c4
GN		 4633 else
4634 r = EMULATE_DONE;
f850e2e6 4635
7ae441ea 4636 if (writeback) {
9d74191a
TY		 4637 toggle_interruptibility(vcpu, ctxt->interruptibility);
4638 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea 4639 kvm_make_request(KVM_REQ_EVENT, vcpu);
9dac77fa 4640 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
7ae441ea 4641 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 4642 kvm_rip_write(vcpu, ctxt->eip);
7ae441ea
GN		 4643 } else
4644 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 4645
4646 return r;
de7d789a 4647}
51d8b661 4648EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 4649
cf8f70bf 4650int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4651{
cf8f70bf 4652 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 4653 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4654 size, port, &val, 1);
cf8f70bf 4655 /* do not return to emulator after return from userspace */
7972995b 4656 vcpu->arch.pio.count = 0;
de7d789a
CO		 4657 return ret;
4658}
cf8f70bf 4659EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4660
8cfdc000
ZA		 4661static void tsc_bad(void *info)
4662{
0a3aee0d 4663 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 4664}
4665
4666static void tsc_khz_changed(void *data)
c8076604 4667{
8cfdc000
ZA		 4668 struct cpufreq_freqs *freq = data;
4669 unsigned long khz = 0;
4670
4671 if (data)
4672 khz = freq->new;
4673 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4674 khz = cpufreq_quick_get(raw_smp_processor_id());
4675 if (!khz)
4676 khz = tsc_khz;
0a3aee0d 4677 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 4678}
4679
c8076604
GH		 4680static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4681 void *data)
4682{
4683 struct cpufreq_freqs *freq = data;
4684 struct kvm *kvm;
4685 struct kvm_vcpu *vcpu;
4686 int i, send_ipi = 0;
4687
8cfdc000
ZA		 4688 /*
4689 * We allow guests to temporarily run on slowing clocks,
4690 * provided we notify them after, or to run on accelerating
4691 * clocks, provided we notify them before. Thus time never
4692 * goes backwards.
4693 *
4694 * However, we have a problem. We can't atomically update
4695 * the frequency of a given CPU from this function; it is
4696 * merely a notifier, which can be called from any CPU.
4697 * Changing the TSC frequency at arbitrary points in time
4698 * requires a recomputation of local variables related to
4699 * the TSC for each VCPU. We must flag these local variables
4700 * to be updated and be sure the update takes place with the
4701 * new frequency before any guests proceed.
4702 *
4703 * Unfortunately, the combination of hotplug CPU and frequency
4704 * change creates an intractable locking scenario; the order
4705 * of when these callouts happen is undefined with respect to
4706 * CPU hotplug, and they can race with each other. As such,
4707 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4708 * undefined; you can actually have a CPU frequency change take
4709 * place in between the computation of X and the setting of the
4710 * variable. To protect against this problem, all updates of
4711 * the per_cpu tsc_khz variable are done in an interrupt
4712 * protected IPI, and all callers wishing to update the value
4713 * must wait for a synchronous IPI to complete (which is trivial
4714 * if the caller is on the CPU already). This establishes the
4715 * necessary total order on variable updates.
4716 *
4717 * Note that because a guest time update may take place
4718 * anytime after the setting of the VCPU's request bit, the
4719 * correct TSC value must be set before the request. However,
4720 * to ensure the update actually makes it to any guest which
4721 * starts running in hardware virtualization between the set
4722 * and the acquisition of the spinlock, we must also ping the
4723 * CPU after setting the request bit.
4724 *
4725 */
4726
c8076604
GH		 4727 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4728 return 0;
4729 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4730 return 0;
8cfdc000
ZA		 4731
4732 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 4733
e935b837 4734 raw_spin_lock(&kvm_lock);
c8076604 4735 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4736 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4737 if (vcpu->cpu != freq->cpu)
4738 continue;
c285545f 4739 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 4740 if (vcpu->cpu != smp_processor_id())
8cfdc000 4741 send_ipi = 1;
c8076604
GH		 4742 }
4743 }
e935b837 4744 raw_spin_unlock(&kvm_lock);
c8076604
GH		 4745
4746 if (freq->old < freq->new && send_ipi) {
4747 /*
4748 * We upscale the frequency. Must make the guest
4749 * doesn't see old kvmclock values while running with
4750 * the new frequency, otherwise we risk the guest sees
4751 * time go backwards.
4752 *
4753 * In case we update the frequency for another cpu
4754 * (which might be in guest context) send an interrupt
4755 * to kick the cpu out of guest context. Next time
4756 * guest context is entered kvmclock will be updated,
4757 * so the guest will not see stale values.
4758 */
8cfdc000 4759 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4760 }
4761 return 0;
4762}
4763
4764static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 4765 .notifier_call = kvmclock_cpufreq_notifier
4766};
4767
4768static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4769 unsigned long action, void *hcpu)
4770{
4771 unsigned int cpu = (unsigned long)hcpu;
4772
4773 switch (action) {
4774 case CPU_ONLINE:
4775 case CPU_DOWN_FAILED:
4776 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4777 break;
4778 case CPU_DOWN_PREPARE:
4779 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4780 break;
4781 }
4782 return NOTIFY_OK;
4783}
4784
4785static struct notifier_block kvmclock_cpu_notifier_block = {
4786 .notifier_call = kvmclock_cpu_notifier,
4787 .priority = -INT_MAX
c8076604
GH		 4788};
4789
b820cc0c
ZA		 4790static void kvm_timer_init(void)
4791{
4792 int cpu;
4793
c285545f 4794 max_tsc_khz = tsc_khz;
8cfdc000 4795 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 4796 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 4797#ifdef CONFIG_CPU_FREQ
4798 struct cpufreq_policy policy;
4799 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 4800 cpu = get_cpu();
4801 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 4802 if (policy.cpuinfo.max_freq)
4803 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 4804 put_cpu();
c285545f 4805#endif
b820cc0c
ZA		 4806 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4807 CPUFREQ_TRANSITION_NOTIFIER);
4808 }
c285545f 4809 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 4810 for_each_online_cpu(cpu)
4811 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 4812}
4813
ff9d07a0
ZY		 4814static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4815
f5132b01 4816int kvm_is_in_guest(void)
ff9d07a0 4817{
086c9855 4818 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 4819}
4820
4821static int kvm_is_user_mode(void)
4822{
4823 int user_mode = 3;
dcf46b94 4824
086c9855
AS		 4825 if (__this_cpu_read(current_vcpu))
4826 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 4827
ff9d07a0
ZY		 4828 return user_mode != 0;
4829}
4830
4831static unsigned long kvm_get_guest_ip(void)
4832{
4833 unsigned long ip = 0;
dcf46b94 4834
086c9855
AS		 4835 if (__this_cpu_read(current_vcpu))
4836 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 4837
ff9d07a0
ZY		 4838 return ip;
4839}
4840
4841static struct perf_guest_info_callbacks kvm_guest_cbs = {
4842 .is_in_guest = kvm_is_in_guest,
4843 .is_user_mode = kvm_is_user_mode,
4844 .get_guest_ip = kvm_get_guest_ip,
4845};
4846
4847void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4848{
086c9855 4849 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 4850}
4851EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4852
4853void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4854{
086c9855 4855 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 4856}
4857EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4858
ce88decf
XG		 4859static void kvm_set_mmio_spte_mask(void)
4860{
4861 u64 mask;
4862 int maxphyaddr = boot_cpu_data.x86_phys_bits;
4863
4864 /*
4865 * Set the reserved bits and the present bit of an paging-structure
4866 * entry to generate page fault with PFER.RSV = 1.
4867 */
4868 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
4869 mask |= 1ull;
4870
4871#ifdef CONFIG_X86_64
4872 /*
4873 * If reserved bit is not supported, clear the present bit to disable
4874 * mmio page fault.
4875 */
4876 if (maxphyaddr == 52)
4877 mask &= ~1ull;
4878#endif
4879
4880 kvm_mmu_set_mmio_spte_mask(mask);
4881}
4882
f8c16bba 4883int kvm_arch_init(void *opaque)
043405e1 4884{
b820cc0c 4885 int r;
f8c16bba
ZX		 4886 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4887
f8c16bba
ZX		 4888 if (kvm_x86_ops) {
4889 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4890 r = -EEXIST;
4891 goto out;
f8c16bba
ZX		 4892 }
4893
4894 if (!ops->cpu_has_kvm_support()) {
4895 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4896 r = -EOPNOTSUPP;
4897 goto out;
f8c16bba
ZX		 4898 }
4899 if (ops->disabled_by_bios()) {
4900 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4901 r = -EOPNOTSUPP;
4902 goto out;
f8c16bba
ZX		 4903 }
4904
97db56ce
AK		 4905 r = kvm_mmu_module_init();
4906 if (r)
4907 goto out;
4908
ce88decf 4909 kvm_set_mmio_spte_mask();
97db56ce
AK		 4910 kvm_init_msr_list();
4911
f8c16bba 4912 kvm_x86_ops = ops;
7b52345e 4913 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4914 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4915
b820cc0c 4916 kvm_timer_init();
c8076604 4917
ff9d07a0
ZY		 4918 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4919
2acf923e
DC		 4920 if (cpu_has_xsave)
4921 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4922
f8c16bba 4923 return 0;
56c6d28a
ZX		 4924
4925out:
56c6d28a 4926 return r;
043405e1 4927}
8776e519 4928
f8c16bba
ZX		 4929void kvm_arch_exit(void)
4930{
ff9d07a0
ZY		 4931 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4932
888d256e
JK		 4933 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4934 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4935 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 4936 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 4937 kvm_x86_ops = NULL;
56c6d28a
ZX		 4938 kvm_mmu_module_exit();
4939}
f8c16bba 4940
8776e519
HB		 4941int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4942{
4943 ++vcpu->stat.halt_exits;
4944 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4945 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4946 return 1;
4947 } else {
4948 vcpu->run->exit_reason = KVM_EXIT_HLT;
4949 return 0;
4950 }
4951}
4952EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4953
55cd8e5a
GN		 4954int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4955{
4956 u64 param, ingpa, outgpa, ret;
4957 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4958 bool fast, longmode;
4959 int cs_db, cs_l;
4960
4961 /*
4962 * hypercall generates UD from non zero cpl and real mode
4963 * per HYPER-V spec
4964 */
3eeb3288 4965 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4966 kvm_queue_exception(vcpu, UD_VECTOR);
4967 return 0;
4968 }
4969
4970 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4971 longmode = is_long_mode(vcpu) && cs_l == 1;
4972
4973 if (!longmode) {
ccd46936
GN		 4974 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4975 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4976 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4977 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4978 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4979 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4980 }
4981#ifdef CONFIG_X86_64
4982 else {
4983 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4984 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4985 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4986 }
4987#endif
4988
4989 code = param & 0xffff;
4990 fast = (param >> 16) & 0x1;
4991 rep_cnt = (param >> 32) & 0xfff;
4992 rep_idx = (param >> 48) & 0xfff;
4993
4994 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4995
c25bc163
GN		 4996 switch (code) {
4997 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4998 kvm_vcpu_on_spin(vcpu);
4999 break;
5000 default:
5001 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5002 break;
5003 }
55cd8e5a
GN		 5004
5005 ret = res | (((u64)rep_done & 0xfff) << 32);
5006 if (longmode) {
5007 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5008 } else {
5009 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5010 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5011 }
5012
5013 return 1;
5014}
5015
8776e519
HB		 5016int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5017{
5018 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 5019 int r = 1;
8776e519 5020
55cd8e5a
GN		 5021 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5022 return kvm_hv_hypercall(vcpu);
5023
5fdbf976
MT		 5024 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5025 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5026 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5027 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5028 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5029
229456fc 5030 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5031
8776e519
HB		 5032 if (!is_long_mode(vcpu)) {
5033 nr &= 0xFFFFFFFF;
5034 a0 &= 0xFFFFFFFF;
5035 a1 &= 0xFFFFFFFF;
5036 a2 &= 0xFFFFFFFF;
5037 a3 &= 0xFFFFFFFF;
5038 }
5039
07708c4a
JK		 5040 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5041 ret = -KVM_EPERM;
5042 goto out;
5043 }
5044
8776e519 5045 switch (nr) {
b93463aa
AK		 5046 case KVM_HC_VAPIC_POLL_IRQ:
5047 ret = 0;
5048 break;
8776e519
HB		 5049 default:
5050 ret = -KVM_ENOSYS;
5051 break;
5052 }
07708c4a 5053out:
5fdbf976 5054 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5055 ++vcpu->stat.hypercalls;
2f333bcb 5056 return r;
8776e519
HB		 5057}
5058EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5059
d6aa1000 5060int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5061{
d6aa1000 5062 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5063 char instruction[3];
5fdbf976 5064 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5065
8776e519
HB		 5066 /*
5067 * Blow out the MMU to ensure that no other VCPU has an active mapping
5068 * to ensure that the updated hypercall appears atomically across all
5069 * VCPUs.
5070 */
5071 kvm_mmu_zap_all(vcpu->kvm);
5072
8776e519 5073 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5074
9d74191a 5075 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5076}
5077
b6c7a5dc
HB		 5078/*
5079 * Check if userspace requested an interrupt window, and that the
5080 * interrupt window is open.
5081 *
5082 * No need to exit to userspace if we already have an interrupt queued.
5083 */
851ba692 5084static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5085{
8061823a 5086 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5087 vcpu->run->request_interrupt_window &&
5df56646 5088 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5089}
5090
851ba692 5091static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5092{
851ba692
AK		 5093 struct kvm_run *kvm_run = vcpu->run;
5094
91586a3b 5095 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5096 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5097 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5098 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5099 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5100 else
b6c7a5dc 5101 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5102 kvm_arch_interrupt_allowed(vcpu) &&
5103 !kvm_cpu_has_interrupt(vcpu) &&
5104 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5105}
5106
b93463aa
AK		 5107static void vapic_enter(struct kvm_vcpu *vcpu)
5108{
5109 struct kvm_lapic *apic = vcpu->arch.apic;
5110 struct page *page;
5111
5112 if (!apic || !apic->vapic_addr)
5113 return;
5114
5115 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 5116
5117 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 5118}
5119
5120static void vapic_exit(struct kvm_vcpu *vcpu)
5121{
5122 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5123 int idx;
b93463aa
AK		 5124
5125 if (!apic || !apic->vapic_addr)
5126 return;
5127
f656ce01 5128 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5129 kvm_release_page_dirty(apic->vapic_page);
5130 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5131 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5132}
5133
95ba8273
GN		 5134static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5135{
5136 int max_irr, tpr;
5137
5138 if (!kvm_x86_ops->update_cr8_intercept)
5139 return;
5140
88c808fd
AK		 5141 if (!vcpu->arch.apic)
5142 return;
5143
8db3baa2
GN		 5144 if (!vcpu->arch.apic->vapic_addr)
5145 max_irr = kvm_lapic_find_highest_irr(vcpu);
5146 else
5147 max_irr = -1;
95ba8273
GN		 5148
5149 if (max_irr != -1)
5150 max_irr >>= 4;
5151
5152 tpr = kvm_lapic_get_cr8(vcpu);
5153
5154 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5155}
5156
851ba692 5157static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5158{
5159 /* try to reinject previous events if any */
b59bb7bd 5160 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5161 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5162 vcpu->arch.exception.has_error_code,
5163 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5164 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5165 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5166 vcpu->arch.exception.error_code,
5167 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5168 return;
5169 }
5170
95ba8273
GN		 5171 if (vcpu->arch.nmi_injected) {
5172 kvm_x86_ops->set_nmi(vcpu);
5173 return;
5174 }
5175
5176 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5177 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5178 return;
5179 }
5180
5181 /* try to inject new event if pending */
5182 if (vcpu->arch.nmi_pending) {
5183 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5184 --vcpu->arch.nmi_pending;
95ba8273
GN		 5185 vcpu->arch.nmi_injected = true;
5186 kvm_x86_ops->set_nmi(vcpu);
5187 }
5188 } else if (kvm_cpu_has_interrupt(vcpu)) {
5189 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5190 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5191 false);
5192 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5193 }
5194 }
5195}
5196
2acf923e
DC		 5197static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5198{
5199 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5200 !vcpu->guest_xcr0_loaded) {
5201 /* kvm_set_xcr() also depends on this */
5202 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5203 vcpu->guest_xcr0_loaded = 1;
5204 }
5205}
5206
5207static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5208{
5209 if (vcpu->guest_xcr0_loaded) {
5210 if (vcpu->arch.xcr0 != host_xcr0)
5211 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5212 vcpu->guest_xcr0_loaded = 0;
5213 }
5214}
5215
7460fb4a
AK		 5216static void process_nmi(struct kvm_vcpu *vcpu)
5217{
5218 unsigned limit = 2;
5219
5220 /*
5221 * x86 is limited to one NMI running, and one NMI pending after it.
5222 * If an NMI is already in progress, limit further NMIs to just one.
5223 * Otherwise, allow two (and we'll inject the first one immediately).
5224 */
5225 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5226 limit = 1;
5227
5228 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5229 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5230 kvm_make_request(KVM_REQ_EVENT, vcpu);
5231}
5232
851ba692 5233static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5234{
5235 int r;
6a8b1d13 5236 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5237 vcpu->run->request_interrupt_window;
d6185f20 5238 bool req_immediate_exit = 0;
b6c7a5dc 5239
3e007509 5240 if (vcpu->requests) {
a8eeb04a 5241 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5242 kvm_mmu_unload(vcpu);
a8eeb04a 5243 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5244 __kvm_migrate_timers(vcpu);
34c238a1
ZA		 5245 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5246 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5247 if (unlikely(r))
5248 goto out;
5249 }
a8eeb04a 5250 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5251 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5252 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5253 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5254 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5255 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5256 r = 0;
5257 goto out;
5258 }
a8eeb04a 5259 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5260 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5261 r = 0;
5262 goto out;
5263 }
a8eeb04a 5264 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5265 vcpu->fpu_active = 0;
5266 kvm_x86_ops->fpu_deactivate(vcpu);
5267 }
af585b92
GN		 5268 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5269 /* Page is swapped out. Do synthetic halt */
5270 vcpu->arch.apf.halted = true;
5271 r = 1;
5272 goto out;
5273 }
c9aaa895
GC		 5274 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5275 record_steal_time(vcpu);
7460fb4a
AK		 5276 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5277 process_nmi(vcpu);
d6185f20
NHE		 5278 req_immediate_exit =
5279 kvm_check_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
f5132b01
GN		 5280 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5281 kvm_handle_pmu_event(vcpu);
5282 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5283 kvm_deliver_pmi(vcpu);
2f52d58c 5284 }
b93463aa 5285
3e007509
AK		 5286 r = kvm_mmu_reload(vcpu);
5287 if (unlikely(r))
5288 goto out;
5289
b463a6f7
AK		 5290 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5291 inject_pending_event(vcpu);
5292
5293 /* enable NMI/IRQ window open exits if needed */
7460fb4a 5294 if (vcpu->arch.nmi_pending)
b463a6f7
AK		 5295 kvm_x86_ops->enable_nmi_window(vcpu);
5296 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5297 kvm_x86_ops->enable_irq_window(vcpu);
5298
5299 if (kvm_lapic_enabled(vcpu)) {
5300 update_cr8_intercept(vcpu);
5301 kvm_lapic_sync_to_vapic(vcpu);
5302 }
5303 }
5304
b6c7a5dc
HB		 5305 preempt_disable();
5306
5307 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5308 if (vcpu->fpu_active)
5309 kvm_load_guest_fpu(vcpu);
2acf923e 5310 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5311
6b7e2d09
XG		 5312 vcpu->mode = IN_GUEST_MODE;
5313
5314 /* We should set ->mode before check ->requests,
5315 * see the comment in make_all_cpus_request.
5316 */
5317 smp_mb();
b6c7a5dc 5318
d94e1dc9 5319 local_irq_disable();
32f88400 5320
6b7e2d09 5321 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5322 || need_resched() || signal_pending(current)) {
6b7e2d09 5323 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5324 smp_wmb();
6c142801
AK		 5325 local_irq_enable();
5326 preempt_enable();
b463a6f7 5327 kvm_x86_ops->cancel_injection(vcpu);
6c142801
AK		 5328 r = 1;
5329 goto out;
5330 }
5331
f656ce01 5332 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5333
d6185f20
NHE		 5334 if (req_immediate_exit)
5335 smp_send_reschedule(vcpu->cpu);
5336
b6c7a5dc
HB		 5337 kvm_guest_enter();
5338
42dbaa5a 5339 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5340 set_debugreg(0, 7);
5341 set_debugreg(vcpu->arch.eff_db[0], 0);
5342 set_debugreg(vcpu->arch.eff_db[1], 1);
5343 set_debugreg(vcpu->arch.eff_db[2], 2);
5344 set_debugreg(vcpu->arch.eff_db[3], 3);
5345 }
b6c7a5dc 5346
229456fc 5347 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5348 kvm_x86_ops->run(vcpu);
b6c7a5dc 5349
24f1e32c
FW		 5350 /*
5351 * If the guest has used debug registers, at least dr7
5352 * will be disabled while returning to the host.
5353 * If we don't have active breakpoints in the host, we don't
5354 * care about the messed up debug address registers. But if
5355 * we have some of them active, restore the old state.
5356 */
59d8eb53 5357 if (hw_breakpoint_active())
24f1e32c 5358 hw_breakpoint_restore();
42dbaa5a 5359
d5c1785d 5360 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
1d5f066e 5361
6b7e2d09 5362 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5363 smp_wmb();
b6c7a5dc
HB		 5364 local_irq_enable();
5365
5366 ++vcpu->stat.exits;
5367
5368 /*
5369 * We must have an instruction between local_irq_enable() and
5370 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5371 * the interrupt shadow. The stat.exits increment will do nicely.
5372 * But we need to prevent reordering, hence this barrier():
5373 */
5374 barrier();
5375
5376 kvm_guest_exit();
5377
5378 preempt_enable();
5379
f656ce01 5380 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5381
b6c7a5dc
HB		 5382 /*
5383 * Profile KVM exit RIPs:
5384 */
5385 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5386 unsigned long rip = kvm_rip_read(vcpu);
5387 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5388 }
5389
cc578287
ZA		 5390 if (unlikely(vcpu->arch.tsc_always_catchup))
5391 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 5392
b93463aa
AK		 5393 kvm_lapic_sync_from_vapic(vcpu);
5394
851ba692 5395 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 5396out:
5397 return r;
5398}
b6c7a5dc 5399
09cec754 5400
851ba692 5401static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5402{
5403 int r;
f656ce01 5404 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5405
5406 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5407 pr_debug("vcpu %d received sipi with vector # %x\n",
5408 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5409 kvm_lapic_reset(vcpu);
5f179287 5410 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5411 if (r)
5412 return r;
5413 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5414 }
5415
f656ce01 5416 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5417 vapic_enter(vcpu);
5418
5419 r = 1;
5420 while (r > 0) {
af585b92
GN		 5421 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5422 !vcpu->arch.apf.halted)
851ba692 5423 r = vcpu_enter_guest(vcpu);
d7690175 5424 else {
f656ce01 5425 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5426 kvm_vcpu_block(vcpu);
f656ce01 5427 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5428 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5429 {
5430 switch(vcpu->arch.mp_state) {
5431 case KVM_MP_STATE_HALTED:
d7690175 5432 vcpu->arch.mp_state =
09cec754
GN		 5433 KVM_MP_STATE_RUNNABLE;
5434 case KVM_MP_STATE_RUNNABLE:
af585b92 5435 vcpu->arch.apf.halted = false;
09cec754
GN		 5436 break;
5437 case KVM_MP_STATE_SIPI_RECEIVED:
5438 default:
5439 r = -EINTR;
5440 break;
5441 }
5442 }
d7690175
MT		 5443 }
5444
09cec754
GN		 5445 if (r <= 0)
5446 break;
5447
5448 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5449 if (kvm_cpu_has_pending_timer(vcpu))
5450 kvm_inject_pending_timer_irqs(vcpu);
5451
851ba692 5452 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5453 r = -EINTR;
851ba692 5454 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5455 ++vcpu->stat.request_irq_exits;
5456 }
af585b92
GN		 5457
5458 kvm_check_async_pf_completion(vcpu);
5459
09cec754
GN		 5460 if (signal_pending(current)) {
5461 r = -EINTR;
851ba692 5462 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5463 ++vcpu->stat.signal_exits;
5464 }
5465 if (need_resched()) {
f656ce01 5466 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5467 kvm_resched(vcpu);
f656ce01 5468 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5469 }
b6c7a5dc
HB		 5470 }
5471
f656ce01 5472 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5473
b93463aa
AK		 5474 vapic_exit(vcpu);
5475
b6c7a5dc
HB		 5476 return r;
5477}
5478
5287f194
AK		 5479static int complete_mmio(struct kvm_vcpu *vcpu)
5480{
5481 struct kvm_run *run = vcpu->run;
5482 int r;
5483
5484 if (!(vcpu->arch.pio.count || vcpu->mmio_needed))
5485 return 1;
5486
5487 if (vcpu->mmio_needed) {
5287f194 5488 vcpu->mmio_needed = 0;
cef4dea0 5489 if (!vcpu->mmio_is_write)
0004c7c2
GN		 5490 memcpy(vcpu->mmio_data + vcpu->mmio_index,
5491 run->mmio.data, 8);
cef4dea0
AK		 5492 vcpu->mmio_index += 8;
5493 if (vcpu->mmio_index < vcpu->mmio_size) {
5494 run->exit_reason = KVM_EXIT_MMIO;
5495 run->mmio.phys_addr = vcpu->mmio_phys_addr + vcpu->mmio_index;
5496 memcpy(run->mmio.data, vcpu->mmio_data + vcpu->mmio_index, 8);
5497 run->mmio.len = min(vcpu->mmio_size - vcpu->mmio_index, 8);
5498 run->mmio.is_write = vcpu->mmio_is_write;
5499 vcpu->mmio_needed = 1;
5500 return 0;
5501 }
5502 if (vcpu->mmio_is_write)
5503 return 1;
5504 vcpu->mmio_read_completed = 1;
5287f194
AK		 5505 }
5506 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5507 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5508 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5509 if (r != EMULATE_DONE)
5510 return 0;
5511 return 1;
5512}
5513
b6c7a5dc
HB		 5514int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5515{
5516 int r;
5517 sigset_t sigsaved;
5518
e5c30142
AK		 5519 if (!tsk_used_math(current) && init_fpu(current))
5520 return -ENOMEM;
5521
ac9f6dc0
AK		 5522 if (vcpu->sigset_active)
5523 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5524
a4535290 5525 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5526 kvm_vcpu_block(vcpu);
d7690175 5527 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5528 r = -EAGAIN;
5529 goto out;
b6c7a5dc
HB		 5530 }
5531
b6c7a5dc 5532 /* re-sync apic's tpr */
eea1cff9
AP		 5533 if (!irqchip_in_kernel(vcpu->kvm)) {
5534 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5535 r = -EINVAL;
5536 goto out;
5537 }
5538 }
b6c7a5dc 5539
5287f194
AK		 5540 r = complete_mmio(vcpu);
5541 if (r <= 0)
5542 goto out;
5543
851ba692 5544 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5545
5546out:
f1d86e46 5547 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5548 if (vcpu->sigset_active)
5549 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5550
b6c7a5dc
HB		 5551 return r;
5552}
5553
5554int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5555{
7ae441ea
GN		 5556 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
5557 /*
5558 * We are here if userspace calls get_regs() in the middle of
5559 * instruction emulation. Registers state needs to be copied
5560 * back from emulation context to vcpu. Usrapace shouldn't do
5561 * that usually, but some bad designed PV devices (vmware
5562 * backdoor interface) need this to work
5563 */
9dac77fa
AK		 5564 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5565 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
7ae441ea
GN		 5566 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5567 }
5fdbf976
MT		 5568 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5569 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5570 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5571 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5572 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5573 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5574 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5575 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5576#ifdef CONFIG_X86_64
5fdbf976
MT		 5577 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5578 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5579 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5580 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5581 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5582 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5583 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5584 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5585#endif
5586
5fdbf976 5587 regs->rip = kvm_rip_read(vcpu);
91586a3b 5588 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5589
b6c7a5dc
HB		 5590 return 0;
5591}
5592
5593int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5594{
7ae441ea
GN		 5595 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
5596 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5597
5fdbf976
MT		 5598 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5599 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5600 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5601 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5602 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5603 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5604 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5605 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5606#ifdef CONFIG_X86_64
5fdbf976
MT		 5607 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5608 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5609 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5610 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5611 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5612 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5613 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5614 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5615#endif
5616
5fdbf976 5617 kvm_rip_write(vcpu, regs->rip);
91586a3b 5618 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5619
b4f14abd
JK		 5620 vcpu->arch.exception.pending = false;
5621
3842d135
AK		 5622 kvm_make_request(KVM_REQ_EVENT, vcpu);
5623
b6c7a5dc
HB		 5624 return 0;
5625}
5626
b6c7a5dc
HB		 5627void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5628{
5629 struct kvm_segment cs;
5630
3e6e0aab 5631 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5632 *db = cs.db;
5633 *l = cs.l;
5634}
5635EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5636
5637int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5638 struct kvm_sregs *sregs)
5639{
89a27f4d 5640 struct desc_ptr dt;
b6c7a5dc 5641
3e6e0aab
GT		 5642 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5643 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5644 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5645 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5646 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5647 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5648
3e6e0aab
GT		 5649 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5650 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5651
5652 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5653 sregs->idt.limit = dt.size;
5654 sregs->idt.base = dt.address;
b6c7a5dc 5655 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5656 sregs->gdt.limit = dt.size;
5657 sregs->gdt.base = dt.address;
b6c7a5dc 5658
4d4ec087 5659 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 5660 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 5661 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 5662 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5663 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5664 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5665 sregs->apic_base = kvm_get_apic_base(vcpu);
5666
923c61bb 5667 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5668
36752c9b 5669 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5670 set_bit(vcpu->arch.interrupt.nr,
5671 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5672
b6c7a5dc
HB		 5673 return 0;
5674}
5675
62d9f0db
MT		 5676int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5677 struct kvm_mp_state *mp_state)
5678{
62d9f0db 5679 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5680 return 0;
5681}
5682
5683int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5684 struct kvm_mp_state *mp_state)
5685{
62d9f0db 5686 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 5687 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 5688 return 0;
5689}
5690
7f3d35fd
KW		 5691int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
5692 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 5693{
9d74191a 5694 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 5695 int ret;
e01c2426 5696
8ec4722d 5697 init_emulate_ctxt(vcpu);
c697518a 5698
7f3d35fd 5699 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 5700 has_error_code, error_code);
c697518a 5701
c697518a 5702 if (ret)
19d04437 5703 return EMULATE_FAIL;
37817f29 5704
9dac77fa 5705 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
9d74191a
TY		 5706 kvm_rip_write(vcpu, ctxt->eip);
5707 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 5708 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 5709 return EMULATE_DONE;
37817f29
IE		 5710}
5711EXPORT_SYMBOL_GPL(kvm_task_switch);
5712
b6c7a5dc
HB		 5713int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5714 struct kvm_sregs *sregs)
5715{
5716 int mmu_reset_needed = 0;
63f42e02 5717 int pending_vec, max_bits, idx;
89a27f4d 5718 struct desc_ptr dt;
b6c7a5dc 5719
89a27f4d
GN		 5720 dt.size = sregs->idt.limit;
5721 dt.address = sregs->idt.base;
b6c7a5dc 5722 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5723 dt.size = sregs->gdt.limit;
5724 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5725 kvm_x86_ops->set_gdt(vcpu, &dt);
5726
ad312c7c 5727 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 5728 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 5729 vcpu->arch.cr3 = sregs->cr3;
aff48baa 5730 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 5731
2d3ad1f4 5732 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5733
f6801dff 5734 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5735 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5736 kvm_set_apic_base(vcpu, sregs->apic_base);
5737
4d4ec087 5738 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5739 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5740 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5741
fc78f519 5742 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5743 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 5744 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 5745 kvm_update_cpuid(vcpu);
63f42e02
XG		 5746
5747 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 5748 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 5749 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 5750 mmu_reset_needed = 1;
5751 }
63f42e02 5752 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 5753
5754 if (mmu_reset_needed)
5755 kvm_mmu_reset_context(vcpu);
5756
923c61bb
GN		 5757 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5758 pending_vec = find_first_bit(
5759 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5760 if (pending_vec < max_bits) {
66fd3f7f 5761 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 5762 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 5763 }
5764
3e6e0aab
GT		 5765 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5766 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5767 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5768 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5769 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5770 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5771
3e6e0aab
GT		 5772 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5773 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5774
5f0269f5
ME		 5775 update_cr8_intercept(vcpu);
5776
9c3e4aab 5777 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5778 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5779 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5780 !is_protmode(vcpu))
9c3e4aab
MT		 5781 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5782
3842d135
AK		 5783 kvm_make_request(KVM_REQ_EVENT, vcpu);
5784
b6c7a5dc
HB		 5785 return 0;
5786}
5787
d0bfb940
JK		 5788int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5789 struct kvm_guest_debug *dbg)
b6c7a5dc 5790{
355be0b9 5791 unsigned long rflags;
ae675ef0 5792 int i, r;
b6c7a5dc 5793
4f926bf2
JK		 5794 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5795 r = -EBUSY;
5796 if (vcpu->arch.exception.pending)
2122ff5e 5797 goto out;
4f926bf2
JK		 5798 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5799 kvm_queue_exception(vcpu, DB_VECTOR);
5800 else
5801 kvm_queue_exception(vcpu, BP_VECTOR);
5802 }
5803
91586a3b
JK		 5804 /*
5805 * Read rflags as long as potentially injected trace flags are still
5806 * filtered out.
5807 */
5808 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5809
5810 vcpu->guest_debug = dbg->control;
5811 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5812 vcpu->guest_debug = 0;
5813
5814 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5815 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5816 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5817 vcpu->arch.switch_db_regs =
5818 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5819 } else {
5820 for (i = 0; i < KVM_NR_DB_REGS; i++)
5821 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5822 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5823 }
5824
f92653ee
JK		 5825 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5826 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5827 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5828
91586a3b
JK		 5829 /*
5830 * Trigger an rflags update that will inject or remove the trace
5831 * flags.
5832 */
5833 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5834
355be0b9 5835 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5836
4f926bf2 5837 r = 0;
d0bfb940 5838
2122ff5e 5839out:
b6c7a5dc
HB		 5840
5841 return r;
5842}
5843
8b006791
ZX		 5844/*
5845 * Translate a guest virtual address to a guest physical address.
5846 */
5847int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5848 struct kvm_translation *tr)
5849{
5850 unsigned long vaddr = tr->linear_address;
5851 gpa_t gpa;
f656ce01 5852 int idx;
8b006791 5853
f656ce01 5854 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5855 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5856 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5857 tr->physical_address = gpa;
5858 tr->valid = gpa != UNMAPPED_GVA;
5859 tr->writeable = 1;
5860 tr->usermode = 0;
8b006791
ZX		 5861
5862 return 0;
5863}
5864
d0752060
HB		 5865int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5866{
98918833
SY		 5867 struct i387_fxsave_struct *fxsave =
5868 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5869
d0752060
HB		 5870 memcpy(fpu->fpr, fxsave->st_space, 128);
5871 fpu->fcw = fxsave->cwd;
5872 fpu->fsw = fxsave->swd;
5873 fpu->ftwx = fxsave->twd;
5874 fpu->last_opcode = fxsave->fop;
5875 fpu->last_ip = fxsave->rip;
5876 fpu->last_dp = fxsave->rdp;
5877 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5878
d0752060
HB		 5879 return 0;
5880}
5881
5882int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5883{
98918833
SY		 5884 struct i387_fxsave_struct *fxsave =
5885 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5886
d0752060
HB		 5887 memcpy(fxsave->st_space, fpu->fpr, 128);
5888 fxsave->cwd = fpu->fcw;
5889 fxsave->swd = fpu->fsw;
5890 fxsave->twd = fpu->ftwx;
5891 fxsave->fop = fpu->last_opcode;
5892 fxsave->rip = fpu->last_ip;
5893 fxsave->rdp = fpu->last_dp;
5894 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5895
d0752060
HB		 5896 return 0;
5897}
5898
10ab25cd 5899int fx_init(struct kvm_vcpu *vcpu)
d0752060 5900{
10ab25cd
JK		 5901 int err;
5902
5903 err = fpu_alloc(&vcpu->arch.guest_fpu);
5904 if (err)
5905 return err;
5906
98918833 5907 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 5908
2acf923e
DC		 5909 /*
5910 * Ensure guest xcr0 is valid for loading
5911 */
5912 vcpu->arch.xcr0 = XSTATE_FP;
5913
ad312c7c 5914 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 5915
5916 return 0;
d0752060
HB		 5917}
5918EXPORT_SYMBOL_GPL(fx_init);
5919
98918833
SY		 5920static void fx_free(struct kvm_vcpu *vcpu)
5921{
5922 fpu_free(&vcpu->arch.guest_fpu);
5923}
5924
d0752060
HB		 5925void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5926{
2608d7a1 5927 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5928 return;
5929
2acf923e
DC		 5930 /*
5931 * Restore all possible states in the guest,
5932 * and assume host would use all available bits.
5933 * Guest xcr0 would be loaded later.
5934 */
5935 kvm_put_guest_xcr0(vcpu);
d0752060 5936 vcpu->guest_fpu_loaded = 1;
7cf30855 5937 unlazy_fpu(current);
98918833 5938 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 5939 trace_kvm_fpu(1);
d0752060 5940}
d0752060
HB		 5941
5942void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5943{
2acf923e
DC		 5944 kvm_put_guest_xcr0(vcpu);
5945
d0752060
HB		 5946 if (!vcpu->guest_fpu_loaded)
5947 return;
5948
5949 vcpu->guest_fpu_loaded = 0;
98918833 5950 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 5951 ++vcpu->stat.fpu_reload;
a8eeb04a 5952 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 5953 trace_kvm_fpu(0);
d0752060 5954}
e9b11c17
ZX		 5955
5956void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5957{
12f9a48f 5958 kvmclock_reset(vcpu);
7f1ea208 5959
f5f48ee1 5960 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 5961 fx_free(vcpu);
e9b11c17
ZX		 5962 kvm_x86_ops->vcpu_free(vcpu);
5963}
5964
5965struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5966 unsigned int id)
5967{
6755bae8
ZA		 5968 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5969 printk_once(KERN_WARNING
5970 "kvm: SMP vm created on host with unstable TSC; "
5971 "guest TSC will not be reliable\n");
26e5215f
AK		 5972 return kvm_x86_ops->vcpu_create(kvm, id);
5973}
e9b11c17 5974
26e5215f
AK		 5975int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5976{
5977 int r;
e9b11c17 5978
0bed3b56 5979 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5980 vcpu_load(vcpu);
5981 r = kvm_arch_vcpu_reset(vcpu);
5982 if (r == 0)
5983 r = kvm_mmu_setup(vcpu);
5984 vcpu_put(vcpu);
e9b11c17 5985
26e5215f 5986 return r;
e9b11c17
ZX		 5987}
5988
d40ccc62 5989void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 5990{
344d9588
GN		 5991 vcpu->arch.apf.msr_val = 0;
5992
e9b11c17
ZX		 5993 vcpu_load(vcpu);
5994 kvm_mmu_unload(vcpu);
5995 vcpu_put(vcpu);
5996
98918833 5997 fx_free(vcpu);
e9b11c17
ZX		 5998 kvm_x86_ops->vcpu_free(vcpu);
5999}
6000
6001int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
6002{
7460fb4a
AK		 6003 atomic_set(&vcpu->arch.nmi_queued, 0);
6004 vcpu->arch.nmi_pending = 0;
448fa4a9
JK		 6005 vcpu->arch.nmi_injected = false;
6006
42dbaa5a
JK		 6007 vcpu->arch.switch_db_regs = 0;
6008 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6009 vcpu->arch.dr6 = DR6_FIXED_1;
6010 vcpu->arch.dr7 = DR7_FIXED_1;
6011
3842d135 6012 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6013 vcpu->arch.apf.msr_val = 0;
c9aaa895 6014 vcpu->arch.st.msr_val = 0;
3842d135 6015
12f9a48f
GC		 6016 kvmclock_reset(vcpu);
6017
af585b92
GN		 6018 kvm_clear_async_pf_completion_queue(vcpu);
6019 kvm_async_pf_hash_reset(vcpu);
6020 vcpu->arch.apf.halted = false;
3842d135 6021
f5132b01
GN		 6022 kvm_pmu_reset(vcpu);
6023
e9b11c17
ZX		 6024 return kvm_x86_ops->vcpu_reset(vcpu);
6025}
6026
10474ae8 6027int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6028{
ca84d1a2
ZA		 6029 struct kvm *kvm;
6030 struct kvm_vcpu *vcpu;
6031 int i;
0dd6a6ed
ZA		 6032 int ret;
6033 u64 local_tsc;
6034 u64 max_tsc = 0;
6035 bool stable, backwards_tsc = false;
18863bdd
AK		 6036
6037 kvm_shared_msr_cpu_online();
0dd6a6ed
ZA		 6038 ret = kvm_x86_ops->hardware_enable(garbage);
6039 if (ret != 0)
6040 return ret;
6041
6042 local_tsc = native_read_tsc();
6043 stable = !check_tsc_unstable();
6044 list_for_each_entry(kvm, &vm_list, vm_list) {
6045 kvm_for_each_vcpu(i, vcpu, kvm) {
6046 if (!stable && vcpu->cpu == smp_processor_id())
6047 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6048 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6049 backwards_tsc = true;
6050 if (vcpu->arch.last_host_tsc > max_tsc)
6051 max_tsc = vcpu->arch.last_host_tsc;
6052 }
6053 }
6054 }
6055
6056 /*
6057 * Sometimes, even reliable TSCs go backwards. This happens on
6058 * platforms that reset TSC during suspend or hibernate actions, but
6059 * maintain synchronization. We must compensate. Fortunately, we can
6060 * detect that condition here, which happens early in CPU bringup,
6061 * before any KVM threads can be running. Unfortunately, we can't
6062 * bring the TSCs fully up to date with real time, as we aren't yet far
6063 * enough into CPU bringup that we know how much real time has actually
6064 * elapsed; our helper function, get_kernel_ns() will be using boot
6065 * variables that haven't been updated yet.
6066 *
6067 * So we simply find the maximum observed TSC above, then record the
6068 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6069 * the adjustment will be applied. Note that we accumulate
6070 * adjustments, in case multiple suspend cycles happen before some VCPU
6071 * gets a chance to run again. In the event that no KVM threads get a
6072 * chance to run, we will miss the entire elapsed period, as we'll have
6073 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6074 * loose cycle time. This isn't too big a deal, since the loss will be
6075 * uniform across all VCPUs (not to mention the scenario is extremely
6076 * unlikely). It is possible that a second hibernate recovery happens
6077 * much faster than a first, causing the observed TSC here to be
6078 * smaller; this would require additional padding adjustment, which is
6079 * why we set last_host_tsc to the local tsc observed here.
6080 *
6081 * N.B. - this code below runs only on platforms with reliable TSC,
6082 * as that is the only way backwards_tsc is set above. Also note
6083 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6084 * have the same delta_cyc adjustment applied if backwards_tsc
6085 * is detected. Note further, this adjustment is only done once,
6086 * as we reset last_host_tsc on all VCPUs to stop this from being
6087 * called multiple times (one for each physical CPU bringup).
6088 *
6089 * Platforms with unnreliable TSCs don't have to deal with this, they
6090 * will be compensated by the logic in vcpu_load, which sets the TSC to
6091 * catchup mode. This will catchup all VCPUs to real time, but cannot
6092 * guarantee that they stay in perfect synchronization.
6093 */
6094 if (backwards_tsc) {
6095 u64 delta_cyc = max_tsc - local_tsc;
6096 list_for_each_entry(kvm, &vm_list, vm_list) {
6097 kvm_for_each_vcpu(i, vcpu, kvm) {
6098 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6099 vcpu->arch.last_host_tsc = local_tsc;
6100 }
6101
6102 /*
6103 * We have to disable TSC offset matching.. if you were
6104 * booting a VM while issuing an S4 host suspend....
6105 * you may have some problem. Solving this issue is
6106 * left as an exercise to the reader.
6107 */
6108 kvm->arch.last_tsc_nsec = 0;
6109 kvm->arch.last_tsc_write = 0;
6110 }
6111
6112 }
6113 return 0;
e9b11c17
ZX		 6114}
6115
6116void kvm_arch_hardware_disable(void *garbage)
6117{
6118 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6119 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6120}
6121
6122int kvm_arch_hardware_setup(void)
6123{
6124 return kvm_x86_ops->hardware_setup();
6125}
6126
6127void kvm_arch_hardware_unsetup(void)
6128{
6129 kvm_x86_ops->hardware_unsetup();
6130}
6131
6132void kvm_arch_check_processor_compat(void *rtn)
6133{
6134 kvm_x86_ops->check_processor_compatibility(rtn);
6135}
6136
3e515705
AK		 6137bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6138{
6139 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6140}
6141
e9b11c17
ZX		 6142int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6143{
6144 struct page *page;
6145 struct kvm *kvm;
6146 int r;
6147
6148 BUG_ON(vcpu->kvm == NULL);
6149 kvm = vcpu->kvm;
6150
9aabc88f 6151 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 6152 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6153 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6154 else
a4535290 6155 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6156
6157 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6158 if (!page) {
6159 r = -ENOMEM;
6160 goto fail;
6161 }
ad312c7c 6162 vcpu->arch.pio_data = page_address(page);
e9b11c17 6163
cc578287 6164 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 6165
e9b11c17
ZX		 6166 r = kvm_mmu_create(vcpu);
6167 if (r < 0)
6168 goto fail_free_pio_data;
6169
6170 if (irqchip_in_kernel(kvm)) {
6171 r = kvm_create_lapic(vcpu);
6172 if (r < 0)
6173 goto fail_mmu_destroy;
6174 }
6175
890ca9ae
HY		 6176 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6177 GFP_KERNEL);
6178 if (!vcpu->arch.mce_banks) {
6179 r = -ENOMEM;
443c39bc 6180 goto fail_free_lapic;
890ca9ae
HY		 6181 }
6182 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6183
f5f48ee1
SY		 6184 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6185 goto fail_free_mce_banks;
6186
af585b92 6187 kvm_async_pf_hash_reset(vcpu);
f5132b01 6188 kvm_pmu_init(vcpu);
af585b92 6189
e9b11c17 6190 return 0;
f5f48ee1
SY		 6191fail_free_mce_banks:
6192 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6193fail_free_lapic:
6194 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6195fail_mmu_destroy:
6196 kvm_mmu_destroy(vcpu);
6197fail_free_pio_data:
ad312c7c 6198 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6199fail:
6200 return r;
6201}
6202
6203void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6204{
f656ce01
MT		 6205 int idx;
6206
f5132b01 6207 kvm_pmu_destroy(vcpu);
36cb93fd 6208 kfree(vcpu->arch.mce_banks);
e9b11c17 6209 kvm_free_lapic(vcpu);
f656ce01 6210 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6211 kvm_mmu_destroy(vcpu);
f656ce01 6212 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6213 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 6214}
d19a9cd2 6215
e08b9637 6216int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 6217{
e08b9637
CO		 6218 if (type)
6219 return -EINVAL;
6220
f05e70ac 6221 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 6222 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 6223
5550af4d
SY		 6224 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6225 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6226
038f8c11 6227 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
53f658b3 6228
d89f5eff 6229 return 0;
d19a9cd2
ZX		 6230}
6231
6232static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6233{
6234 vcpu_load(vcpu);
6235 kvm_mmu_unload(vcpu);
6236 vcpu_put(vcpu);
6237}
6238
6239static void kvm_free_vcpus(struct kvm *kvm)
6240{
6241 unsigned int i;
988a2cae 6242 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 6243
6244 /*
6245 * Unpin any mmu pages first.
6246 */
af585b92
GN		 6247 kvm_for_each_vcpu(i, vcpu, kvm) {
6248 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6249 kvm_unload_vcpu_mmu(vcpu);
af585b92 6250 }
988a2cae
GN		 6251 kvm_for_each_vcpu(i, vcpu, kvm)
6252 kvm_arch_vcpu_free(vcpu);
6253
6254 mutex_lock(&kvm->lock);
6255 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6256 kvm->vcpus[i] = NULL;
d19a9cd2 6257
988a2cae
GN		 6258 atomic_set(&kvm->online_vcpus, 0);
6259 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6260}
6261
ad8ba2cd
SY		 6262void kvm_arch_sync_events(struct kvm *kvm)
6263{
ba4cef31 6264 kvm_free_all_assigned_devices(kvm);
aea924f6 6265 kvm_free_pit(kvm);
ad8ba2cd
SY		 6266}
6267
d19a9cd2
ZX		 6268void kvm_arch_destroy_vm(struct kvm *kvm)
6269{
6eb55818 6270 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 6271 kfree(kvm->arch.vpic);
6272 kfree(kvm->arch.vioapic);
d19a9cd2 6273 kvm_free_vcpus(kvm);
3d45830c
AK		 6274 if (kvm->arch.apic_access_page)
6275 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 6276 if (kvm->arch.ept_identity_pagetable)
6277 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2 6278}
0de10343 6279
db3fe4eb
TY		 6280void kvm_arch_free_memslot(struct kvm_memory_slot *free,
6281 struct kvm_memory_slot *dont)
6282{
6283 int i;
6284
6285 for (i = 0; i < KVM_NR_PAGE_SIZES - 1; ++i) {
6286 if (!dont || free->arch.lpage_info[i] != dont->arch.lpage_info[i]) {
6287 vfree(free->arch.lpage_info[i]);
6288 free->arch.lpage_info[i] = NULL;
6289 }
6290 }
6291}
6292
6293int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
6294{
6295 int i;
6296
6297 for (i = 0; i < KVM_NR_PAGE_SIZES - 1; ++i) {
6298 unsigned long ugfn;
6299 int lpages;
6300 int level = i + 2;
6301
6302 lpages = gfn_to_index(slot->base_gfn + npages - 1,
6303 slot->base_gfn, level) + 1;
6304
6305 slot->arch.lpage_info[i] =
6306 vzalloc(lpages * sizeof(*slot->arch.lpage_info[i]));
6307 if (!slot->arch.lpage_info[i])
6308 goto out_free;
6309
6310 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
6311 slot->arch.lpage_info[i][0].write_count = 1;
6312 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
6313 slot->arch.lpage_info[i][lpages - 1].write_count = 1;
6314 ugfn = slot->userspace_addr >> PAGE_SHIFT;
6315 /*
6316 * If the gfn and userspace address are not aligned wrt each
6317 * other, or if explicitly asked to, disable large page
6318 * support for this slot
6319 */
6320 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
6321 !kvm_largepages_enabled()) {
6322 unsigned long j;
6323
6324 for (j = 0; j < lpages; ++j)
6325 slot->arch.lpage_info[i][j].write_count = 1;
6326 }
6327 }
6328
6329 return 0;
6330
6331out_free:
6332 for (i = 0; i < KVM_NR_PAGE_SIZES - 1; ++i) {
6333 vfree(slot->arch.lpage_info[i]);
6334 slot->arch.lpage_info[i] = NULL;
6335 }
6336 return -ENOMEM;
6337}
6338
f7784b8e
MT		 6339int kvm_arch_prepare_memory_region(struct kvm *kvm,
6340 struct kvm_memory_slot *memslot,
0de10343 6341 struct kvm_memory_slot old,
f7784b8e 6342 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 6343 int user_alloc)
6344{
f7784b8e 6345 int npages = memslot->npages;
7ac77099
AK		 6346 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6347
6348 /* Prevent internal slot pages from being moved by fork()/COW. */
6349 if (memslot->id >= KVM_MEMORY_SLOTS)
6350 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 6351
6352 /*To keep backward compatibility with older userspace,
6353 *x86 needs to hanlde !user_alloc case.
6354 */
6355 if (!user_alloc) {
6356 if (npages && !old.rmap) {
604b38ac
AA		 6357 unsigned long userspace_addr;
6358
72dc67a6 6359 down_write(&current->mm->mmap_sem);
604b38ac
AA		 6360 userspace_addr = do_mmap(NULL, 0,
6361 npages * PAGE_SIZE,
6362 PROT_READ | PROT_WRITE,
7ac77099 6363 map_flags,
604b38ac 6364 0);
72dc67a6 6365 up_write(&current->mm->mmap_sem);
0de10343 6366
604b38ac
AA		 6367 if (IS_ERR((void *)userspace_addr))
6368 return PTR_ERR((void *)userspace_addr);
6369
604b38ac 6370 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 6371 }
6372 }
6373
f7784b8e
MT		 6374
6375 return 0;
6376}
6377
6378void kvm_arch_commit_memory_region(struct kvm *kvm,
6379 struct kvm_userspace_memory_region *mem,
6380 struct kvm_memory_slot old,
6381 int user_alloc)
6382{
6383
48c0e4e9 6384 int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
f7784b8e
MT		 6385
6386 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
6387 int ret;
6388
6389 down_write(&current->mm->mmap_sem);
6390 ret = do_munmap(current->mm, old.userspace_addr,
6391 old.npages * PAGE_SIZE);
6392 up_write(&current->mm->mmap_sem);
6393 if (ret < 0)
6394 printk(KERN_WARNING
6395 "kvm_vm_ioctl_set_memory_region: "
6396 "failed to munmap memory\n");
6397 }
6398
48c0e4e9
XG		 6399 if (!kvm->arch.n_requested_mmu_pages)
6400 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6401
7c8a83b7 6402 spin_lock(&kvm->mmu_lock);
48c0e4e9 6403 if (nr_mmu_pages)
0de10343 6404 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
0de10343 6405 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 6406 spin_unlock(&kvm->mmu_lock);
0de10343 6407}
1d737c8a 6408
34d4cb8f
MT		 6409void kvm_arch_flush_shadow(struct kvm *kvm)
6410{
6411 kvm_mmu_zap_all(kvm);
8986ecc0 6412 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 6413}
6414
1d737c8a
ZX		 6415int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6416{
af585b92
GN		 6417 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6418 !vcpu->arch.apf.halted)
6419 || !list_empty_careful(&vcpu->async_pf.done)
a1b37100 6420 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
7460fb4a 6421 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 6422 (kvm_arch_interrupt_allowed(vcpu) &&
6423 kvm_cpu_has_interrupt(vcpu));
1d737c8a 6424}
5736199a 6425
b6d33834 6426int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 6427{
b6d33834 6428 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 6429}
78646121
GN		 6430
6431int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6432{
6433 return kvm_x86_ops->interrupt_allowed(vcpu);
6434}
229456fc 6435
f92653ee
JK		 6436bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6437{
6438 unsigned long current_rip = kvm_rip_read(vcpu) +
6439 get_segment_base(vcpu, VCPU_SREG_CS);
6440
6441 return current_rip == linear_rip;
6442}
6443EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6444
94fe45da
JK		 6445unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6446{
6447 unsigned long rflags;
6448
6449 rflags = kvm_x86_ops->get_rflags(vcpu);
6450 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 6451 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 6452 return rflags;
6453}
6454EXPORT_SYMBOL_GPL(kvm_get_rflags);
6455
6456void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6457{
6458 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 6459 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 6460 rflags |= X86_EFLAGS_TF;
94fe45da 6461 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 6462 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 6463}
6464EXPORT_SYMBOL_GPL(kvm_set_rflags);
6465
56028d08
GN		 6466void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6467{
6468 int r;
6469
fb67e14f 6470 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
c4806acd 6471 is_error_page(work->page))
56028d08
GN		 6472 return;
6473
6474 r = kvm_mmu_reload(vcpu);
6475 if (unlikely(r))
6476 return;
6477
fb67e14f
XG		 6478 if (!vcpu->arch.mmu.direct_map &&
6479 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
6480 return;
6481
56028d08
GN		 6482 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6483}
6484
af585b92
GN		 6485static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6486{
6487 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6488}
6489
6490static inline u32 kvm_async_pf_next_probe(u32 key)
6491{
6492 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6493}
6494
6495static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6496{
6497 u32 key = kvm_async_pf_hash_fn(gfn);
6498
6499 while (vcpu->arch.apf.gfns[key] != ~0)
6500 key = kvm_async_pf_next_probe(key);
6501
6502 vcpu->arch.apf.gfns[key] = gfn;
6503}
6504
6505static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6506{
6507 int i;
6508 u32 key = kvm_async_pf_hash_fn(gfn);
6509
6510 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 6511 (vcpu->arch.apf.gfns[key] != gfn &&
6512 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 6513 key = kvm_async_pf_next_probe(key);
6514
6515 return key;
6516}
6517
6518bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6519{
6520 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6521}
6522
6523static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6524{
6525 u32 i, j, k;
6526
6527 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6528 while (true) {
6529 vcpu->arch.apf.gfns[i] = ~0;
6530 do {
6531 j = kvm_async_pf_next_probe(j);
6532 if (vcpu->arch.apf.gfns[j] == ~0)
6533 return;
6534 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6535 /*
6536 * k lies cyclically in ]i,j]
6537 * | i.k.j |
6538 * |....j i.k.| or |.k..j i...|
6539 */
6540 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6541 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6542 i = j;
6543 }
6544}
6545
7c90705b
GN		 6546static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6547{
6548
6549 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6550 sizeof(val));
6551}
6552
af585b92
GN		 6553void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6554 struct kvm_async_pf *work)
6555{
6389ee94
AK		 6556 struct x86_exception fault;
6557
7c90705b 6558 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 6559 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 6560
6561 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 6562 (vcpu->arch.apf.send_user_only &&
6563 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 6564 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6565 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 6566 fault.vector = PF_VECTOR;
6567 fault.error_code_valid = true;
6568 fault.error_code = 0;
6569 fault.nested_page_fault = false;
6570 fault.address = work->arch.token;
6571 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6572 }
af585b92
GN		 6573}
6574
6575void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6576 struct kvm_async_pf *work)
6577{
6389ee94
AK		 6578 struct x86_exception fault;
6579
7c90705b
GN		 6580 trace_kvm_async_pf_ready(work->arch.token, work->gva);
6581 if (is_error_page(work->page))
6582 work->arch.token = ~0; /* broadcast wakeup */
6583 else
6584 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6585
6586 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
6587 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 6588 fault.vector = PF_VECTOR;
6589 fault.error_code_valid = true;
6590 fault.error_code = 0;
6591 fault.nested_page_fault = false;
6592 fault.address = work->arch.token;
6593 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6594 }
e6d53e3b 6595 vcpu->arch.apf.halted = false;
7c90705b
GN		 6596}
6597
6598bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
6599{
6600 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
6601 return true;
6602 else
6603 return !kvm_event_needs_reinjection(vcpu) &&
6604 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 6605}
6606
229456fc
MT		 6607EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6608EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6609EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6610EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6611EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 6612EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 6613EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 6614EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 6615EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 6616EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 6617EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 6618EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
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