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NVMe: Add pci suspend/resume driver callbacks
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CommitLineData
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1/*
2 * NVM Express device driver
3 * Copyright (c) 2011, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#include <linux/nvme.h>
20#include <linux/bio.h>
8de05535 21#include <linux/bitops.h>
b60503ba 22#include <linux/blkdev.h>
fd63e9ce 23#include <linux/delay.h>
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24#include <linux/errno.h>
25#include <linux/fs.h>
26#include <linux/genhd.h>
5aff9382 27#include <linux/idr.h>
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28#include <linux/init.h>
29#include <linux/interrupt.h>
30#include <linux/io.h>
31#include <linux/kdev_t.h>
1fa6aead 32#include <linux/kthread.h>
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33#include <linux/kernel.h>
34#include <linux/mm.h>
35#include <linux/module.h>
36#include <linux/moduleparam.h>
37#include <linux/pci.h>
be7b6275 38#include <linux/poison.h>
c3bfe717 39#include <linux/ptrace.h>
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40#include <linux/sched.h>
41#include <linux/slab.h>
42#include <linux/types.h>
5d0f6131 43#include <scsi/sg.h>
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44#include <asm-generic/io-64-nonatomic-lo-hi.h>
45
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46#define NVME_Q_DEPTH 1024
47#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
48#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
49#define NVME_MINORS 64
e85248e5 50#define ADMIN_TIMEOUT (60 * HZ)
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51
52static int nvme_major;
53module_param(nvme_major, int, 0);
54
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55static int use_threaded_interrupts;
56module_param(use_threaded_interrupts, int, 0);
57
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58static DEFINE_SPINLOCK(dev_list_lock);
59static LIST_HEAD(dev_list);
60static struct task_struct *nvme_thread;
61
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62/*
63 * An NVM Express queue. Each device has at least two (one for admin
64 * commands and one for I/O commands).
65 */
66struct nvme_queue {
67 struct device *q_dmadev;
091b6092 68 struct nvme_dev *dev;
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69 spinlock_t q_lock;
70 struct nvme_command *sq_cmds;
71 volatile struct nvme_completion *cqes;
72 dma_addr_t sq_dma_addr;
73 dma_addr_t cq_dma_addr;
74 wait_queue_head_t sq_full;
1fa6aead 75 wait_queue_t sq_cong_wait;
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76 struct bio_list sq_cong;
77 u32 __iomem *q_db;
78 u16 q_depth;
79 u16 cq_vector;
80 u16 sq_head;
81 u16 sq_tail;
82 u16 cq_head;
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83 u8 cq_phase;
84 u8 cqe_seen;
22404274 85 u8 q_suspended;
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86 unsigned long cmdid_data[];
87};
88
89/*
90 * Check we didin't inadvertently grow the command struct
91 */
92static inline void _nvme_check_size(void)
93{
94 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
95 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
96 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
97 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
98 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 99 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
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100 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
101 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
102 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
103 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 104 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
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105}
106
5c1281a3 107typedef void (*nvme_completion_fn)(struct nvme_dev *, void *,
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108 struct nvme_completion *);
109
e85248e5 110struct nvme_cmd_info {
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111 nvme_completion_fn fn;
112 void *ctx;
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113 unsigned long timeout;
114};
115
116static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
117{
118 return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
119}
120
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121static unsigned nvme_queue_extra(int depth)
122{
123 return DIV_ROUND_UP(depth, 8) + (depth * sizeof(struct nvme_cmd_info));
124}
125
b60503ba 126/**
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127 * alloc_cmdid() - Allocate a Command ID
128 * @nvmeq: The queue that will be used for this command
129 * @ctx: A pointer that will be passed to the handler
c2f5b650 130 * @handler: The function to call on completion
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131 *
132 * Allocate a Command ID for a queue. The data passed in will
133 * be passed to the completion handler. This is implemented by using
134 * the bottom two bits of the ctx pointer to store the handler ID.
135 * Passing in a pointer that's not 4-byte aligned will cause a BUG.
136 * We can change this if it becomes a problem.
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137 *
138 * May be called with local interrupts disabled and the q_lock held,
139 * or with interrupts enabled and no locks held.
b60503ba 140 */
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141static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx,
142 nvme_completion_fn handler, unsigned timeout)
b60503ba 143{
e6d15f79 144 int depth = nvmeq->q_depth - 1;
e85248e5 145 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
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146 int cmdid;
147
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148 do {
149 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
150 if (cmdid >= depth)
151 return -EBUSY;
152 } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
153
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154 info[cmdid].fn = handler;
155 info[cmdid].ctx = ctx;
e85248e5 156 info[cmdid].timeout = jiffies + timeout;
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157 return cmdid;
158}
159
160static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
c2f5b650 161 nvme_completion_fn handler, unsigned timeout)
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162{
163 int cmdid;
164 wait_event_killable(nvmeq->sq_full,
e85248e5 165 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
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166 return (cmdid < 0) ? -EINTR : cmdid;
167}
168
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169/* Special values must be less than 0x1000 */
170#define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
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171#define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
172#define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
173#define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
00df5cb4 174#define CMD_CTX_FLUSH (0x318 + CMD_CTX_BASE)
be7b6275 175
5c1281a3 176static void special_completion(struct nvme_dev *dev, void *ctx,
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177 struct nvme_completion *cqe)
178{
179 if (ctx == CMD_CTX_CANCELLED)
180 return;
181 if (ctx == CMD_CTX_FLUSH)
182 return;
183 if (ctx == CMD_CTX_COMPLETED) {
5c1281a3 184 dev_warn(&dev->pci_dev->dev,
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185 "completed id %d twice on queue %d\n",
186 cqe->command_id, le16_to_cpup(&cqe->sq_id));
187 return;
188 }
189 if (ctx == CMD_CTX_INVALID) {
5c1281a3 190 dev_warn(&dev->pci_dev->dev,
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191 "invalid id %d completed on queue %d\n",
192 cqe->command_id, le16_to_cpup(&cqe->sq_id));
193 return;
194 }
195
5c1281a3 196 dev_warn(&dev->pci_dev->dev, "Unknown special completion %p\n", ctx);
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197}
198
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199/*
200 * Called with local interrupts disabled and the q_lock held. May not sleep.
201 */
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202static void *free_cmdid(struct nvme_queue *nvmeq, int cmdid,
203 nvme_completion_fn *fn)
b60503ba 204{
c2f5b650 205 void *ctx;
e85248e5 206 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
b60503ba 207
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208 if (cmdid >= nvmeq->q_depth) {
209 *fn = special_completion;
48e3d398 210 return CMD_CTX_INVALID;
c2f5b650 211 }
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212 if (fn)
213 *fn = info[cmdid].fn;
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214 ctx = info[cmdid].ctx;
215 info[cmdid].fn = special_completion;
e85248e5 216 info[cmdid].ctx = CMD_CTX_COMPLETED;
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217 clear_bit(cmdid, nvmeq->cmdid_data);
218 wake_up(&nvmeq->sq_full);
c2f5b650 219 return ctx;
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220}
221
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222static void *cancel_cmdid(struct nvme_queue *nvmeq, int cmdid,
223 nvme_completion_fn *fn)
3c0cf138 224{
c2f5b650 225 void *ctx;
e85248e5 226 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
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227 if (fn)
228 *fn = info[cmdid].fn;
229 ctx = info[cmdid].ctx;
230 info[cmdid].fn = special_completion;
e85248e5 231 info[cmdid].ctx = CMD_CTX_CANCELLED;
c2f5b650 232 return ctx;
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233}
234
5d0f6131 235struct nvme_queue *get_nvmeq(struct nvme_dev *dev)
b60503ba 236{
040a93b5 237 return dev->queues[get_cpu() + 1];
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238}
239
5d0f6131 240void put_nvmeq(struct nvme_queue *nvmeq)
b60503ba 241{
1b23484b 242 put_cpu();
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243}
244
245/**
714a7a22 246 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
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247 * @nvmeq: The queue to use
248 * @cmd: The command to send
249 *
250 * Safe to use from interrupt context
251 */
252static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
253{
254 unsigned long flags;
255 u16 tail;
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256 spin_lock_irqsave(&nvmeq->q_lock, flags);
257 tail = nvmeq->sq_tail;
258 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
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259 if (++tail == nvmeq->q_depth)
260 tail = 0;
7547881d 261 writel(tail, nvmeq->q_db);
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262 nvmeq->sq_tail = tail;
263 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
264
265 return 0;
266}
267
eca18b23 268static __le64 **iod_list(struct nvme_iod *iod)
e025344c 269{
eca18b23 270 return ((void *)iod) + iod->offset;
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271}
272
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273/*
274 * Will slightly overestimate the number of pages needed. This is OK
275 * as it only leads to a small amount of wasted memory for the lifetime of
276 * the I/O.
277 */
278static int nvme_npages(unsigned size)
279{
280 unsigned nprps = DIV_ROUND_UP(size + PAGE_SIZE, PAGE_SIZE);
281 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
282}
b60503ba 283
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284static struct nvme_iod *
285nvme_alloc_iod(unsigned nseg, unsigned nbytes, gfp_t gfp)
b60503ba 286{
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287 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
288 sizeof(__le64 *) * nvme_npages(nbytes) +
289 sizeof(struct scatterlist) * nseg, gfp);
290
291 if (iod) {
292 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
293 iod->npages = -1;
294 iod->length = nbytes;
2b196034 295 iod->nents = 0;
6198221f 296 iod->start_time = jiffies;
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297 }
298
299 return iod;
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300}
301
5d0f6131 302void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
b60503ba 303{
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304 const int last_prp = PAGE_SIZE / 8 - 1;
305 int i;
306 __le64 **list = iod_list(iod);
307 dma_addr_t prp_dma = iod->first_dma;
308
309 if (iod->npages == 0)
310 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
311 for (i = 0; i < iod->npages; i++) {
312 __le64 *prp_list = list[i];
313 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
314 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
315 prp_dma = next_prp_dma;
316 }
317 kfree(iod);
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318}
319
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320static void nvme_start_io_acct(struct bio *bio)
321{
322 struct gendisk *disk = bio->bi_bdev->bd_disk;
323 const int rw = bio_data_dir(bio);
324 int cpu = part_stat_lock();
325 part_round_stats(cpu, &disk->part0);
326 part_stat_inc(cpu, &disk->part0, ios[rw]);
327 part_stat_add(cpu, &disk->part0, sectors[rw], bio_sectors(bio));
328 part_inc_in_flight(&disk->part0, rw);
329 part_stat_unlock();
330}
331
332static void nvme_end_io_acct(struct bio *bio, unsigned long start_time)
333{
334 struct gendisk *disk = bio->bi_bdev->bd_disk;
335 const int rw = bio_data_dir(bio);
336 unsigned long duration = jiffies - start_time;
337 int cpu = part_stat_lock();
338 part_stat_add(cpu, &disk->part0, ticks[rw], duration);
339 part_round_stats(cpu, &disk->part0);
340 part_dec_in_flight(&disk->part0, rw);
341 part_stat_unlock();
342}
343
5c1281a3 344static void bio_completion(struct nvme_dev *dev, void *ctx,
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345 struct nvme_completion *cqe)
346{
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347 struct nvme_iod *iod = ctx;
348 struct bio *bio = iod->private;
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349 u16 status = le16_to_cpup(&cqe->status) >> 1;
350
9e59d091 351 if (iod->nents) {
2b196034 352 dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
b60503ba 353 bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
9e59d091
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354 nvme_end_io_acct(bio, iod->start_time);
355 }
eca18b23 356 nvme_free_iod(dev, iod);
427e9708 357 if (status)
1ad2f893 358 bio_endio(bio, -EIO);
427e9708 359 else
1ad2f893 360 bio_endio(bio, 0);
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361}
362
184d2944 363/* length is in bytes. gfp flags indicates whether we may sleep. */
5d0f6131
VV
364int nvme_setup_prps(struct nvme_dev *dev, struct nvme_common_command *cmd,
365 struct nvme_iod *iod, int total_len, gfp_t gfp)
ff22b54f 366{
99802a7a 367 struct dma_pool *pool;
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368 int length = total_len;
369 struct scatterlist *sg = iod->sg;
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370 int dma_len = sg_dma_len(sg);
371 u64 dma_addr = sg_dma_address(sg);
372 int offset = offset_in_page(dma_addr);
e025344c 373 __le64 *prp_list;
eca18b23 374 __le64 **list = iod_list(iod);
e025344c 375 dma_addr_t prp_dma;
eca18b23 376 int nprps, i;
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377
378 cmd->prp1 = cpu_to_le64(dma_addr);
379 length -= (PAGE_SIZE - offset);
380 if (length <= 0)
eca18b23 381 return total_len;
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382
383 dma_len -= (PAGE_SIZE - offset);
384 if (dma_len) {
385 dma_addr += (PAGE_SIZE - offset);
386 } else {
387 sg = sg_next(sg);
388 dma_addr = sg_dma_address(sg);
389 dma_len = sg_dma_len(sg);
390 }
391
392 if (length <= PAGE_SIZE) {
393 cmd->prp2 = cpu_to_le64(dma_addr);
eca18b23 394 return total_len;
e025344c
SMM
395 }
396
397 nprps = DIV_ROUND_UP(length, PAGE_SIZE);
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MW
398 if (nprps <= (256 / 8)) {
399 pool = dev->prp_small_pool;
eca18b23 400 iod->npages = 0;
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MW
401 } else {
402 pool = dev->prp_page_pool;
eca18b23 403 iod->npages = 1;
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MW
404 }
405
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406 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
407 if (!prp_list) {
408 cmd->prp2 = cpu_to_le64(dma_addr);
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409 iod->npages = -1;
410 return (total_len - length) + PAGE_SIZE;
b77954cb 411 }
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412 list[0] = prp_list;
413 iod->first_dma = prp_dma;
e025344c
SMM
414 cmd->prp2 = cpu_to_le64(prp_dma);
415 i = 0;
416 for (;;) {
7523d834 417 if (i == PAGE_SIZE / 8) {
e025344c 418 __le64 *old_prp_list = prp_list;
b77954cb 419 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
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420 if (!prp_list)
421 return total_len - length;
422 list[iod->npages++] = prp_list;
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423 prp_list[0] = old_prp_list[i - 1];
424 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
425 i = 1;
e025344c
SMM
426 }
427 prp_list[i++] = cpu_to_le64(dma_addr);
428 dma_len -= PAGE_SIZE;
429 dma_addr += PAGE_SIZE;
430 length -= PAGE_SIZE;
431 if (length <= 0)
432 break;
433 if (dma_len > 0)
434 continue;
435 BUG_ON(dma_len < 0);
436 sg = sg_next(sg);
437 dma_addr = sg_dma_address(sg);
438 dma_len = sg_dma_len(sg);
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439 }
440
eca18b23 441 return total_len;
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442}
443
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444struct nvme_bio_pair {
445 struct bio b1, b2, *parent;
446 struct bio_vec *bv1, *bv2;
447 int err;
448 atomic_t cnt;
449};
450
451static void nvme_bio_pair_endio(struct bio *bio, int err)
452{
453 struct nvme_bio_pair *bp = bio->bi_private;
454
455 if (err)
456 bp->err = err;
457
458 if (atomic_dec_and_test(&bp->cnt)) {
459 bio_endio(bp->parent, bp->err);
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460 kfree(bp->bv1);
461 kfree(bp->bv2);
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462 kfree(bp);
463 }
464}
465
466static struct nvme_bio_pair *nvme_bio_split(struct bio *bio, int idx,
467 int len, int offset)
468{
469 struct nvme_bio_pair *bp;
470
471 BUG_ON(len > bio->bi_size);
472 BUG_ON(idx > bio->bi_vcnt);
473
474 bp = kmalloc(sizeof(*bp), GFP_ATOMIC);
475 if (!bp)
476 return NULL;
477 bp->err = 0;
478
479 bp->b1 = *bio;
480 bp->b2 = *bio;
481
482 bp->b1.bi_size = len;
483 bp->b2.bi_size -= len;
484 bp->b1.bi_vcnt = idx;
485 bp->b2.bi_idx = idx;
486 bp->b2.bi_sector += len >> 9;
487
488 if (offset) {
489 bp->bv1 = kmalloc(bio->bi_max_vecs * sizeof(struct bio_vec),
490 GFP_ATOMIC);
491 if (!bp->bv1)
492 goto split_fail_1;
493
494 bp->bv2 = kmalloc(bio->bi_max_vecs * sizeof(struct bio_vec),
495 GFP_ATOMIC);
496 if (!bp->bv2)
497 goto split_fail_2;
498
499 memcpy(bp->bv1, bio->bi_io_vec,
500 bio->bi_max_vecs * sizeof(struct bio_vec));
501 memcpy(bp->bv2, bio->bi_io_vec,
502 bio->bi_max_vecs * sizeof(struct bio_vec));
503
504 bp->b1.bi_io_vec = bp->bv1;
505 bp->b2.bi_io_vec = bp->bv2;
506 bp->b2.bi_io_vec[idx].bv_offset += offset;
507 bp->b2.bi_io_vec[idx].bv_len -= offset;
508 bp->b1.bi_io_vec[idx].bv_len = offset;
509 bp->b1.bi_vcnt++;
510 } else
511 bp->bv1 = bp->bv2 = NULL;
512
513 bp->b1.bi_private = bp;
514 bp->b2.bi_private = bp;
515
516 bp->b1.bi_end_io = nvme_bio_pair_endio;
517 bp->b2.bi_end_io = nvme_bio_pair_endio;
518
519 bp->parent = bio;
520 atomic_set(&bp->cnt, 2);
521
522 return bp;
523
524 split_fail_2:
525 kfree(bp->bv1);
526 split_fail_1:
527 kfree(bp);
528 return NULL;
529}
530
531static int nvme_split_and_submit(struct bio *bio, struct nvme_queue *nvmeq,
532 int idx, int len, int offset)
533{
534 struct nvme_bio_pair *bp = nvme_bio_split(bio, idx, len, offset);
535 if (!bp)
536 return -ENOMEM;
537
538 if (bio_list_empty(&nvmeq->sq_cong))
539 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
540 bio_list_add(&nvmeq->sq_cong, &bp->b1);
541 bio_list_add(&nvmeq->sq_cong, &bp->b2);
542
543 return 0;
544}
545
1ad2f893
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546/* NVMe scatterlists require no holes in the virtual address */
547#define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2) ((vec2)->bv_offset || \
548 (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE))
549
427e9708 550static int nvme_map_bio(struct nvme_queue *nvmeq, struct nvme_iod *iod,
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551 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
552{
76830840
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553 struct bio_vec *bvec, *bvprv = NULL;
554 struct scatterlist *sg = NULL;
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555 int i, length = 0, nsegs = 0, split_len = bio->bi_size;
556
557 if (nvmeq->dev->stripe_size)
558 split_len = nvmeq->dev->stripe_size -
559 ((bio->bi_sector << 9) & (nvmeq->dev->stripe_size - 1));
b60503ba 560
eca18b23 561 sg_init_table(iod->sg, psegs);
b60503ba 562 bio_for_each_segment(bvec, bio, i) {
76830840
MW
563 if (bvprv && BIOVEC_PHYS_MERGEABLE(bvprv, bvec)) {
564 sg->length += bvec->bv_len;
565 } else {
1ad2f893 566 if (bvprv && BIOVEC_NOT_VIRT_MERGEABLE(bvprv, bvec))
427e9708
KB
567 return nvme_split_and_submit(bio, nvmeq, i,
568 length, 0);
569
eca18b23 570 sg = sg ? sg + 1 : iod->sg;
76830840
MW
571 sg_set_page(sg, bvec->bv_page, bvec->bv_len,
572 bvec->bv_offset);
573 nsegs++;
574 }
159b67d7
KB
575
576 if (split_len - length < bvec->bv_len)
577 return nvme_split_and_submit(bio, nvmeq, i, split_len,
578 split_len - length);
1ad2f893 579 length += bvec->bv_len;
76830840 580 bvprv = bvec;
b60503ba 581 }
eca18b23 582 iod->nents = nsegs;
76830840 583 sg_mark_end(sg);
427e9708 584 if (dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir) == 0)
1ad2f893 585 return -ENOMEM;
427e9708 586
159b67d7 587 BUG_ON(length != bio->bi_size);
1ad2f893 588 return length;
b60503ba
MW
589}
590
0e5e4f0e
KB
591/*
592 * We reuse the small pool to allocate the 16-byte range here as it is not
593 * worth having a special pool for these or additional cases to handle freeing
594 * the iod.
595 */
596static int nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
597 struct bio *bio, struct nvme_iod *iod, int cmdid)
598{
599 struct nvme_dsm_range *range;
600 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
601
602 range = dma_pool_alloc(nvmeq->dev->prp_small_pool, GFP_ATOMIC,
603 &iod->first_dma);
604 if (!range)
605 return -ENOMEM;
606
607 iod_list(iod)[0] = (__le64 *)range;
608 iod->npages = 0;
609
610 range->cattr = cpu_to_le32(0);
611 range->nlb = cpu_to_le32(bio->bi_size >> ns->lba_shift);
063cc6d5 612 range->slba = cpu_to_le64(nvme_block_nr(ns, bio->bi_sector));
0e5e4f0e
KB
613
614 memset(cmnd, 0, sizeof(*cmnd));
615 cmnd->dsm.opcode = nvme_cmd_dsm;
616 cmnd->dsm.command_id = cmdid;
617 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
618 cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
619 cmnd->dsm.nr = 0;
620 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
621
622 if (++nvmeq->sq_tail == nvmeq->q_depth)
623 nvmeq->sq_tail = 0;
624 writel(nvmeq->sq_tail, nvmeq->q_db);
625
626 return 0;
627}
628
00df5cb4
MW
629static int nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
630 int cmdid)
631{
632 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
633
634 memset(cmnd, 0, sizeof(*cmnd));
635 cmnd->common.opcode = nvme_cmd_flush;
636 cmnd->common.command_id = cmdid;
637 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
638
639 if (++nvmeq->sq_tail == nvmeq->q_depth)
640 nvmeq->sq_tail = 0;
641 writel(nvmeq->sq_tail, nvmeq->q_db);
642
643 return 0;
644}
645
5d0f6131 646int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns)
00df5cb4
MW
647{
648 int cmdid = alloc_cmdid(nvmeq, (void *)CMD_CTX_FLUSH,
ff976d72 649 special_completion, NVME_IO_TIMEOUT);
00df5cb4
MW
650 if (unlikely(cmdid < 0))
651 return cmdid;
652
653 return nvme_submit_flush(nvmeq, ns, cmdid);
654}
655
184d2944
MW
656/*
657 * Called with local interrupts disabled and the q_lock held. May not sleep.
658 */
b60503ba
MW
659static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
660 struct bio *bio)
661{
ff22b54f 662 struct nvme_command *cmnd;
eca18b23 663 struct nvme_iod *iod;
b60503ba 664 enum dma_data_direction dma_dir;
1287dabd 665 int cmdid, length, result;
b60503ba
MW
666 u16 control;
667 u32 dsmgmt;
b60503ba
MW
668 int psegs = bio_phys_segments(ns->queue, bio);
669
00df5cb4
MW
670 if ((bio->bi_rw & REQ_FLUSH) && psegs) {
671 result = nvme_submit_flush_data(nvmeq, ns);
672 if (result)
673 return result;
674 }
675
1287dabd 676 result = -ENOMEM;
eca18b23
MW
677 iod = nvme_alloc_iod(psegs, bio->bi_size, GFP_ATOMIC);
678 if (!iod)
eeee3226 679 goto nomem;
eca18b23 680 iod->private = bio;
b60503ba 681
eeee3226 682 result = -EBUSY;
ff976d72 683 cmdid = alloc_cmdid(nvmeq, iod, bio_completion, NVME_IO_TIMEOUT);
b60503ba 684 if (unlikely(cmdid < 0))
eca18b23 685 goto free_iod;
b60503ba 686
0e5e4f0e
KB
687 if (bio->bi_rw & REQ_DISCARD) {
688 result = nvme_submit_discard(nvmeq, ns, bio, iod, cmdid);
689 if (result)
690 goto free_cmdid;
691 return result;
692 }
00df5cb4
MW
693 if ((bio->bi_rw & REQ_FLUSH) && !psegs)
694 return nvme_submit_flush(nvmeq, ns, cmdid);
695
b60503ba
MW
696 control = 0;
697 if (bio->bi_rw & REQ_FUA)
698 control |= NVME_RW_FUA;
699 if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
700 control |= NVME_RW_LR;
701
702 dsmgmt = 0;
703 if (bio->bi_rw & REQ_RAHEAD)
704 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
705
ff22b54f 706 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
b60503ba 707
b8deb62c 708 memset(cmnd, 0, sizeof(*cmnd));
b60503ba 709 if (bio_data_dir(bio)) {
ff22b54f 710 cmnd->rw.opcode = nvme_cmd_write;
b60503ba
MW
711 dma_dir = DMA_TO_DEVICE;
712 } else {
ff22b54f 713 cmnd->rw.opcode = nvme_cmd_read;
b60503ba
MW
714 dma_dir = DMA_FROM_DEVICE;
715 }
716
427e9708
KB
717 result = nvme_map_bio(nvmeq, iod, bio, dma_dir, psegs);
718 if (result <= 0)
859361a2 719 goto free_cmdid;
1ad2f893 720 length = result;
b60503ba 721
ff22b54f
MW
722 cmnd->rw.command_id = cmdid;
723 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
eca18b23
MW
724 length = nvme_setup_prps(nvmeq->dev, &cmnd->common, iod, length,
725 GFP_ATOMIC);
063cc6d5 726 cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, bio->bi_sector));
1ad2f893 727 cmnd->rw.length = cpu_to_le16((length >> ns->lba_shift) - 1);
ff22b54f
MW
728 cmnd->rw.control = cpu_to_le16(control);
729 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
b60503ba 730
6198221f 731 nvme_start_io_acct(bio);
b60503ba
MW
732 if (++nvmeq->sq_tail == nvmeq->q_depth)
733 nvmeq->sq_tail = 0;
7547881d 734 writel(nvmeq->sq_tail, nvmeq->q_db);
b60503ba 735
1974b1ae
MW
736 return 0;
737
859361a2
KB
738 free_cmdid:
739 free_cmdid(nvmeq, cmdid, NULL);
eca18b23
MW
740 free_iod:
741 nvme_free_iod(nvmeq->dev, iod);
eeee3226
MW
742 nomem:
743 return result;
b60503ba
MW
744}
745
e9539f47 746static int nvme_process_cq(struct nvme_queue *nvmeq)
b60503ba 747{
82123460 748 u16 head, phase;
b60503ba 749
b60503ba 750 head = nvmeq->cq_head;
82123460 751 phase = nvmeq->cq_phase;
b60503ba
MW
752
753 for (;;) {
c2f5b650
MW
754 void *ctx;
755 nvme_completion_fn fn;
b60503ba 756 struct nvme_completion cqe = nvmeq->cqes[head];
82123460 757 if ((le16_to_cpu(cqe.status) & 1) != phase)
b60503ba
MW
758 break;
759 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
760 if (++head == nvmeq->q_depth) {
761 head = 0;
82123460 762 phase = !phase;
b60503ba
MW
763 }
764
c2f5b650 765 ctx = free_cmdid(nvmeq, cqe.command_id, &fn);
5c1281a3 766 fn(nvmeq->dev, ctx, &cqe);
b60503ba
MW
767 }
768
769 /* If the controller ignores the cq head doorbell and continuously
770 * writes to the queue, it is theoretically possible to wrap around
771 * the queue twice and mistakenly return IRQ_NONE. Linux only
772 * requires that 0.1% of your interrupts are handled, so this isn't
773 * a big problem.
774 */
82123460 775 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
e9539f47 776 return 0;
b60503ba 777
f1938f6e 778 writel(head, nvmeq->q_db + (1 << nvmeq->dev->db_stride));
b60503ba 779 nvmeq->cq_head = head;
82123460 780 nvmeq->cq_phase = phase;
b60503ba 781
e9539f47
MW
782 nvmeq->cqe_seen = 1;
783 return 1;
b60503ba
MW
784}
785
7d822457
MW
786static void nvme_make_request(struct request_queue *q, struct bio *bio)
787{
788 struct nvme_ns *ns = q->queuedata;
789 struct nvme_queue *nvmeq = get_nvmeq(ns->dev);
790 int result = -EBUSY;
791
cd638946
KB
792 if (!nvmeq) {
793 put_nvmeq(NULL);
794 bio_endio(bio, -EIO);
795 return;
796 }
797
7d822457 798 spin_lock_irq(&nvmeq->q_lock);
22404274 799 if (!nvmeq->q_suspended && bio_list_empty(&nvmeq->sq_cong))
7d822457
MW
800 result = nvme_submit_bio_queue(nvmeq, ns, bio);
801 if (unlikely(result)) {
802 if (bio_list_empty(&nvmeq->sq_cong))
803 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
804 bio_list_add(&nvmeq->sq_cong, bio);
805 }
806
807 nvme_process_cq(nvmeq);
808 spin_unlock_irq(&nvmeq->q_lock);
809 put_nvmeq(nvmeq);
810}
811
b60503ba 812static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5
MW
813{
814 irqreturn_t result;
815 struct nvme_queue *nvmeq = data;
816 spin_lock(&nvmeq->q_lock);
e9539f47
MW
817 nvme_process_cq(nvmeq);
818 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
819 nvmeq->cqe_seen = 0;
58ffacb5
MW
820 spin_unlock(&nvmeq->q_lock);
821 return result;
822}
823
824static irqreturn_t nvme_irq_check(int irq, void *data)
825{
826 struct nvme_queue *nvmeq = data;
827 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
828 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
829 return IRQ_NONE;
830 return IRQ_WAKE_THREAD;
831}
832
3c0cf138
MW
833static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
834{
835 spin_lock_irq(&nvmeq->q_lock);
c2f5b650 836 cancel_cmdid(nvmeq, cmdid, NULL);
3c0cf138
MW
837 spin_unlock_irq(&nvmeq->q_lock);
838}
839
c2f5b650
MW
840struct sync_cmd_info {
841 struct task_struct *task;
842 u32 result;
843 int status;
844};
845
5c1281a3 846static void sync_completion(struct nvme_dev *dev, void *ctx,
c2f5b650
MW
847 struct nvme_completion *cqe)
848{
849 struct sync_cmd_info *cmdinfo = ctx;
850 cmdinfo->result = le32_to_cpup(&cqe->result);
851 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
852 wake_up_process(cmdinfo->task);
853}
854
b60503ba
MW
855/*
856 * Returns 0 on success. If the result is negative, it's a Linux error code;
857 * if the result is positive, it's an NVM Express status code
858 */
5d0f6131
VV
859int nvme_submit_sync_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
860 u32 *result, unsigned timeout)
b60503ba
MW
861{
862 int cmdid;
863 struct sync_cmd_info cmdinfo;
864
865 cmdinfo.task = current;
866 cmdinfo.status = -EINTR;
867
c2f5b650 868 cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion,
e85248e5 869 timeout);
b60503ba
MW
870 if (cmdid < 0)
871 return cmdid;
872 cmd->common.command_id = cmdid;
873
3c0cf138
MW
874 set_current_state(TASK_KILLABLE);
875 nvme_submit_cmd(nvmeq, cmd);
78f8d257 876 schedule_timeout(timeout);
b60503ba 877
3c0cf138
MW
878 if (cmdinfo.status == -EINTR) {
879 nvme_abort_command(nvmeq, cmdid);
880 return -EINTR;
881 }
882
b60503ba
MW
883 if (result)
884 *result = cmdinfo.result;
885
886 return cmdinfo.status;
887}
888
5d0f6131 889int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
b60503ba
MW
890 u32 *result)
891{
e85248e5 892 return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT);
b60503ba
MW
893}
894
895static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
896{
897 int status;
898 struct nvme_command c;
899
900 memset(&c, 0, sizeof(c));
901 c.delete_queue.opcode = opcode;
902 c.delete_queue.qid = cpu_to_le16(id);
903
904 status = nvme_submit_admin_cmd(dev, &c, NULL);
905 if (status)
906 return -EIO;
907 return 0;
908}
909
910static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
911 struct nvme_queue *nvmeq)
912{
913 int status;
914 struct nvme_command c;
915 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
916
917 memset(&c, 0, sizeof(c));
918 c.create_cq.opcode = nvme_admin_create_cq;
919 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
920 c.create_cq.cqid = cpu_to_le16(qid);
921 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
922 c.create_cq.cq_flags = cpu_to_le16(flags);
923 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
924
925 status = nvme_submit_admin_cmd(dev, &c, NULL);
926 if (status)
927 return -EIO;
928 return 0;
929}
930
931static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
932 struct nvme_queue *nvmeq)
933{
934 int status;
935 struct nvme_command c;
936 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
937
938 memset(&c, 0, sizeof(c));
939 c.create_sq.opcode = nvme_admin_create_sq;
940 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
941 c.create_sq.sqid = cpu_to_le16(qid);
942 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
943 c.create_sq.sq_flags = cpu_to_le16(flags);
944 c.create_sq.cqid = cpu_to_le16(qid);
945
946 status = nvme_submit_admin_cmd(dev, &c, NULL);
947 if (status)
948 return -EIO;
949 return 0;
950}
951
952static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
953{
954 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
955}
956
957static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
958{
959 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
960}
961
5d0f6131 962int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns,
bc5fc7e4
MW
963 dma_addr_t dma_addr)
964{
965 struct nvme_command c;
966
967 memset(&c, 0, sizeof(c));
968 c.identify.opcode = nvme_admin_identify;
969 c.identify.nsid = cpu_to_le32(nsid);
970 c.identify.prp1 = cpu_to_le64(dma_addr);
971 c.identify.cns = cpu_to_le32(cns);
972
973 return nvme_submit_admin_cmd(dev, &c, NULL);
974}
975
5d0f6131 976int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
08df1e05 977 dma_addr_t dma_addr, u32 *result)
bc5fc7e4
MW
978{
979 struct nvme_command c;
980
981 memset(&c, 0, sizeof(c));
982 c.features.opcode = nvme_admin_get_features;
a42cecce 983 c.features.nsid = cpu_to_le32(nsid);
bc5fc7e4
MW
984 c.features.prp1 = cpu_to_le64(dma_addr);
985 c.features.fid = cpu_to_le32(fid);
bc5fc7e4 986
08df1e05 987 return nvme_submit_admin_cmd(dev, &c, result);
df348139
MW
988}
989
5d0f6131
VV
990int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
991 dma_addr_t dma_addr, u32 *result)
df348139
MW
992{
993 struct nvme_command c;
994
995 memset(&c, 0, sizeof(c));
996 c.features.opcode = nvme_admin_set_features;
997 c.features.prp1 = cpu_to_le64(dma_addr);
998 c.features.fid = cpu_to_le32(fid);
999 c.features.dword11 = cpu_to_le32(dword11);
1000
bc5fc7e4
MW
1001 return nvme_submit_admin_cmd(dev, &c, result);
1002}
1003
a09115b2
MW
1004/**
1005 * nvme_cancel_ios - Cancel outstanding I/Os
1006 * @queue: The queue to cancel I/Os on
1007 * @timeout: True to only cancel I/Os which have timed out
1008 */
1009static void nvme_cancel_ios(struct nvme_queue *nvmeq, bool timeout)
1010{
1011 int depth = nvmeq->q_depth - 1;
1012 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
1013 unsigned long now = jiffies;
1014 int cmdid;
1015
1016 for_each_set_bit(cmdid, nvmeq->cmdid_data, depth) {
1017 void *ctx;
1018 nvme_completion_fn fn;
1019 static struct nvme_completion cqe = {
af2d9ca7 1020 .status = cpu_to_le16(NVME_SC_ABORT_REQ << 1),
a09115b2
MW
1021 };
1022
1023 if (timeout && !time_after(now, info[cmdid].timeout))
1024 continue;
053ab702
KB
1025 if (info[cmdid].ctx == CMD_CTX_CANCELLED)
1026 continue;
a09115b2
MW
1027 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d\n", cmdid);
1028 ctx = cancel_cmdid(nvmeq, cmdid, &fn);
1029 fn(nvmeq->dev, ctx, &cqe);
1030 }
1031}
1032
22404274 1033static void nvme_free_queue(struct nvme_queue *nvmeq)
9e866774 1034{
22404274
KB
1035 spin_lock_irq(&nvmeq->q_lock);
1036 while (bio_list_peek(&nvmeq->sq_cong)) {
1037 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1038 bio_endio(bio, -EIO);
1039 }
1040 spin_unlock_irq(&nvmeq->q_lock);
1041
9e866774
MW
1042 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1043 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1044 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1045 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1046 kfree(nvmeq);
1047}
1048
22404274
KB
1049static void nvme_free_queues(struct nvme_dev *dev)
1050{
1051 int i;
1052
1053 for (i = dev->queue_count - 1; i >= 0; i--) {
1054 nvme_free_queue(dev->queues[i]);
1055 dev->queue_count--;
1056 dev->queues[i] = NULL;
1057 }
1058}
1059
1060static void nvme_disable_queue(struct nvme_dev *dev, int qid)
b60503ba
MW
1061{
1062 struct nvme_queue *nvmeq = dev->queues[qid];
aba2080f 1063 int vector = dev->entry[nvmeq->cq_vector].vector;
b60503ba 1064
a09115b2 1065 spin_lock_irq(&nvmeq->q_lock);
22404274
KB
1066 if (nvmeq->q_suspended) {
1067 spin_unlock_irq(&nvmeq->q_lock);
1068 return;
3295874b 1069 }
22404274 1070 nvmeq->q_suspended = 1;
a09115b2
MW
1071 spin_unlock_irq(&nvmeq->q_lock);
1072
aba2080f
MW
1073 irq_set_affinity_hint(vector, NULL);
1074 free_irq(vector, nvmeq);
b60503ba
MW
1075
1076 /* Don't tell the adapter to delete the admin queue */
1077 if (qid) {
1078 adapter_delete_sq(dev, qid);
1079 adapter_delete_cq(dev, qid);
1080 }
1081
22404274
KB
1082 spin_lock_irq(&nvmeq->q_lock);
1083 nvme_process_cq(nvmeq);
1084 nvme_cancel_ios(nvmeq, false);
1085 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW
1086}
1087
1088static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1089 int depth, int vector)
1090{
1091 struct device *dmadev = &dev->pci_dev->dev;
22404274 1092 unsigned extra = nvme_queue_extra(depth);
b60503ba
MW
1093 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
1094 if (!nvmeq)
1095 return NULL;
1096
1097 nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
1098 &nvmeq->cq_dma_addr, GFP_KERNEL);
1099 if (!nvmeq->cqes)
1100 goto free_nvmeq;
1101 memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
1102
1103 nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
1104 &nvmeq->sq_dma_addr, GFP_KERNEL);
1105 if (!nvmeq->sq_cmds)
1106 goto free_cqdma;
1107
1108 nvmeq->q_dmadev = dmadev;
091b6092 1109 nvmeq->dev = dev;
b60503ba
MW
1110 spin_lock_init(&nvmeq->q_lock);
1111 nvmeq->cq_head = 0;
82123460 1112 nvmeq->cq_phase = 1;
b60503ba 1113 init_waitqueue_head(&nvmeq->sq_full);
1fa6aead 1114 init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread);
b60503ba 1115 bio_list_init(&nvmeq->sq_cong);
f1938f6e 1116 nvmeq->q_db = &dev->dbs[qid << (dev->db_stride + 1)];
b60503ba
MW
1117 nvmeq->q_depth = depth;
1118 nvmeq->cq_vector = vector;
22404274
KB
1119 nvmeq->q_suspended = 1;
1120 dev->queue_count++;
b60503ba
MW
1121
1122 return nvmeq;
1123
1124 free_cqdma:
68b8eca5 1125 dma_free_coherent(dmadev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW
1126 nvmeq->cq_dma_addr);
1127 free_nvmeq:
1128 kfree(nvmeq);
1129 return NULL;
1130}
1131
3001082c
MW
1132static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1133 const char *name)
1134{
58ffacb5
MW
1135 if (use_threaded_interrupts)
1136 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
ec6ce618 1137 nvme_irq_check, nvme_irq,
58ffacb5
MW
1138 IRQF_DISABLED | IRQF_SHARED,
1139 name, nvmeq);
3001082c
MW
1140 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
1141 IRQF_DISABLED | IRQF_SHARED, name, nvmeq);
1142}
1143
22404274 1144static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1145{
22404274
KB
1146 struct nvme_dev *dev = nvmeq->dev;
1147 unsigned extra = nvme_queue_extra(nvmeq->q_depth);
b60503ba 1148
22404274
KB
1149 nvmeq->sq_tail = 0;
1150 nvmeq->cq_head = 0;
1151 nvmeq->cq_phase = 1;
1152 nvmeq->q_db = &dev->dbs[qid << (dev->db_stride + 1)];
1153 memset(nvmeq->cmdid_data, 0, extra);
1154 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1155 nvme_cancel_ios(nvmeq, false);
1156 nvmeq->q_suspended = 0;
1157}
1158
1159static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1160{
1161 struct nvme_dev *dev = nvmeq->dev;
1162 int result;
3f85d50b 1163
b60503ba
MW
1164 result = adapter_alloc_cq(dev, qid, nvmeq);
1165 if (result < 0)
22404274 1166 return result;
b60503ba
MW
1167
1168 result = adapter_alloc_sq(dev, qid, nvmeq);
1169 if (result < 0)
1170 goto release_cq;
1171
3001082c 1172 result = queue_request_irq(dev, nvmeq, "nvme");
b60503ba
MW
1173 if (result < 0)
1174 goto release_sq;
1175
22404274
KB
1176 spin_lock(&nvmeq->q_lock);
1177 nvme_init_queue(nvmeq, qid);
1178 spin_unlock(&nvmeq->q_lock);
1179
1180 return result;
b60503ba
MW
1181
1182 release_sq:
1183 adapter_delete_sq(dev, qid);
1184 release_cq:
1185 adapter_delete_cq(dev, qid);
22404274 1186 return result;
b60503ba
MW
1187}
1188
ba47e386
MW
1189static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1190{
1191 unsigned long timeout;
1192 u32 bit = enabled ? NVME_CSTS_RDY : 0;
1193
1194 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1195
1196 while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1197 msleep(100);
1198 if (fatal_signal_pending(current))
1199 return -EINTR;
1200 if (time_after(jiffies, timeout)) {
1201 dev_err(&dev->pci_dev->dev,
1202 "Device not ready; aborting initialisation\n");
1203 return -ENODEV;
1204 }
1205 }
1206
1207 return 0;
1208}
1209
1210/*
1211 * If the device has been passed off to us in an enabled state, just clear
1212 * the enabled bit. The spec says we should set the 'shutdown notification
1213 * bits', but doing so may cause the device to complete commands to the
1214 * admin queue ... and we don't know what memory that might be pointing at!
1215 */
1216static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1217{
44af146a
MW
1218 u32 cc = readl(&dev->bar->cc);
1219
1220 if (cc & NVME_CC_ENABLE)
1221 writel(cc & ~NVME_CC_ENABLE, &dev->bar->cc);
ba47e386
MW
1222 return nvme_wait_ready(dev, cap, false);
1223}
1224
1225static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1226{
1227 return nvme_wait_ready(dev, cap, true);
1228}
1229
1894d8f1
KB
1230static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1231{
1232 unsigned long timeout;
1233 u32 cc;
1234
1235 cc = (readl(&dev->bar->cc) & ~NVME_CC_SHN_MASK) | NVME_CC_SHN_NORMAL;
1236 writel(cc, &dev->bar->cc);
1237
1238 timeout = 2 * HZ + jiffies;
1239 while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
1240 NVME_CSTS_SHST_CMPLT) {
1241 msleep(100);
1242 if (fatal_signal_pending(current))
1243 return -EINTR;
1244 if (time_after(jiffies, timeout)) {
1245 dev_err(&dev->pci_dev->dev,
1246 "Device shutdown incomplete; abort shutdown\n");
1247 return -ENODEV;
1248 }
1249 }
1250
1251 return 0;
1252}
1253
8d85fce7 1254static int nvme_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1255{
ba47e386 1256 int result;
b60503ba 1257 u32 aqa;
ba47e386 1258 u64 cap = readq(&dev->bar->cap);
b60503ba
MW
1259 struct nvme_queue *nvmeq;
1260
ba47e386
MW
1261 result = nvme_disable_ctrl(dev, cap);
1262 if (result < 0)
1263 return result;
b60503ba 1264
cd638946
KB
1265 nvmeq = dev->queues[0];
1266 if (!nvmeq) {
1267 nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
1268 if (!nvmeq)
1269 return -ENOMEM;
1270 dev->queues[0] = nvmeq;
1271 }
b60503ba
MW
1272
1273 aqa = nvmeq->q_depth - 1;
1274 aqa |= aqa << 16;
1275
1276 dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
1277 dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
1278 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
7f53f9d2 1279 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
b60503ba
MW
1280
1281 writel(aqa, &dev->bar->aqa);
1282 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1283 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
1284 writel(dev->ctrl_config, &dev->bar->cc);
1285
ba47e386 1286 result = nvme_enable_ctrl(dev, cap);
025c557a 1287 if (result)
cd638946 1288 return result;
9e866774 1289
3001082c 1290 result = queue_request_irq(dev, nvmeq, "nvme admin");
025c557a 1291 if (result)
cd638946 1292 return result;
025c557a 1293
22404274
KB
1294 spin_lock(&nvmeq->q_lock);
1295 nvme_init_queue(nvmeq, 0);
1296 spin_unlock(&nvmeq->q_lock);
b60503ba
MW
1297 return result;
1298}
1299
5d0f6131 1300struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
eca18b23 1301 unsigned long addr, unsigned length)
b60503ba 1302{
36c14ed9 1303 int i, err, count, nents, offset;
7fc3cdab
MW
1304 struct scatterlist *sg;
1305 struct page **pages;
eca18b23 1306 struct nvme_iod *iod;
36c14ed9
MW
1307
1308 if (addr & 3)
eca18b23 1309 return ERR_PTR(-EINVAL);
5460fc03 1310 if (!length || length > INT_MAX - PAGE_SIZE)
eca18b23 1311 return ERR_PTR(-EINVAL);
7fc3cdab 1312
36c14ed9 1313 offset = offset_in_page(addr);
7fc3cdab
MW
1314 count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
1315 pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
22fff826
DC
1316 if (!pages)
1317 return ERR_PTR(-ENOMEM);
36c14ed9
MW
1318
1319 err = get_user_pages_fast(addr, count, 1, pages);
1320 if (err < count) {
1321 count = err;
1322 err = -EFAULT;
1323 goto put_pages;
1324 }
7fc3cdab 1325
eca18b23
MW
1326 iod = nvme_alloc_iod(count, length, GFP_KERNEL);
1327 sg = iod->sg;
36c14ed9 1328 sg_init_table(sg, count);
d0ba1e49
MW
1329 for (i = 0; i < count; i++) {
1330 sg_set_page(&sg[i], pages[i],
5460fc03
DC
1331 min_t(unsigned, length, PAGE_SIZE - offset),
1332 offset);
d0ba1e49
MW
1333 length -= (PAGE_SIZE - offset);
1334 offset = 0;
7fc3cdab 1335 }
fe304c43 1336 sg_mark_end(&sg[i - 1]);
1c2ad9fa 1337 iod->nents = count;
7fc3cdab
MW
1338
1339 err = -ENOMEM;
1340 nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
1341 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
36c14ed9 1342 if (!nents)
eca18b23 1343 goto free_iod;
b60503ba 1344
7fc3cdab 1345 kfree(pages);
eca18b23 1346 return iod;
b60503ba 1347
eca18b23
MW
1348 free_iod:
1349 kfree(iod);
7fc3cdab
MW
1350 put_pages:
1351 for (i = 0; i < count; i++)
1352 put_page(pages[i]);
1353 kfree(pages);
eca18b23 1354 return ERR_PTR(err);
7fc3cdab 1355}
b60503ba 1356
5d0f6131 1357void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
1c2ad9fa 1358 struct nvme_iod *iod)
7fc3cdab 1359{
1c2ad9fa 1360 int i;
b60503ba 1361
1c2ad9fa
MW
1362 dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
1363 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
7fc3cdab 1364
1c2ad9fa
MW
1365 for (i = 0; i < iod->nents; i++)
1366 put_page(sg_page(&iod->sg[i]));
7fc3cdab 1367}
b60503ba 1368
a53295b6
MW
1369static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1370{
1371 struct nvme_dev *dev = ns->dev;
1372 struct nvme_queue *nvmeq;
1373 struct nvme_user_io io;
1374 struct nvme_command c;
f410c680
KB
1375 unsigned length, meta_len;
1376 int status, i;
1377 struct nvme_iod *iod, *meta_iod = NULL;
1378 dma_addr_t meta_dma_addr;
1379 void *meta, *uninitialized_var(meta_mem);
a53295b6
MW
1380
1381 if (copy_from_user(&io, uio, sizeof(io)))
1382 return -EFAULT;
6c7d4945 1383 length = (io.nblocks + 1) << ns->lba_shift;
f410c680
KB
1384 meta_len = (io.nblocks + 1) * ns->ms;
1385
1386 if (meta_len && ((io.metadata & 3) || !io.metadata))
1387 return -EINVAL;
6c7d4945
MW
1388
1389 switch (io.opcode) {
1390 case nvme_cmd_write:
1391 case nvme_cmd_read:
6bbf1acd 1392 case nvme_cmd_compare:
eca18b23 1393 iod = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length);
6413214c 1394 break;
6c7d4945 1395 default:
6bbf1acd 1396 return -EINVAL;
6c7d4945
MW
1397 }
1398
eca18b23
MW
1399 if (IS_ERR(iod))
1400 return PTR_ERR(iod);
a53295b6
MW
1401
1402 memset(&c, 0, sizeof(c));
1403 c.rw.opcode = io.opcode;
1404 c.rw.flags = io.flags;
6c7d4945 1405 c.rw.nsid = cpu_to_le32(ns->ns_id);
a53295b6 1406 c.rw.slba = cpu_to_le64(io.slba);
6c7d4945 1407 c.rw.length = cpu_to_le16(io.nblocks);
a53295b6 1408 c.rw.control = cpu_to_le16(io.control);
1c9b5265
MW
1409 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1410 c.rw.reftag = cpu_to_le32(io.reftag);
1411 c.rw.apptag = cpu_to_le16(io.apptag);
1412 c.rw.appmask = cpu_to_le16(io.appmask);
f410c680
KB
1413
1414 if (meta_len) {
1b56749e
KB
1415 meta_iod = nvme_map_user_pages(dev, io.opcode & 1, io.metadata,
1416 meta_len);
f410c680
KB
1417 if (IS_ERR(meta_iod)) {
1418 status = PTR_ERR(meta_iod);
1419 meta_iod = NULL;
1420 goto unmap;
1421 }
1422
1423 meta_mem = dma_alloc_coherent(&dev->pci_dev->dev, meta_len,
1424 &meta_dma_addr, GFP_KERNEL);
1425 if (!meta_mem) {
1426 status = -ENOMEM;
1427 goto unmap;
1428 }
1429
1430 if (io.opcode & 1) {
1431 int meta_offset = 0;
1432
1433 for (i = 0; i < meta_iod->nents; i++) {
1434 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1435 meta_iod->sg[i].offset;
1436 memcpy(meta_mem + meta_offset, meta,
1437 meta_iod->sg[i].length);
1438 kunmap_atomic(meta);
1439 meta_offset += meta_iod->sg[i].length;
1440 }
1441 }
1442
1443 c.rw.metadata = cpu_to_le64(meta_dma_addr);
1444 }
1445
eca18b23 1446 length = nvme_setup_prps(dev, &c.common, iod, length, GFP_KERNEL);
a53295b6 1447
040a93b5 1448 nvmeq = get_nvmeq(dev);
fa922821
MW
1449 /*
1450 * Since nvme_submit_sync_cmd sleeps, we can't keep preemption
b1ad37ef
MW
1451 * disabled. We may be preempted at any point, and be rescheduled
1452 * to a different CPU. That will cause cacheline bouncing, but no
1453 * additional races since q_lock already protects against other CPUs.
1454 */
a53295b6 1455 put_nvmeq(nvmeq);
b77954cb
MW
1456 if (length != (io.nblocks + 1) << ns->lba_shift)
1457 status = -ENOMEM;
22404274
KB
1458 else if (!nvmeq || nvmeq->q_suspended)
1459 status = -EBUSY;
b77954cb 1460 else
ff976d72 1461 status = nvme_submit_sync_cmd(nvmeq, &c, NULL, NVME_IO_TIMEOUT);
a53295b6 1462
f410c680
KB
1463 if (meta_len) {
1464 if (status == NVME_SC_SUCCESS && !(io.opcode & 1)) {
1465 int meta_offset = 0;
1466
1467 for (i = 0; i < meta_iod->nents; i++) {
1468 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1469 meta_iod->sg[i].offset;
1470 memcpy(meta, meta_mem + meta_offset,
1471 meta_iod->sg[i].length);
1472 kunmap_atomic(meta);
1473 meta_offset += meta_iod->sg[i].length;
1474 }
1475 }
1476
1477 dma_free_coherent(&dev->pci_dev->dev, meta_len, meta_mem,
1478 meta_dma_addr);
1479 }
1480
1481 unmap:
1c2ad9fa 1482 nvme_unmap_user_pages(dev, io.opcode & 1, iod);
eca18b23 1483 nvme_free_iod(dev, iod);
f410c680
KB
1484
1485 if (meta_iod) {
1486 nvme_unmap_user_pages(dev, io.opcode & 1, meta_iod);
1487 nvme_free_iod(dev, meta_iod);
1488 }
1489
a53295b6
MW
1490 return status;
1491}
1492
50af8bae 1493static int nvme_user_admin_cmd(struct nvme_dev *dev,
6bbf1acd 1494 struct nvme_admin_cmd __user *ucmd)
6ee44cdc 1495{
6bbf1acd 1496 struct nvme_admin_cmd cmd;
6ee44cdc 1497 struct nvme_command c;
eca18b23 1498 int status, length;
c7d36ab8 1499 struct nvme_iod *uninitialized_var(iod);
94f370ca 1500 unsigned timeout;
6ee44cdc 1501
6bbf1acd
MW
1502 if (!capable(CAP_SYS_ADMIN))
1503 return -EACCES;
1504 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
6ee44cdc 1505 return -EFAULT;
6ee44cdc
MW
1506
1507 memset(&c, 0, sizeof(c));
6bbf1acd
MW
1508 c.common.opcode = cmd.opcode;
1509 c.common.flags = cmd.flags;
1510 c.common.nsid = cpu_to_le32(cmd.nsid);
1511 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1512 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1513 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1514 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1515 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1516 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1517 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1518 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1519
1520 length = cmd.data_len;
1521 if (cmd.data_len) {
49742188
MW
1522 iod = nvme_map_user_pages(dev, cmd.opcode & 1, cmd.addr,
1523 length);
eca18b23
MW
1524 if (IS_ERR(iod))
1525 return PTR_ERR(iod);
1526 length = nvme_setup_prps(dev, &c.common, iod, length,
1527 GFP_KERNEL);
6bbf1acd
MW
1528 }
1529
94f370ca
KB
1530 timeout = cmd.timeout_ms ? msecs_to_jiffies(cmd.timeout_ms) :
1531 ADMIN_TIMEOUT;
6bbf1acd 1532 if (length != cmd.data_len)
b77954cb
MW
1533 status = -ENOMEM;
1534 else
94f370ca
KB
1535 status = nvme_submit_sync_cmd(dev->queues[0], &c, &cmd.result,
1536 timeout);
eca18b23 1537
6bbf1acd 1538 if (cmd.data_len) {
1c2ad9fa 1539 nvme_unmap_user_pages(dev, cmd.opcode & 1, iod);
eca18b23 1540 nvme_free_iod(dev, iod);
6bbf1acd 1541 }
f4f117f6 1542
cf90bc48 1543 if ((status >= 0) && copy_to_user(&ucmd->result, &cmd.result,
f4f117f6
KB
1544 sizeof(cmd.result)))
1545 status = -EFAULT;
1546
6ee44cdc
MW
1547 return status;
1548}
1549
b60503ba
MW
1550static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1551 unsigned long arg)
1552{
1553 struct nvme_ns *ns = bdev->bd_disk->private_data;
1554
1555 switch (cmd) {
6bbf1acd 1556 case NVME_IOCTL_ID:
c3bfe717 1557 force_successful_syscall_return();
6bbf1acd
MW
1558 return ns->ns_id;
1559 case NVME_IOCTL_ADMIN_CMD:
50af8bae 1560 return nvme_user_admin_cmd(ns->dev, (void __user *)arg);
a53295b6
MW
1561 case NVME_IOCTL_SUBMIT_IO:
1562 return nvme_submit_io(ns, (void __user *)arg);
5d0f6131
VV
1563 case SG_GET_VERSION_NUM:
1564 return nvme_sg_get_version_num((void __user *)arg);
1565 case SG_IO:
1566 return nvme_sg_io(ns, (void __user *)arg);
b60503ba
MW
1567 default:
1568 return -ENOTTY;
1569 }
1570}
1571
1572static const struct block_device_operations nvme_fops = {
1573 .owner = THIS_MODULE,
1574 .ioctl = nvme_ioctl,
49481682 1575 .compat_ioctl = nvme_ioctl,
b60503ba
MW
1576};
1577
1fa6aead
MW
1578static void nvme_resubmit_bios(struct nvme_queue *nvmeq)
1579{
1580 while (bio_list_peek(&nvmeq->sq_cong)) {
1581 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1582 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
427e9708
KB
1583
1584 if (bio_list_empty(&nvmeq->sq_cong))
1585 remove_wait_queue(&nvmeq->sq_full,
1586 &nvmeq->sq_cong_wait);
1fa6aead 1587 if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
427e9708
KB
1588 if (bio_list_empty(&nvmeq->sq_cong))
1589 add_wait_queue(&nvmeq->sq_full,
1590 &nvmeq->sq_cong_wait);
1fa6aead
MW
1591 bio_list_add_head(&nvmeq->sq_cong, bio);
1592 break;
1593 }
1594 }
1595}
1596
1597static int nvme_kthread(void *data)
1598{
1599 struct nvme_dev *dev;
1600
1601 while (!kthread_should_stop()) {
564a232c 1602 set_current_state(TASK_INTERRUPTIBLE);
1fa6aead
MW
1603 spin_lock(&dev_list_lock);
1604 list_for_each_entry(dev, &dev_list, node) {
1605 int i;
1606 for (i = 0; i < dev->queue_count; i++) {
1607 struct nvme_queue *nvmeq = dev->queues[i];
740216fc
MW
1608 if (!nvmeq)
1609 continue;
1fa6aead 1610 spin_lock_irq(&nvmeq->q_lock);
22404274
KB
1611 if (nvmeq->q_suspended)
1612 goto unlock;
bc57a0f7 1613 nvme_process_cq(nvmeq);
a09115b2 1614 nvme_cancel_ios(nvmeq, true);
1fa6aead 1615 nvme_resubmit_bios(nvmeq);
22404274 1616 unlock:
1fa6aead
MW
1617 spin_unlock_irq(&nvmeq->q_lock);
1618 }
1619 }
1620 spin_unlock(&dev_list_lock);
acb7aa0d 1621 schedule_timeout(round_jiffies_relative(HZ));
1fa6aead
MW
1622 }
1623 return 0;
1624}
1625
5aff9382
MW
1626static DEFINE_IDA(nvme_index_ida);
1627
1628static int nvme_get_ns_idx(void)
1629{
1630 int index, error;
1631
1632 do {
1633 if (!ida_pre_get(&nvme_index_ida, GFP_KERNEL))
1634 return -1;
1635
1636 spin_lock(&dev_list_lock);
1637 error = ida_get_new(&nvme_index_ida, &index);
1638 spin_unlock(&dev_list_lock);
1639 } while (error == -EAGAIN);
1640
1641 if (error)
1642 index = -1;
1643 return index;
1644}
1645
1646static void nvme_put_ns_idx(int index)
1647{
1648 spin_lock(&dev_list_lock);
1649 ida_remove(&nvme_index_ida, index);
1650 spin_unlock(&dev_list_lock);
1651}
1652
0e5e4f0e
KB
1653static void nvme_config_discard(struct nvme_ns *ns)
1654{
1655 u32 logical_block_size = queue_logical_block_size(ns->queue);
1656 ns->queue->limits.discard_zeroes_data = 0;
1657 ns->queue->limits.discard_alignment = logical_block_size;
1658 ns->queue->limits.discard_granularity = logical_block_size;
1659 ns->queue->limits.max_discard_sectors = 0xffffffff;
1660 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
1661}
1662
c3bfe717 1663static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid,
b60503ba
MW
1664 struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1665{
1666 struct nvme_ns *ns;
1667 struct gendisk *disk;
1668 int lbaf;
1669
1670 if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1671 return NULL;
1672
1673 ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1674 if (!ns)
1675 return NULL;
1676 ns->queue = blk_alloc_queue(GFP_KERNEL);
1677 if (!ns->queue)
1678 goto out_free_ns;
4eeb9215
MW
1679 ns->queue->queue_flags = QUEUE_FLAG_DEFAULT;
1680 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
1681 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
b60503ba
MW
1682 blk_queue_make_request(ns->queue, nvme_make_request);
1683 ns->dev = dev;
1684 ns->queue->queuedata = ns;
1685
1686 disk = alloc_disk(NVME_MINORS);
1687 if (!disk)
1688 goto out_free_queue;
5aff9382 1689 ns->ns_id = nsid;
b60503ba
MW
1690 ns->disk = disk;
1691 lbaf = id->flbas & 0xf;
1692 ns->lba_shift = id->lbaf[lbaf].ds;
f410c680 1693 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
e9ef4636 1694 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
8fc23e03
KB
1695 if (dev->max_hw_sectors)
1696 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
b60503ba
MW
1697
1698 disk->major = nvme_major;
1699 disk->minors = NVME_MINORS;
5aff9382 1700 disk->first_minor = NVME_MINORS * nvme_get_ns_idx();
b60503ba
MW
1701 disk->fops = &nvme_fops;
1702 disk->private_data = ns;
1703 disk->queue = ns->queue;
388f037f 1704 disk->driverfs_dev = &dev->pci_dev->dev;
5aff9382 1705 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
b60503ba
MW
1706 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1707
0e5e4f0e
KB
1708 if (dev->oncs & NVME_CTRL_ONCS_DSM)
1709 nvme_config_discard(ns);
1710
b60503ba
MW
1711 return ns;
1712
1713 out_free_queue:
1714 blk_cleanup_queue(ns->queue);
1715 out_free_ns:
1716 kfree(ns);
1717 return NULL;
1718}
1719
1720static void nvme_ns_free(struct nvme_ns *ns)
1721{
5aff9382 1722 int index = ns->disk->first_minor / NVME_MINORS;
b60503ba 1723 put_disk(ns->disk);
5aff9382 1724 nvme_put_ns_idx(index);
b60503ba
MW
1725 blk_cleanup_queue(ns->queue);
1726 kfree(ns);
1727}
1728
b3b06812 1729static int set_queue_count(struct nvme_dev *dev, int count)
b60503ba
MW
1730{
1731 int status;
1732 u32 result;
b3b06812 1733 u32 q_count = (count - 1) | ((count - 1) << 16);
b60503ba 1734
df348139 1735 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
bc5fc7e4 1736 &result);
b60503ba 1737 if (status)
7e03b124 1738 return status < 0 ? -EIO : -EBUSY;
b60503ba
MW
1739 return min(result & 0xffff, result >> 16) + 1;
1740}
1741
8d85fce7 1742static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 1743{
fa08a396 1744 struct pci_dev *pdev = dev->pci_dev;
063a8096 1745 int result, cpu, i, vecs, nr_io_queues, db_bar_size, q_depth;
b60503ba 1746
b348b7d5
MW
1747 nr_io_queues = num_online_cpus();
1748 result = set_queue_count(dev, nr_io_queues);
1b23484b
MW
1749 if (result < 0)
1750 return result;
b348b7d5
MW
1751 if (result < nr_io_queues)
1752 nr_io_queues = result;
b60503ba 1753
1b23484b
MW
1754 /* Deregister the admin queue's interrupt */
1755 free_irq(dev->entry[0].vector, dev->queues[0]);
1756
f1938f6e
MW
1757 db_bar_size = 4096 + ((nr_io_queues + 1) << (dev->db_stride + 3));
1758 if (db_bar_size > 8192) {
1759 iounmap(dev->bar);
fa08a396 1760 dev->bar = ioremap(pci_resource_start(pdev, 0), db_bar_size);
f1938f6e
MW
1761 dev->dbs = ((void __iomem *)dev->bar) + 4096;
1762 dev->queues[0]->q_db = dev->dbs;
1763 }
1764
063a8096
MW
1765 vecs = nr_io_queues;
1766 for (i = 0; i < vecs; i++)
1b23484b
MW
1767 dev->entry[i].entry = i;
1768 for (;;) {
063a8096
MW
1769 result = pci_enable_msix(pdev, dev->entry, vecs);
1770 if (result <= 0)
1b23484b 1771 break;
063a8096 1772 vecs = result;
1b23484b
MW
1773 }
1774
063a8096
MW
1775 if (result < 0) {
1776 vecs = nr_io_queues;
1777 if (vecs > 32)
1778 vecs = 32;
fa08a396 1779 for (;;) {
063a8096 1780 result = pci_enable_msi_block(pdev, vecs);
fa08a396 1781 if (result == 0) {
063a8096 1782 for (i = 0; i < vecs; i++)
fa08a396
RRG
1783 dev->entry[i].vector = i + pdev->irq;
1784 break;
063a8096
MW
1785 } else if (result < 0) {
1786 vecs = 1;
fa08a396
RRG
1787 break;
1788 }
063a8096 1789 vecs = result;
fa08a396
RRG
1790 }
1791 }
1792
063a8096
MW
1793 /*
1794 * Should investigate if there's a performance win from allocating
1795 * more queues than interrupt vectors; it might allow the submission
1796 * path to scale better, even if the receive path is limited by the
1797 * number of interrupts.
1798 */
1799 nr_io_queues = vecs;
1800
1b23484b 1801 result = queue_request_irq(dev, dev->queues[0], "nvme admin");
22404274
KB
1802 if (result)
1803 goto free_queues;
1b23484b 1804
cd638946
KB
1805 /* Free previously allocated queues that are no longer usable */
1806 spin_lock(&dev_list_lock);
1807 for (i = dev->queue_count - 1; i > nr_io_queues; i--) {
1808 struct nvme_queue *nvmeq = dev->queues[i];
1809
1810 spin_lock(&nvmeq->q_lock);
1811 nvme_cancel_ios(nvmeq, false);
1812 spin_unlock(&nvmeq->q_lock);
1813
1814 nvme_free_queue(nvmeq);
1815 dev->queue_count--;
1816 dev->queues[i] = NULL;
1817 }
1818 spin_unlock(&dev_list_lock);
1819
1b23484b 1820 cpu = cpumask_first(cpu_online_mask);
b348b7d5 1821 for (i = 0; i < nr_io_queues; i++) {
1b23484b
MW
1822 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
1823 cpu = cpumask_next(cpu, cpu_online_mask);
1824 }
1825
a0cadb85
KB
1826 q_depth = min_t(int, NVME_CAP_MQES(readq(&dev->bar->cap)) + 1,
1827 NVME_Q_DEPTH);
cd638946 1828 for (i = dev->queue_count - 1; i < nr_io_queues; i++) {
22404274
KB
1829 dev->queues[i + 1] = nvme_alloc_queue(dev, i + 1, q_depth, i);
1830 if (!dev->queues[i + 1]) {
1831 result = -ENOMEM;
1832 goto free_queues;
1833 }
1b23484b 1834 }
b60503ba 1835
9ecdc946
MW
1836 for (; i < num_possible_cpus(); i++) {
1837 int target = i % rounddown_pow_of_two(dev->queue_count - 1);
1838 dev->queues[i + 1] = dev->queues[target + 1];
1839 }
1840
22404274
KB
1841 for (i = 1; i < dev->queue_count; i++) {
1842 result = nvme_create_queue(dev->queues[i], i);
1843 if (result) {
1844 for (--i; i > 0; i--)
1845 nvme_disable_queue(dev, i);
1846 goto free_queues;
1847 }
1848 }
b60503ba 1849
22404274 1850 return 0;
b60503ba 1851
22404274
KB
1852 free_queues:
1853 nvme_free_queues(dev);
1854 return result;
b60503ba
MW
1855}
1856
422ef0c7
MW
1857/*
1858 * Return: error value if an error occurred setting up the queues or calling
1859 * Identify Device. 0 if these succeeded, even if adding some of the
1860 * namespaces failed. At the moment, these failures are silent. TBD which
1861 * failures should be reported.
1862 */
8d85fce7 1863static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 1864{
c3bfe717
MW
1865 int res;
1866 unsigned nn, i;
cbb6218f 1867 struct nvme_ns *ns;
51814232 1868 struct nvme_id_ctrl *ctrl;
bc5fc7e4
MW
1869 struct nvme_id_ns *id_ns;
1870 void *mem;
b60503ba 1871 dma_addr_t dma_addr;
159b67d7 1872 int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
b60503ba 1873
bc5fc7e4 1874 mem = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr,
b60503ba 1875 GFP_KERNEL);
a9ef4343
KB
1876 if (!mem)
1877 return -ENOMEM;
b60503ba 1878
bc5fc7e4 1879 res = nvme_identify(dev, 0, 1, dma_addr);
b60503ba
MW
1880 if (res) {
1881 res = -EIO;
cbb6218f 1882 goto out;
b60503ba
MW
1883 }
1884
bc5fc7e4 1885 ctrl = mem;
51814232 1886 nn = le32_to_cpup(&ctrl->nn);
0e5e4f0e 1887 dev->oncs = le16_to_cpup(&ctrl->oncs);
51814232
MW
1888 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
1889 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
1890 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
159b67d7 1891 if (ctrl->mdts)
8fc23e03 1892 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
159b67d7
KB
1893 if ((dev->pci_dev->vendor == PCI_VENDOR_ID_INTEL) &&
1894 (dev->pci_dev->device == 0x0953) && ctrl->vs[3])
1895 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
b60503ba 1896
bc5fc7e4 1897 id_ns = mem;
2b2c1896 1898 for (i = 1; i <= nn; i++) {
bc5fc7e4 1899 res = nvme_identify(dev, i, 0, dma_addr);
b60503ba
MW
1900 if (res)
1901 continue;
1902
bc5fc7e4 1903 if (id_ns->ncap == 0)
b60503ba
MW
1904 continue;
1905
bc5fc7e4 1906 res = nvme_get_features(dev, NVME_FEAT_LBA_RANGE, i,
08df1e05 1907 dma_addr + 4096, NULL);
b60503ba 1908 if (res)
12209036 1909 memset(mem + 4096, 0, 4096);
b60503ba 1910
bc5fc7e4 1911 ns = nvme_alloc_ns(dev, i, mem, mem + 4096);
b60503ba
MW
1912 if (ns)
1913 list_add_tail(&ns->list, &dev->namespaces);
1914 }
1915 list_for_each_entry(ns, &dev->namespaces, list)
1916 add_disk(ns->disk);
422ef0c7 1917 res = 0;
b60503ba 1918
bc5fc7e4 1919 out:
684f5c20 1920 dma_free_coherent(&dev->pci_dev->dev, 8192, mem, dma_addr);
b60503ba
MW
1921 return res;
1922}
1923
0877cb0d
KB
1924static int nvme_dev_map(struct nvme_dev *dev)
1925{
1926 int bars, result = -ENOMEM;
1927 struct pci_dev *pdev = dev->pci_dev;
1928
1929 if (pci_enable_device_mem(pdev))
1930 return result;
1931
1932 dev->entry[0].vector = pdev->irq;
1933 pci_set_master(pdev);
1934 bars = pci_select_bars(pdev, IORESOURCE_MEM);
1935 if (pci_request_selected_regions(pdev, bars, "nvme"))
1936 goto disable_pci;
1937
1938 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)))
1939 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1940 else if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)))
1941 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1942 else
1943 goto disable_pci;
1944
1945 pci_set_drvdata(pdev, dev);
1946 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1947 if (!dev->bar)
1948 goto disable;
1949
1950 dev->db_stride = NVME_CAP_STRIDE(readq(&dev->bar->cap));
1951 dev->dbs = ((void __iomem *)dev->bar) + 4096;
1952
1953 return 0;
1954
1955 disable:
1956 pci_release_regions(pdev);
1957 disable_pci:
1958 pci_disable_device(pdev);
1959 return result;
1960}
1961
1962static void nvme_dev_unmap(struct nvme_dev *dev)
1963{
1964 if (dev->pci_dev->msi_enabled)
1965 pci_disable_msi(dev->pci_dev);
1966 else if (dev->pci_dev->msix_enabled)
1967 pci_disable_msix(dev->pci_dev);
1968
1969 if (dev->bar) {
1970 iounmap(dev->bar);
1971 dev->bar = NULL;
1972 }
1973
1974 pci_release_regions(dev->pci_dev);
1975 if (pci_is_enabled(dev->pci_dev))
1976 pci_disable_device(dev->pci_dev);
1977}
1978
f0b50732 1979static void nvme_dev_shutdown(struct nvme_dev *dev)
b60503ba 1980{
22404274
KB
1981 int i;
1982
1983 for (i = dev->queue_count - 1; i >= 0; i--)
1984 nvme_disable_queue(dev, i);
b60503ba 1985
1fa6aead 1986 spin_lock(&dev_list_lock);
f0b50732 1987 list_del_init(&dev->node);
1fa6aead
MW
1988 spin_unlock(&dev_list_lock);
1989
1894d8f1
KB
1990 if (dev->bar)
1991 nvme_shutdown_ctrl(dev);
f0b50732
KB
1992 nvme_dev_unmap(dev);
1993}
1994
1995static void nvme_dev_remove(struct nvme_dev *dev)
1996{
1997 struct nvme_ns *ns, *next;
1998
b60503ba
MW
1999 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
2000 list_del(&ns->list);
2001 del_gendisk(ns->disk);
2002 nvme_ns_free(ns);
2003 }
b60503ba
MW
2004}
2005
091b6092
MW
2006static int nvme_setup_prp_pools(struct nvme_dev *dev)
2007{
2008 struct device *dmadev = &dev->pci_dev->dev;
2009 dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
2010 PAGE_SIZE, PAGE_SIZE, 0);
2011 if (!dev->prp_page_pool)
2012 return -ENOMEM;
2013
99802a7a
MW
2014 /* Optimisation for I/Os between 4k and 128k */
2015 dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
2016 256, 256, 0);
2017 if (!dev->prp_small_pool) {
2018 dma_pool_destroy(dev->prp_page_pool);
2019 return -ENOMEM;
2020 }
091b6092
MW
2021 return 0;
2022}
2023
2024static void nvme_release_prp_pools(struct nvme_dev *dev)
2025{
2026 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2027 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW
2028}
2029
cd58ad7d
QSA
2030static DEFINE_IDA(nvme_instance_ida);
2031
2032static int nvme_set_instance(struct nvme_dev *dev)
b60503ba 2033{
cd58ad7d
QSA
2034 int instance, error;
2035
2036 do {
2037 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2038 return -ENODEV;
2039
2040 spin_lock(&dev_list_lock);
2041 error = ida_get_new(&nvme_instance_ida, &instance);
2042 spin_unlock(&dev_list_lock);
2043 } while (error == -EAGAIN);
2044
2045 if (error)
2046 return -ENODEV;
2047
2048 dev->instance = instance;
2049 return 0;
b60503ba
MW
2050}
2051
2052static void nvme_release_instance(struct nvme_dev *dev)
2053{
cd58ad7d
QSA
2054 spin_lock(&dev_list_lock);
2055 ida_remove(&nvme_instance_ida, dev->instance);
2056 spin_unlock(&dev_list_lock);
b60503ba
MW
2057}
2058
5e82e952
KB
2059static void nvme_free_dev(struct kref *kref)
2060{
2061 struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
2062 nvme_dev_remove(dev);
f0b50732
KB
2063 nvme_dev_shutdown(dev);
2064 nvme_free_queues(dev);
5e82e952
KB
2065 nvme_release_instance(dev);
2066 nvme_release_prp_pools(dev);
5e82e952
KB
2067 kfree(dev->queues);
2068 kfree(dev->entry);
2069 kfree(dev);
2070}
2071
2072static int nvme_dev_open(struct inode *inode, struct file *f)
2073{
2074 struct nvme_dev *dev = container_of(f->private_data, struct nvme_dev,
2075 miscdev);
2076 kref_get(&dev->kref);
2077 f->private_data = dev;
2078 return 0;
2079}
2080
2081static int nvme_dev_release(struct inode *inode, struct file *f)
2082{
2083 struct nvme_dev *dev = f->private_data;
2084 kref_put(&dev->kref, nvme_free_dev);
2085 return 0;
2086}
2087
2088static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
2089{
2090 struct nvme_dev *dev = f->private_data;
2091 switch (cmd) {
2092 case NVME_IOCTL_ADMIN_CMD:
2093 return nvme_user_admin_cmd(dev, (void __user *)arg);
2094 default:
2095 return -ENOTTY;
2096 }
2097}
2098
2099static const struct file_operations nvme_dev_fops = {
2100 .owner = THIS_MODULE,
2101 .open = nvme_dev_open,
2102 .release = nvme_dev_release,
2103 .unlocked_ioctl = nvme_dev_ioctl,
2104 .compat_ioctl = nvme_dev_ioctl,
2105};
2106
f0b50732
KB
2107static int nvme_dev_start(struct nvme_dev *dev)
2108{
2109 int result;
2110
2111 result = nvme_dev_map(dev);
2112 if (result)
2113 return result;
2114
2115 result = nvme_configure_admin_queue(dev);
2116 if (result)
2117 goto unmap;
2118
2119 spin_lock(&dev_list_lock);
2120 list_add(&dev->node, &dev_list);
2121 spin_unlock(&dev_list_lock);
2122
2123 result = nvme_setup_io_queues(dev);
2124 if (result)
2125 goto disable;
2126
2127 return 0;
2128
2129 disable:
2130 spin_lock(&dev_list_lock);
2131 list_del_init(&dev->node);
2132 spin_unlock(&dev_list_lock);
2133 unmap:
2134 nvme_dev_unmap(dev);
2135 return result;
2136}
2137
8d85fce7 2138static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2139{
0877cb0d 2140 int result = -ENOMEM;
b60503ba
MW
2141 struct nvme_dev *dev;
2142
2143 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
2144 if (!dev)
2145 return -ENOMEM;
2146 dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
2147 GFP_KERNEL);
2148 if (!dev->entry)
2149 goto free;
1b23484b
MW
2150 dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
2151 GFP_KERNEL);
b60503ba
MW
2152 if (!dev->queues)
2153 goto free;
2154
2155 INIT_LIST_HEAD(&dev->namespaces);
2156 dev->pci_dev = pdev;
cd58ad7d
QSA
2157 result = nvme_set_instance(dev);
2158 if (result)
0877cb0d 2159 goto free;
b60503ba 2160
091b6092
MW
2161 result = nvme_setup_prp_pools(dev);
2162 if (result)
0877cb0d 2163 goto release;
091b6092 2164
f0b50732 2165 result = nvme_dev_start(dev);
0877cb0d
KB
2166 if (result)
2167 goto release_pools;
b60503ba 2168
740216fc 2169 result = nvme_dev_add(dev);
7e03b124 2170 if (result && result != -EBUSY)
f0b50732 2171 goto shutdown;
740216fc 2172
5e82e952
KB
2173 scnprintf(dev->name, sizeof(dev->name), "nvme%d", dev->instance);
2174 dev->miscdev.minor = MISC_DYNAMIC_MINOR;
2175 dev->miscdev.parent = &pdev->dev;
2176 dev->miscdev.name = dev->name;
2177 dev->miscdev.fops = &nvme_dev_fops;
2178 result = misc_register(&dev->miscdev);
2179 if (result)
2180 goto remove;
2181
2182 kref_init(&dev->kref);
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2183 return 0;
2184
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2185 remove:
2186 nvme_dev_remove(dev);
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2187 shutdown:
2188 nvme_dev_shutdown(dev);
0877cb0d 2189 release_pools:
f0b50732 2190 nvme_free_queues(dev);
091b6092 2191 nvme_release_prp_pools(dev);
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2192 release:
2193 nvme_release_instance(dev);
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2194 free:
2195 kfree(dev->queues);
2196 kfree(dev->entry);
2197 kfree(dev);
2198 return result;
2199}
2200
8d85fce7 2201static void nvme_remove(struct pci_dev *pdev)
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2202{
2203 struct nvme_dev *dev = pci_get_drvdata(pdev);
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2204 misc_deregister(&dev->miscdev);
2205 kref_put(&dev->kref, nvme_free_dev);
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2206}
2207
2208/* These functions are yet to be implemented */
2209#define nvme_error_detected NULL
2210#define nvme_dump_registers NULL
2211#define nvme_link_reset NULL
2212#define nvme_slot_reset NULL
2213#define nvme_error_resume NULL
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2214
2215static int nvme_suspend(struct device *dev)
2216{
2217 struct pci_dev *pdev = to_pci_dev(dev);
2218 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2219
2220 nvme_dev_shutdown(ndev);
2221 return 0;
2222}
2223
2224static int nvme_resume(struct device *dev)
2225{
2226 struct pci_dev *pdev = to_pci_dev(dev);
2227 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2228 int ret;
2229
2230 ret = nvme_dev_start(ndev);
2231 /* XXX: should remove gendisks if resume fails */
2232 if (ret)
2233 nvme_free_queues(ndev);
2234 return ret;
2235}
2236
2237static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 2238
1d352035 2239static const struct pci_error_handlers nvme_err_handler = {
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2240 .error_detected = nvme_error_detected,
2241 .mmio_enabled = nvme_dump_registers,
2242 .link_reset = nvme_link_reset,
2243 .slot_reset = nvme_slot_reset,
2244 .resume = nvme_error_resume,
2245};
2246
2247/* Move to pci_ids.h later */
2248#define PCI_CLASS_STORAGE_EXPRESS 0x010802
2249
2250static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
2251 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2252 { 0, }
2253};
2254MODULE_DEVICE_TABLE(pci, nvme_id_table);
2255
2256static struct pci_driver nvme_driver = {
2257 .name = "nvme",
2258 .id_table = nvme_id_table,
2259 .probe = nvme_probe,
8d85fce7 2260 .remove = nvme_remove,
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2261 .driver = {
2262 .pm = &nvme_dev_pm_ops,
2263 },
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2264 .err_handler = &nvme_err_handler,
2265};
2266
2267static int __init nvme_init(void)
2268{
0ac13140 2269 int result;
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2270
2271 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
2272 if (IS_ERR(nvme_thread))
2273 return PTR_ERR(nvme_thread);
b60503ba 2274
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2275 result = register_blkdev(nvme_major, "nvme");
2276 if (result < 0)
1fa6aead 2277 goto kill_kthread;
5c42ea16 2278 else if (result > 0)
0ac13140 2279 nvme_major = result;
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2280
2281 result = pci_register_driver(&nvme_driver);
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2282 if (result)
2283 goto unregister_blkdev;
2284 return 0;
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1fa6aead 2286 unregister_blkdev:
b60503ba 2287 unregister_blkdev(nvme_major, "nvme");
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2288 kill_kthread:
2289 kthread_stop(nvme_thread);
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2290 return result;
2291}
2292
2293static void __exit nvme_exit(void)
2294{
2295 pci_unregister_driver(&nvme_driver);
2296 unregister_blkdev(nvme_major, "nvme");
1fa6aead 2297 kthread_stop(nvme_thread);
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2298}
2299
2300MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2301MODULE_LICENSE("GPL");
366e8217 2302MODULE_VERSION("0.8");
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2303module_init(nvme_init);
2304module_exit(nvme_exit);