1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 1994 Linus Torvalds
5 * Cyrix stuff, June 1998 by:
6 * - Rafael R. Reilova (moved everything from head.S),
7 * <rreilova@ececs.uc.edu>
8 * - Channing Corn (tests & fixes),
9 * - Andrew D. Balsa (code cleanup).
11 #include <linux/init.h>
12 #include <linux/utsname.h>
13 #include <linux/cpu.h>
14 #include <linux/module.h>
15 #include <linux/nospec.h>
16 #include <linux/prctl.h>
17 #include <linux/sched/smt.h>
19 #include <asm/spec-ctrl.h>
20 #include <asm/cmdline.h>
22 #include <asm/processor.h>
23 #include <asm/processor-flags.h>
24 #include <asm/fpu/internal.h>
27 #include <asm/paravirt.h>
28 #include <asm/alternative.h>
29 #include <asm/pgtable.h>
30 #include <asm/set_memory.h>
31 #include <asm/intel-family.h>
32 #include <asm/e820/api.h>
33 #include <asm/hypervisor.h>
35 static void __init
spectre_v2_select_mitigation(void);
36 static void __init
ssb_select_mitigation(void);
37 static void __init
l1tf_select_mitigation(void);
38 static void __init
mds_select_mitigation(void);
40 /* The base value of the SPEC_CTRL MSR that always has to be preserved. */
41 u64 x86_spec_ctrl_base
;
42 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base
);
43 static DEFINE_MUTEX(spec_ctrl_mutex
);
46 * The vendor and possibly platform specific bits which can be modified in
49 static u64 __ro_after_init x86_spec_ctrl_mask
= SPEC_CTRL_IBRS
;
52 * AMD specific MSR info for Speculative Store Bypass control.
53 * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
55 u64 __ro_after_init x86_amd_ls_cfg_base
;
56 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask
;
58 /* Control conditional STIBP in switch_to() */
59 DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp
);
60 /* Control conditional IBPB in switch_mm() */
61 DEFINE_STATIC_KEY_FALSE(switch_mm_cond_ibpb
);
62 /* Control unconditional IBPB in switch_mm() */
63 DEFINE_STATIC_KEY_FALSE(switch_mm_always_ibpb
);
65 /* Control MDS CPU buffer clear before returning to user space */
66 DEFINE_STATIC_KEY_FALSE(mds_user_clear
);
67 EXPORT_SYMBOL_GPL(mds_user_clear
);
68 /* Control MDS CPU buffer clear before idling (halt, mwait) */
69 DEFINE_STATIC_KEY_FALSE(mds_idle_clear
);
70 EXPORT_SYMBOL_GPL(mds_idle_clear
);
72 void __init
check_bugs(void)
77 * identify_boot_cpu() initialized SMT support information, let the
80 cpu_smt_check_topology_early();
82 if (!IS_ENABLED(CONFIG_SMP
)) {
84 print_cpu_info(&boot_cpu_data
);
88 * Read the SPEC_CTRL MSR to account for reserved bits which may
89 * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
90 * init code as it is not enumerated and depends on the family.
92 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL
))
93 rdmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
95 /* Allow STIBP in MSR_SPEC_CTRL if supported */
96 if (boot_cpu_has(X86_FEATURE_STIBP
))
97 x86_spec_ctrl_mask
|= SPEC_CTRL_STIBP
;
99 /* Select the proper spectre mitigation before patching alternatives */
100 spectre_v2_select_mitigation();
103 * Select proper mitigation for any exposure to the Speculative Store
104 * Bypass vulnerability.
106 ssb_select_mitigation();
108 l1tf_select_mitigation();
110 mds_select_mitigation();
116 * Check whether we are able to run this kernel safely on SMP.
118 * - i386 is no longer supported.
119 * - In order to run on anything without a TSC, we need to be
120 * compiled for a i486.
122 if (boot_cpu_data
.x86
< 4)
123 panic("Kernel requires i486+ for 'invlpg' and other features");
125 init_utsname()->machine
[1] =
126 '0' + (boot_cpu_data
.x86
> 6 ? 6 : boot_cpu_data
.x86
);
127 alternative_instructions();
129 fpu__init_check_bugs();
130 #else /* CONFIG_X86_64 */
131 alternative_instructions();
134 * Make sure the first 2MB area is not mapped by huge pages
135 * There are typically fixed size MTRRs in there and overlapping
136 * MTRRs into large pages causes slow downs.
138 * Right now we don't do that with gbpages because there seems
139 * very little benefit for that case.
142 set_memory_4k((unsigned long)__va(0), 1);
147 x86_virt_spec_ctrl(u64 guest_spec_ctrl
, u64 guest_virt_spec_ctrl
, bool setguest
)
149 u64 msrval
, guestval
, hostval
= x86_spec_ctrl_base
;
150 struct thread_info
*ti
= current_thread_info();
152 /* Is MSR_SPEC_CTRL implemented ? */
153 if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL
)) {
155 * Restrict guest_spec_ctrl to supported values. Clear the
156 * modifiable bits in the host base value and or the
157 * modifiable bits from the guest value.
159 guestval
= hostval
& ~x86_spec_ctrl_mask
;
160 guestval
|= guest_spec_ctrl
& x86_spec_ctrl_mask
;
162 /* SSBD controlled in MSR_SPEC_CTRL */
163 if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD
) ||
164 static_cpu_has(X86_FEATURE_AMD_SSBD
))
165 hostval
|= ssbd_tif_to_spec_ctrl(ti
->flags
);
167 /* Conditional STIBP enabled? */
168 if (static_branch_unlikely(&switch_to_cond_stibp
))
169 hostval
|= stibp_tif_to_spec_ctrl(ti
->flags
);
171 if (hostval
!= guestval
) {
172 msrval
= setguest
? guestval
: hostval
;
173 wrmsrl(MSR_IA32_SPEC_CTRL
, msrval
);
178 * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
179 * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
181 if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD
) &&
182 !static_cpu_has(X86_FEATURE_VIRT_SSBD
))
186 * If the host has SSBD mitigation enabled, force it in the host's
187 * virtual MSR value. If its not permanently enabled, evaluate
188 * current's TIF_SSBD thread flag.
190 if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE
))
191 hostval
= SPEC_CTRL_SSBD
;
193 hostval
= ssbd_tif_to_spec_ctrl(ti
->flags
);
195 /* Sanitize the guest value */
196 guestval
= guest_virt_spec_ctrl
& SPEC_CTRL_SSBD
;
198 if (hostval
!= guestval
) {
201 tif
= setguest
? ssbd_spec_ctrl_to_tif(guestval
) :
202 ssbd_spec_ctrl_to_tif(hostval
);
204 speculation_ctrl_update(tif
);
207 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl
);
209 static void x86_amd_ssb_disable(void)
211 u64 msrval
= x86_amd_ls_cfg_base
| x86_amd_ls_cfg_ssbd_mask
;
213 if (boot_cpu_has(X86_FEATURE_VIRT_SSBD
))
214 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL
, SPEC_CTRL_SSBD
);
215 else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD
))
216 wrmsrl(MSR_AMD64_LS_CFG
, msrval
);
220 #define pr_fmt(fmt) "MDS: " fmt
222 /* Default mitigation for MDS-affected CPUs */
223 static enum mds_mitigations mds_mitigation __ro_after_init
= MDS_MITIGATION_FULL
;
224 static bool mds_nosmt __ro_after_init
= false;
226 static const char * const mds_strings
[] = {
227 [MDS_MITIGATION_OFF
] = "Vulnerable",
228 [MDS_MITIGATION_FULL
] = "Mitigation: Clear CPU buffers",
229 [MDS_MITIGATION_VMWERV
] = "Vulnerable: Clear CPU buffers attempted, no microcode",
232 static void __init
mds_select_mitigation(void)
234 if (!boot_cpu_has_bug(X86_BUG_MDS
) || cpu_mitigations_off()) {
235 mds_mitigation
= MDS_MITIGATION_OFF
;
239 if (mds_mitigation
== MDS_MITIGATION_FULL
) {
240 if (!boot_cpu_has(X86_FEATURE_MD_CLEAR
))
241 mds_mitigation
= MDS_MITIGATION_VMWERV
;
243 static_branch_enable(&mds_user_clear
);
245 if (!boot_cpu_has(X86_BUG_MSBDS_ONLY
) &&
246 (mds_nosmt
|| cpu_mitigations_auto_nosmt()))
247 cpu_smt_disable(false);
250 pr_info("%s\n", mds_strings
[mds_mitigation
]);
253 static int __init
mds_cmdline(char *str
)
255 if (!boot_cpu_has_bug(X86_BUG_MDS
))
261 if (!strcmp(str
, "off"))
262 mds_mitigation
= MDS_MITIGATION_OFF
;
263 else if (!strcmp(str
, "full"))
264 mds_mitigation
= MDS_MITIGATION_FULL
;
265 else if (!strcmp(str
, "full,nosmt")) {
266 mds_mitigation
= MDS_MITIGATION_FULL
;
272 early_param("mds", mds_cmdline
);
275 #define pr_fmt(fmt) "Spectre V2 : " fmt
277 static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init
=
280 static enum spectre_v2_user_mitigation spectre_v2_user __ro_after_init
=
281 SPECTRE_V2_USER_NONE
;
283 #ifdef CONFIG_RETPOLINE
284 static bool spectre_v2_bad_module
;
286 bool retpoline_module_ok(bool has_retpoline
)
288 if (spectre_v2_enabled
== SPECTRE_V2_NONE
|| has_retpoline
)
291 pr_err("System may be vulnerable to spectre v2\n");
292 spectre_v2_bad_module
= true;
296 static inline const char *spectre_v2_module_string(void)
298 return spectre_v2_bad_module
? " - vulnerable module loaded" : "";
301 static inline const char *spectre_v2_module_string(void) { return ""; }
304 static inline bool match_option(const char *arg
, int arglen
, const char *opt
)
306 int len
= strlen(opt
);
308 return len
== arglen
&& !strncmp(arg
, opt
, len
);
311 /* The kernel command line selection for spectre v2 */
312 enum spectre_v2_mitigation_cmd
{
315 SPECTRE_V2_CMD_FORCE
,
316 SPECTRE_V2_CMD_RETPOLINE
,
317 SPECTRE_V2_CMD_RETPOLINE_GENERIC
,
318 SPECTRE_V2_CMD_RETPOLINE_AMD
,
321 enum spectre_v2_user_cmd
{
322 SPECTRE_V2_USER_CMD_NONE
,
323 SPECTRE_V2_USER_CMD_AUTO
,
324 SPECTRE_V2_USER_CMD_FORCE
,
325 SPECTRE_V2_USER_CMD_PRCTL
,
326 SPECTRE_V2_USER_CMD_PRCTL_IBPB
,
327 SPECTRE_V2_USER_CMD_SECCOMP
,
328 SPECTRE_V2_USER_CMD_SECCOMP_IBPB
,
331 static const char * const spectre_v2_user_strings
[] = {
332 [SPECTRE_V2_USER_NONE
] = "User space: Vulnerable",
333 [SPECTRE_V2_USER_STRICT
] = "User space: Mitigation: STIBP protection",
334 [SPECTRE_V2_USER_STRICT_PREFERRED
] = "User space: Mitigation: STIBP always-on protection",
335 [SPECTRE_V2_USER_PRCTL
] = "User space: Mitigation: STIBP via prctl",
336 [SPECTRE_V2_USER_SECCOMP
] = "User space: Mitigation: STIBP via seccomp and prctl",
339 static const struct {
341 enum spectre_v2_user_cmd cmd
;
343 } v2_user_options
[] __initdata
= {
344 { "auto", SPECTRE_V2_USER_CMD_AUTO
, false },
345 { "off", SPECTRE_V2_USER_CMD_NONE
, false },
346 { "on", SPECTRE_V2_USER_CMD_FORCE
, true },
347 { "prctl", SPECTRE_V2_USER_CMD_PRCTL
, false },
348 { "prctl,ibpb", SPECTRE_V2_USER_CMD_PRCTL_IBPB
, false },
349 { "seccomp", SPECTRE_V2_USER_CMD_SECCOMP
, false },
350 { "seccomp,ibpb", SPECTRE_V2_USER_CMD_SECCOMP_IBPB
, false },
353 static void __init
spec_v2_user_print_cond(const char *reason
, bool secure
)
355 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2
) != secure
)
356 pr_info("spectre_v2_user=%s forced on command line.\n", reason
);
359 static enum spectre_v2_user_cmd __init
360 spectre_v2_parse_user_cmdline(enum spectre_v2_mitigation_cmd v2_cmd
)
366 case SPECTRE_V2_CMD_NONE
:
367 return SPECTRE_V2_USER_CMD_NONE
;
368 case SPECTRE_V2_CMD_FORCE
:
369 return SPECTRE_V2_USER_CMD_FORCE
;
374 ret
= cmdline_find_option(boot_command_line
, "spectre_v2_user",
377 return SPECTRE_V2_USER_CMD_AUTO
;
379 for (i
= 0; i
< ARRAY_SIZE(v2_user_options
); i
++) {
380 if (match_option(arg
, ret
, v2_user_options
[i
].option
)) {
381 spec_v2_user_print_cond(v2_user_options
[i
].option
,
382 v2_user_options
[i
].secure
);
383 return v2_user_options
[i
].cmd
;
387 pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg
);
388 return SPECTRE_V2_USER_CMD_AUTO
;
392 spectre_v2_user_select_mitigation(enum spectre_v2_mitigation_cmd v2_cmd
)
394 enum spectre_v2_user_mitigation mode
= SPECTRE_V2_USER_NONE
;
395 bool smt_possible
= IS_ENABLED(CONFIG_SMP
);
396 enum spectre_v2_user_cmd cmd
;
398 if (!boot_cpu_has(X86_FEATURE_IBPB
) && !boot_cpu_has(X86_FEATURE_STIBP
))
401 if (cpu_smt_control
== CPU_SMT_FORCE_DISABLED
||
402 cpu_smt_control
== CPU_SMT_NOT_SUPPORTED
)
403 smt_possible
= false;
405 cmd
= spectre_v2_parse_user_cmdline(v2_cmd
);
407 case SPECTRE_V2_USER_CMD_NONE
:
409 case SPECTRE_V2_USER_CMD_FORCE
:
410 mode
= SPECTRE_V2_USER_STRICT
;
412 case SPECTRE_V2_USER_CMD_PRCTL
:
413 case SPECTRE_V2_USER_CMD_PRCTL_IBPB
:
414 mode
= SPECTRE_V2_USER_PRCTL
;
416 case SPECTRE_V2_USER_CMD_AUTO
:
417 case SPECTRE_V2_USER_CMD_SECCOMP
:
418 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB
:
419 if (IS_ENABLED(CONFIG_SECCOMP
))
420 mode
= SPECTRE_V2_USER_SECCOMP
;
422 mode
= SPECTRE_V2_USER_PRCTL
;
427 * At this point, an STIBP mode other than "off" has been set.
428 * If STIBP support is not being forced, check if STIBP always-on
431 if (mode
!= SPECTRE_V2_USER_STRICT
&&
432 boot_cpu_has(X86_FEATURE_AMD_STIBP_ALWAYS_ON
))
433 mode
= SPECTRE_V2_USER_STRICT_PREFERRED
;
435 /* Initialize Indirect Branch Prediction Barrier */
436 if (boot_cpu_has(X86_FEATURE_IBPB
)) {
437 setup_force_cpu_cap(X86_FEATURE_USE_IBPB
);
440 case SPECTRE_V2_USER_CMD_FORCE
:
441 case SPECTRE_V2_USER_CMD_PRCTL_IBPB
:
442 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB
:
443 static_branch_enable(&switch_mm_always_ibpb
);
445 case SPECTRE_V2_USER_CMD_PRCTL
:
446 case SPECTRE_V2_USER_CMD_AUTO
:
447 case SPECTRE_V2_USER_CMD_SECCOMP
:
448 static_branch_enable(&switch_mm_cond_ibpb
);
454 pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n",
455 static_key_enabled(&switch_mm_always_ibpb
) ?
456 "always-on" : "conditional");
459 /* If enhanced IBRS is enabled no STIBP required */
460 if (spectre_v2_enabled
== SPECTRE_V2_IBRS_ENHANCED
)
464 * If SMT is not possible or STIBP is not available clear the STIBP
467 if (!smt_possible
|| !boot_cpu_has(X86_FEATURE_STIBP
))
468 mode
= SPECTRE_V2_USER_NONE
;
470 spectre_v2_user
= mode
;
471 /* Only print the STIBP mode when SMT possible */
473 pr_info("%s\n", spectre_v2_user_strings
[mode
]);
476 static const char * const spectre_v2_strings
[] = {
477 [SPECTRE_V2_NONE
] = "Vulnerable",
478 [SPECTRE_V2_RETPOLINE_GENERIC
] = "Mitigation: Full generic retpoline",
479 [SPECTRE_V2_RETPOLINE_AMD
] = "Mitigation: Full AMD retpoline",
480 [SPECTRE_V2_IBRS_ENHANCED
] = "Mitigation: Enhanced IBRS",
483 static const struct {
485 enum spectre_v2_mitigation_cmd cmd
;
487 } mitigation_options
[] __initdata
= {
488 { "off", SPECTRE_V2_CMD_NONE
, false },
489 { "on", SPECTRE_V2_CMD_FORCE
, true },
490 { "retpoline", SPECTRE_V2_CMD_RETPOLINE
, false },
491 { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD
, false },
492 { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC
, false },
493 { "auto", SPECTRE_V2_CMD_AUTO
, false },
496 static void __init
spec_v2_print_cond(const char *reason
, bool secure
)
498 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2
) != secure
)
499 pr_info("%s selected on command line.\n", reason
);
502 static enum spectre_v2_mitigation_cmd __init
spectre_v2_parse_cmdline(void)
504 enum spectre_v2_mitigation_cmd cmd
= SPECTRE_V2_CMD_AUTO
;
508 if (cmdline_find_option_bool(boot_command_line
, "nospectre_v2") ||
509 cpu_mitigations_off())
510 return SPECTRE_V2_CMD_NONE
;
512 ret
= cmdline_find_option(boot_command_line
, "spectre_v2", arg
, sizeof(arg
));
514 return SPECTRE_V2_CMD_AUTO
;
516 for (i
= 0; i
< ARRAY_SIZE(mitigation_options
); i
++) {
517 if (!match_option(arg
, ret
, mitigation_options
[i
].option
))
519 cmd
= mitigation_options
[i
].cmd
;
523 if (i
>= ARRAY_SIZE(mitigation_options
)) {
524 pr_err("unknown option (%s). Switching to AUTO select\n", arg
);
525 return SPECTRE_V2_CMD_AUTO
;
528 if ((cmd
== SPECTRE_V2_CMD_RETPOLINE
||
529 cmd
== SPECTRE_V2_CMD_RETPOLINE_AMD
||
530 cmd
== SPECTRE_V2_CMD_RETPOLINE_GENERIC
) &&
531 !IS_ENABLED(CONFIG_RETPOLINE
)) {
532 pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options
[i
].option
);
533 return SPECTRE_V2_CMD_AUTO
;
536 if (cmd
== SPECTRE_V2_CMD_RETPOLINE_AMD
&&
537 boot_cpu_data
.x86_vendor
!= X86_VENDOR_AMD
) {
538 pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n");
539 return SPECTRE_V2_CMD_AUTO
;
542 spec_v2_print_cond(mitigation_options
[i
].option
,
543 mitigation_options
[i
].secure
);
547 static void __init
spectre_v2_select_mitigation(void)
549 enum spectre_v2_mitigation_cmd cmd
= spectre_v2_parse_cmdline();
550 enum spectre_v2_mitigation mode
= SPECTRE_V2_NONE
;
553 * If the CPU is not affected and the command line mode is NONE or AUTO
554 * then nothing to do.
556 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2
) &&
557 (cmd
== SPECTRE_V2_CMD_NONE
|| cmd
== SPECTRE_V2_CMD_AUTO
))
561 case SPECTRE_V2_CMD_NONE
:
564 case SPECTRE_V2_CMD_FORCE
:
565 case SPECTRE_V2_CMD_AUTO
:
566 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED
)) {
567 mode
= SPECTRE_V2_IBRS_ENHANCED
;
568 /* Force it so VMEXIT will restore correctly */
569 x86_spec_ctrl_base
|= SPEC_CTRL_IBRS
;
570 wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
571 goto specv2_set_mode
;
573 if (IS_ENABLED(CONFIG_RETPOLINE
))
576 case SPECTRE_V2_CMD_RETPOLINE_AMD
:
577 if (IS_ENABLED(CONFIG_RETPOLINE
))
580 case SPECTRE_V2_CMD_RETPOLINE_GENERIC
:
581 if (IS_ENABLED(CONFIG_RETPOLINE
))
582 goto retpoline_generic
;
584 case SPECTRE_V2_CMD_RETPOLINE
:
585 if (IS_ENABLED(CONFIG_RETPOLINE
))
589 pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!");
593 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) {
595 if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC
)) {
596 pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n");
597 goto retpoline_generic
;
599 mode
= SPECTRE_V2_RETPOLINE_AMD
;
600 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD
);
601 setup_force_cpu_cap(X86_FEATURE_RETPOLINE
);
604 mode
= SPECTRE_V2_RETPOLINE_GENERIC
;
605 setup_force_cpu_cap(X86_FEATURE_RETPOLINE
);
609 spectre_v2_enabled
= mode
;
610 pr_info("%s\n", spectre_v2_strings
[mode
]);
613 * If spectre v2 protection has been enabled, unconditionally fill
614 * RSB during a context switch; this protects against two independent
617 * - RSB underflow (and switch to BTB) on Skylake+
618 * - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs
620 setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW
);
621 pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n");
624 * Retpoline means the kernel is safe because it has no indirect
625 * branches. Enhanced IBRS protects firmware too, so, enable restricted
626 * speculation around firmware calls only when Enhanced IBRS isn't
629 * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because
630 * the user might select retpoline on the kernel command line and if
631 * the CPU supports Enhanced IBRS, kernel might un-intentionally not
632 * enable IBRS around firmware calls.
634 if (boot_cpu_has(X86_FEATURE_IBRS
) && mode
!= SPECTRE_V2_IBRS_ENHANCED
) {
635 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW
);
636 pr_info("Enabling Restricted Speculation for firmware calls\n");
639 /* Set up IBPB and STIBP depending on the general spectre V2 command */
640 spectre_v2_user_select_mitigation(cmd
);
643 static void update_stibp_msr(void * __unused
)
645 wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
648 /* Update x86_spec_ctrl_base in case SMT state changed. */
649 static void update_stibp_strict(void)
651 u64 mask
= x86_spec_ctrl_base
& ~SPEC_CTRL_STIBP
;
653 if (sched_smt_active())
654 mask
|= SPEC_CTRL_STIBP
;
656 if (mask
== x86_spec_ctrl_base
)
659 pr_info("Update user space SMT mitigation: STIBP %s\n",
660 mask
& SPEC_CTRL_STIBP
? "always-on" : "off");
661 x86_spec_ctrl_base
= mask
;
662 on_each_cpu(update_stibp_msr
, NULL
, 1);
665 /* Update the static key controlling the evaluation of TIF_SPEC_IB */
666 static void update_indir_branch_cond(void)
668 if (sched_smt_active())
669 static_branch_enable(&switch_to_cond_stibp
);
671 static_branch_disable(&switch_to_cond_stibp
);
675 #define pr_fmt(fmt) fmt
677 /* Update the static key controlling the MDS CPU buffer clear in idle */
678 static void update_mds_branch_idle(void)
681 * Enable the idle clearing if SMT is active on CPUs which are
682 * affected only by MSBDS and not any other MDS variant.
684 * The other variants cannot be mitigated when SMT is enabled, so
685 * clearing the buffers on idle just to prevent the Store Buffer
686 * repartitioning leak would be a window dressing exercise.
688 if (!boot_cpu_has_bug(X86_BUG_MSBDS_ONLY
))
691 if (sched_smt_active())
692 static_branch_enable(&mds_idle_clear
);
694 static_branch_disable(&mds_idle_clear
);
697 #define MDS_MSG_SMT "MDS CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for more details.\n"
699 void arch_smt_update(void)
701 /* Enhanced IBRS implies STIBP. No update required. */
702 if (spectre_v2_enabled
== SPECTRE_V2_IBRS_ENHANCED
)
705 mutex_lock(&spec_ctrl_mutex
);
707 switch (spectre_v2_user
) {
708 case SPECTRE_V2_USER_NONE
:
710 case SPECTRE_V2_USER_STRICT
:
711 case SPECTRE_V2_USER_STRICT_PREFERRED
:
712 update_stibp_strict();
714 case SPECTRE_V2_USER_PRCTL
:
715 case SPECTRE_V2_USER_SECCOMP
:
716 update_indir_branch_cond();
720 switch (mds_mitigation
) {
721 case MDS_MITIGATION_FULL
:
722 case MDS_MITIGATION_VMWERV
:
723 if (sched_smt_active() && !boot_cpu_has(X86_BUG_MSBDS_ONLY
))
724 pr_warn_once(MDS_MSG_SMT
);
725 update_mds_branch_idle();
727 case MDS_MITIGATION_OFF
:
731 mutex_unlock(&spec_ctrl_mutex
);
735 #define pr_fmt(fmt) "Speculative Store Bypass: " fmt
737 static enum ssb_mitigation ssb_mode __ro_after_init
= SPEC_STORE_BYPASS_NONE
;
739 /* The kernel command line selection */
740 enum ssb_mitigation_cmd
{
741 SPEC_STORE_BYPASS_CMD_NONE
,
742 SPEC_STORE_BYPASS_CMD_AUTO
,
743 SPEC_STORE_BYPASS_CMD_ON
,
744 SPEC_STORE_BYPASS_CMD_PRCTL
,
745 SPEC_STORE_BYPASS_CMD_SECCOMP
,
748 static const char * const ssb_strings
[] = {
749 [SPEC_STORE_BYPASS_NONE
] = "Vulnerable",
750 [SPEC_STORE_BYPASS_DISABLE
] = "Mitigation: Speculative Store Bypass disabled",
751 [SPEC_STORE_BYPASS_PRCTL
] = "Mitigation: Speculative Store Bypass disabled via prctl",
752 [SPEC_STORE_BYPASS_SECCOMP
] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
755 static const struct {
757 enum ssb_mitigation_cmd cmd
;
758 } ssb_mitigation_options
[] __initdata
= {
759 { "auto", SPEC_STORE_BYPASS_CMD_AUTO
}, /* Platform decides */
760 { "on", SPEC_STORE_BYPASS_CMD_ON
}, /* Disable Speculative Store Bypass */
761 { "off", SPEC_STORE_BYPASS_CMD_NONE
}, /* Don't touch Speculative Store Bypass */
762 { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL
}, /* Disable Speculative Store Bypass via prctl */
763 { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP
}, /* Disable Speculative Store Bypass via prctl and seccomp */
766 static enum ssb_mitigation_cmd __init
ssb_parse_cmdline(void)
768 enum ssb_mitigation_cmd cmd
= SPEC_STORE_BYPASS_CMD_AUTO
;
772 if (cmdline_find_option_bool(boot_command_line
, "nospec_store_bypass_disable") ||
773 cpu_mitigations_off()) {
774 return SPEC_STORE_BYPASS_CMD_NONE
;
776 ret
= cmdline_find_option(boot_command_line
, "spec_store_bypass_disable",
779 return SPEC_STORE_BYPASS_CMD_AUTO
;
781 for (i
= 0; i
< ARRAY_SIZE(ssb_mitigation_options
); i
++) {
782 if (!match_option(arg
, ret
, ssb_mitigation_options
[i
].option
))
785 cmd
= ssb_mitigation_options
[i
].cmd
;
789 if (i
>= ARRAY_SIZE(ssb_mitigation_options
)) {
790 pr_err("unknown option (%s). Switching to AUTO select\n", arg
);
791 return SPEC_STORE_BYPASS_CMD_AUTO
;
798 static enum ssb_mitigation __init
__ssb_select_mitigation(void)
800 enum ssb_mitigation mode
= SPEC_STORE_BYPASS_NONE
;
801 enum ssb_mitigation_cmd cmd
;
803 if (!boot_cpu_has(X86_FEATURE_SSBD
))
806 cmd
= ssb_parse_cmdline();
807 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS
) &&
808 (cmd
== SPEC_STORE_BYPASS_CMD_NONE
||
809 cmd
== SPEC_STORE_BYPASS_CMD_AUTO
))
813 case SPEC_STORE_BYPASS_CMD_AUTO
:
814 case SPEC_STORE_BYPASS_CMD_SECCOMP
:
816 * Choose prctl+seccomp as the default mode if seccomp is
819 if (IS_ENABLED(CONFIG_SECCOMP
))
820 mode
= SPEC_STORE_BYPASS_SECCOMP
;
822 mode
= SPEC_STORE_BYPASS_PRCTL
;
824 case SPEC_STORE_BYPASS_CMD_ON
:
825 mode
= SPEC_STORE_BYPASS_DISABLE
;
827 case SPEC_STORE_BYPASS_CMD_PRCTL
:
828 mode
= SPEC_STORE_BYPASS_PRCTL
;
830 case SPEC_STORE_BYPASS_CMD_NONE
:
835 * We have three CPU feature flags that are in play here:
836 * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
837 * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
838 * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
840 if (mode
== SPEC_STORE_BYPASS_DISABLE
) {
841 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE
);
843 * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
844 * use a completely different MSR and bit dependent on family.
846 if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD
) &&
847 !static_cpu_has(X86_FEATURE_AMD_SSBD
)) {
848 x86_amd_ssb_disable();
850 x86_spec_ctrl_base
|= SPEC_CTRL_SSBD
;
851 x86_spec_ctrl_mask
|= SPEC_CTRL_SSBD
;
852 wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
859 static void ssb_select_mitigation(void)
861 ssb_mode
= __ssb_select_mitigation();
863 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS
))
864 pr_info("%s\n", ssb_strings
[ssb_mode
]);
868 #define pr_fmt(fmt) "Speculation prctl: " fmt
870 static void task_update_spec_tif(struct task_struct
*tsk
)
872 /* Force the update of the real TIF bits */
873 set_tsk_thread_flag(tsk
, TIF_SPEC_FORCE_UPDATE
);
876 * Immediately update the speculation control MSRs for the current
877 * task, but for a non-current task delay setting the CPU
878 * mitigation until it is scheduled next.
880 * This can only happen for SECCOMP mitigation. For PRCTL it's
881 * always the current task.
884 speculation_ctrl_update_current();
887 static int ssb_prctl_set(struct task_struct
*task
, unsigned long ctrl
)
889 if (ssb_mode
!= SPEC_STORE_BYPASS_PRCTL
&&
890 ssb_mode
!= SPEC_STORE_BYPASS_SECCOMP
)
895 /* If speculation is force disabled, enable is not allowed */
896 if (task_spec_ssb_force_disable(task
))
898 task_clear_spec_ssb_disable(task
);
899 task_update_spec_tif(task
);
901 case PR_SPEC_DISABLE
:
902 task_set_spec_ssb_disable(task
);
903 task_update_spec_tif(task
);
905 case PR_SPEC_FORCE_DISABLE
:
906 task_set_spec_ssb_disable(task
);
907 task_set_spec_ssb_force_disable(task
);
908 task_update_spec_tif(task
);
916 static int ib_prctl_set(struct task_struct
*task
, unsigned long ctrl
)
920 if (spectre_v2_user
== SPECTRE_V2_USER_NONE
)
923 * Indirect branch speculation is always disabled in strict
926 if (spectre_v2_user
== SPECTRE_V2_USER_STRICT
||
927 spectre_v2_user
== SPECTRE_V2_USER_STRICT_PREFERRED
)
929 task_clear_spec_ib_disable(task
);
930 task_update_spec_tif(task
);
932 case PR_SPEC_DISABLE
:
933 case PR_SPEC_FORCE_DISABLE
:
935 * Indirect branch speculation is always allowed when
936 * mitigation is force disabled.
938 if (spectre_v2_user
== SPECTRE_V2_USER_NONE
)
940 if (spectre_v2_user
== SPECTRE_V2_USER_STRICT
||
941 spectre_v2_user
== SPECTRE_V2_USER_STRICT_PREFERRED
)
943 task_set_spec_ib_disable(task
);
944 if (ctrl
== PR_SPEC_FORCE_DISABLE
)
945 task_set_spec_ib_force_disable(task
);
946 task_update_spec_tif(task
);
954 int arch_prctl_spec_ctrl_set(struct task_struct
*task
, unsigned long which
,
958 case PR_SPEC_STORE_BYPASS
:
959 return ssb_prctl_set(task
, ctrl
);
960 case PR_SPEC_INDIRECT_BRANCH
:
961 return ib_prctl_set(task
, ctrl
);
967 #ifdef CONFIG_SECCOMP
968 void arch_seccomp_spec_mitigate(struct task_struct
*task
)
970 if (ssb_mode
== SPEC_STORE_BYPASS_SECCOMP
)
971 ssb_prctl_set(task
, PR_SPEC_FORCE_DISABLE
);
972 if (spectre_v2_user
== SPECTRE_V2_USER_SECCOMP
)
973 ib_prctl_set(task
, PR_SPEC_FORCE_DISABLE
);
977 static int ssb_prctl_get(struct task_struct
*task
)
980 case SPEC_STORE_BYPASS_DISABLE
:
981 return PR_SPEC_DISABLE
;
982 case SPEC_STORE_BYPASS_SECCOMP
:
983 case SPEC_STORE_BYPASS_PRCTL
:
984 if (task_spec_ssb_force_disable(task
))
985 return PR_SPEC_PRCTL
| PR_SPEC_FORCE_DISABLE
;
986 if (task_spec_ssb_disable(task
))
987 return PR_SPEC_PRCTL
| PR_SPEC_DISABLE
;
988 return PR_SPEC_PRCTL
| PR_SPEC_ENABLE
;
990 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS
))
991 return PR_SPEC_ENABLE
;
992 return PR_SPEC_NOT_AFFECTED
;
996 static int ib_prctl_get(struct task_struct
*task
)
998 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2
))
999 return PR_SPEC_NOT_AFFECTED
;
1001 switch (spectre_v2_user
) {
1002 case SPECTRE_V2_USER_NONE
:
1003 return PR_SPEC_ENABLE
;
1004 case SPECTRE_V2_USER_PRCTL
:
1005 case SPECTRE_V2_USER_SECCOMP
:
1006 if (task_spec_ib_force_disable(task
))
1007 return PR_SPEC_PRCTL
| PR_SPEC_FORCE_DISABLE
;
1008 if (task_spec_ib_disable(task
))
1009 return PR_SPEC_PRCTL
| PR_SPEC_DISABLE
;
1010 return PR_SPEC_PRCTL
| PR_SPEC_ENABLE
;
1011 case SPECTRE_V2_USER_STRICT
:
1012 case SPECTRE_V2_USER_STRICT_PREFERRED
:
1013 return PR_SPEC_DISABLE
;
1015 return PR_SPEC_NOT_AFFECTED
;
1019 int arch_prctl_spec_ctrl_get(struct task_struct
*task
, unsigned long which
)
1022 case PR_SPEC_STORE_BYPASS
:
1023 return ssb_prctl_get(task
);
1024 case PR_SPEC_INDIRECT_BRANCH
:
1025 return ib_prctl_get(task
);
1031 void x86_spec_ctrl_setup_ap(void)
1033 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL
))
1034 wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
1036 if (ssb_mode
== SPEC_STORE_BYPASS_DISABLE
)
1037 x86_amd_ssb_disable();
1041 #define pr_fmt(fmt) "L1TF: " fmt
1043 /* Default mitigation for L1TF-affected CPUs */
1044 enum l1tf_mitigations l1tf_mitigation __ro_after_init
= L1TF_MITIGATION_FLUSH
;
1045 #if IS_ENABLED(CONFIG_KVM_INTEL)
1046 EXPORT_SYMBOL_GPL(l1tf_mitigation
);
1048 enum vmx_l1d_flush_state l1tf_vmx_mitigation
= VMENTER_L1D_FLUSH_AUTO
;
1049 EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation
);
1053 * These CPUs all support 44bits physical address space internally in the
1054 * cache but CPUID can report a smaller number of physical address bits.
1056 * The L1TF mitigation uses the top most address bit for the inversion of
1057 * non present PTEs. When the installed memory reaches into the top most
1058 * address bit due to memory holes, which has been observed on machines
1059 * which report 36bits physical address bits and have 32G RAM installed,
1060 * then the mitigation range check in l1tf_select_mitigation() triggers.
1061 * This is a false positive because the mitigation is still possible due to
1062 * the fact that the cache uses 44bit internally. Use the cache bits
1063 * instead of the reported physical bits and adjust them on the affected
1064 * machines to 44bit if the reported bits are less than 44.
1066 static void override_cache_bits(struct cpuinfo_x86
*c
)
1071 switch (c
->x86_model
) {
1072 case INTEL_FAM6_NEHALEM
:
1073 case INTEL_FAM6_WESTMERE
:
1074 case INTEL_FAM6_SANDYBRIDGE
:
1075 case INTEL_FAM6_IVYBRIDGE
:
1076 case INTEL_FAM6_HASWELL_CORE
:
1077 case INTEL_FAM6_HASWELL_ULT
:
1078 case INTEL_FAM6_HASWELL_GT3E
:
1079 case INTEL_FAM6_BROADWELL_CORE
:
1080 case INTEL_FAM6_BROADWELL_GT3E
:
1081 case INTEL_FAM6_SKYLAKE_MOBILE
:
1082 case INTEL_FAM6_SKYLAKE_DESKTOP
:
1083 case INTEL_FAM6_KABYLAKE_MOBILE
:
1084 case INTEL_FAM6_KABYLAKE_DESKTOP
:
1085 if (c
->x86_cache_bits
< 44)
1086 c
->x86_cache_bits
= 44;
1091 static void __init
l1tf_select_mitigation(void)
1095 if (!boot_cpu_has_bug(X86_BUG_L1TF
))
1098 if (cpu_mitigations_off())
1099 l1tf_mitigation
= L1TF_MITIGATION_OFF
;
1100 else if (cpu_mitigations_auto_nosmt())
1101 l1tf_mitigation
= L1TF_MITIGATION_FLUSH_NOSMT
;
1103 override_cache_bits(&boot_cpu_data
);
1105 switch (l1tf_mitigation
) {
1106 case L1TF_MITIGATION_OFF
:
1107 case L1TF_MITIGATION_FLUSH_NOWARN
:
1108 case L1TF_MITIGATION_FLUSH
:
1110 case L1TF_MITIGATION_FLUSH_NOSMT
:
1111 case L1TF_MITIGATION_FULL
:
1112 cpu_smt_disable(false);
1114 case L1TF_MITIGATION_FULL_FORCE
:
1115 cpu_smt_disable(true);
1119 #if CONFIG_PGTABLE_LEVELS == 2
1120 pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n");
1124 half_pa
= (u64
)l1tf_pfn_limit() << PAGE_SHIFT
;
1125 if (e820__mapped_any(half_pa
, ULLONG_MAX
- half_pa
, E820_TYPE_RAM
)) {
1126 pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n");
1127 pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n",
1129 pr_info("However, doing so will make a part of your RAM unusable.\n");
1130 pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html might help you decide.\n");
1134 setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV
);
1137 static int __init
l1tf_cmdline(char *str
)
1139 if (!boot_cpu_has_bug(X86_BUG_L1TF
))
1145 if (!strcmp(str
, "off"))
1146 l1tf_mitigation
= L1TF_MITIGATION_OFF
;
1147 else if (!strcmp(str
, "flush,nowarn"))
1148 l1tf_mitigation
= L1TF_MITIGATION_FLUSH_NOWARN
;
1149 else if (!strcmp(str
, "flush"))
1150 l1tf_mitigation
= L1TF_MITIGATION_FLUSH
;
1151 else if (!strcmp(str
, "flush,nosmt"))
1152 l1tf_mitigation
= L1TF_MITIGATION_FLUSH_NOSMT
;
1153 else if (!strcmp(str
, "full"))
1154 l1tf_mitigation
= L1TF_MITIGATION_FULL
;
1155 else if (!strcmp(str
, "full,force"))
1156 l1tf_mitigation
= L1TF_MITIGATION_FULL_FORCE
;
1160 early_param("l1tf", l1tf_cmdline
);
1163 #define pr_fmt(fmt) fmt
1167 #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion"
1169 #if IS_ENABLED(CONFIG_KVM_INTEL)
1170 static const char * const l1tf_vmx_states
[] = {
1171 [VMENTER_L1D_FLUSH_AUTO
] = "auto",
1172 [VMENTER_L1D_FLUSH_NEVER
] = "vulnerable",
1173 [VMENTER_L1D_FLUSH_COND
] = "conditional cache flushes",
1174 [VMENTER_L1D_FLUSH_ALWAYS
] = "cache flushes",
1175 [VMENTER_L1D_FLUSH_EPT_DISABLED
] = "EPT disabled",
1176 [VMENTER_L1D_FLUSH_NOT_REQUIRED
] = "flush not necessary"
1179 static ssize_t
l1tf_show_state(char *buf
)
1181 if (l1tf_vmx_mitigation
== VMENTER_L1D_FLUSH_AUTO
)
1182 return sprintf(buf
, "%s\n", L1TF_DEFAULT_MSG
);
1184 if (l1tf_vmx_mitigation
== VMENTER_L1D_FLUSH_EPT_DISABLED
||
1185 (l1tf_vmx_mitigation
== VMENTER_L1D_FLUSH_NEVER
&&
1186 sched_smt_active())) {
1187 return sprintf(buf
, "%s; VMX: %s\n", L1TF_DEFAULT_MSG
,
1188 l1tf_vmx_states
[l1tf_vmx_mitigation
]);
1191 return sprintf(buf
, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG
,
1192 l1tf_vmx_states
[l1tf_vmx_mitigation
],
1193 sched_smt_active() ? "vulnerable" : "disabled");
1196 static ssize_t
l1tf_show_state(char *buf
)
1198 return sprintf(buf
, "%s\n", L1TF_DEFAULT_MSG
);
1202 static ssize_t
mds_show_state(char *buf
)
1204 if (!hypervisor_is_type(X86_HYPER_NATIVE
)) {
1205 return sprintf(buf
, "%s; SMT Host state unknown\n",
1206 mds_strings
[mds_mitigation
]);
1209 if (boot_cpu_has(X86_BUG_MSBDS_ONLY
)) {
1210 return sprintf(buf
, "%s; SMT %s\n", mds_strings
[mds_mitigation
],
1211 (mds_mitigation
== MDS_MITIGATION_OFF
? "vulnerable" :
1212 sched_smt_active() ? "mitigated" : "disabled"));
1215 return sprintf(buf
, "%s; SMT %s\n", mds_strings
[mds_mitigation
],
1216 sched_smt_active() ? "vulnerable" : "disabled");
1219 static char *stibp_state(void)
1221 if (spectre_v2_enabled
== SPECTRE_V2_IBRS_ENHANCED
)
1224 switch (spectre_v2_user
) {
1225 case SPECTRE_V2_USER_NONE
:
1226 return ", STIBP: disabled";
1227 case SPECTRE_V2_USER_STRICT
:
1228 return ", STIBP: forced";
1229 case SPECTRE_V2_USER_STRICT_PREFERRED
:
1230 return ", STIBP: always-on";
1231 case SPECTRE_V2_USER_PRCTL
:
1232 case SPECTRE_V2_USER_SECCOMP
:
1233 if (static_key_enabled(&switch_to_cond_stibp
))
1234 return ", STIBP: conditional";
1239 static char *ibpb_state(void)
1241 if (boot_cpu_has(X86_FEATURE_IBPB
)) {
1242 if (static_key_enabled(&switch_mm_always_ibpb
))
1243 return ", IBPB: always-on";
1244 if (static_key_enabled(&switch_mm_cond_ibpb
))
1245 return ", IBPB: conditional";
1246 return ", IBPB: disabled";
1251 static ssize_t
cpu_show_common(struct device
*dev
, struct device_attribute
*attr
,
1252 char *buf
, unsigned int bug
)
1254 if (!boot_cpu_has_bug(bug
))
1255 return sprintf(buf
, "Not affected\n");
1258 case X86_BUG_CPU_MELTDOWN
:
1259 if (boot_cpu_has(X86_FEATURE_PTI
))
1260 return sprintf(buf
, "Mitigation: PTI\n");
1264 case X86_BUG_SPECTRE_V1
:
1265 return sprintf(buf
, "Mitigation: __user pointer sanitization\n");
1267 case X86_BUG_SPECTRE_V2
:
1268 return sprintf(buf
, "%s%s%s%s%s%s\n", spectre_v2_strings
[spectre_v2_enabled
],
1270 boot_cpu_has(X86_FEATURE_USE_IBRS_FW
) ? ", IBRS_FW" : "",
1272 boot_cpu_has(X86_FEATURE_RSB_CTXSW
) ? ", RSB filling" : "",
1273 spectre_v2_module_string());
1275 case X86_BUG_SPEC_STORE_BYPASS
:
1276 return sprintf(buf
, "%s\n", ssb_strings
[ssb_mode
]);
1279 if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV
))
1280 return l1tf_show_state(buf
);
1284 return mds_show_state(buf
);
1290 return sprintf(buf
, "Vulnerable\n");
1293 ssize_t
cpu_show_meltdown(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1295 return cpu_show_common(dev
, attr
, buf
, X86_BUG_CPU_MELTDOWN
);
1298 ssize_t
cpu_show_spectre_v1(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1300 return cpu_show_common(dev
, attr
, buf
, X86_BUG_SPECTRE_V1
);
1303 ssize_t
cpu_show_spectre_v2(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1305 return cpu_show_common(dev
, attr
, buf
, X86_BUG_SPECTRE_V2
);
1308 ssize_t
cpu_show_spec_store_bypass(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1310 return cpu_show_common(dev
, attr
, buf
, X86_BUG_SPEC_STORE_BYPASS
);
1313 ssize_t
cpu_show_l1tf(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1315 return cpu_show_common(dev
, attr
, buf
, X86_BUG_L1TF
);
1318 ssize_t
cpu_show_mds(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1320 return cpu_show_common(dev
, attr
, buf
, X86_BUG_MDS
);