arch/x86/kernel/cpu/bugs.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *  Copyright (C) 1994  Linus Torvalds
   4  *
   5  *  Cyrix stuff, June 1998 by:
   6  *      - Rafael R. Reilova (moved everything from head.S),
   7  *        <rreilova@ececs.uc.edu>
   8  *      - Channing Corn (tests & fixes),
   9  *      - Andrew D. Balsa (code cleanup).
  10  */
  11 #include <linux/init.h>
  12 #include <linux/utsname.h>
  13 #include <linux/cpu.h>
  14 #include <linux/module.h>
  15 #include <linux/nospec.h>
  16 #include <linux/prctl.h>
  17
  18 #include <asm/spec-ctrl.h>
  19 #include <asm/cmdline.h>
  20 #include <asm/bugs.h>
  21 #include <asm/processor.h>
  22 #include <asm/processor-flags.h>
  23 #include <asm/fpu/internal.h>
  24 #include <asm/msr.h>
  25 #include <asm/paravirt.h>
  26 #include <asm/alternative.h>
  27 #include <asm/pgtable.h>
  28 #include <asm/set_memory.h>
  29 #include <asm/intel-family.h>
  30
  31 static void __init spectre_v2_select_mitigation(void);
  32 static void __init ssb_select_mitigation(void);
  33
  34 /*
  35  * Our boot-time value of the SPEC_CTRL MSR. We read it once so that any
  36  * writes to SPEC_CTRL contain whatever reserved bits have been set.
  37  */
  38 u64 __ro_after_init x86_spec_ctrl_base;
  39
  40 /*
  41  * The vendor and possibly platform specific bits which can be modified in
  42  * x86_spec_ctrl_base.
  43  */
  44 static u64 __ro_after_init x86_spec_ctrl_mask = ~SPEC_CTRL_IBRS;
  45
  46 /*
  47  * AMD specific MSR info for Speculative Store Bypass control.
  48  * x86_amd_ls_cfg_rds_mask is initialized in identify_boot_cpu().
  49  */
  50 u64 __ro_after_init x86_amd_ls_cfg_base;
  51 u64 __ro_after_init x86_amd_ls_cfg_rds_mask;
  52
  53 void __init check_bugs(void)
  54 {
  55         identify_boot_cpu();
  56
  57         if (!IS_ENABLED(CONFIG_SMP)) {
  58                 pr_info("CPU: ");
  59                 print_cpu_info(&boot_cpu_data);
  60         }
  61
  62         /*
  63          * Read the SPEC_CTRL MSR to account for reserved bits which may
  64          * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
  65          * init code as it is not enumerated and depends on the family.
  66          */
  67         if (boot_cpu_has(X86_FEATURE_IBRS))
  68                 rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
  69
  70         /* Select the proper spectre mitigation before patching alternatives */
  71         spectre_v2_select_mitigation();
  72
  73         /*
  74          * Select proper mitigation for any exposure to the Speculative Store
  75          * Bypass vulnerability.
  76          */
  77         ssb_select_mitigation();
  78
  79 #ifdef CONFIG_X86_32
  80         /*
  81          * Check whether we are able to run this kernel safely on SMP.
  82          *
  83          * - i386 is no longer supported.
  84          * - In order to run on anything without a TSC, we need to be
  85          *   compiled for a i486.
  86          */
  87         if (boot_cpu_data.x86 < 4)
  88                 panic("Kernel requires i486+ for 'invlpg' and other features");
  89
  90         init_utsname()->machine[1] =
  91                 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
  92         alternative_instructions();
  93
  94         fpu__init_check_bugs();
  95 #else /* CONFIG_X86_64 */
  96         alternative_instructions();
  97
  98         /*
  99          * Make sure the first 2MB area is not mapped by huge pages
 100          * There are typically fixed size MTRRs in there and overlapping
 101          * MTRRs into large pages causes slow downs.
 102          *
 103          * Right now we don't do that with gbpages because there seems
 104          * very little benefit for that case.
 105          */
 106         if (!direct_gbpages)
 107                 set_memory_4k((unsigned long)__va(0), 1);
 108 #endif
 109 }
 110
 111 /* The kernel command line selection */
 112 enum spectre_v2_mitigation_cmd {
 113         SPECTRE_V2_CMD_NONE,
 114         SPECTRE_V2_CMD_AUTO,
 115         SPECTRE_V2_CMD_FORCE,
 116         SPECTRE_V2_CMD_RETPOLINE,
 117         SPECTRE_V2_CMD_RETPOLINE_GENERIC,
 118         SPECTRE_V2_CMD_RETPOLINE_AMD,
 119 };
 120
 121 static const char *spectre_v2_strings[] = {
 122         [SPECTRE_V2_NONE]                       = "Vulnerable",
 123         [SPECTRE_V2_RETPOLINE_MINIMAL]          = "Vulnerable: Minimal generic ASM retpoline",
 124         [SPECTRE_V2_RETPOLINE_MINIMAL_AMD]      = "Vulnerable: Minimal AMD ASM retpoline",
 125         [SPECTRE_V2_RETPOLINE_GENERIC]          = "Mitigation: Full generic retpoline",
 126         [SPECTRE_V2_RETPOLINE_AMD]              = "Mitigation: Full AMD retpoline",
 127 };
 128
 129 #undef pr_fmt
 130 #define pr_fmt(fmt)     "Spectre V2 : " fmt
 131
 132 static enum spectre_v2_mitigation spectre_v2_enabled = SPECTRE_V2_NONE;
 133
 134 void x86_spec_ctrl_set(u64 val)
 135 {
 136         if (val & x86_spec_ctrl_mask)
 137                 WARN_ONCE(1, "SPEC_CTRL MSR value 0x%16llx is unknown.\n", val);
 138         else
 139                 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base | val);
 140 }
 141 EXPORT_SYMBOL_GPL(x86_spec_ctrl_set);
 142
 143 u64 x86_spec_ctrl_get_default(void)
 144 {
 145         u64 msrval = x86_spec_ctrl_base;
 146
 147         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
 148                 msrval |= rds_tif_to_spec_ctrl(current_thread_info()->flags);
 149         return msrval;
 150 }
 151 EXPORT_SYMBOL_GPL(x86_spec_ctrl_get_default);
 152
 153 void x86_spec_ctrl_set_guest(u64 guest_spec_ctrl)
 154 {
 155         u64 host = x86_spec_ctrl_base;
 156
 157         if (!boot_cpu_has(X86_FEATURE_IBRS))
 158                 return;
 159
 160         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
 161                 host |= rds_tif_to_spec_ctrl(current_thread_info()->flags);
 162
 163         if (host != guest_spec_ctrl)
 164                 wrmsrl(MSR_IA32_SPEC_CTRL, guest_spec_ctrl);
 165 }
 166 EXPORT_SYMBOL_GPL(x86_spec_ctrl_set_guest);
 167
 168 void x86_spec_ctrl_restore_host(u64 guest_spec_ctrl)
 169 {
 170         u64 host = x86_spec_ctrl_base;
 171
 172         if (!boot_cpu_has(X86_FEATURE_IBRS))
 173                 return;
 174
 175         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
 176                 host |= rds_tif_to_spec_ctrl(current_thread_info()->flags);
 177
 178         if (host != guest_spec_ctrl)
 179                 wrmsrl(MSR_IA32_SPEC_CTRL, host);
 180 }
 181 EXPORT_SYMBOL_GPL(x86_spec_ctrl_restore_host);
 182
 183 static void x86_amd_rds_enable(void)
 184 {
 185         u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_rds_mask;
 186
 187         if (boot_cpu_has(X86_FEATURE_AMD_RDS))
 188                 wrmsrl(MSR_AMD64_LS_CFG, msrval);
 189 }
 190
 191 #ifdef RETPOLINE
 192 static bool spectre_v2_bad_module;
 193
 194 bool retpoline_module_ok(bool has_retpoline)
 195 {
 196         if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline)
 197                 return true;
 198
 199         pr_err("System may be vulnerable to spectre v2\n");
 200         spectre_v2_bad_module = true;
 201         return false;
 202 }
 203
 204 static inline const char *spectre_v2_module_string(void)
 205 {
 206         return spectre_v2_bad_module ? " - vulnerable module loaded" : "";
 207 }
 208 #else
 209 static inline const char *spectre_v2_module_string(void) { return ""; }
 210 #endif
 211
 212 static void __init spec2_print_if_insecure(const char *reason)
 213 {
 214         if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
 215                 pr_info("%s selected on command line.\n", reason);
 216 }
 217
 218 static void __init spec2_print_if_secure(const char *reason)
 219 {
 220         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
 221                 pr_info("%s selected on command line.\n", reason);
 222 }
 223
 224 static inline bool retp_compiler(void)
 225 {
 226         return __is_defined(RETPOLINE);
 227 }
 228
 229 static inline bool match_option(const char *arg, int arglen, const char *opt)
 230 {
 231         int len = strlen(opt);
 232
 233         return len == arglen && !strncmp(arg, opt, len);
 234 }
 235
 236 static const struct {
 237         const char *option;
 238         enum spectre_v2_mitigation_cmd cmd;
 239         bool secure;
 240 } mitigation_options[] = {
 241         { "off",               SPECTRE_V2_CMD_NONE,              false },
 242         { "on",                SPECTRE_V2_CMD_FORCE,             true },
 243         { "retpoline",         SPECTRE_V2_CMD_RETPOLINE,         false },
 244         { "retpoline,amd",     SPECTRE_V2_CMD_RETPOLINE_AMD,     false },
 245         { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false },
 246         { "auto",              SPECTRE_V2_CMD_AUTO,              false },
 247 };
 248
 249 static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
 250 {
 251         char arg[20];
 252         int ret, i;
 253         enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO;
 254
 255         if (cmdline_find_option_bool(boot_command_line, "nospectre_v2"))
 256                 return SPECTRE_V2_CMD_NONE;
 257         else {
 258                 ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg));
 259                 if (ret < 0)
 260                         return SPECTRE_V2_CMD_AUTO;
 261
 262                 for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) {
 263                         if (!match_option(arg, ret, mitigation_options[i].option))
 264                                 continue;
 265                         cmd = mitigation_options[i].cmd;
 266                         break;
 267                 }
 268
 269                 if (i >= ARRAY_SIZE(mitigation_options)) {
 270                         pr_err("unknown option (%s). Switching to AUTO select\n", arg);
 271                         return SPECTRE_V2_CMD_AUTO;
 272                 }
 273         }
 274
 275         if ((cmd == SPECTRE_V2_CMD_RETPOLINE ||
 276              cmd == SPECTRE_V2_CMD_RETPOLINE_AMD ||
 277              cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) &&
 278             !IS_ENABLED(CONFIG_RETPOLINE)) {
 279                 pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option);
 280                 return SPECTRE_V2_CMD_AUTO;
 281         }
 282
 283         if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD &&
 284             boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
 285                 pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n");
 286                 return SPECTRE_V2_CMD_AUTO;
 287         }
 288
 289         if (mitigation_options[i].secure)
 290                 spec2_print_if_secure(mitigation_options[i].option);
 291         else
 292                 spec2_print_if_insecure(mitigation_options[i].option);
 293
 294         return cmd;
 295 }
 296
 297 /* Check for Skylake-like CPUs (for RSB handling) */
 298 static bool __init is_skylake_era(void)
 299 {
 300         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
 301             boot_cpu_data.x86 == 6) {
 302                 switch (boot_cpu_data.x86_model) {
 303                 case INTEL_FAM6_SKYLAKE_MOBILE:
 304                 case INTEL_FAM6_SKYLAKE_DESKTOP:
 305                 case INTEL_FAM6_SKYLAKE_X:
 306                 case INTEL_FAM6_KABYLAKE_MOBILE:
 307                 case INTEL_FAM6_KABYLAKE_DESKTOP:
 308                         return true;
 309                 }
 310         }
 311         return false;
 312 }
 313
 314 static void __init spectre_v2_select_mitigation(void)
 315 {
 316         enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
 317         enum spectre_v2_mitigation mode = SPECTRE_V2_NONE;
 318
 319         /*
 320          * If the CPU is not affected and the command line mode is NONE or AUTO
 321          * then nothing to do.
 322          */
 323         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) &&
 324             (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO))
 325                 return;
 326
 327         switch (cmd) {
 328         case SPECTRE_V2_CMD_NONE:
 329                 return;
 330
 331         case SPECTRE_V2_CMD_FORCE:
 332         case SPECTRE_V2_CMD_AUTO:
 333                 if (IS_ENABLED(CONFIG_RETPOLINE))
 334                         goto retpoline_auto;
 335                 break;
 336         case SPECTRE_V2_CMD_RETPOLINE_AMD:
 337                 if (IS_ENABLED(CONFIG_RETPOLINE))
 338                         goto retpoline_amd;
 339                 break;
 340         case SPECTRE_V2_CMD_RETPOLINE_GENERIC:
 341                 if (IS_ENABLED(CONFIG_RETPOLINE))
 342                         goto retpoline_generic;
 343                 break;
 344         case SPECTRE_V2_CMD_RETPOLINE:
 345                 if (IS_ENABLED(CONFIG_RETPOLINE))
 346                         goto retpoline_auto;
 347                 break;
 348         }
 349         pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!");
 350         return;
 351
 352 retpoline_auto:
 353         if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
 354         retpoline_amd:
 355                 if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
 356                         pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n");
 357                         goto retpoline_generic;
 358                 }
 359                 mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_AMD :
 360                                          SPECTRE_V2_RETPOLINE_MINIMAL_AMD;
 361                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD);
 362                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
 363         } else {
 364         retpoline_generic:
 365                 mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_GENERIC :
 366                                          SPECTRE_V2_RETPOLINE_MINIMAL;
 367                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
 368         }
 369
 370         spectre_v2_enabled = mode;
 371         pr_info("%s\n", spectre_v2_strings[mode]);
 372
 373         /*
 374          * If neither SMEP nor PTI are available, there is a risk of
 375          * hitting userspace addresses in the RSB after a context switch
 376          * from a shallow call stack to a deeper one. To prevent this fill
 377          * the entire RSB, even when using IBRS.
 378          *
 379          * Skylake era CPUs have a separate issue with *underflow* of the
 380          * RSB, when they will predict 'ret' targets from the generic BTB.
 381          * The proper mitigation for this is IBRS. If IBRS is not supported
 382          * or deactivated in favour of retpolines the RSB fill on context
 383          * switch is required.
 384          */
 385         if ((!boot_cpu_has(X86_FEATURE_PTI) &&
 386              !boot_cpu_has(X86_FEATURE_SMEP)) || is_skylake_era()) {
 387                 setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
 388                 pr_info("Spectre v2 mitigation: Filling RSB on context switch\n");
 389         }
 390
 391         /* Initialize Indirect Branch Prediction Barrier if supported */
 392         if (boot_cpu_has(X86_FEATURE_IBPB)) {
 393                 setup_force_cpu_cap(X86_FEATURE_USE_IBPB);
 394                 pr_info("Spectre v2 mitigation: Enabling Indirect Branch Prediction Barrier\n");
 395         }
 396
 397         /*
 398          * Retpoline means the kernel is safe because it has no indirect
 399          * branches. But firmware isn't, so use IBRS to protect that.
 400          */
 401         if (boot_cpu_has(X86_FEATURE_IBRS)) {
 402                 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW);
 403                 pr_info("Enabling Restricted Speculation for firmware calls\n");
 404         }
 405 }
 406
 407 #undef pr_fmt
 408 #define pr_fmt(fmt)     "Speculative Store Bypass: " fmt
 409
 410 static enum ssb_mitigation ssb_mode = SPEC_STORE_BYPASS_NONE;
 411
 412 /* The kernel command line selection */
 413 enum ssb_mitigation_cmd {
 414         SPEC_STORE_BYPASS_CMD_NONE,
 415         SPEC_STORE_BYPASS_CMD_AUTO,
 416         SPEC_STORE_BYPASS_CMD_ON,
 417         SPEC_STORE_BYPASS_CMD_PRCTL,
 418 };
 419
 420 static const char *ssb_strings[] = {
 421         [SPEC_STORE_BYPASS_NONE]        = "Vulnerable",
 422         [SPEC_STORE_BYPASS_DISABLE]     = "Mitigation: Speculative Store Bypass disabled",
 423         [SPEC_STORE_BYPASS_PRCTL]       = "Mitigation: Speculative Store Bypass disabled via prctl"
 424 };
 425
 426 static const struct {
 427         const char *option;
 428         enum ssb_mitigation_cmd cmd;
 429 } ssb_mitigation_options[] = {
 430         { "auto",       SPEC_STORE_BYPASS_CMD_AUTO },  /* Platform decides */
 431         { "on",         SPEC_STORE_BYPASS_CMD_ON },    /* Disable Speculative Store Bypass */
 432         { "off",        SPEC_STORE_BYPASS_CMD_NONE },  /* Don't touch Speculative Store Bypass */
 433         { "prctl",      SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */
 434 };
 435
 436 static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void)
 437 {
 438         enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO;
 439         char arg[20];
 440         int ret, i;
 441
 442         if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable")) {
 443                 return SPEC_STORE_BYPASS_CMD_NONE;
 444         } else {
 445                 ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable",
 446                                           arg, sizeof(arg));
 447                 if (ret < 0)
 448                         return SPEC_STORE_BYPASS_CMD_AUTO;
 449
 450                 for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) {
 451                         if (!match_option(arg, ret, ssb_mitigation_options[i].option))
 452                                 continue;
 453
 454                         cmd = ssb_mitigation_options[i].cmd;
 455                         break;
 456                 }
 457
 458                 if (i >= ARRAY_SIZE(ssb_mitigation_options)) {
 459                         pr_err("unknown option (%s). Switching to AUTO select\n", arg);
 460                         return SPEC_STORE_BYPASS_CMD_AUTO;
 461                 }
 462         }
 463
 464         return cmd;
 465 }
 466
 467 static enum ssb_mitigation_cmd __init __ssb_select_mitigation(void)
 468 {
 469         enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE;
 470         enum ssb_mitigation_cmd cmd;
 471
 472         if (!boot_cpu_has(X86_FEATURE_RDS))
 473                 return mode;
 474
 475         cmd = ssb_parse_cmdline();
 476         if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) &&
 477             (cmd == SPEC_STORE_BYPASS_CMD_NONE ||
 478              cmd == SPEC_STORE_BYPASS_CMD_AUTO))
 479                 return mode;
 480
 481         switch (cmd) {
 482         case SPEC_STORE_BYPASS_CMD_AUTO:
 483                 /* Choose prctl as the default mode */
 484                 mode = SPEC_STORE_BYPASS_PRCTL;
 485                 break;
 486         case SPEC_STORE_BYPASS_CMD_ON:
 487                 mode = SPEC_STORE_BYPASS_DISABLE;
 488                 break;
 489         case SPEC_STORE_BYPASS_CMD_PRCTL:
 490                 mode = SPEC_STORE_BYPASS_PRCTL;
 491                 break;
 492         case SPEC_STORE_BYPASS_CMD_NONE:
 493                 break;
 494         }
 495
 496         /*
 497          * We have three CPU feature flags that are in play here:
 498          *  - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
 499          *  - X86_FEATURE_RDS - CPU is able to turn off speculative store bypass
 500          *  - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
 501          */
 502         if (mode == SPEC_STORE_BYPASS_DISABLE) {
 503                 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE);
 504                 /*
 505                  * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD uses
 506                  * a completely different MSR and bit dependent on family.
 507                  */
 508                 switch (boot_cpu_data.x86_vendor) {
 509                 case X86_VENDOR_INTEL:
 510                         x86_spec_ctrl_base |= SPEC_CTRL_RDS;
 511                         x86_spec_ctrl_mask &= ~SPEC_CTRL_RDS;
 512                         x86_spec_ctrl_set(SPEC_CTRL_RDS);
 513                         break;
 514                 case X86_VENDOR_AMD:
 515                         x86_amd_rds_enable();
 516                         break;
 517                 }
 518         }
 519
 520         return mode;
 521 }
 522
 523 static void ssb_select_mitigation()
 524 {
 525         ssb_mode = __ssb_select_mitigation();
 526
 527         if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
 528                 pr_info("%s\n", ssb_strings[ssb_mode]);
 529 }
 530
 531 #undef pr_fmt
 532
 533 static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl)
 534 {
 535         bool rds = !!test_tsk_thread_flag(task, TIF_RDS);
 536
 537         if (ssb_mode != SPEC_STORE_BYPASS_PRCTL)
 538                 return -ENXIO;
 539
 540         if (ctrl == PR_SPEC_ENABLE)
 541                 clear_tsk_thread_flag(task, TIF_RDS);
 542         else
 543                 set_tsk_thread_flag(task, TIF_RDS);
 544
 545         /*
 546          * If being set on non-current task, delay setting the CPU
 547          * mitigation until it is next scheduled.
 548          */
 549         if (task == current && rds != !!test_tsk_thread_flag(task, TIF_RDS))
 550                 speculative_store_bypass_update();
 551
 552         return 0;
 553 }
 554
 555 static int ssb_prctl_get(struct task_struct *task)
 556 {
 557         switch (ssb_mode) {
 558         case SPEC_STORE_BYPASS_DISABLE:
 559                 return PR_SPEC_DISABLE;
 560         case SPEC_STORE_BYPASS_PRCTL:
 561                 if (test_tsk_thread_flag(task, TIF_RDS))
 562                         return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
 563                 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
 564         default:
 565                 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
 566                         return PR_SPEC_ENABLE;
 567                 return PR_SPEC_NOT_AFFECTED;
 568         }
 569 }
 570
 571 int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which,
 572                              unsigned long ctrl)
 573 {
 574         if (ctrl != PR_SPEC_ENABLE && ctrl != PR_SPEC_DISABLE)
 575                 return -ERANGE;
 576
 577         switch (which) {
 578         case PR_SPEC_STORE_BYPASS:
 579                 return ssb_prctl_set(task, ctrl);
 580         default:
 581                 return -ENODEV;
 582         }
 583 }
 584
 585 int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
 586 {
 587         switch (which) {
 588         case PR_SPEC_STORE_BYPASS:
 589                 return ssb_prctl_get(task);
 590         default:
 591                 return -ENODEV;
 592         }
 593 }
 594
 595 void x86_spec_ctrl_setup_ap(void)
 596 {
 597         if (boot_cpu_has(X86_FEATURE_IBRS))
 598                 x86_spec_ctrl_set(x86_spec_ctrl_base & ~x86_spec_ctrl_mask);
 599
 600         if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
 601                 x86_amd_rds_enable();
 602 }
 603
 604 #ifdef CONFIG_SYSFS
 605
 606 ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr,
 607                         char *buf, unsigned int bug)
 608 {
 609         if (!boot_cpu_has_bug(bug))
 610                 return sprintf(buf, "Not affected\n");
 611
 612         switch (bug) {
 613         case X86_BUG_CPU_MELTDOWN:
 614                 if (boot_cpu_has(X86_FEATURE_PTI))
 615                         return sprintf(buf, "Mitigation: PTI\n");
 616
 617                 break;
 618
 619         case X86_BUG_SPECTRE_V1:
 620                 return sprintf(buf, "Mitigation: __user pointer sanitization\n");
 621
 622         case X86_BUG_SPECTRE_V2:
 623                 return sprintf(buf, "%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled],
 624                                boot_cpu_has(X86_FEATURE_USE_IBPB) ? ", IBPB" : "",
 625                                boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "",
 626                                spectre_v2_module_string());
 627
 628         case X86_BUG_SPEC_STORE_BYPASS:
 629                 return sprintf(buf, "%s\n", ssb_strings[ssb_mode]);
 630
 631         default:
 632                 break;
 633         }
 634
 635         return sprintf(buf, "Vulnerable\n");
 636 }
 637
 638 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf)
 639 {
 640         return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN);
 641 }
 642
 643 ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf)
 644 {
 645         return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1);
 646 }
 647
 648 ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf)
 649 {
 650         return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2);
 651 }
 652
 653 ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf)
 654 {
 655         return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS);
 656 }
 657 #endif