arch/x86/kernel/cpu/bugs.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *  Copyright (C) 1994  Linus Torvalds
   4  *
   5  *  Cyrix stuff, June 1998 by:
   6  *      - Rafael R. Reilova (moved everything from head.S),
   7  *        <rreilova@ececs.uc.edu>
   8  *      - Channing Corn (tests & fixes),
   9  *      - Andrew D. Balsa (code cleanup).
  10  */
  11 #include <linux/init.h>
  12 #include <linux/utsname.h>
  13 #include <linux/cpu.h>
  14 #include <linux/module.h>
  15 #include <linux/nospec.h>
  16 #include <linux/prctl.h>
  17
  18 #include <asm/spec-ctrl.h>
  19 #include <asm/cmdline.h>
  20 #include <asm/bugs.h>
  21 #include <asm/processor.h>
  22 #include <asm/processor-flags.h>
  23 #include <asm/fpu/internal.h>
  24 #include <asm/msr.h>
  25 #include <asm/paravirt.h>
  26 #include <asm/alternative.h>
  27 #include <asm/pgtable.h>
  28 #include <asm/set_memory.h>
  29 #include <asm/intel-family.h>
  30
  31 static void __init spectre_v2_select_mitigation(void);
  32 static void __init ssb_select_mitigation(void);
  33
  34 /*
  35  * Our boot-time value of the SPEC_CTRL MSR. We read it once so that any
  36  * writes to SPEC_CTRL contain whatever reserved bits have been set.
  37  */
  38 u64 __ro_after_init x86_spec_ctrl_base;
  39
  40 /*
  41  * The vendor and possibly platform specific bits which can be modified in
  42  * x86_spec_ctrl_base.
  43  */
  44 static u64 __ro_after_init x86_spec_ctrl_mask = ~SPEC_CTRL_IBRS;
  45
  46 /*
  47  * AMD specific MSR info for Speculative Store Bypass control.
  48  * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
  49  */
  50 u64 __ro_after_init x86_amd_ls_cfg_base;
  51 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask;
  52
  53 void __init check_bugs(void)
  54 {
  55         identify_boot_cpu();
  56
  57         if (!IS_ENABLED(CONFIG_SMP)) {
  58                 pr_info("CPU: ");
  59                 print_cpu_info(&boot_cpu_data);
  60         }
  61
  62         /*
  63          * Read the SPEC_CTRL MSR to account for reserved bits which may
  64          * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
  65          * init code as it is not enumerated and depends on the family.
  66          */
  67         if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
  68                 rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
  69
  70         /* Select the proper spectre mitigation before patching alternatives */
  71         spectre_v2_select_mitigation();
  72
  73         /*
  74          * Select proper mitigation for any exposure to the Speculative Store
  75          * Bypass vulnerability.
  76          */
  77         ssb_select_mitigation();
  78
  79 #ifdef CONFIG_X86_32
  80         /*
  81          * Check whether we are able to run this kernel safely on SMP.
  82          *
  83          * - i386 is no longer supported.
  84          * - In order to run on anything without a TSC, we need to be
  85          *   compiled for a i486.
  86          */
  87         if (boot_cpu_data.x86 < 4)
  88                 panic("Kernel requires i486+ for 'invlpg' and other features");
  89
  90         init_utsname()->machine[1] =
  91                 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
  92         alternative_instructions();
  93
  94         fpu__init_check_bugs();
  95 #else /* CONFIG_X86_64 */
  96         alternative_instructions();
  97
  98         /*
  99          * Make sure the first 2MB area is not mapped by huge pages
 100          * There are typically fixed size MTRRs in there and overlapping
 101          * MTRRs into large pages causes slow downs.
 102          *
 103          * Right now we don't do that with gbpages because there seems
 104          * very little benefit for that case.
 105          */
 106         if (!direct_gbpages)
 107                 set_memory_4k((unsigned long)__va(0), 1);
 108 #endif
 109 }
 110
 111 /* The kernel command line selection */
 112 enum spectre_v2_mitigation_cmd {
 113         SPECTRE_V2_CMD_NONE,
 114         SPECTRE_V2_CMD_AUTO,
 115         SPECTRE_V2_CMD_FORCE,
 116         SPECTRE_V2_CMD_RETPOLINE,
 117         SPECTRE_V2_CMD_RETPOLINE_GENERIC,
 118         SPECTRE_V2_CMD_RETPOLINE_AMD,
 119 };
 120
 121 static const char *spectre_v2_strings[] = {
 122         [SPECTRE_V2_NONE]                       = "Vulnerable",
 123         [SPECTRE_V2_RETPOLINE_MINIMAL]          = "Vulnerable: Minimal generic ASM retpoline",
 124         [SPECTRE_V2_RETPOLINE_MINIMAL_AMD]      = "Vulnerable: Minimal AMD ASM retpoline",
 125         [SPECTRE_V2_RETPOLINE_GENERIC]          = "Mitigation: Full generic retpoline",
 126         [SPECTRE_V2_RETPOLINE_AMD]              = "Mitigation: Full AMD retpoline",
 127 };
 128
 129 #undef pr_fmt
 130 #define pr_fmt(fmt)     "Spectre V2 : " fmt
 131
 132 static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init =
 133         SPECTRE_V2_NONE;
 134
 135 void x86_spec_ctrl_set(u64 val)
 136 {
 137         if (val & x86_spec_ctrl_mask)
 138                 WARN_ONCE(1, "SPEC_CTRL MSR value 0x%16llx is unknown.\n", val);
 139         else
 140                 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base | val);
 141 }
 142 EXPORT_SYMBOL_GPL(x86_spec_ctrl_set);
 143
 144 u64 x86_spec_ctrl_get_default(void)
 145 {
 146         u64 msrval = x86_spec_ctrl_base;
 147
 148         if (static_cpu_has(X86_FEATURE_SPEC_CTRL))
 149                 msrval |= ssbd_tif_to_spec_ctrl(current_thread_info()->flags);
 150         return msrval;
 151 }
 152 EXPORT_SYMBOL_GPL(x86_spec_ctrl_get_default);
 153
 154 void
 155 x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest)
 156 {
 157         struct thread_info *ti = current_thread_info();
 158         u64 msr, host = x86_spec_ctrl_base;
 159
 160         /* Is MSR_SPEC_CTRL implemented ? */
 161         if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) {
 162                 /* SSBD controlled in MSR_SPEC_CTRL */
 163                 if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD))
 164                         host |= ssbd_tif_to_spec_ctrl(ti->flags);
 165
 166                 if (host != guest_spec_ctrl) {
 167                         msr = setguest ? guest_spec_ctrl : host;
 168                         wrmsrl(MSR_IA32_SPEC_CTRL, msr);
 169                 }
 170         }
 171 }
 172 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl);
 173
 174 static void x86_amd_ssb_disable(void)
 175 {
 176         u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask;
 177
 178         if (boot_cpu_has(X86_FEATURE_VIRT_SSBD))
 179                 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD);
 180         else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))
 181                 wrmsrl(MSR_AMD64_LS_CFG, msrval);
 182 }
 183
 184 #ifdef RETPOLINE
 185 static bool spectre_v2_bad_module;
 186
 187 bool retpoline_module_ok(bool has_retpoline)
 188 {
 189         if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline)
 190                 return true;
 191
 192         pr_err("System may be vulnerable to spectre v2\n");
 193         spectre_v2_bad_module = true;
 194         return false;
 195 }
 196
 197 static inline const char *spectre_v2_module_string(void)
 198 {
 199         return spectre_v2_bad_module ? " - vulnerable module loaded" : "";
 200 }
 201 #else
 202 static inline const char *spectre_v2_module_string(void) { return ""; }
 203 #endif
 204
 205 static void __init spec2_print_if_insecure(const char *reason)
 206 {
 207         if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
 208                 pr_info("%s selected on command line.\n", reason);
 209 }
 210
 211 static void __init spec2_print_if_secure(const char *reason)
 212 {
 213         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
 214                 pr_info("%s selected on command line.\n", reason);
 215 }
 216
 217 static inline bool retp_compiler(void)
 218 {
 219         return __is_defined(RETPOLINE);
 220 }
 221
 222 static inline bool match_option(const char *arg, int arglen, const char *opt)
 223 {
 224         int len = strlen(opt);
 225
 226         return len == arglen && !strncmp(arg, opt, len);
 227 }
 228
 229 static const struct {
 230         const char *option;
 231         enum spectre_v2_mitigation_cmd cmd;
 232         bool secure;
 233 } mitigation_options[] = {
 234         { "off",               SPECTRE_V2_CMD_NONE,              false },
 235         { "on",                SPECTRE_V2_CMD_FORCE,             true },
 236         { "retpoline",         SPECTRE_V2_CMD_RETPOLINE,         false },
 237         { "retpoline,amd",     SPECTRE_V2_CMD_RETPOLINE_AMD,     false },
 238         { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false },
 239         { "auto",              SPECTRE_V2_CMD_AUTO,              false },
 240 };
 241
 242 static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
 243 {
 244         char arg[20];
 245         int ret, i;
 246         enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO;
 247
 248         if (cmdline_find_option_bool(boot_command_line, "nospectre_v2"))
 249                 return SPECTRE_V2_CMD_NONE;
 250         else {
 251                 ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg));
 252                 if (ret < 0)
 253                         return SPECTRE_V2_CMD_AUTO;
 254
 255                 for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) {
 256                         if (!match_option(arg, ret, mitigation_options[i].option))
 257                                 continue;
 258                         cmd = mitigation_options[i].cmd;
 259                         break;
 260                 }
 261
 262                 if (i >= ARRAY_SIZE(mitigation_options)) {
 263                         pr_err("unknown option (%s). Switching to AUTO select\n", arg);
 264                         return SPECTRE_V2_CMD_AUTO;
 265                 }
 266         }
 267
 268         if ((cmd == SPECTRE_V2_CMD_RETPOLINE ||
 269              cmd == SPECTRE_V2_CMD_RETPOLINE_AMD ||
 270              cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) &&
 271             !IS_ENABLED(CONFIG_RETPOLINE)) {
 272                 pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option);
 273                 return SPECTRE_V2_CMD_AUTO;
 274         }
 275
 276         if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD &&
 277             boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
 278                 pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n");
 279                 return SPECTRE_V2_CMD_AUTO;
 280         }
 281
 282         if (mitigation_options[i].secure)
 283                 spec2_print_if_secure(mitigation_options[i].option);
 284         else
 285                 spec2_print_if_insecure(mitigation_options[i].option);
 286
 287         return cmd;
 288 }
 289
 290 /* Check for Skylake-like CPUs (for RSB handling) */
 291 static bool __init is_skylake_era(void)
 292 {
 293         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
 294             boot_cpu_data.x86 == 6) {
 295                 switch (boot_cpu_data.x86_model) {
 296                 case INTEL_FAM6_SKYLAKE_MOBILE:
 297                 case INTEL_FAM6_SKYLAKE_DESKTOP:
 298                 case INTEL_FAM6_SKYLAKE_X:
 299                 case INTEL_FAM6_KABYLAKE_MOBILE:
 300                 case INTEL_FAM6_KABYLAKE_DESKTOP:
 301                         return true;
 302                 }
 303         }
 304         return false;
 305 }
 306
 307 static void __init spectre_v2_select_mitigation(void)
 308 {
 309         enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
 310         enum spectre_v2_mitigation mode = SPECTRE_V2_NONE;
 311
 312         /*
 313          * If the CPU is not affected and the command line mode is NONE or AUTO
 314          * then nothing to do.
 315          */
 316         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) &&
 317             (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO))
 318                 return;
 319
 320         switch (cmd) {
 321         case SPECTRE_V2_CMD_NONE:
 322                 return;
 323
 324         case SPECTRE_V2_CMD_FORCE:
 325         case SPECTRE_V2_CMD_AUTO:
 326                 if (IS_ENABLED(CONFIG_RETPOLINE))
 327                         goto retpoline_auto;
 328                 break;
 329         case SPECTRE_V2_CMD_RETPOLINE_AMD:
 330                 if (IS_ENABLED(CONFIG_RETPOLINE))
 331                         goto retpoline_amd;
 332                 break;
 333         case SPECTRE_V2_CMD_RETPOLINE_GENERIC:
 334                 if (IS_ENABLED(CONFIG_RETPOLINE))
 335                         goto retpoline_generic;
 336                 break;
 337         case SPECTRE_V2_CMD_RETPOLINE:
 338                 if (IS_ENABLED(CONFIG_RETPOLINE))
 339                         goto retpoline_auto;
 340                 break;
 341         }
 342         pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!");
 343         return;
 344
 345 retpoline_auto:
 346         if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
 347         retpoline_amd:
 348                 if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
 349                         pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n");
 350                         goto retpoline_generic;
 351                 }
 352                 mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_AMD :
 353                                          SPECTRE_V2_RETPOLINE_MINIMAL_AMD;
 354                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD);
 355                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
 356         } else {
 357         retpoline_generic:
 358                 mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_GENERIC :
 359                                          SPECTRE_V2_RETPOLINE_MINIMAL;
 360                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
 361         }
 362
 363         spectre_v2_enabled = mode;
 364         pr_info("%s\n", spectre_v2_strings[mode]);
 365
 366         /*
 367          * If neither SMEP nor PTI are available, there is a risk of
 368          * hitting userspace addresses in the RSB after a context switch
 369          * from a shallow call stack to a deeper one. To prevent this fill
 370          * the entire RSB, even when using IBRS.
 371          *
 372          * Skylake era CPUs have a separate issue with *underflow* of the
 373          * RSB, when they will predict 'ret' targets from the generic BTB.
 374          * The proper mitigation for this is IBRS. If IBRS is not supported
 375          * or deactivated in favour of retpolines the RSB fill on context
 376          * switch is required.
 377          */
 378         if ((!boot_cpu_has(X86_FEATURE_PTI) &&
 379              !boot_cpu_has(X86_FEATURE_SMEP)) || is_skylake_era()) {
 380                 setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
 381                 pr_info("Spectre v2 mitigation: Filling RSB on context switch\n");
 382         }
 383
 384         /* Initialize Indirect Branch Prediction Barrier if supported */
 385         if (boot_cpu_has(X86_FEATURE_IBPB)) {
 386                 setup_force_cpu_cap(X86_FEATURE_USE_IBPB);
 387                 pr_info("Spectre v2 mitigation: Enabling Indirect Branch Prediction Barrier\n");
 388         }
 389
 390         /*
 391          * Retpoline means the kernel is safe because it has no indirect
 392          * branches. But firmware isn't, so use IBRS to protect that.
 393          */
 394         if (boot_cpu_has(X86_FEATURE_IBRS)) {
 395                 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW);
 396                 pr_info("Enabling Restricted Speculation for firmware calls\n");
 397         }
 398 }
 399
 400 #undef pr_fmt
 401 #define pr_fmt(fmt)     "Speculative Store Bypass: " fmt
 402
 403 static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE;
 404
 405 /* The kernel command line selection */
 406 enum ssb_mitigation_cmd {
 407         SPEC_STORE_BYPASS_CMD_NONE,
 408         SPEC_STORE_BYPASS_CMD_AUTO,
 409         SPEC_STORE_BYPASS_CMD_ON,
 410         SPEC_STORE_BYPASS_CMD_PRCTL,
 411         SPEC_STORE_BYPASS_CMD_SECCOMP,
 412 };
 413
 414 static const char *ssb_strings[] = {
 415         [SPEC_STORE_BYPASS_NONE]        = "Vulnerable",
 416         [SPEC_STORE_BYPASS_DISABLE]     = "Mitigation: Speculative Store Bypass disabled",
 417         [SPEC_STORE_BYPASS_PRCTL]       = "Mitigation: Speculative Store Bypass disabled via prctl",
 418         [SPEC_STORE_BYPASS_SECCOMP]     = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
 419 };
 420
 421 static const struct {
 422         const char *option;
 423         enum ssb_mitigation_cmd cmd;
 424 } ssb_mitigation_options[] = {
 425         { "auto",       SPEC_STORE_BYPASS_CMD_AUTO },    /* Platform decides */
 426         { "on",         SPEC_STORE_BYPASS_CMD_ON },      /* Disable Speculative Store Bypass */
 427         { "off",        SPEC_STORE_BYPASS_CMD_NONE },    /* Don't touch Speculative Store Bypass */
 428         { "prctl",      SPEC_STORE_BYPASS_CMD_PRCTL },   /* Disable Speculative Store Bypass via prctl */
 429         { "seccomp",    SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */
 430 };
 431
 432 static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void)
 433 {
 434         enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO;
 435         char arg[20];
 436         int ret, i;
 437
 438         if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable")) {
 439                 return SPEC_STORE_BYPASS_CMD_NONE;
 440         } else {
 441                 ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable",
 442                                           arg, sizeof(arg));
 443                 if (ret < 0)
 444                         return SPEC_STORE_BYPASS_CMD_AUTO;
 445
 446                 for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) {
 447                         if (!match_option(arg, ret, ssb_mitigation_options[i].option))
 448                                 continue;
 449
 450                         cmd = ssb_mitigation_options[i].cmd;
 451                         break;
 452                 }
 453
 454                 if (i >= ARRAY_SIZE(ssb_mitigation_options)) {
 455                         pr_err("unknown option (%s). Switching to AUTO select\n", arg);
 456                         return SPEC_STORE_BYPASS_CMD_AUTO;
 457                 }
 458         }
 459
 460         return cmd;
 461 }
 462
 463 static enum ssb_mitigation __init __ssb_select_mitigation(void)
 464 {
 465         enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE;
 466         enum ssb_mitigation_cmd cmd;
 467
 468         if (!boot_cpu_has(X86_FEATURE_SSBD))
 469                 return mode;
 470
 471         cmd = ssb_parse_cmdline();
 472         if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) &&
 473             (cmd == SPEC_STORE_BYPASS_CMD_NONE ||
 474              cmd == SPEC_STORE_BYPASS_CMD_AUTO))
 475                 return mode;
 476
 477         switch (cmd) {
 478         case SPEC_STORE_BYPASS_CMD_AUTO:
 479         case SPEC_STORE_BYPASS_CMD_SECCOMP:
 480                 /*
 481                  * Choose prctl+seccomp as the default mode if seccomp is
 482                  * enabled.
 483                  */
 484                 if (IS_ENABLED(CONFIG_SECCOMP))
 485                         mode = SPEC_STORE_BYPASS_SECCOMP;
 486                 else
 487                         mode = SPEC_STORE_BYPASS_PRCTL;
 488                 break;
 489         case SPEC_STORE_BYPASS_CMD_ON:
 490                 mode = SPEC_STORE_BYPASS_DISABLE;
 491                 break;
 492         case SPEC_STORE_BYPASS_CMD_PRCTL:
 493                 mode = SPEC_STORE_BYPASS_PRCTL;
 494                 break;
 495         case SPEC_STORE_BYPASS_CMD_NONE:
 496                 break;
 497         }
 498
 499         /*
 500          * We have three CPU feature flags that are in play here:
 501          *  - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
 502          *  - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
 503          *  - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
 504          */
 505         if (mode == SPEC_STORE_BYPASS_DISABLE) {
 506                 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE);
 507                 /*
 508                  * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD uses
 509                  * a completely different MSR and bit dependent on family.
 510                  */
 511                 switch (boot_cpu_data.x86_vendor) {
 512                 case X86_VENDOR_INTEL:
 513                         x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
 514                         x86_spec_ctrl_mask &= ~SPEC_CTRL_SSBD;
 515                         x86_spec_ctrl_set(SPEC_CTRL_SSBD);
 516                         break;
 517                 case X86_VENDOR_AMD:
 518                         x86_amd_ssb_disable();
 519                         break;
 520                 }
 521         }
 522
 523         return mode;
 524 }
 525
 526 static void ssb_select_mitigation(void)
 527 {
 528         ssb_mode = __ssb_select_mitigation();
 529
 530         if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
 531                 pr_info("%s\n", ssb_strings[ssb_mode]);
 532 }
 533
 534 #undef pr_fmt
 535 #define pr_fmt(fmt)     "Speculation prctl: " fmt
 536
 537 static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl)
 538 {
 539         bool update;
 540
 541         if (ssb_mode != SPEC_STORE_BYPASS_PRCTL &&
 542             ssb_mode != SPEC_STORE_BYPASS_SECCOMP)
 543                 return -ENXIO;
 544
 545         switch (ctrl) {
 546         case PR_SPEC_ENABLE:
 547                 /* If speculation is force disabled, enable is not allowed */
 548                 if (task_spec_ssb_force_disable(task))
 549                         return -EPERM;
 550                 task_clear_spec_ssb_disable(task);
 551                 update = test_and_clear_tsk_thread_flag(task, TIF_SSBD);
 552                 break;
 553         case PR_SPEC_DISABLE:
 554                 task_set_spec_ssb_disable(task);
 555                 update = !test_and_set_tsk_thread_flag(task, TIF_SSBD);
 556                 break;
 557         case PR_SPEC_FORCE_DISABLE:
 558                 task_set_spec_ssb_disable(task);
 559                 task_set_spec_ssb_force_disable(task);
 560                 update = !test_and_set_tsk_thread_flag(task, TIF_SSBD);
 561                 break;
 562         default:
 563                 return -ERANGE;
 564         }
 565
 566         /*
 567          * If being set on non-current task, delay setting the CPU
 568          * mitigation until it is next scheduled.
 569          */
 570         if (task == current && update)
 571                 speculative_store_bypass_update_current();
 572
 573         return 0;
 574 }
 575
 576 int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which,
 577                              unsigned long ctrl)
 578 {
 579         switch (which) {
 580         case PR_SPEC_STORE_BYPASS:
 581                 return ssb_prctl_set(task, ctrl);
 582         default:
 583                 return -ENODEV;
 584         }
 585 }
 586
 587 #ifdef CONFIG_SECCOMP
 588 void arch_seccomp_spec_mitigate(struct task_struct *task)
 589 {
 590         if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP)
 591                 ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE);
 592 }
 593 #endif
 594
 595 static int ssb_prctl_get(struct task_struct *task)
 596 {
 597         switch (ssb_mode) {
 598         case SPEC_STORE_BYPASS_DISABLE:
 599                 return PR_SPEC_DISABLE;
 600         case SPEC_STORE_BYPASS_SECCOMP:
 601         case SPEC_STORE_BYPASS_PRCTL:
 602                 if (task_spec_ssb_force_disable(task))
 603                         return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
 604                 if (task_spec_ssb_disable(task))
 605                         return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
 606                 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
 607         default:
 608                 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
 609                         return PR_SPEC_ENABLE;
 610                 return PR_SPEC_NOT_AFFECTED;
 611         }
 612 }
 613
 614 int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
 615 {
 616         switch (which) {
 617         case PR_SPEC_STORE_BYPASS:
 618                 return ssb_prctl_get(task);
 619         default:
 620                 return -ENODEV;
 621         }
 622 }
 623
 624 void x86_spec_ctrl_setup_ap(void)
 625 {
 626         if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
 627                 x86_spec_ctrl_set(x86_spec_ctrl_base & ~x86_spec_ctrl_mask);
 628
 629         if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
 630                 x86_amd_ssb_disable();
 631 }
 632
 633 #ifdef CONFIG_SYSFS
 634
 635 static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr,
 636                                char *buf, unsigned int bug)
 637 {
 638         if (!boot_cpu_has_bug(bug))
 639                 return sprintf(buf, "Not affected\n");
 640
 641         switch (bug) {
 642         case X86_BUG_CPU_MELTDOWN:
 643                 if (boot_cpu_has(X86_FEATURE_PTI))
 644                         return sprintf(buf, "Mitigation: PTI\n");
 645
 646                 break;
 647
 648         case X86_BUG_SPECTRE_V1:
 649                 return sprintf(buf, "Mitigation: __user pointer sanitization\n");
 650
 651         case X86_BUG_SPECTRE_V2:
 652                 return sprintf(buf, "%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled],
 653                                boot_cpu_has(X86_FEATURE_USE_IBPB) ? ", IBPB" : "",
 654                                boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "",
 655                                spectre_v2_module_string());
 656
 657         case X86_BUG_SPEC_STORE_BYPASS:
 658                 return sprintf(buf, "%s\n", ssb_strings[ssb_mode]);
 659
 660         default:
 661                 break;
 662         }
 663
 664         return sprintf(buf, "Vulnerable\n");
 665 }
 666
 667 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf)
 668 {
 669         return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN);
 670 }
 671
 672 ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf)
 673 {
 674         return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1);
 675 }
 676
 677 ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf)
 678 {
 679         return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2);
 680 }
 681
 682 ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf)
 683 {
 684         return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS);
 685 }
 686 #endif