arch/x86/kernel/cpu/bugs.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *  Copyright (C) 1994  Linus Torvalds
   4  *
   5  *  Cyrix stuff, June 1998 by:
   6  *      - Rafael R. Reilova (moved everything from head.S),
   7  *        <rreilova@ececs.uc.edu>
   8  *      - Channing Corn (tests & fixes),
   9  *      - Andrew D. Balsa (code cleanup).
  10  */
  11 #include <linux/init.h>
  12 #include <linux/utsname.h>
  13 #include <linux/cpu.h>
  14 #include <linux/module.h>
  15 #include <linux/nospec.h>
  16 #include <linux/prctl.h>
  17
  18 #include <asm/spec-ctrl.h>
  19 #include <asm/cmdline.h>
  20 #include <asm/bugs.h>
  21 #include <asm/processor.h>
  22 #include <asm/processor-flags.h>
  23 #include <asm/fpu/internal.h>
  24 #include <asm/msr.h>
  25 #include <asm/vmx.h>
  26 #include <asm/paravirt.h>
  27 #include <asm/alternative.h>
  28 #include <asm/pgtable.h>
  29 #include <asm/set_memory.h>
  30 #include <asm/intel-family.h>
  31 #include <asm/e820/api.h>
  32
  33 static void __init spectre_v2_select_mitigation(void);
  34 static void __init ssb_select_mitigation(void);
  35 static void __init l1tf_select_mitigation(void);
  36
  37 /*
  38  * Our boot-time value of the SPEC_CTRL MSR. We read it once so that any
  39  * writes to SPEC_CTRL contain whatever reserved bits have been set.
  40  */
  41 u64 __ro_after_init x86_spec_ctrl_base;
  42 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base);
  43
  44 /*
  45  * The vendor and possibly platform specific bits which can be modified in
  46  * x86_spec_ctrl_base.
  47  */
  48 static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS;
  49
  50 /*
  51  * AMD specific MSR info for Speculative Store Bypass control.
  52  * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
  53  */
  54 u64 __ro_after_init x86_amd_ls_cfg_base;
  55 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask;
  56
  57 void __init check_bugs(void)
  58 {
  59         identify_boot_cpu();
  60
  61         /*
  62          * identify_boot_cpu() initialized SMT support information, let the
  63          * core code know.
  64          */
  65         cpu_smt_check_topology();
  66
  67         if (!IS_ENABLED(CONFIG_SMP)) {
  68                 pr_info("CPU: ");
  69                 print_cpu_info(&boot_cpu_data);
  70         }
  71
  72         /*
  73          * Read the SPEC_CTRL MSR to account for reserved bits which may
  74          * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
  75          * init code as it is not enumerated and depends on the family.
  76          */
  77         if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
  78                 rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
  79
  80         /* Allow STIBP in MSR_SPEC_CTRL if supported */
  81         if (boot_cpu_has(X86_FEATURE_STIBP))
  82                 x86_spec_ctrl_mask |= SPEC_CTRL_STIBP;
  83
  84         /* Select the proper spectre mitigation before patching alternatives */
  85         spectre_v2_select_mitigation();
  86
  87         /*
  88          * Select proper mitigation for any exposure to the Speculative Store
  89          * Bypass vulnerability.
  90          */
  91         ssb_select_mitigation();
  92
  93         l1tf_select_mitigation();
  94
  95 #ifdef CONFIG_X86_32
  96         /*
  97          * Check whether we are able to run this kernel safely on SMP.
  98          *
  99          * - i386 is no longer supported.
 100          * - In order to run on anything without a TSC, we need to be
 101          *   compiled for a i486.
 102          */
 103         if (boot_cpu_data.x86 < 4)
 104                 panic("Kernel requires i486+ for 'invlpg' and other features");
 105
 106         init_utsname()->machine[1] =
 107                 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
 108         alternative_instructions();
 109
 110         fpu__init_check_bugs();
 111 #else /* CONFIG_X86_64 */
 112         alternative_instructions();
 113
 114         /*
 115          * Make sure the first 2MB area is not mapped by huge pages
 116          * There are typically fixed size MTRRs in there and overlapping
 117          * MTRRs into large pages causes slow downs.
 118          *
 119          * Right now we don't do that with gbpages because there seems
 120          * very little benefit for that case.
 121          */
 122         if (!direct_gbpages)
 123                 set_memory_4k((unsigned long)__va(0), 1);
 124 #endif
 125 }
 126
 127 /* The kernel command line selection */
 128 enum spectre_v2_mitigation_cmd {
 129         SPECTRE_V2_CMD_NONE,
 130         SPECTRE_V2_CMD_AUTO,
 131         SPECTRE_V2_CMD_FORCE,
 132         SPECTRE_V2_CMD_RETPOLINE,
 133         SPECTRE_V2_CMD_RETPOLINE_GENERIC,
 134         SPECTRE_V2_CMD_RETPOLINE_AMD,
 135 };
 136
 137 static const char *spectre_v2_strings[] = {
 138         [SPECTRE_V2_NONE]                       = "Vulnerable",
 139         [SPECTRE_V2_RETPOLINE_MINIMAL]          = "Vulnerable: Minimal generic ASM retpoline",
 140         [SPECTRE_V2_RETPOLINE_MINIMAL_AMD]      = "Vulnerable: Minimal AMD ASM retpoline",
 141         [SPECTRE_V2_RETPOLINE_GENERIC]          = "Mitigation: Full generic retpoline",
 142         [SPECTRE_V2_RETPOLINE_AMD]              = "Mitigation: Full AMD retpoline",
 143 };
 144
 145 #undef pr_fmt
 146 #define pr_fmt(fmt)     "Spectre V2 : " fmt
 147
 148 static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init =
 149         SPECTRE_V2_NONE;
 150
 151 void
 152 x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest)
 153 {
 154         u64 msrval, guestval, hostval = x86_spec_ctrl_base;
 155         struct thread_info *ti = current_thread_info();
 156
 157         /* Is MSR_SPEC_CTRL implemented ? */
 158         if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) {
 159                 /*
 160                  * Restrict guest_spec_ctrl to supported values. Clear the
 161                  * modifiable bits in the host base value and or the
 162                  * modifiable bits from the guest value.
 163                  */
 164                 guestval = hostval & ~x86_spec_ctrl_mask;
 165                 guestval |= guest_spec_ctrl & x86_spec_ctrl_mask;
 166
 167                 /* SSBD controlled in MSR_SPEC_CTRL */
 168                 if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD))
 169                         hostval |= ssbd_tif_to_spec_ctrl(ti->flags);
 170
 171                 if (hostval != guestval) {
 172                         msrval = setguest ? guestval : hostval;
 173                         wrmsrl(MSR_IA32_SPEC_CTRL, msrval);
 174                 }
 175         }
 176
 177         /*
 178          * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
 179          * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
 180          */
 181         if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
 182             !static_cpu_has(X86_FEATURE_VIRT_SSBD))
 183                 return;
 184
 185         /*
 186          * If the host has SSBD mitigation enabled, force it in the host's
 187          * virtual MSR value. If its not permanently enabled, evaluate
 188          * current's TIF_SSBD thread flag.
 189          */
 190         if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE))
 191                 hostval = SPEC_CTRL_SSBD;
 192         else
 193                 hostval = ssbd_tif_to_spec_ctrl(ti->flags);
 194
 195         /* Sanitize the guest value */
 196         guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD;
 197
 198         if (hostval != guestval) {
 199                 unsigned long tif;
 200
 201                 tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) :
 202                                  ssbd_spec_ctrl_to_tif(hostval);
 203
 204                 speculative_store_bypass_update(tif);
 205         }
 206 }
 207 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl);
 208
 209 static void x86_amd_ssb_disable(void)
 210 {
 211         u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask;
 212
 213         if (boot_cpu_has(X86_FEATURE_VIRT_SSBD))
 214                 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD);
 215         else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))
 216                 wrmsrl(MSR_AMD64_LS_CFG, msrval);
 217 }
 218
 219 #ifdef RETPOLINE
 220 static bool spectre_v2_bad_module;
 221
 222 bool retpoline_module_ok(bool has_retpoline)
 223 {
 224         if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline)
 225                 return true;
 226
 227         pr_err("System may be vulnerable to spectre v2\n");
 228         spectre_v2_bad_module = true;
 229         return false;
 230 }
 231
 232 static inline const char *spectre_v2_module_string(void)
 233 {
 234         return spectre_v2_bad_module ? " - vulnerable module loaded" : "";
 235 }
 236 #else
 237 static inline const char *spectre_v2_module_string(void) { return ""; }
 238 #endif
 239
 240 static void __init spec2_print_if_insecure(const char *reason)
 241 {
 242         if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
 243                 pr_info("%s selected on command line.\n", reason);
 244 }
 245
 246 static void __init spec2_print_if_secure(const char *reason)
 247 {
 248         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
 249                 pr_info("%s selected on command line.\n", reason);
 250 }
 251
 252 static inline bool retp_compiler(void)
 253 {
 254         return __is_defined(RETPOLINE);
 255 }
 256
 257 static inline bool match_option(const char *arg, int arglen, const char *opt)
 258 {
 259         int len = strlen(opt);
 260
 261         return len == arglen && !strncmp(arg, opt, len);
 262 }
 263
 264 static const struct {
 265         const char *option;
 266         enum spectre_v2_mitigation_cmd cmd;
 267         bool secure;
 268 } mitigation_options[] = {
 269         { "off",               SPECTRE_V2_CMD_NONE,              false },
 270         { "on",                SPECTRE_V2_CMD_FORCE,             true },
 271         { "retpoline",         SPECTRE_V2_CMD_RETPOLINE,         false },
 272         { "retpoline,amd",     SPECTRE_V2_CMD_RETPOLINE_AMD,     false },
 273         { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false },
 274         { "auto",              SPECTRE_V2_CMD_AUTO,              false },
 275 };
 276
 277 static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
 278 {
 279         char arg[20];
 280         int ret, i;
 281         enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO;
 282
 283         if (cmdline_find_option_bool(boot_command_line, "nospectre_v2"))
 284                 return SPECTRE_V2_CMD_NONE;
 285         else {
 286                 ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg));
 287                 if (ret < 0)
 288                         return SPECTRE_V2_CMD_AUTO;
 289
 290                 for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) {
 291                         if (!match_option(arg, ret, mitigation_options[i].option))
 292                                 continue;
 293                         cmd = mitigation_options[i].cmd;
 294                         break;
 295                 }
 296
 297                 if (i >= ARRAY_SIZE(mitigation_options)) {
 298                         pr_err("unknown option (%s). Switching to AUTO select\n", arg);
 299                         return SPECTRE_V2_CMD_AUTO;
 300                 }
 301         }
 302
 303         if ((cmd == SPECTRE_V2_CMD_RETPOLINE ||
 304              cmd == SPECTRE_V2_CMD_RETPOLINE_AMD ||
 305              cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) &&
 306             !IS_ENABLED(CONFIG_RETPOLINE)) {
 307                 pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option);
 308                 return SPECTRE_V2_CMD_AUTO;
 309         }
 310
 311         if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD &&
 312             boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
 313                 pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n");
 314                 return SPECTRE_V2_CMD_AUTO;
 315         }
 316
 317         if (mitigation_options[i].secure)
 318                 spec2_print_if_secure(mitigation_options[i].option);
 319         else
 320                 spec2_print_if_insecure(mitigation_options[i].option);
 321
 322         return cmd;
 323 }
 324
 325 /* Check for Skylake-like CPUs (for RSB handling) */
 326 static bool __init is_skylake_era(void)
 327 {
 328         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
 329             boot_cpu_data.x86 == 6) {
 330                 switch (boot_cpu_data.x86_model) {
 331                 case INTEL_FAM6_SKYLAKE_MOBILE:
 332                 case INTEL_FAM6_SKYLAKE_DESKTOP:
 333                 case INTEL_FAM6_SKYLAKE_X:
 334                 case INTEL_FAM6_KABYLAKE_MOBILE:
 335                 case INTEL_FAM6_KABYLAKE_DESKTOP:
 336                         return true;
 337                 }
 338         }
 339         return false;
 340 }
 341
 342 static void __init spectre_v2_select_mitigation(void)
 343 {
 344         enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
 345         enum spectre_v2_mitigation mode = SPECTRE_V2_NONE;
 346
 347         /*
 348          * If the CPU is not affected and the command line mode is NONE or AUTO
 349          * then nothing to do.
 350          */
 351         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) &&
 352             (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO))
 353                 return;
 354
 355         switch (cmd) {
 356         case SPECTRE_V2_CMD_NONE:
 357                 return;
 358
 359         case SPECTRE_V2_CMD_FORCE:
 360         case SPECTRE_V2_CMD_AUTO:
 361                 if (IS_ENABLED(CONFIG_RETPOLINE))
 362                         goto retpoline_auto;
 363                 break;
 364         case SPECTRE_V2_CMD_RETPOLINE_AMD:
 365                 if (IS_ENABLED(CONFIG_RETPOLINE))
 366                         goto retpoline_amd;
 367                 break;
 368         case SPECTRE_V2_CMD_RETPOLINE_GENERIC:
 369                 if (IS_ENABLED(CONFIG_RETPOLINE))
 370                         goto retpoline_generic;
 371                 break;
 372         case SPECTRE_V2_CMD_RETPOLINE:
 373                 if (IS_ENABLED(CONFIG_RETPOLINE))
 374                         goto retpoline_auto;
 375                 break;
 376         }
 377         pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!");
 378         return;
 379
 380 retpoline_auto:
 381         if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
 382         retpoline_amd:
 383                 if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
 384                         pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n");
 385                         goto retpoline_generic;
 386                 }
 387                 mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_AMD :
 388                                          SPECTRE_V2_RETPOLINE_MINIMAL_AMD;
 389                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD);
 390                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
 391         } else {
 392         retpoline_generic:
 393                 mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_GENERIC :
 394                                          SPECTRE_V2_RETPOLINE_MINIMAL;
 395                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
 396         }
 397
 398         spectre_v2_enabled = mode;
 399         pr_info("%s\n", spectre_v2_strings[mode]);
 400
 401         /*
 402          * If neither SMEP nor PTI are available, there is a risk of
 403          * hitting userspace addresses in the RSB after a context switch
 404          * from a shallow call stack to a deeper one. To prevent this fill
 405          * the entire RSB, even when using IBRS.
 406          *
 407          * Skylake era CPUs have a separate issue with *underflow* of the
 408          * RSB, when they will predict 'ret' targets from the generic BTB.
 409          * The proper mitigation for this is IBRS. If IBRS is not supported
 410          * or deactivated in favour of retpolines the RSB fill on context
 411          * switch is required.
 412          */
 413         if ((!boot_cpu_has(X86_FEATURE_PTI) &&
 414              !boot_cpu_has(X86_FEATURE_SMEP)) || is_skylake_era()) {
 415                 setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
 416                 pr_info("Spectre v2 mitigation: Filling RSB on context switch\n");
 417         }
 418
 419         /* Initialize Indirect Branch Prediction Barrier if supported */
 420         if (boot_cpu_has(X86_FEATURE_IBPB)) {
 421                 setup_force_cpu_cap(X86_FEATURE_USE_IBPB);
 422                 pr_info("Spectre v2 mitigation: Enabling Indirect Branch Prediction Barrier\n");
 423         }
 424
 425         /*
 426          * Retpoline means the kernel is safe because it has no indirect
 427          * branches. But firmware isn't, so use IBRS to protect that.
 428          */
 429         if (boot_cpu_has(X86_FEATURE_IBRS)) {
 430                 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW);
 431                 pr_info("Enabling Restricted Speculation for firmware calls\n");
 432         }
 433 }
 434
 435 #undef pr_fmt
 436 #define pr_fmt(fmt)     "Speculative Store Bypass: " fmt
 437
 438 static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE;
 439
 440 /* The kernel command line selection */
 441 enum ssb_mitigation_cmd {
 442         SPEC_STORE_BYPASS_CMD_NONE,
 443         SPEC_STORE_BYPASS_CMD_AUTO,
 444         SPEC_STORE_BYPASS_CMD_ON,
 445         SPEC_STORE_BYPASS_CMD_PRCTL,
 446         SPEC_STORE_BYPASS_CMD_SECCOMP,
 447 };
 448
 449 static const char *ssb_strings[] = {
 450         [SPEC_STORE_BYPASS_NONE]        = "Vulnerable",
 451         [SPEC_STORE_BYPASS_DISABLE]     = "Mitigation: Speculative Store Bypass disabled",
 452         [SPEC_STORE_BYPASS_PRCTL]       = "Mitigation: Speculative Store Bypass disabled via prctl",
 453         [SPEC_STORE_BYPASS_SECCOMP]     = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
 454 };
 455
 456 static const struct {
 457         const char *option;
 458         enum ssb_mitigation_cmd cmd;
 459 } ssb_mitigation_options[] = {
 460         { "auto",       SPEC_STORE_BYPASS_CMD_AUTO },    /* Platform decides */
 461         { "on",         SPEC_STORE_BYPASS_CMD_ON },      /* Disable Speculative Store Bypass */
 462         { "off",        SPEC_STORE_BYPASS_CMD_NONE },    /* Don't touch Speculative Store Bypass */
 463         { "prctl",      SPEC_STORE_BYPASS_CMD_PRCTL },   /* Disable Speculative Store Bypass via prctl */
 464         { "seccomp",    SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */
 465 };
 466
 467 static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void)
 468 {
 469         enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO;
 470         char arg[20];
 471         int ret, i;
 472
 473         if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable")) {
 474                 return SPEC_STORE_BYPASS_CMD_NONE;
 475         } else {
 476                 ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable",
 477                                           arg, sizeof(arg));
 478                 if (ret < 0)
 479                         return SPEC_STORE_BYPASS_CMD_AUTO;
 480
 481                 for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) {
 482                         if (!match_option(arg, ret, ssb_mitigation_options[i].option))
 483                                 continue;
 484
 485                         cmd = ssb_mitigation_options[i].cmd;
 486                         break;
 487                 }
 488
 489                 if (i >= ARRAY_SIZE(ssb_mitigation_options)) {
 490                         pr_err("unknown option (%s). Switching to AUTO select\n", arg);
 491                         return SPEC_STORE_BYPASS_CMD_AUTO;
 492                 }
 493         }
 494
 495         return cmd;
 496 }
 497
 498 static enum ssb_mitigation __init __ssb_select_mitigation(void)
 499 {
 500         enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE;
 501         enum ssb_mitigation_cmd cmd;
 502
 503         if (!boot_cpu_has(X86_FEATURE_SSBD))
 504                 return mode;
 505
 506         cmd = ssb_parse_cmdline();
 507         if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) &&
 508             (cmd == SPEC_STORE_BYPASS_CMD_NONE ||
 509              cmd == SPEC_STORE_BYPASS_CMD_AUTO))
 510                 return mode;
 511
 512         switch (cmd) {
 513         case SPEC_STORE_BYPASS_CMD_AUTO:
 514         case SPEC_STORE_BYPASS_CMD_SECCOMP:
 515                 /*
 516                  * Choose prctl+seccomp as the default mode if seccomp is
 517                  * enabled.
 518                  */
 519                 if (IS_ENABLED(CONFIG_SECCOMP))
 520                         mode = SPEC_STORE_BYPASS_SECCOMP;
 521                 else
 522                         mode = SPEC_STORE_BYPASS_PRCTL;
 523                 break;
 524         case SPEC_STORE_BYPASS_CMD_ON:
 525                 mode = SPEC_STORE_BYPASS_DISABLE;
 526                 break;
 527         case SPEC_STORE_BYPASS_CMD_PRCTL:
 528                 mode = SPEC_STORE_BYPASS_PRCTL;
 529                 break;
 530         case SPEC_STORE_BYPASS_CMD_NONE:
 531                 break;
 532         }
 533
 534         /*
 535          * We have three CPU feature flags that are in play here:
 536          *  - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
 537          *  - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
 538          *  - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
 539          */
 540         if (mode == SPEC_STORE_BYPASS_DISABLE) {
 541                 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE);
 542                 /*
 543                  * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD uses
 544                  * a completely different MSR and bit dependent on family.
 545                  */
 546                 switch (boot_cpu_data.x86_vendor) {
 547                 case X86_VENDOR_INTEL:
 548                         x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
 549                         x86_spec_ctrl_mask |= SPEC_CTRL_SSBD;
 550                         wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
 551                         break;
 552                 case X86_VENDOR_AMD:
 553                         x86_amd_ssb_disable();
 554                         break;
 555                 }
 556         }
 557
 558         return mode;
 559 }
 560
 561 static void ssb_select_mitigation(void)
 562 {
 563         ssb_mode = __ssb_select_mitigation();
 564
 565         if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
 566                 pr_info("%s\n", ssb_strings[ssb_mode]);
 567 }
 568
 569 #undef pr_fmt
 570 #define pr_fmt(fmt)     "Speculation prctl: " fmt
 571
 572 static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl)
 573 {
 574         bool update;
 575
 576         if (ssb_mode != SPEC_STORE_BYPASS_PRCTL &&
 577             ssb_mode != SPEC_STORE_BYPASS_SECCOMP)
 578                 return -ENXIO;
 579
 580         switch (ctrl) {
 581         case PR_SPEC_ENABLE:
 582                 /* If speculation is force disabled, enable is not allowed */
 583                 if (task_spec_ssb_force_disable(task))
 584                         return -EPERM;
 585                 task_clear_spec_ssb_disable(task);
 586                 update = test_and_clear_tsk_thread_flag(task, TIF_SSBD);
 587                 break;
 588         case PR_SPEC_DISABLE:
 589                 task_set_spec_ssb_disable(task);
 590                 update = !test_and_set_tsk_thread_flag(task, TIF_SSBD);
 591                 break;
 592         case PR_SPEC_FORCE_DISABLE:
 593                 task_set_spec_ssb_disable(task);
 594                 task_set_spec_ssb_force_disable(task);
 595                 update = !test_and_set_tsk_thread_flag(task, TIF_SSBD);
 596                 break;
 597         default:
 598                 return -ERANGE;
 599         }
 600
 601         /*
 602          * If being set on non-current task, delay setting the CPU
 603          * mitigation until it is next scheduled.
 604          */
 605         if (task == current && update)
 606                 speculative_store_bypass_update_current();
 607
 608         return 0;
 609 }
 610
 611 int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which,
 612                              unsigned long ctrl)
 613 {
 614         switch (which) {
 615         case PR_SPEC_STORE_BYPASS:
 616                 return ssb_prctl_set(task, ctrl);
 617         default:
 618                 return -ENODEV;
 619         }
 620 }
 621
 622 #ifdef CONFIG_SECCOMP
 623 void arch_seccomp_spec_mitigate(struct task_struct *task)
 624 {
 625         if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP)
 626                 ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE);
 627 }
 628 #endif
 629
 630 static int ssb_prctl_get(struct task_struct *task)
 631 {
 632         switch (ssb_mode) {
 633         case SPEC_STORE_BYPASS_DISABLE:
 634                 return PR_SPEC_DISABLE;
 635         case SPEC_STORE_BYPASS_SECCOMP:
 636         case SPEC_STORE_BYPASS_PRCTL:
 637                 if (task_spec_ssb_force_disable(task))
 638                         return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
 639                 if (task_spec_ssb_disable(task))
 640                         return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
 641                 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
 642         default:
 643                 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
 644                         return PR_SPEC_ENABLE;
 645                 return PR_SPEC_NOT_AFFECTED;
 646         }
 647 }
 648
 649 int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
 650 {
 651         switch (which) {
 652         case PR_SPEC_STORE_BYPASS:
 653                 return ssb_prctl_get(task);
 654         default:
 655                 return -ENODEV;
 656         }
 657 }
 658
 659 void x86_spec_ctrl_setup_ap(void)
 660 {
 661         if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
 662                 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
 663
 664         if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
 665                 x86_amd_ssb_disable();
 666 }
 667
 668 #undef pr_fmt
 669 #define pr_fmt(fmt)     "L1TF: " fmt
 670
 671 /* Default mitigation for L1TF-affected CPUs */
 672 enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH;
 673 #if IS_ENABLED(CONFIG_KVM_INTEL)
 674 EXPORT_SYMBOL_GPL(l1tf_mitigation);
 675
 676 enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
 677 EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation);
 678 #endif
 679
 680 static void __init l1tf_select_mitigation(void)
 681 {
 682         u64 half_pa;
 683
 684         if (!boot_cpu_has_bug(X86_BUG_L1TF))
 685                 return;
 686
 687         switch (l1tf_mitigation) {
 688         case L1TF_MITIGATION_OFF:
 689         case L1TF_MITIGATION_FLUSH_NOWARN:
 690         case L1TF_MITIGATION_FLUSH:
 691                 break;
 692         case L1TF_MITIGATION_FLUSH_NOSMT:
 693         case L1TF_MITIGATION_FULL:
 694                 cpu_smt_disable(false);
 695                 break;
 696         case L1TF_MITIGATION_FULL_FORCE:
 697                 cpu_smt_disable(true);
 698                 break;
 699         }
 700
 701 #if CONFIG_PGTABLE_LEVELS == 2
 702         pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n");
 703         return;
 704 #endif
 705
 706         /*
 707          * This is extremely unlikely to happen because almost all
 708          * systems have far more MAX_PA/2 than RAM can be fit into
 709          * DIMM slots.
 710          */
 711         half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT;
 712         if (e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) {
 713                 pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n");
 714                 return;
 715         }
 716
 717         setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV);
 718 }
 719
 720 static int __init l1tf_cmdline(char *str)
 721 {
 722         if (!boot_cpu_has_bug(X86_BUG_L1TF))
 723                 return 0;
 724
 725         if (!str)
 726                 return -EINVAL;
 727
 728         if (!strcmp(str, "off"))
 729                 l1tf_mitigation = L1TF_MITIGATION_OFF;
 730         else if (!strcmp(str, "flush,nowarn"))
 731                 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN;
 732         else if (!strcmp(str, "flush"))
 733                 l1tf_mitigation = L1TF_MITIGATION_FLUSH;
 734         else if (!strcmp(str, "flush,nosmt"))
 735                 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT;
 736         else if (!strcmp(str, "full"))
 737                 l1tf_mitigation = L1TF_MITIGATION_FULL;
 738         else if (!strcmp(str, "full,force"))
 739                 l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE;
 740
 741         return 0;
 742 }
 743 early_param("l1tf", l1tf_cmdline);
 744
 745 #undef pr_fmt
 746
 747 #ifdef CONFIG_SYSFS
 748
 749 #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion"
 750
 751 #if IS_ENABLED(CONFIG_KVM_INTEL)
 752 static const char *l1tf_vmx_states[] = {
 753         [VMENTER_L1D_FLUSH_AUTO]                = "auto",
 754         [VMENTER_L1D_FLUSH_NEVER]               = "vulnerable",
 755         [VMENTER_L1D_FLUSH_COND]                = "conditional cache flushes",
 756         [VMENTER_L1D_FLUSH_ALWAYS]              = "cache flushes",
 757         [VMENTER_L1D_FLUSH_EPT_DISABLED]        = "EPT disabled",
 758         [VMENTER_L1D_FLUSH_NOT_REQUIRED]        = "flush not necessary"
 759 };
 760
 761 static ssize_t l1tf_show_state(char *buf)
 762 {
 763         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO)
 764                 return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
 765
 766         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED ||
 767             (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER &&
 768              cpu_smt_control == CPU_SMT_ENABLED))
 769                 return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG,
 770                                l1tf_vmx_states[l1tf_vmx_mitigation]);
 771
 772         return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG,
 773                        l1tf_vmx_states[l1tf_vmx_mitigation],
 774                        cpu_smt_control == CPU_SMT_ENABLED ? "vulnerable" : "disabled");
 775 }
 776 #else
 777 static ssize_t l1tf_show_state(char *buf)
 778 {
 779         return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
 780 }
 781 #endif
 782
 783 static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr,
 784                                char *buf, unsigned int bug)
 785 {
 786         if (!boot_cpu_has_bug(bug))
 787                 return sprintf(buf, "Not affected\n");
 788
 789         switch (bug) {
 790         case X86_BUG_CPU_MELTDOWN:
 791                 if (boot_cpu_has(X86_FEATURE_PTI))
 792                         return sprintf(buf, "Mitigation: PTI\n");
 793
 794                 break;
 795
 796         case X86_BUG_SPECTRE_V1:
 797                 return sprintf(buf, "Mitigation: __user pointer sanitization\n");
 798
 799         case X86_BUG_SPECTRE_V2:
 800                 return sprintf(buf, "%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled],
 801                                boot_cpu_has(X86_FEATURE_USE_IBPB) ? ", IBPB" : "",
 802                                boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "",
 803                                spectre_v2_module_string());
 804
 805         case X86_BUG_SPEC_STORE_BYPASS:
 806                 return sprintf(buf, "%s\n", ssb_strings[ssb_mode]);
 807
 808         case X86_BUG_L1TF:
 809                 if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV))
 810                         return l1tf_show_state(buf);
 811                 break;
 812         default:
 813                 break;
 814         }
 815
 816         return sprintf(buf, "Vulnerable\n");
 817 }
 818
 819 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf)
 820 {
 821         return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN);
 822 }
 823
 824 ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf)
 825 {
 826         return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1);
 827 }
 828
 829 ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf)
 830 {
 831         return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2);
 832 }
 833
 834 ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf)
 835 {
 836         return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS);
 837 }
 838
 839 ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf)
 840 {
 841         return cpu_show_common(dev, attr, buf, X86_BUG_L1TF);
 842 }
 843 #endif