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1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 1994 Linus Torvalds
4 *
5 * Cyrix stuff, June 1998 by:
6 * - Rafael R. Reilova (moved everything from head.S),
7 * <rreilova@ececs.uc.edu>
8 * - Channing Corn (tests & fixes),
9 * - Andrew D. Balsa (code cleanup).
10 */
11 #include <linux/init.h>
12 #include <linux/utsname.h>
13 #include <linux/cpu.h>
14 #include <linux/module.h>
15 #include <linux/nospec.h>
16 #include <linux/prctl.h>
17
18 #include <asm/spec-ctrl.h>
19 #include <asm/cmdline.h>
20 #include <asm/bugs.h>
21 #include <asm/processor.h>
22 #include <asm/processor-flags.h>
23 #include <asm/fpu/internal.h>
24 #include <asm/msr.h>
25 #include <asm/vmx.h>
26 #include <asm/paravirt.h>
27 #include <asm/alternative.h>
28 #include <asm/pgtable.h>
29 #include <asm/set_memory.h>
30 #include <asm/intel-family.h>
31 #include <asm/e820/api.h>
32
33 static void __init spectre_v2_select_mitigation(void);
34 static void __init ssb_select_mitigation(void);
35 static void __init l1tf_select_mitigation(void);
36
37 /* The base value of the SPEC_CTRL MSR that always has to be preserved. */
38 u64 x86_spec_ctrl_base;
39 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base);
40 static DEFINE_MUTEX(spec_ctrl_mutex);
41
42 /*
43 * The vendor and possibly platform specific bits which can be modified in
44 * x86_spec_ctrl_base.
45 */
46 static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS;
47
48 /*
49 * AMD specific MSR info for Speculative Store Bypass control.
50 * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
51 */
52 u64 __ro_after_init x86_amd_ls_cfg_base;
53 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask;
54
55 void __init check_bugs(void)
56 {
57 identify_boot_cpu();
58
59 /*
60 * identify_boot_cpu() initialized SMT support information, let the
61 * core code know.
62 */
63 cpu_smt_check_topology_early();
64
65 if (!IS_ENABLED(CONFIG_SMP)) {
66 pr_info("CPU: ");
67 print_cpu_info(&boot_cpu_data);
68 }
69
70 /*
71 * Read the SPEC_CTRL MSR to account for reserved bits which may
72 * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
73 * init code as it is not enumerated and depends on the family.
74 */
75 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
76 rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
77
78 /* Allow STIBP in MSR_SPEC_CTRL if supported */
79 if (boot_cpu_has(X86_FEATURE_STIBP))
80 x86_spec_ctrl_mask |= SPEC_CTRL_STIBP;
81
82 /* Select the proper spectre mitigation before patching alternatives */
83 spectre_v2_select_mitigation();
84
85 /*
86 * Select proper mitigation for any exposure to the Speculative Store
87 * Bypass vulnerability.
88 */
89 ssb_select_mitigation();
90
91 l1tf_select_mitigation();
92
93 #ifdef CONFIG_X86_32
94 /*
95 * Check whether we are able to run this kernel safely on SMP.
96 *
97 * - i386 is no longer supported.
98 * - In order to run on anything without a TSC, we need to be
99 * compiled for a i486.
100 */
101 if (boot_cpu_data.x86 < 4)
102 panic("Kernel requires i486+ for 'invlpg' and other features");
103
104 init_utsname()->machine[1] =
105 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
106 alternative_instructions();
107
108 fpu__init_check_bugs();
109 #else /* CONFIG_X86_64 */
110 alternative_instructions();
111
112 /*
113 * Make sure the first 2MB area is not mapped by huge pages
114 * There are typically fixed size MTRRs in there and overlapping
115 * MTRRs into large pages causes slow downs.
116 *
117 * Right now we don't do that with gbpages because there seems
118 * very little benefit for that case.
119 */
120 if (!direct_gbpages)
121 set_memory_4k((unsigned long)__va(0), 1);
122 #endif
123 }
124
125 /* The kernel command line selection */
126 enum spectre_v2_mitigation_cmd {
127 SPECTRE_V2_CMD_NONE,
128 SPECTRE_V2_CMD_AUTO,
129 SPECTRE_V2_CMD_FORCE,
130 SPECTRE_V2_CMD_RETPOLINE,
131 SPECTRE_V2_CMD_RETPOLINE_GENERIC,
132 SPECTRE_V2_CMD_RETPOLINE_AMD,
133 };
134
135 static const char *spectre_v2_strings[] = {
136 [SPECTRE_V2_NONE] = "Vulnerable",
137 [SPECTRE_V2_RETPOLINE_GENERIC] = "Mitigation: Full generic retpoline",
138 [SPECTRE_V2_RETPOLINE_AMD] = "Mitigation: Full AMD retpoline",
139 [SPECTRE_V2_IBRS_ENHANCED] = "Mitigation: Enhanced IBRS",
140 };
141
142 #undef pr_fmt
143 #define pr_fmt(fmt) "Spectre V2 : " fmt
144
145 static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init =
146 SPECTRE_V2_NONE;
147
148 void
149 x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest)
150 {
151 u64 msrval, guestval, hostval = x86_spec_ctrl_base;
152 struct thread_info *ti = current_thread_info();
153
154 /* Is MSR_SPEC_CTRL implemented ? */
155 if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) {
156 /*
157 * Restrict guest_spec_ctrl to supported values. Clear the
158 * modifiable bits in the host base value and or the
159 * modifiable bits from the guest value.
160 */
161 guestval = hostval & ~x86_spec_ctrl_mask;
162 guestval |= guest_spec_ctrl & x86_spec_ctrl_mask;
163
164 /* SSBD controlled in MSR_SPEC_CTRL */
165 if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
166 static_cpu_has(X86_FEATURE_AMD_SSBD))
167 hostval |= ssbd_tif_to_spec_ctrl(ti->flags);
168
169 if (hostval != guestval) {
170 msrval = setguest ? guestval : hostval;
171 wrmsrl(MSR_IA32_SPEC_CTRL, msrval);
172 }
173 }
174
175 /*
176 * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
177 * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
178 */
179 if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
180 !static_cpu_has(X86_FEATURE_VIRT_SSBD))
181 return;
182
183 /*
184 * If the host has SSBD mitigation enabled, force it in the host's
185 * virtual MSR value. If its not permanently enabled, evaluate
186 * current's TIF_SSBD thread flag.
187 */
188 if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE))
189 hostval = SPEC_CTRL_SSBD;
190 else
191 hostval = ssbd_tif_to_spec_ctrl(ti->flags);
192
193 /* Sanitize the guest value */
194 guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD;
195
196 if (hostval != guestval) {
197 unsigned long tif;
198
199 tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) :
200 ssbd_spec_ctrl_to_tif(hostval);
201
202 speculative_store_bypass_update(tif);
203 }
204 }
205 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl);
206
207 static void x86_amd_ssb_disable(void)
208 {
209 u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask;
210
211 if (boot_cpu_has(X86_FEATURE_VIRT_SSBD))
212 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD);
213 else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))
214 wrmsrl(MSR_AMD64_LS_CFG, msrval);
215 }
216
217 #ifdef RETPOLINE
218 static bool spectre_v2_bad_module;
219
220 bool retpoline_module_ok(bool has_retpoline)
221 {
222 if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline)
223 return true;
224
225 pr_err("System may be vulnerable to spectre v2\n");
226 spectre_v2_bad_module = true;
227 return false;
228 }
229
230 static inline const char *spectre_v2_module_string(void)
231 {
232 return spectre_v2_bad_module ? " - vulnerable module loaded" : "";
233 }
234 #else
235 static inline const char *spectre_v2_module_string(void) { return ""; }
236 #endif
237
238 static void __init spec2_print_if_insecure(const char *reason)
239 {
240 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
241 pr_info("%s selected on command line.\n", reason);
242 }
243
244 static void __init spec2_print_if_secure(const char *reason)
245 {
246 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
247 pr_info("%s selected on command line.\n", reason);
248 }
249
250 static inline bool match_option(const char *arg, int arglen, const char *opt)
251 {
252 int len = strlen(opt);
253
254 return len == arglen && !strncmp(arg, opt, len);
255 }
256
257 static const struct {
258 const char *option;
259 enum spectre_v2_mitigation_cmd cmd;
260 bool secure;
261 } mitigation_options[] = {
262 { "off", SPECTRE_V2_CMD_NONE, false },
263 { "on", SPECTRE_V2_CMD_FORCE, true },
264 { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false },
265 { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD, false },
266 { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false },
267 { "auto", SPECTRE_V2_CMD_AUTO, false },
268 };
269
270 static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
271 {
272 char arg[20];
273 int ret, i;
274 enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO;
275
276 if (cmdline_find_option_bool(boot_command_line, "nospectre_v2"))
277 return SPECTRE_V2_CMD_NONE;
278
279 ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg));
280 if (ret < 0)
281 return SPECTRE_V2_CMD_AUTO;
282
283 for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) {
284 if (!match_option(arg, ret, mitigation_options[i].option))
285 continue;
286 cmd = mitigation_options[i].cmd;
287 break;
288 }
289
290 if (i >= ARRAY_SIZE(mitigation_options)) {
291 pr_err("unknown option (%s). Switching to AUTO select\n", arg);
292 return SPECTRE_V2_CMD_AUTO;
293 }
294
295 if ((cmd == SPECTRE_V2_CMD_RETPOLINE ||
296 cmd == SPECTRE_V2_CMD_RETPOLINE_AMD ||
297 cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) &&
298 !IS_ENABLED(CONFIG_RETPOLINE)) {
299 pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option);
300 return SPECTRE_V2_CMD_AUTO;
301 }
302
303 if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD &&
304 boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
305 pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n");
306 return SPECTRE_V2_CMD_AUTO;
307 }
308
309 if (mitigation_options[i].secure)
310 spec2_print_if_secure(mitigation_options[i].option);
311 else
312 spec2_print_if_insecure(mitigation_options[i].option);
313
314 return cmd;
315 }
316
317 static bool stibp_needed(void)
318 {
319 if (spectre_v2_enabled == SPECTRE_V2_NONE)
320 return false;
321
322 /* Enhanced IBRS makes using STIBP unnecessary. */
323 if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED)
324 return false;
325
326 if (!boot_cpu_has(X86_FEATURE_STIBP))
327 return false;
328
329 return true;
330 }
331
332 static void update_stibp_msr(void *info)
333 {
334 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
335 }
336
337 void arch_smt_update(void)
338 {
339 u64 mask;
340
341 if (!stibp_needed())
342 return;
343
344 mutex_lock(&spec_ctrl_mutex);
345 mask = x86_spec_ctrl_base;
346 if (cpu_smt_control == CPU_SMT_ENABLED)
347 mask |= SPEC_CTRL_STIBP;
348 else
349 mask &= ~SPEC_CTRL_STIBP;
350
351 if (mask != x86_spec_ctrl_base) {
352 pr_info("Spectre v2 cross-process SMT mitigation: %s STIBP\n",
353 cpu_smt_control == CPU_SMT_ENABLED ?
354 "Enabling" : "Disabling");
355 x86_spec_ctrl_base = mask;
356 on_each_cpu(update_stibp_msr, NULL, 1);
357 }
358 mutex_unlock(&spec_ctrl_mutex);
359 }
360
361 static void __init spectre_v2_select_mitigation(void)
362 {
363 enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
364 enum spectre_v2_mitigation mode = SPECTRE_V2_NONE;
365
366 /*
367 * If the CPU is not affected and the command line mode is NONE or AUTO
368 * then nothing to do.
369 */
370 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) &&
371 (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO))
372 return;
373
374 switch (cmd) {
375 case SPECTRE_V2_CMD_NONE:
376 return;
377
378 case SPECTRE_V2_CMD_FORCE:
379 case SPECTRE_V2_CMD_AUTO:
380 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) {
381 mode = SPECTRE_V2_IBRS_ENHANCED;
382 /* Force it so VMEXIT will restore correctly */
383 x86_spec_ctrl_base |= SPEC_CTRL_IBRS;
384 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
385 goto specv2_set_mode;
386 }
387 if (IS_ENABLED(CONFIG_RETPOLINE))
388 goto retpoline_auto;
389 break;
390 case SPECTRE_V2_CMD_RETPOLINE_AMD:
391 if (IS_ENABLED(CONFIG_RETPOLINE))
392 goto retpoline_amd;
393 break;
394 case SPECTRE_V2_CMD_RETPOLINE_GENERIC:
395 if (IS_ENABLED(CONFIG_RETPOLINE))
396 goto retpoline_generic;
397 break;
398 case SPECTRE_V2_CMD_RETPOLINE:
399 if (IS_ENABLED(CONFIG_RETPOLINE))
400 goto retpoline_auto;
401 break;
402 }
403 pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!");
404 return;
405
406 retpoline_auto:
407 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
408 retpoline_amd:
409 if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
410 pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n");
411 goto retpoline_generic;
412 }
413 mode = SPECTRE_V2_RETPOLINE_AMD;
414 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD);
415 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
416 } else {
417 retpoline_generic:
418 mode = SPECTRE_V2_RETPOLINE_GENERIC;
419 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
420 }
421
422 specv2_set_mode:
423 spectre_v2_enabled = mode;
424 pr_info("%s\n", spectre_v2_strings[mode]);
425
426 /*
427 * If spectre v2 protection has been enabled, unconditionally fill
428 * RSB during a context switch; this protects against two independent
429 * issues:
430 *
431 * - RSB underflow (and switch to BTB) on Skylake+
432 * - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs
433 */
434 setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
435 pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n");
436
437 /* Initialize Indirect Branch Prediction Barrier if supported */
438 if (boot_cpu_has(X86_FEATURE_IBPB)) {
439 setup_force_cpu_cap(X86_FEATURE_USE_IBPB);
440 pr_info("Spectre v2 mitigation: Enabling Indirect Branch Prediction Barrier\n");
441 }
442
443 /*
444 * Retpoline means the kernel is safe because it has no indirect
445 * branches. Enhanced IBRS protects firmware too, so, enable restricted
446 * speculation around firmware calls only when Enhanced IBRS isn't
447 * supported.
448 *
449 * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because
450 * the user might select retpoline on the kernel command line and if
451 * the CPU supports Enhanced IBRS, kernel might un-intentionally not
452 * enable IBRS around firmware calls.
453 */
454 if (boot_cpu_has(X86_FEATURE_IBRS) && mode != SPECTRE_V2_IBRS_ENHANCED) {
455 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW);
456 pr_info("Enabling Restricted Speculation for firmware calls\n");
457 }
458
459 /* Enable STIBP if appropriate */
460 arch_smt_update();
461 }
462
463 #undef pr_fmt
464 #define pr_fmt(fmt) "Speculative Store Bypass: " fmt
465
466 static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE;
467
468 /* The kernel command line selection */
469 enum ssb_mitigation_cmd {
470 SPEC_STORE_BYPASS_CMD_NONE,
471 SPEC_STORE_BYPASS_CMD_AUTO,
472 SPEC_STORE_BYPASS_CMD_ON,
473 SPEC_STORE_BYPASS_CMD_PRCTL,
474 SPEC_STORE_BYPASS_CMD_SECCOMP,
475 };
476
477 static const char *ssb_strings[] = {
478 [SPEC_STORE_BYPASS_NONE] = "Vulnerable",
479 [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled",
480 [SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl",
481 [SPEC_STORE_BYPASS_SECCOMP] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
482 };
483
484 static const struct {
485 const char *option;
486 enum ssb_mitigation_cmd cmd;
487 } ssb_mitigation_options[] = {
488 { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */
489 { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */
490 { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */
491 { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */
492 { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */
493 };
494
495 static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void)
496 {
497 enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO;
498 char arg[20];
499 int ret, i;
500
501 if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable")) {
502 return SPEC_STORE_BYPASS_CMD_NONE;
503 } else {
504 ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable",
505 arg, sizeof(arg));
506 if (ret < 0)
507 return SPEC_STORE_BYPASS_CMD_AUTO;
508
509 for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) {
510 if (!match_option(arg, ret, ssb_mitigation_options[i].option))
511 continue;
512
513 cmd = ssb_mitigation_options[i].cmd;
514 break;
515 }
516
517 if (i >= ARRAY_SIZE(ssb_mitigation_options)) {
518 pr_err("unknown option (%s). Switching to AUTO select\n", arg);
519 return SPEC_STORE_BYPASS_CMD_AUTO;
520 }
521 }
522
523 return cmd;
524 }
525
526 static enum ssb_mitigation __init __ssb_select_mitigation(void)
527 {
528 enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE;
529 enum ssb_mitigation_cmd cmd;
530
531 if (!boot_cpu_has(X86_FEATURE_SSBD))
532 return mode;
533
534 cmd = ssb_parse_cmdline();
535 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) &&
536 (cmd == SPEC_STORE_BYPASS_CMD_NONE ||
537 cmd == SPEC_STORE_BYPASS_CMD_AUTO))
538 return mode;
539
540 switch (cmd) {
541 case SPEC_STORE_BYPASS_CMD_AUTO:
542 case SPEC_STORE_BYPASS_CMD_SECCOMP:
543 /*
544 * Choose prctl+seccomp as the default mode if seccomp is
545 * enabled.
546 */
547 if (IS_ENABLED(CONFIG_SECCOMP))
548 mode = SPEC_STORE_BYPASS_SECCOMP;
549 else
550 mode = SPEC_STORE_BYPASS_PRCTL;
551 break;
552 case SPEC_STORE_BYPASS_CMD_ON:
553 mode = SPEC_STORE_BYPASS_DISABLE;
554 break;
555 case SPEC_STORE_BYPASS_CMD_PRCTL:
556 mode = SPEC_STORE_BYPASS_PRCTL;
557 break;
558 case SPEC_STORE_BYPASS_CMD_NONE:
559 break;
560 }
561
562 /*
563 * We have three CPU feature flags that are in play here:
564 * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
565 * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
566 * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
567 */
568 if (mode == SPEC_STORE_BYPASS_DISABLE) {
569 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE);
570 /*
571 * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
572 * use a completely different MSR and bit dependent on family.
573 */
574 if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
575 !static_cpu_has(X86_FEATURE_AMD_SSBD)) {
576 x86_amd_ssb_disable();
577 } else {
578 x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
579 x86_spec_ctrl_mask |= SPEC_CTRL_SSBD;
580 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
581 }
582 }
583
584 return mode;
585 }
586
587 static void ssb_select_mitigation(void)
588 {
589 ssb_mode = __ssb_select_mitigation();
590
591 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
592 pr_info("%s\n", ssb_strings[ssb_mode]);
593 }
594
595 #undef pr_fmt
596 #define pr_fmt(fmt) "Speculation prctl: " fmt
597
598 static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl)
599 {
600 bool update;
601
602 if (ssb_mode != SPEC_STORE_BYPASS_PRCTL &&
603 ssb_mode != SPEC_STORE_BYPASS_SECCOMP)
604 return -ENXIO;
605
606 switch (ctrl) {
607 case PR_SPEC_ENABLE:
608 /* If speculation is force disabled, enable is not allowed */
609 if (task_spec_ssb_force_disable(task))
610 return -EPERM;
611 task_clear_spec_ssb_disable(task);
612 update = test_and_clear_tsk_thread_flag(task, TIF_SSBD);
613 break;
614 case PR_SPEC_DISABLE:
615 task_set_spec_ssb_disable(task);
616 update = !test_and_set_tsk_thread_flag(task, TIF_SSBD);
617 break;
618 case PR_SPEC_FORCE_DISABLE:
619 task_set_spec_ssb_disable(task);
620 task_set_spec_ssb_force_disable(task);
621 update = !test_and_set_tsk_thread_flag(task, TIF_SSBD);
622 break;
623 default:
624 return -ERANGE;
625 }
626
627 /*
628 * If being set on non-current task, delay setting the CPU
629 * mitigation until it is next scheduled.
630 */
631 if (task == current && update)
632 speculative_store_bypass_update_current();
633
634 return 0;
635 }
636
637 int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which,
638 unsigned long ctrl)
639 {
640 switch (which) {
641 case PR_SPEC_STORE_BYPASS:
642 return ssb_prctl_set(task, ctrl);
643 default:
644 return -ENODEV;
645 }
646 }
647
648 #ifdef CONFIG_SECCOMP
649 void arch_seccomp_spec_mitigate(struct task_struct *task)
650 {
651 if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP)
652 ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE);
653 }
654 #endif
655
656 static int ssb_prctl_get(struct task_struct *task)
657 {
658 switch (ssb_mode) {
659 case SPEC_STORE_BYPASS_DISABLE:
660 return PR_SPEC_DISABLE;
661 case SPEC_STORE_BYPASS_SECCOMP:
662 case SPEC_STORE_BYPASS_PRCTL:
663 if (task_spec_ssb_force_disable(task))
664 return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
665 if (task_spec_ssb_disable(task))
666 return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
667 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
668 default:
669 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
670 return PR_SPEC_ENABLE;
671 return PR_SPEC_NOT_AFFECTED;
672 }
673 }
674
675 int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
676 {
677 switch (which) {
678 case PR_SPEC_STORE_BYPASS:
679 return ssb_prctl_get(task);
680 default:
681 return -ENODEV;
682 }
683 }
684
685 void x86_spec_ctrl_setup_ap(void)
686 {
687 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
688 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
689
690 if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
691 x86_amd_ssb_disable();
692 }
693
694 #undef pr_fmt
695 #define pr_fmt(fmt) "L1TF: " fmt
696
697 /* Default mitigation for L1TF-affected CPUs */
698 enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH;
699 #if IS_ENABLED(CONFIG_KVM_INTEL)
700 EXPORT_SYMBOL_GPL(l1tf_mitigation);
701
702 enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
703 EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation);
704 #endif
705
706 /*
707 * These CPUs all support 44bits physical address space internally in the
708 * cache but CPUID can report a smaller number of physical address bits.
709 *
710 * The L1TF mitigation uses the top most address bit for the inversion of
711 * non present PTEs. When the installed memory reaches into the top most
712 * address bit due to memory holes, which has been observed on machines
713 * which report 36bits physical address bits and have 32G RAM installed,
714 * then the mitigation range check in l1tf_select_mitigation() triggers.
715 * This is a false positive because the mitigation is still possible due to
716 * the fact that the cache uses 44bit internally. Use the cache bits
717 * instead of the reported physical bits and adjust them on the affected
718 * machines to 44bit if the reported bits are less than 44.
719 */
720 static void override_cache_bits(struct cpuinfo_x86 *c)
721 {
722 if (c->x86 != 6)
723 return;
724
725 switch (c->x86_model) {
726 case INTEL_FAM6_NEHALEM:
727 case INTEL_FAM6_WESTMERE:
728 case INTEL_FAM6_SANDYBRIDGE:
729 case INTEL_FAM6_IVYBRIDGE:
730 case INTEL_FAM6_HASWELL_CORE:
731 case INTEL_FAM6_HASWELL_ULT:
732 case INTEL_FAM6_HASWELL_GT3E:
733 case INTEL_FAM6_BROADWELL_CORE:
734 case INTEL_FAM6_BROADWELL_GT3E:
735 case INTEL_FAM6_SKYLAKE_MOBILE:
736 case INTEL_FAM6_SKYLAKE_DESKTOP:
737 case INTEL_FAM6_KABYLAKE_MOBILE:
738 case INTEL_FAM6_KABYLAKE_DESKTOP:
739 if (c->x86_cache_bits < 44)
740 c->x86_cache_bits = 44;
741 break;
742 }
743 }
744
745 static void __init l1tf_select_mitigation(void)
746 {
747 u64 half_pa;
748
749 if (!boot_cpu_has_bug(X86_BUG_L1TF))
750 return;
751
752 override_cache_bits(&boot_cpu_data);
753
754 switch (l1tf_mitigation) {
755 case L1TF_MITIGATION_OFF:
756 case L1TF_MITIGATION_FLUSH_NOWARN:
757 case L1TF_MITIGATION_FLUSH:
758 break;
759 case L1TF_MITIGATION_FLUSH_NOSMT:
760 case L1TF_MITIGATION_FULL:
761 cpu_smt_disable(false);
762 break;
763 case L1TF_MITIGATION_FULL_FORCE:
764 cpu_smt_disable(true);
765 break;
766 }
767
768 #if CONFIG_PGTABLE_LEVELS == 2
769 pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n");
770 return;
771 #endif
772
773 half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT;
774 if (e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) {
775 pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n");
776 return;
777 }
778
779 setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV);
780 }
781
782 static int __init l1tf_cmdline(char *str)
783 {
784 if (!boot_cpu_has_bug(X86_BUG_L1TF))
785 return 0;
786
787 if (!str)
788 return -EINVAL;
789
790 if (!strcmp(str, "off"))
791 l1tf_mitigation = L1TF_MITIGATION_OFF;
792 else if (!strcmp(str, "flush,nowarn"))
793 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN;
794 else if (!strcmp(str, "flush"))
795 l1tf_mitigation = L1TF_MITIGATION_FLUSH;
796 else if (!strcmp(str, "flush,nosmt"))
797 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT;
798 else if (!strcmp(str, "full"))
799 l1tf_mitigation = L1TF_MITIGATION_FULL;
800 else if (!strcmp(str, "full,force"))
801 l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE;
802
803 return 0;
804 }
805 early_param("l1tf", l1tf_cmdline);
806
807 #undef pr_fmt
808
809 #ifdef CONFIG_SYSFS
810
811 #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion"
812
813 #if IS_ENABLED(CONFIG_KVM_INTEL)
814 static const char *l1tf_vmx_states[] = {
815 [VMENTER_L1D_FLUSH_AUTO] = "auto",
816 [VMENTER_L1D_FLUSH_NEVER] = "vulnerable",
817 [VMENTER_L1D_FLUSH_COND] = "conditional cache flushes",
818 [VMENTER_L1D_FLUSH_ALWAYS] = "cache flushes",
819 [VMENTER_L1D_FLUSH_EPT_DISABLED] = "EPT disabled",
820 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = "flush not necessary"
821 };
822
823 static ssize_t l1tf_show_state(char *buf)
824 {
825 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO)
826 return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
827
828 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED ||
829 (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER &&
830 cpu_smt_control == CPU_SMT_ENABLED))
831 return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG,
832 l1tf_vmx_states[l1tf_vmx_mitigation]);
833
834 return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG,
835 l1tf_vmx_states[l1tf_vmx_mitigation],
836 cpu_smt_control == CPU_SMT_ENABLED ? "vulnerable" : "disabled");
837 }
838 #else
839 static ssize_t l1tf_show_state(char *buf)
840 {
841 return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
842 }
843 #endif
844
845 static char *stibp_state(void)
846 {
847 if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED)
848 return "";
849
850 if (x86_spec_ctrl_base & SPEC_CTRL_STIBP)
851 return ", STIBP";
852 else
853 return "";
854 }
855
856 static char *ibpb_state(void)
857 {
858 if (boot_cpu_has(X86_FEATURE_USE_IBPB))
859 return ", IBPB";
860 else
861 return "";
862 }
863
864 static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr,
865 char *buf, unsigned int bug)
866 {
867 if (!boot_cpu_has_bug(bug))
868 return sprintf(buf, "Not affected\n");
869
870 switch (bug) {
871 case X86_BUG_CPU_MELTDOWN:
872 if (boot_cpu_has(X86_FEATURE_PTI))
873 return sprintf(buf, "Mitigation: PTI\n");
874
875 break;
876
877 case X86_BUG_SPECTRE_V1:
878 return sprintf(buf, "Mitigation: __user pointer sanitization\n");
879
880 case X86_BUG_SPECTRE_V2:
881 return sprintf(buf, "%s%s%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled],
882 ibpb_state(),
883 boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "",
884 stibp_state(),
885 boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? ", RSB filling" : "",
886 spectre_v2_module_string());
887
888 case X86_BUG_SPEC_STORE_BYPASS:
889 return sprintf(buf, "%s\n", ssb_strings[ssb_mode]);
890
891 case X86_BUG_L1TF:
892 if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV))
893 return l1tf_show_state(buf);
894 break;
895 default:
896 break;
897 }
898
899 return sprintf(buf, "Vulnerable\n");
900 }
901
902 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf)
903 {
904 return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN);
905 }
906
907 ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf)
908 {
909 return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1);
910 }
911
912 ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf)
913 {
914 return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2);
915 }
916
917 ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf)
918 {
919 return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS);
920 }
921
922 ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf)
923 {
924 return cpu_show_common(dev, attr, buf, X86_BUG_L1TF);
925 }
926 #endif