1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 1994 Linus Torvalds
5 * Cyrix stuff, June 1998 by:
6 * - Rafael R. Reilova (moved everything from head.S),
7 * <rreilova@ececs.uc.edu>
8 * - Channing Corn (tests & fixes),
9 * - Andrew D. Balsa (code cleanup).
11 #include <linux/init.h>
12 #include <linux/utsname.h>
13 #include <linux/cpu.h>
14 #include <linux/module.h>
15 #include <linux/nospec.h>
16 #include <linux/prctl.h>
18 #include <asm/spec-ctrl.h>
19 #include <asm/cmdline.h>
21 #include <asm/processor.h>
22 #include <asm/processor-flags.h>
23 #include <asm/fpu/internal.h>
26 #include <asm/paravirt.h>
27 #include <asm/alternative.h>
28 #include <asm/pgtable.h>
29 #include <asm/set_memory.h>
30 #include <asm/intel-family.h>
31 #include <asm/e820/api.h>
33 static void __init
spectre_v2_select_mitigation(void);
34 static void __init
ssb_select_mitigation(void);
35 static void __init
l1tf_select_mitigation(void);
37 /* The base value of the SPEC_CTRL MSR that always has to be preserved. */
38 u64 x86_spec_ctrl_base
;
39 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base
);
40 static DEFINE_MUTEX(spec_ctrl_mutex
);
43 * The vendor and possibly platform specific bits which can be modified in
46 static u64 __ro_after_init x86_spec_ctrl_mask
= SPEC_CTRL_IBRS
;
49 * AMD specific MSR info for Speculative Store Bypass control.
50 * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
52 u64 __ro_after_init x86_amd_ls_cfg_base
;
53 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask
;
55 void __init
check_bugs(void)
60 * identify_boot_cpu() initialized SMT support information, let the
63 cpu_smt_check_topology_early();
65 if (!IS_ENABLED(CONFIG_SMP
)) {
67 print_cpu_info(&boot_cpu_data
);
71 * Read the SPEC_CTRL MSR to account for reserved bits which may
72 * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
73 * init code as it is not enumerated and depends on the family.
75 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL
))
76 rdmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
78 /* Allow STIBP in MSR_SPEC_CTRL if supported */
79 if (boot_cpu_has(X86_FEATURE_STIBP
))
80 x86_spec_ctrl_mask
|= SPEC_CTRL_STIBP
;
82 /* Select the proper spectre mitigation before patching alternatives */
83 spectre_v2_select_mitigation();
86 * Select proper mitigation for any exposure to the Speculative Store
87 * Bypass vulnerability.
89 ssb_select_mitigation();
91 l1tf_select_mitigation();
95 * Check whether we are able to run this kernel safely on SMP.
97 * - i386 is no longer supported.
98 * - In order to run on anything without a TSC, we need to be
99 * compiled for a i486.
101 if (boot_cpu_data
.x86
< 4)
102 panic("Kernel requires i486+ for 'invlpg' and other features");
104 init_utsname()->machine
[1] =
105 '0' + (boot_cpu_data
.x86
> 6 ? 6 : boot_cpu_data
.x86
);
106 alternative_instructions();
108 fpu__init_check_bugs();
109 #else /* CONFIG_X86_64 */
110 alternative_instructions();
113 * Make sure the first 2MB area is not mapped by huge pages
114 * There are typically fixed size MTRRs in there and overlapping
115 * MTRRs into large pages causes slow downs.
117 * Right now we don't do that with gbpages because there seems
118 * very little benefit for that case.
121 set_memory_4k((unsigned long)__va(0), 1);
125 /* The kernel command line selection */
126 enum spectre_v2_mitigation_cmd
{
129 SPECTRE_V2_CMD_FORCE
,
130 SPECTRE_V2_CMD_RETPOLINE
,
131 SPECTRE_V2_CMD_RETPOLINE_GENERIC
,
132 SPECTRE_V2_CMD_RETPOLINE_AMD
,
135 static const char *spectre_v2_strings
[] = {
136 [SPECTRE_V2_NONE
] = "Vulnerable",
137 [SPECTRE_V2_RETPOLINE_MINIMAL
] = "Vulnerable: Minimal generic ASM retpoline",
138 [SPECTRE_V2_RETPOLINE_MINIMAL_AMD
] = "Vulnerable: Minimal AMD ASM retpoline",
139 [SPECTRE_V2_RETPOLINE_GENERIC
] = "Mitigation: Full generic retpoline",
140 [SPECTRE_V2_RETPOLINE_AMD
] = "Mitigation: Full AMD retpoline",
141 [SPECTRE_V2_IBRS_ENHANCED
] = "Mitigation: Enhanced IBRS",
145 #define pr_fmt(fmt) "Spectre V2 : " fmt
147 static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init
=
151 x86_virt_spec_ctrl(u64 guest_spec_ctrl
, u64 guest_virt_spec_ctrl
, bool setguest
)
153 u64 msrval
, guestval
, hostval
= x86_spec_ctrl_base
;
154 struct thread_info
*ti
= current_thread_info();
156 /* Is MSR_SPEC_CTRL implemented ? */
157 if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL
)) {
159 * Restrict guest_spec_ctrl to supported values. Clear the
160 * modifiable bits in the host base value and or the
161 * modifiable bits from the guest value.
163 guestval
= hostval
& ~x86_spec_ctrl_mask
;
164 guestval
|= guest_spec_ctrl
& x86_spec_ctrl_mask
;
166 /* SSBD controlled in MSR_SPEC_CTRL */
167 if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD
) ||
168 static_cpu_has(X86_FEATURE_AMD_SSBD
))
169 hostval
|= ssbd_tif_to_spec_ctrl(ti
->flags
);
171 if (hostval
!= guestval
) {
172 msrval
= setguest
? guestval
: hostval
;
173 wrmsrl(MSR_IA32_SPEC_CTRL
, msrval
);
178 * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
179 * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
181 if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD
) &&
182 !static_cpu_has(X86_FEATURE_VIRT_SSBD
))
186 * If the host has SSBD mitigation enabled, force it in the host's
187 * virtual MSR value. If its not permanently enabled, evaluate
188 * current's TIF_SSBD thread flag.
190 if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE
))
191 hostval
= SPEC_CTRL_SSBD
;
193 hostval
= ssbd_tif_to_spec_ctrl(ti
->flags
);
195 /* Sanitize the guest value */
196 guestval
= guest_virt_spec_ctrl
& SPEC_CTRL_SSBD
;
198 if (hostval
!= guestval
) {
201 tif
= setguest
? ssbd_spec_ctrl_to_tif(guestval
) :
202 ssbd_spec_ctrl_to_tif(hostval
);
204 speculative_store_bypass_update(tif
);
207 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl
);
209 static void x86_amd_ssb_disable(void)
211 u64 msrval
= x86_amd_ls_cfg_base
| x86_amd_ls_cfg_ssbd_mask
;
213 if (boot_cpu_has(X86_FEATURE_VIRT_SSBD
))
214 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL
, SPEC_CTRL_SSBD
);
215 else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD
))
216 wrmsrl(MSR_AMD64_LS_CFG
, msrval
);
220 static bool spectre_v2_bad_module
;
222 bool retpoline_module_ok(bool has_retpoline
)
224 if (spectre_v2_enabled
== SPECTRE_V2_NONE
|| has_retpoline
)
227 pr_err("System may be vulnerable to spectre v2\n");
228 spectre_v2_bad_module
= true;
232 static inline const char *spectre_v2_module_string(void)
234 return spectre_v2_bad_module
? " - vulnerable module loaded" : "";
237 static inline const char *spectre_v2_module_string(void) { return ""; }
240 static void __init
spec2_print_if_insecure(const char *reason
)
242 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2
))
243 pr_info("%s selected on command line.\n", reason
);
246 static void __init
spec2_print_if_secure(const char *reason
)
248 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2
))
249 pr_info("%s selected on command line.\n", reason
);
252 static inline bool retp_compiler(void)
254 return __is_defined(RETPOLINE
);
257 static inline bool match_option(const char *arg
, int arglen
, const char *opt
)
259 int len
= strlen(opt
);
261 return len
== arglen
&& !strncmp(arg
, opt
, len
);
264 static const struct {
266 enum spectre_v2_mitigation_cmd cmd
;
268 } mitigation_options
[] = {
269 { "off", SPECTRE_V2_CMD_NONE
, false },
270 { "on", SPECTRE_V2_CMD_FORCE
, true },
271 { "retpoline", SPECTRE_V2_CMD_RETPOLINE
, false },
272 { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD
, false },
273 { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC
, false },
274 { "auto", SPECTRE_V2_CMD_AUTO
, false },
277 static enum spectre_v2_mitigation_cmd __init
spectre_v2_parse_cmdline(void)
281 enum spectre_v2_mitigation_cmd cmd
= SPECTRE_V2_CMD_AUTO
;
283 if (cmdline_find_option_bool(boot_command_line
, "nospectre_v2"))
284 return SPECTRE_V2_CMD_NONE
;
286 ret
= cmdline_find_option(boot_command_line
, "spectre_v2", arg
, sizeof(arg
));
288 return SPECTRE_V2_CMD_AUTO
;
290 for (i
= 0; i
< ARRAY_SIZE(mitigation_options
); i
++) {
291 if (!match_option(arg
, ret
, mitigation_options
[i
].option
))
293 cmd
= mitigation_options
[i
].cmd
;
297 if (i
>= ARRAY_SIZE(mitigation_options
)) {
298 pr_err("unknown option (%s). Switching to AUTO select\n", arg
);
299 return SPECTRE_V2_CMD_AUTO
;
303 if ((cmd
== SPECTRE_V2_CMD_RETPOLINE
||
304 cmd
== SPECTRE_V2_CMD_RETPOLINE_AMD
||
305 cmd
== SPECTRE_V2_CMD_RETPOLINE_GENERIC
) &&
306 !IS_ENABLED(CONFIG_RETPOLINE
)) {
307 pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options
[i
].option
);
308 return SPECTRE_V2_CMD_AUTO
;
311 if (cmd
== SPECTRE_V2_CMD_RETPOLINE_AMD
&&
312 boot_cpu_data
.x86_vendor
!= X86_VENDOR_AMD
) {
313 pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n");
314 return SPECTRE_V2_CMD_AUTO
;
317 if (mitigation_options
[i
].secure
)
318 spec2_print_if_secure(mitigation_options
[i
].option
);
320 spec2_print_if_insecure(mitigation_options
[i
].option
);
325 static bool stibp_needed(void)
327 if (spectre_v2_enabled
== SPECTRE_V2_NONE
)
330 if (!boot_cpu_has(X86_FEATURE_STIBP
))
336 static void update_stibp_msr(void *info
)
338 wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
341 void arch_smt_update(void)
348 mutex_lock(&spec_ctrl_mutex
);
349 mask
= x86_spec_ctrl_base
;
350 if (cpu_smt_control
== CPU_SMT_ENABLED
)
351 mask
|= SPEC_CTRL_STIBP
;
353 mask
&= ~SPEC_CTRL_STIBP
;
355 if (mask
!= x86_spec_ctrl_base
) {
356 pr_info("Spectre v2 cross-process SMT mitigation: %s STIBP\n",
357 cpu_smt_control
== CPU_SMT_ENABLED
?
358 "Enabling" : "Disabling");
359 x86_spec_ctrl_base
= mask
;
360 on_each_cpu(update_stibp_msr
, NULL
, 1);
362 mutex_unlock(&spec_ctrl_mutex
);
365 static void __init
spectre_v2_select_mitigation(void)
367 enum spectre_v2_mitigation_cmd cmd
= spectre_v2_parse_cmdline();
368 enum spectre_v2_mitigation mode
= SPECTRE_V2_NONE
;
371 * If the CPU is not affected and the command line mode is NONE or AUTO
372 * then nothing to do.
374 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2
) &&
375 (cmd
== SPECTRE_V2_CMD_NONE
|| cmd
== SPECTRE_V2_CMD_AUTO
))
379 case SPECTRE_V2_CMD_NONE
:
382 case SPECTRE_V2_CMD_FORCE
:
383 case SPECTRE_V2_CMD_AUTO
:
384 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED
)) {
385 mode
= SPECTRE_V2_IBRS_ENHANCED
;
386 /* Force it so VMEXIT will restore correctly */
387 x86_spec_ctrl_base
|= SPEC_CTRL_IBRS
;
388 wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
389 goto specv2_set_mode
;
391 if (IS_ENABLED(CONFIG_RETPOLINE
))
394 case SPECTRE_V2_CMD_RETPOLINE_AMD
:
395 if (IS_ENABLED(CONFIG_RETPOLINE
))
398 case SPECTRE_V2_CMD_RETPOLINE_GENERIC
:
399 if (IS_ENABLED(CONFIG_RETPOLINE
))
400 goto retpoline_generic
;
402 case SPECTRE_V2_CMD_RETPOLINE
:
403 if (IS_ENABLED(CONFIG_RETPOLINE
))
407 pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!");
411 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) {
413 if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC
)) {
414 pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n");
415 goto retpoline_generic
;
417 mode
= retp_compiler() ? SPECTRE_V2_RETPOLINE_AMD
:
418 SPECTRE_V2_RETPOLINE_MINIMAL_AMD
;
419 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD
);
420 setup_force_cpu_cap(X86_FEATURE_RETPOLINE
);
423 mode
= retp_compiler() ? SPECTRE_V2_RETPOLINE_GENERIC
:
424 SPECTRE_V2_RETPOLINE_MINIMAL
;
425 setup_force_cpu_cap(X86_FEATURE_RETPOLINE
);
429 spectre_v2_enabled
= mode
;
430 pr_info("%s\n", spectre_v2_strings
[mode
]);
433 * If spectre v2 protection has been enabled, unconditionally fill
434 * RSB during a context switch; this protects against two independent
437 * - RSB underflow (and switch to BTB) on Skylake+
438 * - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs
440 setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW
);
441 pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n");
443 /* Initialize Indirect Branch Prediction Barrier if supported */
444 if (boot_cpu_has(X86_FEATURE_IBPB
)) {
445 setup_force_cpu_cap(X86_FEATURE_USE_IBPB
);
446 pr_info("Spectre v2 mitigation: Enabling Indirect Branch Prediction Barrier\n");
450 * Retpoline means the kernel is safe because it has no indirect
451 * branches. Enhanced IBRS protects firmware too, so, enable restricted
452 * speculation around firmware calls only when Enhanced IBRS isn't
455 * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because
456 * the user might select retpoline on the kernel command line and if
457 * the CPU supports Enhanced IBRS, kernel might un-intentionally not
458 * enable IBRS around firmware calls.
460 if (boot_cpu_has(X86_FEATURE_IBRS
) && mode
!= SPECTRE_V2_IBRS_ENHANCED
) {
461 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW
);
462 pr_info("Enabling Restricted Speculation for firmware calls\n");
465 /* Enable STIBP if appropriate */
470 #define pr_fmt(fmt) "Speculative Store Bypass: " fmt
472 static enum ssb_mitigation ssb_mode __ro_after_init
= SPEC_STORE_BYPASS_NONE
;
474 /* The kernel command line selection */
475 enum ssb_mitigation_cmd
{
476 SPEC_STORE_BYPASS_CMD_NONE
,
477 SPEC_STORE_BYPASS_CMD_AUTO
,
478 SPEC_STORE_BYPASS_CMD_ON
,
479 SPEC_STORE_BYPASS_CMD_PRCTL
,
480 SPEC_STORE_BYPASS_CMD_SECCOMP
,
483 static const char *ssb_strings
[] = {
484 [SPEC_STORE_BYPASS_NONE
] = "Vulnerable",
485 [SPEC_STORE_BYPASS_DISABLE
] = "Mitigation: Speculative Store Bypass disabled",
486 [SPEC_STORE_BYPASS_PRCTL
] = "Mitigation: Speculative Store Bypass disabled via prctl",
487 [SPEC_STORE_BYPASS_SECCOMP
] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
490 static const struct {
492 enum ssb_mitigation_cmd cmd
;
493 } ssb_mitigation_options
[] = {
494 { "auto", SPEC_STORE_BYPASS_CMD_AUTO
}, /* Platform decides */
495 { "on", SPEC_STORE_BYPASS_CMD_ON
}, /* Disable Speculative Store Bypass */
496 { "off", SPEC_STORE_BYPASS_CMD_NONE
}, /* Don't touch Speculative Store Bypass */
497 { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL
}, /* Disable Speculative Store Bypass via prctl */
498 { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP
}, /* Disable Speculative Store Bypass via prctl and seccomp */
501 static enum ssb_mitigation_cmd __init
ssb_parse_cmdline(void)
503 enum ssb_mitigation_cmd cmd
= SPEC_STORE_BYPASS_CMD_AUTO
;
507 if (cmdline_find_option_bool(boot_command_line
, "nospec_store_bypass_disable")) {
508 return SPEC_STORE_BYPASS_CMD_NONE
;
510 ret
= cmdline_find_option(boot_command_line
, "spec_store_bypass_disable",
513 return SPEC_STORE_BYPASS_CMD_AUTO
;
515 for (i
= 0; i
< ARRAY_SIZE(ssb_mitigation_options
); i
++) {
516 if (!match_option(arg
, ret
, ssb_mitigation_options
[i
].option
))
519 cmd
= ssb_mitigation_options
[i
].cmd
;
523 if (i
>= ARRAY_SIZE(ssb_mitigation_options
)) {
524 pr_err("unknown option (%s). Switching to AUTO select\n", arg
);
525 return SPEC_STORE_BYPASS_CMD_AUTO
;
532 static enum ssb_mitigation __init
__ssb_select_mitigation(void)
534 enum ssb_mitigation mode
= SPEC_STORE_BYPASS_NONE
;
535 enum ssb_mitigation_cmd cmd
;
537 if (!boot_cpu_has(X86_FEATURE_SSBD
))
540 cmd
= ssb_parse_cmdline();
541 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS
) &&
542 (cmd
== SPEC_STORE_BYPASS_CMD_NONE
||
543 cmd
== SPEC_STORE_BYPASS_CMD_AUTO
))
547 case SPEC_STORE_BYPASS_CMD_AUTO
:
548 case SPEC_STORE_BYPASS_CMD_SECCOMP
:
550 * Choose prctl+seccomp as the default mode if seccomp is
553 if (IS_ENABLED(CONFIG_SECCOMP
))
554 mode
= SPEC_STORE_BYPASS_SECCOMP
;
556 mode
= SPEC_STORE_BYPASS_PRCTL
;
558 case SPEC_STORE_BYPASS_CMD_ON
:
559 mode
= SPEC_STORE_BYPASS_DISABLE
;
561 case SPEC_STORE_BYPASS_CMD_PRCTL
:
562 mode
= SPEC_STORE_BYPASS_PRCTL
;
564 case SPEC_STORE_BYPASS_CMD_NONE
:
569 * We have three CPU feature flags that are in play here:
570 * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
571 * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
572 * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
574 if (mode
== SPEC_STORE_BYPASS_DISABLE
) {
575 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE
);
577 * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
578 * use a completely different MSR and bit dependent on family.
580 if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD
) &&
581 !static_cpu_has(X86_FEATURE_AMD_SSBD
)) {
582 x86_amd_ssb_disable();
584 x86_spec_ctrl_base
|= SPEC_CTRL_SSBD
;
585 x86_spec_ctrl_mask
|= SPEC_CTRL_SSBD
;
586 wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
593 static void ssb_select_mitigation(void)
595 ssb_mode
= __ssb_select_mitigation();
597 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS
))
598 pr_info("%s\n", ssb_strings
[ssb_mode
]);
602 #define pr_fmt(fmt) "Speculation prctl: " fmt
604 static int ssb_prctl_set(struct task_struct
*task
, unsigned long ctrl
)
608 if (ssb_mode
!= SPEC_STORE_BYPASS_PRCTL
&&
609 ssb_mode
!= SPEC_STORE_BYPASS_SECCOMP
)
614 /* If speculation is force disabled, enable is not allowed */
615 if (task_spec_ssb_force_disable(task
))
617 task_clear_spec_ssb_disable(task
);
618 update
= test_and_clear_tsk_thread_flag(task
, TIF_SSBD
);
620 case PR_SPEC_DISABLE
:
621 task_set_spec_ssb_disable(task
);
622 update
= !test_and_set_tsk_thread_flag(task
, TIF_SSBD
);
624 case PR_SPEC_FORCE_DISABLE
:
625 task_set_spec_ssb_disable(task
);
626 task_set_spec_ssb_force_disable(task
);
627 update
= !test_and_set_tsk_thread_flag(task
, TIF_SSBD
);
634 * If being set on non-current task, delay setting the CPU
635 * mitigation until it is next scheduled.
637 if (task
== current
&& update
)
638 speculative_store_bypass_update_current();
643 int arch_prctl_spec_ctrl_set(struct task_struct
*task
, unsigned long which
,
647 case PR_SPEC_STORE_BYPASS
:
648 return ssb_prctl_set(task
, ctrl
);
654 #ifdef CONFIG_SECCOMP
655 void arch_seccomp_spec_mitigate(struct task_struct
*task
)
657 if (ssb_mode
== SPEC_STORE_BYPASS_SECCOMP
)
658 ssb_prctl_set(task
, PR_SPEC_FORCE_DISABLE
);
662 static int ssb_prctl_get(struct task_struct
*task
)
665 case SPEC_STORE_BYPASS_DISABLE
:
666 return PR_SPEC_DISABLE
;
667 case SPEC_STORE_BYPASS_SECCOMP
:
668 case SPEC_STORE_BYPASS_PRCTL
:
669 if (task_spec_ssb_force_disable(task
))
670 return PR_SPEC_PRCTL
| PR_SPEC_FORCE_DISABLE
;
671 if (task_spec_ssb_disable(task
))
672 return PR_SPEC_PRCTL
| PR_SPEC_DISABLE
;
673 return PR_SPEC_PRCTL
| PR_SPEC_ENABLE
;
675 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS
))
676 return PR_SPEC_ENABLE
;
677 return PR_SPEC_NOT_AFFECTED
;
681 int arch_prctl_spec_ctrl_get(struct task_struct
*task
, unsigned long which
)
684 case PR_SPEC_STORE_BYPASS
:
685 return ssb_prctl_get(task
);
691 void x86_spec_ctrl_setup_ap(void)
693 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL
))
694 wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
696 if (ssb_mode
== SPEC_STORE_BYPASS_DISABLE
)
697 x86_amd_ssb_disable();
701 #define pr_fmt(fmt) "L1TF: " fmt
703 /* Default mitigation for L1TF-affected CPUs */
704 enum l1tf_mitigations l1tf_mitigation __ro_after_init
= L1TF_MITIGATION_FLUSH
;
705 #if IS_ENABLED(CONFIG_KVM_INTEL)
706 EXPORT_SYMBOL_GPL(l1tf_mitigation
);
708 enum vmx_l1d_flush_state l1tf_vmx_mitigation
= VMENTER_L1D_FLUSH_AUTO
;
709 EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation
);
713 * These CPUs all support 44bits physical address space internally in the
714 * cache but CPUID can report a smaller number of physical address bits.
716 * The L1TF mitigation uses the top most address bit for the inversion of
717 * non present PTEs. When the installed memory reaches into the top most
718 * address bit due to memory holes, which has been observed on machines
719 * which report 36bits physical address bits and have 32G RAM installed,
720 * then the mitigation range check in l1tf_select_mitigation() triggers.
721 * This is a false positive because the mitigation is still possible due to
722 * the fact that the cache uses 44bit internally. Use the cache bits
723 * instead of the reported physical bits and adjust them on the affected
724 * machines to 44bit if the reported bits are less than 44.
726 static void override_cache_bits(struct cpuinfo_x86
*c
)
731 switch (c
->x86_model
) {
732 case INTEL_FAM6_NEHALEM
:
733 case INTEL_FAM6_WESTMERE
:
734 case INTEL_FAM6_SANDYBRIDGE
:
735 case INTEL_FAM6_IVYBRIDGE
:
736 case INTEL_FAM6_HASWELL_CORE
:
737 case INTEL_FAM6_HASWELL_ULT
:
738 case INTEL_FAM6_HASWELL_GT3E
:
739 case INTEL_FAM6_BROADWELL_CORE
:
740 case INTEL_FAM6_BROADWELL_GT3E
:
741 case INTEL_FAM6_SKYLAKE_MOBILE
:
742 case INTEL_FAM6_SKYLAKE_DESKTOP
:
743 case INTEL_FAM6_KABYLAKE_MOBILE
:
744 case INTEL_FAM6_KABYLAKE_DESKTOP
:
745 if (c
->x86_cache_bits
< 44)
746 c
->x86_cache_bits
= 44;
751 static void __init
l1tf_select_mitigation(void)
755 if (!boot_cpu_has_bug(X86_BUG_L1TF
))
758 override_cache_bits(&boot_cpu_data
);
760 switch (l1tf_mitigation
) {
761 case L1TF_MITIGATION_OFF
:
762 case L1TF_MITIGATION_FLUSH_NOWARN
:
763 case L1TF_MITIGATION_FLUSH
:
765 case L1TF_MITIGATION_FLUSH_NOSMT
:
766 case L1TF_MITIGATION_FULL
:
767 cpu_smt_disable(false);
769 case L1TF_MITIGATION_FULL_FORCE
:
770 cpu_smt_disable(true);
774 #if CONFIG_PGTABLE_LEVELS == 2
775 pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n");
779 half_pa
= (u64
)l1tf_pfn_limit() << PAGE_SHIFT
;
780 if (e820__mapped_any(half_pa
, ULLONG_MAX
- half_pa
, E820_TYPE_RAM
)) {
781 pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n");
785 setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV
);
788 static int __init
l1tf_cmdline(char *str
)
790 if (!boot_cpu_has_bug(X86_BUG_L1TF
))
796 if (!strcmp(str
, "off"))
797 l1tf_mitigation
= L1TF_MITIGATION_OFF
;
798 else if (!strcmp(str
, "flush,nowarn"))
799 l1tf_mitigation
= L1TF_MITIGATION_FLUSH_NOWARN
;
800 else if (!strcmp(str
, "flush"))
801 l1tf_mitigation
= L1TF_MITIGATION_FLUSH
;
802 else if (!strcmp(str
, "flush,nosmt"))
803 l1tf_mitigation
= L1TF_MITIGATION_FLUSH_NOSMT
;
804 else if (!strcmp(str
, "full"))
805 l1tf_mitigation
= L1TF_MITIGATION_FULL
;
806 else if (!strcmp(str
, "full,force"))
807 l1tf_mitigation
= L1TF_MITIGATION_FULL_FORCE
;
811 early_param("l1tf", l1tf_cmdline
);
817 #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion"
819 #if IS_ENABLED(CONFIG_KVM_INTEL)
820 static const char *l1tf_vmx_states
[] = {
821 [VMENTER_L1D_FLUSH_AUTO
] = "auto",
822 [VMENTER_L1D_FLUSH_NEVER
] = "vulnerable",
823 [VMENTER_L1D_FLUSH_COND
] = "conditional cache flushes",
824 [VMENTER_L1D_FLUSH_ALWAYS
] = "cache flushes",
825 [VMENTER_L1D_FLUSH_EPT_DISABLED
] = "EPT disabled",
826 [VMENTER_L1D_FLUSH_NOT_REQUIRED
] = "flush not necessary"
829 static ssize_t
l1tf_show_state(char *buf
)
831 if (l1tf_vmx_mitigation
== VMENTER_L1D_FLUSH_AUTO
)
832 return sprintf(buf
, "%s\n", L1TF_DEFAULT_MSG
);
834 if (l1tf_vmx_mitigation
== VMENTER_L1D_FLUSH_EPT_DISABLED
||
835 (l1tf_vmx_mitigation
== VMENTER_L1D_FLUSH_NEVER
&&
836 cpu_smt_control
== CPU_SMT_ENABLED
))
837 return sprintf(buf
, "%s; VMX: %s\n", L1TF_DEFAULT_MSG
,
838 l1tf_vmx_states
[l1tf_vmx_mitigation
]);
840 return sprintf(buf
, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG
,
841 l1tf_vmx_states
[l1tf_vmx_mitigation
],
842 cpu_smt_control
== CPU_SMT_ENABLED
? "vulnerable" : "disabled");
845 static ssize_t
l1tf_show_state(char *buf
)
847 return sprintf(buf
, "%s\n", L1TF_DEFAULT_MSG
);
851 static ssize_t
cpu_show_common(struct device
*dev
, struct device_attribute
*attr
,
852 char *buf
, unsigned int bug
)
856 if (!boot_cpu_has_bug(bug
))
857 return sprintf(buf
, "Not affected\n");
860 case X86_BUG_CPU_MELTDOWN
:
861 if (boot_cpu_has(X86_FEATURE_PTI
))
862 return sprintf(buf
, "Mitigation: PTI\n");
866 case X86_BUG_SPECTRE_V1
:
867 return sprintf(buf
, "Mitigation: __user pointer sanitization\n");
869 case X86_BUG_SPECTRE_V2
:
870 ret
= sprintf(buf
, "%s%s%s%s%s\n", spectre_v2_strings
[spectre_v2_enabled
],
871 boot_cpu_has(X86_FEATURE_USE_IBPB
) ? ", IBPB" : "",
872 boot_cpu_has(X86_FEATURE_USE_IBRS_FW
) ? ", IBRS_FW" : "",
873 (x86_spec_ctrl_base
& SPEC_CTRL_STIBP
) ? ", STIBP" : "",
874 spectre_v2_module_string());
877 case X86_BUG_SPEC_STORE_BYPASS
:
878 return sprintf(buf
, "%s\n", ssb_strings
[ssb_mode
]);
881 if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV
))
882 return l1tf_show_state(buf
);
888 return sprintf(buf
, "Vulnerable\n");
891 ssize_t
cpu_show_meltdown(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
893 return cpu_show_common(dev
, attr
, buf
, X86_BUG_CPU_MELTDOWN
);
896 ssize_t
cpu_show_spectre_v1(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
898 return cpu_show_common(dev
, attr
, buf
, X86_BUG_SPECTRE_V1
);
901 ssize_t
cpu_show_spectre_v2(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
903 return cpu_show_common(dev
, attr
, buf
, X86_BUG_SPECTRE_V2
);
906 ssize_t
cpu_show_spec_store_bypass(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
908 return cpu_show_common(dev
, attr
, buf
, X86_BUG_SPEC_STORE_BYPASS
);
911 ssize_t
cpu_show_l1tf(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
913 return cpu_show_common(dev
, attr
, buf
, X86_BUG_L1TF
);