arch/x86/kernel/cpu/bugs.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *  Copyright (C) 1994  Linus Torvalds
   4  *
   5  *  Cyrix stuff, June 1998 by:
   6  *      - Rafael R. Reilova (moved everything from head.S),
   7  *        <rreilova@ececs.uc.edu>
   8  *      - Channing Corn (tests & fixes),
   9  *      - Andrew D. Balsa (code cleanup).
  10  */
  11 #include <linux/init.h>
  12 #include <linux/utsname.h>
  13 #include <linux/cpu.h>
  14 #include <linux/module.h>
  15 #include <linux/nospec.h>
  16 #include <linux/prctl.h>
  17
  18 #include <asm/spec-ctrl.h>
  19 #include <asm/cmdline.h>
  20 #include <asm/bugs.h>
  21 #include <asm/processor.h>
  22 #include <asm/processor-flags.h>
  23 #include <asm/fpu/internal.h>
  24 #include <asm/msr.h>
  25 #include <asm/paravirt.h>
  26 #include <asm/alternative.h>
  27 #include <asm/pgtable.h>
  28 #include <asm/set_memory.h>
  29 #include <asm/intel-family.h>
  30 #include <asm/e820/api.h>
  31
  32 static void __init spectre_v2_select_mitigation(void);
  33 static void __init ssb_select_mitigation(void);
  34 static void __init l1tf_select_mitigation(void);
  35
  36 /*
  37  * Our boot-time value of the SPEC_CTRL MSR. We read it once so that any
  38  * writes to SPEC_CTRL contain whatever reserved bits have been set.
  39  */
  40 u64 __ro_after_init x86_spec_ctrl_base;
  41 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base);
  42
  43 /*
  44  * The vendor and possibly platform specific bits which can be modified in
  45  * x86_spec_ctrl_base.
  46  */
  47 static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS;
  48
  49 /*
  50  * AMD specific MSR info for Speculative Store Bypass control.
  51  * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
  52  */
  53 u64 __ro_after_init x86_amd_ls_cfg_base;
  54 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask;
  55
  56 void __init check_bugs(void)
  57 {
  58         identify_boot_cpu();
  59
  60         if (!IS_ENABLED(CONFIG_SMP)) {
  61                 pr_info("CPU: ");
  62                 print_cpu_info(&boot_cpu_data);
  63         }
  64
  65         /*
  66          * Read the SPEC_CTRL MSR to account for reserved bits which may
  67          * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
  68          * init code as it is not enumerated and depends on the family.
  69          */
  70         if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
  71                 rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
  72
  73         /* Allow STIBP in MSR_SPEC_CTRL if supported */
  74         if (boot_cpu_has(X86_FEATURE_STIBP))
  75                 x86_spec_ctrl_mask |= SPEC_CTRL_STIBP;
  76
  77         /* Select the proper spectre mitigation before patching alternatives */
  78         spectre_v2_select_mitigation();
  79
  80         /*
  81          * Select proper mitigation for any exposure to the Speculative Store
  82          * Bypass vulnerability.
  83          */
  84         ssb_select_mitigation();
  85
  86         l1tf_select_mitigation();
  87
  88 #ifdef CONFIG_X86_32
  89         /*
  90          * Check whether we are able to run this kernel safely on SMP.
  91          *
  92          * - i386 is no longer supported.
  93          * - In order to run on anything without a TSC, we need to be
  94          *   compiled for a i486.
  95          */
  96         if (boot_cpu_data.x86 < 4)
  97                 panic("Kernel requires i486+ for 'invlpg' and other features");
  98
  99         init_utsname()->machine[1] =
 100                 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
 101         alternative_instructions();
 102
 103         fpu__init_check_bugs();
 104 #else /* CONFIG_X86_64 */
 105         alternative_instructions();
 106
 107         /*
 108          * Make sure the first 2MB area is not mapped by huge pages
 109          * There are typically fixed size MTRRs in there and overlapping
 110          * MTRRs into large pages causes slow downs.
 111          *
 112          * Right now we don't do that with gbpages because there seems
 113          * very little benefit for that case.
 114          */
 115         if (!direct_gbpages)
 116                 set_memory_4k((unsigned long)__va(0), 1);
 117 #endif
 118 }
 119
 120 /* The kernel command line selection */
 121 enum spectre_v2_mitigation_cmd {
 122         SPECTRE_V2_CMD_NONE,
 123         SPECTRE_V2_CMD_AUTO,
 124         SPECTRE_V2_CMD_FORCE,
 125         SPECTRE_V2_CMD_RETPOLINE,
 126         SPECTRE_V2_CMD_RETPOLINE_GENERIC,
 127         SPECTRE_V2_CMD_RETPOLINE_AMD,
 128 };
 129
 130 static const char *spectre_v2_strings[] = {
 131         [SPECTRE_V2_NONE]                       = "Vulnerable",
 132         [SPECTRE_V2_RETPOLINE_MINIMAL]          = "Vulnerable: Minimal generic ASM retpoline",
 133         [SPECTRE_V2_RETPOLINE_MINIMAL_AMD]      = "Vulnerable: Minimal AMD ASM retpoline",
 134         [SPECTRE_V2_RETPOLINE_GENERIC]          = "Mitigation: Full generic retpoline",
 135         [SPECTRE_V2_RETPOLINE_AMD]              = "Mitigation: Full AMD retpoline",
 136 };
 137
 138 #undef pr_fmt
 139 #define pr_fmt(fmt)     "Spectre V2 : " fmt
 140
 141 static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init =
 142         SPECTRE_V2_NONE;
 143
 144 void
 145 x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest)
 146 {
 147         u64 msrval, guestval, hostval = x86_spec_ctrl_base;
 148         struct thread_info *ti = current_thread_info();
 149
 150         /* Is MSR_SPEC_CTRL implemented ? */
 151         if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) {
 152                 /*
 153                  * Restrict guest_spec_ctrl to supported values. Clear the
 154                  * modifiable bits in the host base value and or the
 155                  * modifiable bits from the guest value.
 156                  */
 157                 guestval = hostval & ~x86_spec_ctrl_mask;
 158                 guestval |= guest_spec_ctrl & x86_spec_ctrl_mask;
 159
 160                 /* SSBD controlled in MSR_SPEC_CTRL */
 161                 if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD))
 162                         hostval |= ssbd_tif_to_spec_ctrl(ti->flags);
 163
 164                 if (hostval != guestval) {
 165                         msrval = setguest ? guestval : hostval;
 166                         wrmsrl(MSR_IA32_SPEC_CTRL, msrval);
 167                 }
 168         }
 169
 170         /*
 171          * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
 172          * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
 173          */
 174         if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
 175             !static_cpu_has(X86_FEATURE_VIRT_SSBD))
 176                 return;
 177
 178         /*
 179          * If the host has SSBD mitigation enabled, force it in the host's
 180          * virtual MSR value. If its not permanently enabled, evaluate
 181          * current's TIF_SSBD thread flag.
 182          */
 183         if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE))
 184                 hostval = SPEC_CTRL_SSBD;
 185         else
 186                 hostval = ssbd_tif_to_spec_ctrl(ti->flags);
 187
 188         /* Sanitize the guest value */
 189         guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD;
 190
 191         if (hostval != guestval) {
 192                 unsigned long tif;
 193
 194                 tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) :
 195                                  ssbd_spec_ctrl_to_tif(hostval);
 196
 197                 speculative_store_bypass_update(tif);
 198         }
 199 }
 200 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl);
 201
 202 static void x86_amd_ssb_disable(void)
 203 {
 204         u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask;
 205
 206         if (boot_cpu_has(X86_FEATURE_VIRT_SSBD))
 207                 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD);
 208         else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))
 209                 wrmsrl(MSR_AMD64_LS_CFG, msrval);
 210 }
 211
 212 #ifdef RETPOLINE
 213 static bool spectre_v2_bad_module;
 214
 215 bool retpoline_module_ok(bool has_retpoline)
 216 {
 217         if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline)
 218                 return true;
 219
 220         pr_err("System may be vulnerable to spectre v2\n");
 221         spectre_v2_bad_module = true;
 222         return false;
 223 }
 224
 225 static inline const char *spectre_v2_module_string(void)
 226 {
 227         return spectre_v2_bad_module ? " - vulnerable module loaded" : "";
 228 }
 229 #else
 230 static inline const char *spectre_v2_module_string(void) { return ""; }
 231 #endif
 232
 233 static void __init spec2_print_if_insecure(const char *reason)
 234 {
 235         if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
 236                 pr_info("%s selected on command line.\n", reason);
 237 }
 238
 239 static void __init spec2_print_if_secure(const char *reason)
 240 {
 241         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
 242                 pr_info("%s selected on command line.\n", reason);
 243 }
 244
 245 static inline bool retp_compiler(void)
 246 {
 247         return __is_defined(RETPOLINE);
 248 }
 249
 250 static inline bool match_option(const char *arg, int arglen, const char *opt)
 251 {
 252         int len = strlen(opt);
 253
 254         return len == arglen && !strncmp(arg, opt, len);
 255 }
 256
 257 static const struct {
 258         const char *option;
 259         enum spectre_v2_mitigation_cmd cmd;
 260         bool secure;
 261 } mitigation_options[] = {
 262         { "off",               SPECTRE_V2_CMD_NONE,              false },
 263         { "on",                SPECTRE_V2_CMD_FORCE,             true },
 264         { "retpoline",         SPECTRE_V2_CMD_RETPOLINE,         false },
 265         { "retpoline,amd",     SPECTRE_V2_CMD_RETPOLINE_AMD,     false },
 266         { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false },
 267         { "auto",              SPECTRE_V2_CMD_AUTO,              false },
 268 };
 269
 270 static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
 271 {
 272         char arg[20];
 273         int ret, i;
 274         enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO;
 275
 276         if (cmdline_find_option_bool(boot_command_line, "nospectre_v2"))
 277                 return SPECTRE_V2_CMD_NONE;
 278         else {
 279                 ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg));
 280                 if (ret < 0)
 281                         return SPECTRE_V2_CMD_AUTO;
 282
 283                 for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) {
 284                         if (!match_option(arg, ret, mitigation_options[i].option))
 285                                 continue;
 286                         cmd = mitigation_options[i].cmd;
 287                         break;
 288                 }
 289
 290                 if (i >= ARRAY_SIZE(mitigation_options)) {
 291                         pr_err("unknown option (%s). Switching to AUTO select\n", arg);
 292                         return SPECTRE_V2_CMD_AUTO;
 293                 }
 294         }
 295
 296         if ((cmd == SPECTRE_V2_CMD_RETPOLINE ||
 297              cmd == SPECTRE_V2_CMD_RETPOLINE_AMD ||
 298              cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) &&
 299             !IS_ENABLED(CONFIG_RETPOLINE)) {
 300                 pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option);
 301                 return SPECTRE_V2_CMD_AUTO;
 302         }
 303
 304         if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD &&
 305             boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
 306                 pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n");
 307                 return SPECTRE_V2_CMD_AUTO;
 308         }
 309
 310         if (mitigation_options[i].secure)
 311                 spec2_print_if_secure(mitigation_options[i].option);
 312         else
 313                 spec2_print_if_insecure(mitigation_options[i].option);
 314
 315         return cmd;
 316 }
 317
 318 /* Check for Skylake-like CPUs (for RSB handling) */
 319 static bool __init is_skylake_era(void)
 320 {
 321         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
 322             boot_cpu_data.x86 == 6) {
 323                 switch (boot_cpu_data.x86_model) {
 324                 case INTEL_FAM6_SKYLAKE_MOBILE:
 325                 case INTEL_FAM6_SKYLAKE_DESKTOP:
 326                 case INTEL_FAM6_SKYLAKE_X:
 327                 case INTEL_FAM6_KABYLAKE_MOBILE:
 328                 case INTEL_FAM6_KABYLAKE_DESKTOP:
 329                         return true;
 330                 }
 331         }
 332         return false;
 333 }
 334
 335 static void __init spectre_v2_select_mitigation(void)
 336 {
 337         enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
 338         enum spectre_v2_mitigation mode = SPECTRE_V2_NONE;
 339
 340         /*
 341          * If the CPU is not affected and the command line mode is NONE or AUTO
 342          * then nothing to do.
 343          */
 344         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) &&
 345             (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO))
 346                 return;
 347
 348         switch (cmd) {
 349         case SPECTRE_V2_CMD_NONE:
 350                 return;
 351
 352         case SPECTRE_V2_CMD_FORCE:
 353         case SPECTRE_V2_CMD_AUTO:
 354                 if (IS_ENABLED(CONFIG_RETPOLINE))
 355                         goto retpoline_auto;
 356                 break;
 357         case SPECTRE_V2_CMD_RETPOLINE_AMD:
 358                 if (IS_ENABLED(CONFIG_RETPOLINE))
 359                         goto retpoline_amd;
 360                 break;
 361         case SPECTRE_V2_CMD_RETPOLINE_GENERIC:
 362                 if (IS_ENABLED(CONFIG_RETPOLINE))
 363                         goto retpoline_generic;
 364                 break;
 365         case SPECTRE_V2_CMD_RETPOLINE:
 366                 if (IS_ENABLED(CONFIG_RETPOLINE))
 367                         goto retpoline_auto;
 368                 break;
 369         }
 370         pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!");
 371         return;
 372
 373 retpoline_auto:
 374         if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
 375         retpoline_amd:
 376                 if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
 377                         pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n");
 378                         goto retpoline_generic;
 379                 }
 380                 mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_AMD :
 381                                          SPECTRE_V2_RETPOLINE_MINIMAL_AMD;
 382                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD);
 383                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
 384         } else {
 385         retpoline_generic:
 386                 mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_GENERIC :
 387                                          SPECTRE_V2_RETPOLINE_MINIMAL;
 388                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
 389         }
 390
 391         spectre_v2_enabled = mode;
 392         pr_info("%s\n", spectre_v2_strings[mode]);
 393
 394         /*
 395          * If neither SMEP nor PTI are available, there is a risk of
 396          * hitting userspace addresses in the RSB after a context switch
 397          * from a shallow call stack to a deeper one. To prevent this fill
 398          * the entire RSB, even when using IBRS.
 399          *
 400          * Skylake era CPUs have a separate issue with *underflow* of the
 401          * RSB, when they will predict 'ret' targets from the generic BTB.
 402          * The proper mitigation for this is IBRS. If IBRS is not supported
 403          * or deactivated in favour of retpolines the RSB fill on context
 404          * switch is required.
 405          */
 406         if ((!boot_cpu_has(X86_FEATURE_PTI) &&
 407              !boot_cpu_has(X86_FEATURE_SMEP)) || is_skylake_era()) {
 408                 setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
 409                 pr_info("Spectre v2 mitigation: Filling RSB on context switch\n");
 410         }
 411
 412         /* Initialize Indirect Branch Prediction Barrier if supported */
 413         if (boot_cpu_has(X86_FEATURE_IBPB)) {
 414                 setup_force_cpu_cap(X86_FEATURE_USE_IBPB);
 415                 pr_info("Spectre v2 mitigation: Enabling Indirect Branch Prediction Barrier\n");
 416         }
 417
 418         /*
 419          * Retpoline means the kernel is safe because it has no indirect
 420          * branches. But firmware isn't, so use IBRS to protect that.
 421          */
 422         if (boot_cpu_has(X86_FEATURE_IBRS)) {
 423                 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW);
 424                 pr_info("Enabling Restricted Speculation for firmware calls\n");
 425         }
 426 }
 427
 428 #undef pr_fmt
 429 #define pr_fmt(fmt)     "Speculative Store Bypass: " fmt
 430
 431 static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE;
 432
 433 /* The kernel command line selection */
 434 enum ssb_mitigation_cmd {
 435         SPEC_STORE_BYPASS_CMD_NONE,
 436         SPEC_STORE_BYPASS_CMD_AUTO,
 437         SPEC_STORE_BYPASS_CMD_ON,
 438         SPEC_STORE_BYPASS_CMD_PRCTL,
 439         SPEC_STORE_BYPASS_CMD_SECCOMP,
 440 };
 441
 442 static const char *ssb_strings[] = {
 443         [SPEC_STORE_BYPASS_NONE]        = "Vulnerable",
 444         [SPEC_STORE_BYPASS_DISABLE]     = "Mitigation: Speculative Store Bypass disabled",
 445         [SPEC_STORE_BYPASS_PRCTL]       = "Mitigation: Speculative Store Bypass disabled via prctl",
 446         [SPEC_STORE_BYPASS_SECCOMP]     = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
 447 };
 448
 449 static const struct {
 450         const char *option;
 451         enum ssb_mitigation_cmd cmd;
 452 } ssb_mitigation_options[] = {
 453         { "auto",       SPEC_STORE_BYPASS_CMD_AUTO },    /* Platform decides */
 454         { "on",         SPEC_STORE_BYPASS_CMD_ON },      /* Disable Speculative Store Bypass */
 455         { "off",        SPEC_STORE_BYPASS_CMD_NONE },    /* Don't touch Speculative Store Bypass */
 456         { "prctl",      SPEC_STORE_BYPASS_CMD_PRCTL },   /* Disable Speculative Store Bypass via prctl */
 457         { "seccomp",    SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */
 458 };
 459
 460 static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void)
 461 {
 462         enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO;
 463         char arg[20];
 464         int ret, i;
 465
 466         if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable")) {
 467                 return SPEC_STORE_BYPASS_CMD_NONE;
 468         } else {
 469                 ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable",
 470                                           arg, sizeof(arg));
 471                 if (ret < 0)
 472                         return SPEC_STORE_BYPASS_CMD_AUTO;
 473
 474                 for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) {
 475                         if (!match_option(arg, ret, ssb_mitigation_options[i].option))
 476                                 continue;
 477
 478                         cmd = ssb_mitigation_options[i].cmd;
 479                         break;
 480                 }
 481
 482                 if (i >= ARRAY_SIZE(ssb_mitigation_options)) {
 483                         pr_err("unknown option (%s). Switching to AUTO select\n", arg);
 484                         return SPEC_STORE_BYPASS_CMD_AUTO;
 485                 }
 486         }
 487
 488         return cmd;
 489 }
 490
 491 static enum ssb_mitigation __init __ssb_select_mitigation(void)
 492 {
 493         enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE;
 494         enum ssb_mitigation_cmd cmd;
 495
 496         if (!boot_cpu_has(X86_FEATURE_SSBD))
 497                 return mode;
 498
 499         cmd = ssb_parse_cmdline();
 500         if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) &&
 501             (cmd == SPEC_STORE_BYPASS_CMD_NONE ||
 502              cmd == SPEC_STORE_BYPASS_CMD_AUTO))
 503                 return mode;
 504
 505         switch (cmd) {
 506         case SPEC_STORE_BYPASS_CMD_AUTO:
 507         case SPEC_STORE_BYPASS_CMD_SECCOMP:
 508                 /*
 509                  * Choose prctl+seccomp as the default mode if seccomp is
 510                  * enabled.
 511                  */
 512                 if (IS_ENABLED(CONFIG_SECCOMP))
 513                         mode = SPEC_STORE_BYPASS_SECCOMP;
 514                 else
 515                         mode = SPEC_STORE_BYPASS_PRCTL;
 516                 break;
 517         case SPEC_STORE_BYPASS_CMD_ON:
 518                 mode = SPEC_STORE_BYPASS_DISABLE;
 519                 break;
 520         case SPEC_STORE_BYPASS_CMD_PRCTL:
 521                 mode = SPEC_STORE_BYPASS_PRCTL;
 522                 break;
 523         case SPEC_STORE_BYPASS_CMD_NONE:
 524                 break;
 525         }
 526
 527         /*
 528          * We have three CPU feature flags that are in play here:
 529          *  - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
 530          *  - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
 531          *  - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
 532          */
 533         if (mode == SPEC_STORE_BYPASS_DISABLE) {
 534                 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE);
 535                 /*
 536                  * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD uses
 537                  * a completely different MSR and bit dependent on family.
 538                  */
 539                 switch (boot_cpu_data.x86_vendor) {
 540                 case X86_VENDOR_INTEL:
 541                         x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
 542                         x86_spec_ctrl_mask |= SPEC_CTRL_SSBD;
 543                         wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
 544                         break;
 545                 case X86_VENDOR_AMD:
 546                         x86_amd_ssb_disable();
 547                         break;
 548                 }
 549         }
 550
 551         return mode;
 552 }
 553
 554 static void ssb_select_mitigation(void)
 555 {
 556         ssb_mode = __ssb_select_mitigation();
 557
 558         if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
 559                 pr_info("%s\n", ssb_strings[ssb_mode]);
 560 }
 561
 562 #undef pr_fmt
 563 #define pr_fmt(fmt)     "Speculation prctl: " fmt
 564
 565 static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl)
 566 {
 567         bool update;
 568
 569         if (ssb_mode != SPEC_STORE_BYPASS_PRCTL &&
 570             ssb_mode != SPEC_STORE_BYPASS_SECCOMP)
 571                 return -ENXIO;
 572
 573         switch (ctrl) {
 574         case PR_SPEC_ENABLE:
 575                 /* If speculation is force disabled, enable is not allowed */
 576                 if (task_spec_ssb_force_disable(task))
 577                         return -EPERM;
 578                 task_clear_spec_ssb_disable(task);
 579                 update = test_and_clear_tsk_thread_flag(task, TIF_SSBD);
 580                 break;
 581         case PR_SPEC_DISABLE:
 582                 task_set_spec_ssb_disable(task);
 583                 update = !test_and_set_tsk_thread_flag(task, TIF_SSBD);
 584                 break;
 585         case PR_SPEC_FORCE_DISABLE:
 586                 task_set_spec_ssb_disable(task);
 587                 task_set_spec_ssb_force_disable(task);
 588                 update = !test_and_set_tsk_thread_flag(task, TIF_SSBD);
 589                 break;
 590         default:
 591                 return -ERANGE;
 592         }
 593
 594         /*
 595          * If being set on non-current task, delay setting the CPU
 596          * mitigation until it is next scheduled.
 597          */
 598         if (task == current && update)
 599                 speculative_store_bypass_update_current();
 600
 601         return 0;
 602 }
 603
 604 int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which,
 605                              unsigned long ctrl)
 606 {
 607         switch (which) {
 608         case PR_SPEC_STORE_BYPASS:
 609                 return ssb_prctl_set(task, ctrl);
 610         default:
 611                 return -ENODEV;
 612         }
 613 }
 614
 615 #ifdef CONFIG_SECCOMP
 616 void arch_seccomp_spec_mitigate(struct task_struct *task)
 617 {
 618         if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP)
 619                 ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE);
 620 }
 621 #endif
 622
 623 static int ssb_prctl_get(struct task_struct *task)
 624 {
 625         switch (ssb_mode) {
 626         case SPEC_STORE_BYPASS_DISABLE:
 627                 return PR_SPEC_DISABLE;
 628         case SPEC_STORE_BYPASS_SECCOMP:
 629         case SPEC_STORE_BYPASS_PRCTL:
 630                 if (task_spec_ssb_force_disable(task))
 631                         return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
 632                 if (task_spec_ssb_disable(task))
 633                         return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
 634                 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
 635         default:
 636                 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
 637                         return PR_SPEC_ENABLE;
 638                 return PR_SPEC_NOT_AFFECTED;
 639         }
 640 }
 641
 642 int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
 643 {
 644         switch (which) {
 645         case PR_SPEC_STORE_BYPASS:
 646                 return ssb_prctl_get(task);
 647         default:
 648                 return -ENODEV;
 649         }
 650 }
 651
 652 void x86_spec_ctrl_setup_ap(void)
 653 {
 654         if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
 655                 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
 656
 657         if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
 658                 x86_amd_ssb_disable();
 659 }
 660
 661 #undef pr_fmt
 662 #define pr_fmt(fmt)     "L1TF: " fmt
 663 static void __init l1tf_select_mitigation(void)
 664 {
 665         u64 half_pa;
 666
 667         if (!boot_cpu_has_bug(X86_BUG_L1TF))
 668                 return;
 669
 670 #if CONFIG_PGTABLE_LEVELS == 2
 671         pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n");
 672         return;
 673 #endif
 674
 675         /*
 676          * This is extremely unlikely to happen because almost all
 677          * systems have far more MAX_PA/2 than RAM can be fit into
 678          * DIMM slots.
 679          */
 680         half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT;
 681         if (e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) {
 682                 pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n");
 683                 return;
 684         }
 685
 686         setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV);
 687 }
 688 #undef pr_fmt
 689
 690 #ifdef CONFIG_SYSFS
 691
 692 static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr,
 693                                char *buf, unsigned int bug)
 694 {
 695         if (!boot_cpu_has_bug(bug))
 696                 return sprintf(buf, "Not affected\n");
 697
 698         switch (bug) {
 699         case X86_BUG_CPU_MELTDOWN:
 700                 if (boot_cpu_has(X86_FEATURE_PTI))
 701                         return sprintf(buf, "Mitigation: PTI\n");
 702
 703                 break;
 704
 705         case X86_BUG_SPECTRE_V1:
 706                 return sprintf(buf, "Mitigation: __user pointer sanitization\n");
 707
 708         case X86_BUG_SPECTRE_V2:
 709                 return sprintf(buf, "%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled],
 710                                boot_cpu_has(X86_FEATURE_USE_IBPB) ? ", IBPB" : "",
 711                                boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "",
 712                                spectre_v2_module_string());
 713
 714         case X86_BUG_SPEC_STORE_BYPASS:
 715                 return sprintf(buf, "%s\n", ssb_strings[ssb_mode]);
 716
 717         case X86_BUG_L1TF:
 718                 if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV))
 719                         return sprintf(buf, "Mitigation: Page Table Inversion\n");
 720                 break;
 721
 722         default:
 723                 break;
 724         }
 725
 726         return sprintf(buf, "Vulnerable\n");
 727 }
 728
 729 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf)
 730 {
 731         return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN);
 732 }
 733
 734 ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf)
 735 {
 736         return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1);
 737 }
 738
 739 ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf)
 740 {
 741         return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2);
 742 }
 743
 744 ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf)
 745 {
 746         return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS);
 747 }
 748
 749 ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf)
 750 {
 751         return cpu_show_common(dev, attr, buf, X86_BUG_L1TF);
 752 }
 753 #endif