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scsi: ips: fix missing break in switch
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / ips.c
1 /*****************************************************************************/
2 /* ips.c -- driver for the Adaptec / IBM ServeRAID controller */
3 /* */
4 /* Written By: Keith Mitchell, IBM Corporation */
5 /* Jack Hammer, Adaptec, Inc. */
6 /* David Jeffery, Adaptec, Inc. */
7 /* */
8 /* Copyright (C) 2000 IBM Corporation */
9 /* Copyright (C) 2002,2003 Adaptec, Inc. */
10 /* */
11 /* This program is free software; you can redistribute it and/or modify */
12 /* it under the terms of the GNU General Public License as published by */
13 /* the Free Software Foundation; either version 2 of the License, or */
14 /* (at your option) any later version. */
15 /* */
16 /* This program is distributed in the hope that it will be useful, */
17 /* but WITHOUT ANY WARRANTY; without even the implied warranty of */
18 /* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */
19 /* GNU General Public License for more details. */
20 /* */
21 /* NO WARRANTY */
22 /* THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR */
23 /* CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT */
24 /* LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, */
25 /* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is */
26 /* solely responsible for determining the appropriateness of using and */
27 /* distributing the Program and assumes all risks associated with its */
28 /* exercise of rights under this Agreement, including but not limited to */
29 /* the risks and costs of program errors, damage to or loss of data, */
30 /* programs or equipment, and unavailability or interruption of operations. */
31 /* */
32 /* DISCLAIMER OF LIABILITY */
33 /* NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY */
34 /* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL */
35 /* DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND */
36 /* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR */
37 /* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE */
38 /* USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED */
39 /* HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES */
40 /* */
41 /* You should have received a copy of the GNU General Public License */
42 /* along with this program; if not, write to the Free Software */
43 /* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
44 /* */
45 /* Bugs/Comments/Suggestions about this driver should be mailed to: */
46 /* ipslinux@adaptec.com */
47 /* */
48 /* For system support issues, contact your local IBM Customer support. */
49 /* Directions to find IBM Customer Support for each country can be found at: */
50 /* http://www.ibm.com/planetwide/ */
51 /* */
52 /*****************************************************************************/
53
54 /*****************************************************************************/
55 /* Change Log */
56 /* */
57 /* 0.99.02 - Breakup commands that are bigger than 8 * the stripe size */
58 /* 0.99.03 - Make interrupt routine handle all completed request on the */
59 /* adapter not just the first one */
60 /* - Make sure passthru commands get woken up if we run out of */
61 /* SCBs */
62 /* - Send all of the commands on the queue at once rather than */
63 /* one at a time since the card will support it. */
64 /* 0.99.04 - Fix race condition in the passthru mechanism -- this required */
65 /* the interface to the utilities to change */
66 /* - Fix error recovery code */
67 /* 0.99.05 - Fix an oops when we get certain passthru commands */
68 /* 1.00.00 - Initial Public Release */
69 /* Functionally equivalent to 0.99.05 */
70 /* 3.60.00 - Bump max commands to 128 for use with firmware 3.60 */
71 /* - Change version to 3.60 to coincide with release numbering. */
72 /* 3.60.01 - Remove bogus error check in passthru routine */
73 /* 3.60.02 - Make DCDB direction based on lookup table */
74 /* - Only allow one DCDB command to a SCSI ID at a time */
75 /* 4.00.00 - Add support for ServeRAID 4 */
76 /* 4.00.01 - Add support for First Failure Data Capture */
77 /* 4.00.02 - Fix problem with PT DCDB with no buffer */
78 /* 4.00.03 - Add alternative passthru interface */
79 /* - Add ability to flash BIOS */
80 /* 4.00.04 - Rename structures/constants to be prefixed with IPS_ */
81 /* 4.00.05 - Remove wish_block from init routine */
82 /* - Use linux/spinlock.h instead of asm/spinlock.h for kernels */
83 /* 2.3.18 and later */
84 /* - Sync with other changes from the 2.3 kernels */
85 /* 4.00.06 - Fix timeout with initial FFDC command */
86 /* 4.00.06a - Port to 2.4 (trivial) -- Christoph Hellwig <hch@infradead.org> */
87 /* 4.10.00 - Add support for ServeRAID 4M/4L */
88 /* 4.10.13 - Fix for dynamic unload and proc file system */
89 /* 4.20.03 - Rename version to coincide with new release schedules */
90 /* Performance fixes */
91 /* Fix truncation of /proc files with cat */
92 /* Merge in changes through kernel 2.4.0test1ac21 */
93 /* 4.20.13 - Fix some failure cases / reset code */
94 /* - Hook into the reboot_notifier to flush the controller cache */
95 /* 4.50.01 - Fix problem when there is a hole in logical drive numbering */
96 /* 4.70.09 - Use a Common ( Large Buffer ) for Flashing from the JCRM CD */
97 /* - Add IPSSEND Flash Support */
98 /* - Set Sense Data for Unknown SCSI Command */
99 /* - Use Slot Number from NVRAM Page 5 */
100 /* - Restore caller's DCDB Structure */
101 /* 4.70.12 - Corrective actions for bad controller ( during initialization )*/
102 /* 4.70.13 - Don't Send CDB's if we already know the device is not present */
103 /* - Don't release HA Lock in ips_next() until SC taken off queue */
104 /* - Unregister SCSI device in ips_release() */
105 /* 4.70.15 - Fix Breakup for very large ( non-SG ) requests in ips_done() */
106 /* 4.71.00 - Change all memory allocations to not use GFP_DMA flag */
107 /* Code Clean-Up for 2.4.x kernel */
108 /* 4.72.00 - Allow for a Scatter-Gather Element to exceed MAX_XFER Size */
109 /* 4.72.01 - I/O Mapped Memory release ( so "insmod ips" does not Fail ) */
110 /* - Don't Issue Internal FFDC Command if there are Active Commands */
111 /* - Close Window for getting too many IOCTL's active */
112 /* 4.80.00 - Make ia64 Safe */
113 /* 4.80.04 - Eliminate calls to strtok() if 2.4.x or greater */
114 /* - Adjustments to Device Queue Depth */
115 /* 4.80.14 - Take all semaphores off stack */
116 /* - Clean Up New_IOCTL path */
117 /* 4.80.20 - Set max_sectors in Scsi_Host structure ( if >= 2.4.7 kernel ) */
118 /* - 5 second delay needed after resetting an i960 adapter */
119 /* 4.80.26 - Clean up potential code problems ( Arjan's recommendations ) */
120 /* 4.90.01 - Version Matching for FirmWare, BIOS, and Driver */
121 /* 4.90.05 - Use New PCI Architecture to facilitate Hot Plug Development */
122 /* 4.90.08 - Increase Delays in Flashing ( Trombone Only - 4H ) */
123 /* 4.90.08 - Data Corruption if First Scatter Gather Element is > 64K */
124 /* 4.90.11 - Don't actually RESET unless it's physically required */
125 /* - Remove unused compile options */
126 /* 5.00.01 - Sarasota ( 5i ) adapters must always be scanned first */
127 /* - Get rid on IOCTL_NEW_COMMAND code */
128 /* - Add Extended DCDB Commands for Tape Support in 5I */
129 /* 5.10.12 - use pci_dma interfaces, update for 2.5 kernel changes */
130 /* 5.10.15 - remove unused code (sem, macros, etc.) */
131 /* 5.30.00 - use __devexit_p() */
132 /* 6.00.00 - Add 6x Adapters and Battery Flash */
133 /* 6.10.00 - Remove 1G Addressing Limitations */
134 /* 6.11.xx - Get VersionInfo buffer off the stack ! DDTS 60401 */
135 /* 6.11.xx - Make Logical Drive Info structure safe for DMA DDTS 60639 */
136 /* 7.10.18 - Add highmem_io flag in SCSI Templete for 2.4 kernels */
137 /* - Fix path/name for scsi_hosts.h include for 2.6 kernels */
138 /* - Fix sort order of 7k */
139 /* - Remove 3 unused "inline" functions */
140 /* 7.12.xx - Use STATIC functions wherever possible */
141 /* - Clean up deprecated MODULE_PARM calls */
142 /* 7.12.05 - Remove Version Matching per IBM request */
143 /*****************************************************************************/
144
145 /*
146 * Conditional Compilation directives for this driver:
147 *
148 * IPS_DEBUG - Turn on debugging info
149 *
150 * Parameters:
151 *
152 * debug:<number> - Set debug level to <number>
153 * NOTE: only works when IPS_DEBUG compile directive is used.
154 * 1 - Normal debug messages
155 * 2 - Verbose debug messages
156 * 11 - Method trace (non interrupt)
157 * 12 - Method trace (includes interrupt)
158 *
159 * noi2o - Don't use I2O Queues (ServeRAID 4 only)
160 * nommap - Don't use memory mapped I/O
161 * ioctlsize - Initial size of the IOCTL buffer
162 */
163
164 #include <asm/io.h>
165 #include <asm/byteorder.h>
166 #include <asm/page.h>
167 #include <linux/stddef.h>
168 #include <linux/string.h>
169 #include <linux/errno.h>
170 #include <linux/kernel.h>
171 #include <linux/ioport.h>
172 #include <linux/slab.h>
173 #include <linux/delay.h>
174 #include <linux/pci.h>
175 #include <linux/proc_fs.h>
176 #include <linux/reboot.h>
177 #include <linux/interrupt.h>
178
179 #include <linux/blkdev.h>
180 #include <linux/types.h>
181 #include <linux/dma-mapping.h>
182
183 #include <scsi/sg.h>
184 #include "scsi.h"
185 #include <scsi/scsi_host.h>
186
187 #include "ips.h"
188
189 #include <linux/module.h>
190
191 #include <linux/stat.h>
192
193 #include <linux/spinlock.h>
194 #include <linux/init.h>
195
196 #include <linux/smp.h>
197
198 #ifdef MODULE
199 static char *ips = NULL;
200 module_param(ips, charp, 0);
201 #endif
202
203 /*
204 * DRIVER_VER
205 */
206 #define IPS_VERSION_HIGH IPS_VER_MAJOR_STRING "." IPS_VER_MINOR_STRING
207 #define IPS_VERSION_LOW "." IPS_VER_BUILD_STRING " "
208
209 #define IPS_DMA_DIR(scb) ((!scb->scsi_cmd || ips_is_passthru(scb->scsi_cmd) || \
210 DMA_NONE == scb->scsi_cmd->sc_data_direction) ? \
211 PCI_DMA_BIDIRECTIONAL : \
212 scb->scsi_cmd->sc_data_direction)
213
214 #ifdef IPS_DEBUG
215 #define METHOD_TRACE(s, i) if (ips_debug >= (i+10)) printk(KERN_NOTICE s "\n");
216 #define DEBUG(i, s) if (ips_debug >= i) printk(KERN_NOTICE s "\n");
217 #define DEBUG_VAR(i, s, v...) if (ips_debug >= i) printk(KERN_NOTICE s "\n", v);
218 #else
219 #define METHOD_TRACE(s, i)
220 #define DEBUG(i, s)
221 #define DEBUG_VAR(i, s, v...)
222 #endif
223
224 /*
225 * Function prototypes
226 */
227 static int ips_detect(struct scsi_host_template *);
228 static int ips_release(struct Scsi_Host *);
229 static int ips_eh_abort(struct scsi_cmnd *);
230 static int ips_eh_reset(struct scsi_cmnd *);
231 static int ips_queue(struct Scsi_Host *, struct scsi_cmnd *);
232 static const char *ips_info(struct Scsi_Host *);
233 static irqreturn_t do_ipsintr(int, void *);
234 static int ips_hainit(ips_ha_t *);
235 static int ips_map_status(ips_ha_t *, ips_scb_t *, ips_stat_t *);
236 static int ips_send_wait(ips_ha_t *, ips_scb_t *, int, int);
237 static int ips_send_cmd(ips_ha_t *, ips_scb_t *);
238 static int ips_online(ips_ha_t *, ips_scb_t *);
239 static int ips_inquiry(ips_ha_t *, ips_scb_t *);
240 static int ips_rdcap(ips_ha_t *, ips_scb_t *);
241 static int ips_msense(ips_ha_t *, ips_scb_t *);
242 static int ips_reqsen(ips_ha_t *, ips_scb_t *);
243 static int ips_deallocatescbs(ips_ha_t *, int);
244 static int ips_allocatescbs(ips_ha_t *);
245 static int ips_reset_copperhead(ips_ha_t *);
246 static int ips_reset_copperhead_memio(ips_ha_t *);
247 static int ips_reset_morpheus(ips_ha_t *);
248 static int ips_issue_copperhead(ips_ha_t *, ips_scb_t *);
249 static int ips_issue_copperhead_memio(ips_ha_t *, ips_scb_t *);
250 static int ips_issue_i2o(ips_ha_t *, ips_scb_t *);
251 static int ips_issue_i2o_memio(ips_ha_t *, ips_scb_t *);
252 static int ips_isintr_copperhead(ips_ha_t *);
253 static int ips_isintr_copperhead_memio(ips_ha_t *);
254 static int ips_isintr_morpheus(ips_ha_t *);
255 static int ips_wait(ips_ha_t *, int, int);
256 static int ips_write_driver_status(ips_ha_t *, int);
257 static int ips_read_adapter_status(ips_ha_t *, int);
258 static int ips_read_subsystem_parameters(ips_ha_t *, int);
259 static int ips_read_config(ips_ha_t *, int);
260 static int ips_clear_adapter(ips_ha_t *, int);
261 static int ips_readwrite_page5(ips_ha_t *, int, int);
262 static int ips_init_copperhead(ips_ha_t *);
263 static int ips_init_copperhead_memio(ips_ha_t *);
264 static int ips_init_morpheus(ips_ha_t *);
265 static int ips_isinit_copperhead(ips_ha_t *);
266 static int ips_isinit_copperhead_memio(ips_ha_t *);
267 static int ips_isinit_morpheus(ips_ha_t *);
268 static int ips_erase_bios(ips_ha_t *);
269 static int ips_program_bios(ips_ha_t *, char *, uint32_t, uint32_t);
270 static int ips_verify_bios(ips_ha_t *, char *, uint32_t, uint32_t);
271 static int ips_erase_bios_memio(ips_ha_t *);
272 static int ips_program_bios_memio(ips_ha_t *, char *, uint32_t, uint32_t);
273 static int ips_verify_bios_memio(ips_ha_t *, char *, uint32_t, uint32_t);
274 static int ips_flash_copperhead(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
275 static int ips_flash_bios(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
276 static int ips_flash_firmware(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
277 static void ips_free_flash_copperhead(ips_ha_t * ha);
278 static void ips_get_bios_version(ips_ha_t *, int);
279 static void ips_identify_controller(ips_ha_t *);
280 static void ips_chkstatus(ips_ha_t *, IPS_STATUS *);
281 static void ips_enable_int_copperhead(ips_ha_t *);
282 static void ips_enable_int_copperhead_memio(ips_ha_t *);
283 static void ips_enable_int_morpheus(ips_ha_t *);
284 static int ips_intr_copperhead(ips_ha_t *);
285 static int ips_intr_morpheus(ips_ha_t *);
286 static void ips_next(ips_ha_t *, int);
287 static void ipsintr_blocking(ips_ha_t *, struct ips_scb *);
288 static void ipsintr_done(ips_ha_t *, struct ips_scb *);
289 static void ips_done(ips_ha_t *, ips_scb_t *);
290 static void ips_free(ips_ha_t *);
291 static void ips_init_scb(ips_ha_t *, ips_scb_t *);
292 static void ips_freescb(ips_ha_t *, ips_scb_t *);
293 static void ips_setup_funclist(ips_ha_t *);
294 static void ips_statinit(ips_ha_t *);
295 static void ips_statinit_memio(ips_ha_t *);
296 static void ips_fix_ffdc_time(ips_ha_t *, ips_scb_t *, time_t);
297 static void ips_ffdc_reset(ips_ha_t *, int);
298 static void ips_ffdc_time(ips_ha_t *);
299 static uint32_t ips_statupd_copperhead(ips_ha_t *);
300 static uint32_t ips_statupd_copperhead_memio(ips_ha_t *);
301 static uint32_t ips_statupd_morpheus(ips_ha_t *);
302 static ips_scb_t *ips_getscb(ips_ha_t *);
303 static void ips_putq_scb_head(ips_scb_queue_t *, ips_scb_t *);
304 static void ips_putq_wait_tail(ips_wait_queue_entry_t *, struct scsi_cmnd *);
305 static void ips_putq_copp_tail(ips_copp_queue_t *,
306 ips_copp_wait_item_t *);
307 static ips_scb_t *ips_removeq_scb_head(ips_scb_queue_t *);
308 static ips_scb_t *ips_removeq_scb(ips_scb_queue_t *, ips_scb_t *);
309 static struct scsi_cmnd *ips_removeq_wait_head(ips_wait_queue_entry_t *);
310 static struct scsi_cmnd *ips_removeq_wait(ips_wait_queue_entry_t *,
311 struct scsi_cmnd *);
312 static ips_copp_wait_item_t *ips_removeq_copp(ips_copp_queue_t *,
313 ips_copp_wait_item_t *);
314 static ips_copp_wait_item_t *ips_removeq_copp_head(ips_copp_queue_t *);
315
316 static int ips_is_passthru(struct scsi_cmnd *);
317 static int ips_make_passthru(ips_ha_t *, struct scsi_cmnd *, ips_scb_t *, int);
318 static int ips_usrcmd(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
319 static void ips_cleanup_passthru(ips_ha_t *, ips_scb_t *);
320 static void ips_scmd_buf_write(struct scsi_cmnd * scmd, void *data,
321 unsigned int count);
322 static void ips_scmd_buf_read(struct scsi_cmnd * scmd, void *data,
323 unsigned int count);
324
325 static int ips_write_info(struct Scsi_Host *, char *, int);
326 static int ips_show_info(struct seq_file *, struct Scsi_Host *);
327 static int ips_host_info(ips_ha_t *, struct seq_file *);
328 static int ips_abort_init(ips_ha_t * ha, int index);
329 static int ips_init_phase2(int index);
330
331 static int ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr);
332 static int ips_register_scsi(int index);
333
334 static int ips_poll_for_flush_complete(ips_ha_t * ha);
335 static void ips_flush_and_reset(ips_ha_t *ha);
336
337 /*
338 * global variables
339 */
340 static const char ips_name[] = "ips";
341 static struct Scsi_Host *ips_sh[IPS_MAX_ADAPTERS]; /* Array of host controller structures */
342 static ips_ha_t *ips_ha[IPS_MAX_ADAPTERS]; /* Array of HA structures */
343 static unsigned int ips_next_controller;
344 static unsigned int ips_num_controllers;
345 static unsigned int ips_released_controllers;
346 static int ips_hotplug;
347 static int ips_cmd_timeout = 60;
348 static int ips_reset_timeout = 60 * 5;
349 static int ips_force_memio = 1; /* Always use Memory Mapped I/O */
350 static int ips_force_i2o = 1; /* Always use I2O command delivery */
351 static int ips_ioctlsize = IPS_IOCTL_SIZE; /* Size of the ioctl buffer */
352 static int ips_cd_boot; /* Booting from Manager CD */
353 static char *ips_FlashData = NULL; /* CD Boot - Flash Data Buffer */
354 static dma_addr_t ips_flashbusaddr;
355 static long ips_FlashDataInUse; /* CD Boot - Flash Data In Use Flag */
356 static uint32_t MaxLiteCmds = 32; /* Max Active Cmds for a Lite Adapter */
357 static struct scsi_host_template ips_driver_template = {
358 .detect = ips_detect,
359 .release = ips_release,
360 .info = ips_info,
361 .queuecommand = ips_queue,
362 .eh_abort_handler = ips_eh_abort,
363 .eh_host_reset_handler = ips_eh_reset,
364 .proc_name = "ips",
365 .show_info = ips_show_info,
366 .write_info = ips_write_info,
367 .slave_configure = ips_slave_configure,
368 .bios_param = ips_biosparam,
369 .this_id = -1,
370 .sg_tablesize = IPS_MAX_SG,
371 .cmd_per_lun = 3,
372 .use_clustering = ENABLE_CLUSTERING,
373 .no_write_same = 1,
374 };
375
376
377 /* This table describes all ServeRAID Adapters */
378 static struct pci_device_id ips_pci_table[] = {
379 { 0x1014, 0x002E, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
380 { 0x1014, 0x01BD, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
381 { 0x9005, 0x0250, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
382 { 0, }
383 };
384
385 MODULE_DEVICE_TABLE( pci, ips_pci_table );
386
387 static char ips_hot_plug_name[] = "ips";
388
389 static int ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent);
390 static void ips_remove_device(struct pci_dev *pci_dev);
391
392 static struct pci_driver ips_pci_driver = {
393 .name = ips_hot_plug_name,
394 .id_table = ips_pci_table,
395 .probe = ips_insert_device,
396 .remove = ips_remove_device,
397 };
398
399
400 /*
401 * Necessary forward function protoypes
402 */
403 static int ips_halt(struct notifier_block *nb, ulong event, void *buf);
404
405 #define MAX_ADAPTER_NAME 15
406
407 static char ips_adapter_name[][30] = {
408 "ServeRAID",
409 "ServeRAID II",
410 "ServeRAID on motherboard",
411 "ServeRAID on motherboard",
412 "ServeRAID 3H",
413 "ServeRAID 3L",
414 "ServeRAID 4H",
415 "ServeRAID 4M",
416 "ServeRAID 4L",
417 "ServeRAID 4Mx",
418 "ServeRAID 4Lx",
419 "ServeRAID 5i",
420 "ServeRAID 5i",
421 "ServeRAID 6M",
422 "ServeRAID 6i",
423 "ServeRAID 7t",
424 "ServeRAID 7k",
425 "ServeRAID 7M"
426 };
427
428 static struct notifier_block ips_notifier = {
429 ips_halt, NULL, 0
430 };
431
432 /*
433 * Direction table
434 */
435 static char ips_command_direction[] = {
436 IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT,
437 IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK,
438 IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
439 IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_OUT,
440 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_OUT,
441 IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_OUT,
442 IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_IN,
443 IPS_DATA_UNK, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK,
444 IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_UNK,
445 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT,
446 IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_NONE,
447 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT,
448 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT,
449 IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_NONE,
450 IPS_DATA_UNK, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_UNK,
451 IPS_DATA_NONE, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK,
452 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
453 IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
454 IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
455 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
456 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
457 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
458 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
459 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
460 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
461 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
462 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
463 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
464 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
465 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
466 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
467 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
468 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
469 IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_NONE,
470 IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_OUT,
471 IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_NONE,
472 IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_IN,
473 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
474 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
475 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
476 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
477 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
478 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
479 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
480 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
481 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
482 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_OUT,
483 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
484 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
485 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
486 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK
487 };
488
489
490 /****************************************************************************/
491 /* */
492 /* Routine Name: ips_setup */
493 /* */
494 /* Routine Description: */
495 /* */
496 /* setup parameters to the driver */
497 /* */
498 /****************************************************************************/
499 static int
500 ips_setup(char *ips_str)
501 {
502
503 int i;
504 char *key;
505 char *value;
506 IPS_OPTION options[] = {
507 {"noi2o", &ips_force_i2o, 0},
508 {"nommap", &ips_force_memio, 0},
509 {"ioctlsize", &ips_ioctlsize, IPS_IOCTL_SIZE},
510 {"cdboot", &ips_cd_boot, 0},
511 {"maxcmds", &MaxLiteCmds, 32},
512 };
513
514 /* Don't use strtok() anymore ( if 2.4 Kernel or beyond ) */
515 /* Search for value */
516 while ((key = strsep(&ips_str, ",."))) {
517 if (!*key)
518 continue;
519 value = strchr(key, ':');
520 if (value)
521 *value++ = '\0';
522 /*
523 * We now have key/value pairs.
524 * Update the variables
525 */
526 for (i = 0; i < ARRAY_SIZE(options); i++) {
527 if (strncasecmp
528 (key, options[i].option_name,
529 strlen(options[i].option_name)) == 0) {
530 if (value)
531 *options[i].option_flag =
532 simple_strtoul(value, NULL, 0);
533 else
534 *options[i].option_flag =
535 options[i].option_value;
536 break;
537 }
538 }
539 }
540
541 return (1);
542 }
543
544 __setup("ips=", ips_setup);
545
546 /****************************************************************************/
547 /* */
548 /* Routine Name: ips_detect */
549 /* */
550 /* Routine Description: */
551 /* */
552 /* Detect and initialize the driver */
553 /* */
554 /* NOTE: this routine is called under the io_request_lock spinlock */
555 /* */
556 /****************************************************************************/
557 static int
558 ips_detect(struct scsi_host_template * SHT)
559 {
560 int i;
561
562 METHOD_TRACE("ips_detect", 1);
563
564 #ifdef MODULE
565 if (ips)
566 ips_setup(ips);
567 #endif
568
569 for (i = 0; i < ips_num_controllers; i++) {
570 if (ips_register_scsi(i))
571 ips_free(ips_ha[i]);
572 ips_released_controllers++;
573 }
574 ips_hotplug = 1;
575 return (ips_num_controllers);
576 }
577
578 /****************************************************************************/
579 /* configure the function pointers to use the functions that will work */
580 /* with the found version of the adapter */
581 /****************************************************************************/
582 static void
583 ips_setup_funclist(ips_ha_t * ha)
584 {
585
586 /*
587 * Setup Functions
588 */
589 if (IPS_IS_MORPHEUS(ha) || IPS_IS_MARCO(ha)) {
590 /* morpheus / marco / sebring */
591 ha->func.isintr = ips_isintr_morpheus;
592 ha->func.isinit = ips_isinit_morpheus;
593 ha->func.issue = ips_issue_i2o_memio;
594 ha->func.init = ips_init_morpheus;
595 ha->func.statupd = ips_statupd_morpheus;
596 ha->func.reset = ips_reset_morpheus;
597 ha->func.intr = ips_intr_morpheus;
598 ha->func.enableint = ips_enable_int_morpheus;
599 } else if (IPS_USE_MEMIO(ha)) {
600 /* copperhead w/MEMIO */
601 ha->func.isintr = ips_isintr_copperhead_memio;
602 ha->func.isinit = ips_isinit_copperhead_memio;
603 ha->func.init = ips_init_copperhead_memio;
604 ha->func.statupd = ips_statupd_copperhead_memio;
605 ha->func.statinit = ips_statinit_memio;
606 ha->func.reset = ips_reset_copperhead_memio;
607 ha->func.intr = ips_intr_copperhead;
608 ha->func.erasebios = ips_erase_bios_memio;
609 ha->func.programbios = ips_program_bios_memio;
610 ha->func.verifybios = ips_verify_bios_memio;
611 ha->func.enableint = ips_enable_int_copperhead_memio;
612 if (IPS_USE_I2O_DELIVER(ha))
613 ha->func.issue = ips_issue_i2o_memio;
614 else
615 ha->func.issue = ips_issue_copperhead_memio;
616 } else {
617 /* copperhead */
618 ha->func.isintr = ips_isintr_copperhead;
619 ha->func.isinit = ips_isinit_copperhead;
620 ha->func.init = ips_init_copperhead;
621 ha->func.statupd = ips_statupd_copperhead;
622 ha->func.statinit = ips_statinit;
623 ha->func.reset = ips_reset_copperhead;
624 ha->func.intr = ips_intr_copperhead;
625 ha->func.erasebios = ips_erase_bios;
626 ha->func.programbios = ips_program_bios;
627 ha->func.verifybios = ips_verify_bios;
628 ha->func.enableint = ips_enable_int_copperhead;
629
630 if (IPS_USE_I2O_DELIVER(ha))
631 ha->func.issue = ips_issue_i2o;
632 else
633 ha->func.issue = ips_issue_copperhead;
634 }
635 }
636
637 /****************************************************************************/
638 /* */
639 /* Routine Name: ips_release */
640 /* */
641 /* Routine Description: */
642 /* */
643 /* Remove a driver */
644 /* */
645 /****************************************************************************/
646 static int
647 ips_release(struct Scsi_Host *sh)
648 {
649 ips_scb_t *scb;
650 ips_ha_t *ha;
651 int i;
652
653 METHOD_TRACE("ips_release", 1);
654
655 scsi_remove_host(sh);
656
657 for (i = 0; i < IPS_MAX_ADAPTERS && ips_sh[i] != sh; i++) ;
658
659 if (i == IPS_MAX_ADAPTERS) {
660 printk(KERN_WARNING
661 "(%s) release, invalid Scsi_Host pointer.\n", ips_name);
662 BUG();
663 return (FALSE);
664 }
665
666 ha = IPS_HA(sh);
667
668 if (!ha)
669 return (FALSE);
670
671 /* flush the cache on the controller */
672 scb = &ha->scbs[ha->max_cmds - 1];
673
674 ips_init_scb(ha, scb);
675
676 scb->timeout = ips_cmd_timeout;
677 scb->cdb[0] = IPS_CMD_FLUSH;
678
679 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
680 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
681 scb->cmd.flush_cache.state = IPS_NORM_STATE;
682 scb->cmd.flush_cache.reserved = 0;
683 scb->cmd.flush_cache.reserved2 = 0;
684 scb->cmd.flush_cache.reserved3 = 0;
685 scb->cmd.flush_cache.reserved4 = 0;
686
687 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Cache.\n");
688
689 /* send command */
690 if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) == IPS_FAILURE)
691 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Incomplete Flush.\n");
692
693 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Complete.\n");
694
695 ips_sh[i] = NULL;
696 ips_ha[i] = NULL;
697
698 /* free extra memory */
699 ips_free(ha);
700
701 /* free IRQ */
702 free_irq(ha->pcidev->irq, ha);
703
704 scsi_host_put(sh);
705
706 ips_released_controllers++;
707
708 return (FALSE);
709 }
710
711 /****************************************************************************/
712 /* */
713 /* Routine Name: ips_halt */
714 /* */
715 /* Routine Description: */
716 /* */
717 /* Perform cleanup when the system reboots */
718 /* */
719 /****************************************************************************/
720 static int
721 ips_halt(struct notifier_block *nb, ulong event, void *buf)
722 {
723 ips_scb_t *scb;
724 ips_ha_t *ha;
725 int i;
726
727 if ((event != SYS_RESTART) && (event != SYS_HALT) &&
728 (event != SYS_POWER_OFF))
729 return (NOTIFY_DONE);
730
731 for (i = 0; i < ips_next_controller; i++) {
732 ha = (ips_ha_t *) ips_ha[i];
733
734 if (!ha)
735 continue;
736
737 if (!ha->active)
738 continue;
739
740 /* flush the cache on the controller */
741 scb = &ha->scbs[ha->max_cmds - 1];
742
743 ips_init_scb(ha, scb);
744
745 scb->timeout = ips_cmd_timeout;
746 scb->cdb[0] = IPS_CMD_FLUSH;
747
748 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
749 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
750 scb->cmd.flush_cache.state = IPS_NORM_STATE;
751 scb->cmd.flush_cache.reserved = 0;
752 scb->cmd.flush_cache.reserved2 = 0;
753 scb->cmd.flush_cache.reserved3 = 0;
754 scb->cmd.flush_cache.reserved4 = 0;
755
756 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Cache.\n");
757
758 /* send command */
759 if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) ==
760 IPS_FAILURE)
761 IPS_PRINTK(KERN_WARNING, ha->pcidev,
762 "Incomplete Flush.\n");
763 else
764 IPS_PRINTK(KERN_WARNING, ha->pcidev,
765 "Flushing Complete.\n");
766 }
767
768 return (NOTIFY_OK);
769 }
770
771 /****************************************************************************/
772 /* */
773 /* Routine Name: ips_eh_abort */
774 /* */
775 /* Routine Description: */
776 /* */
777 /* Abort a command (using the new error code stuff) */
778 /* Note: this routine is called under the io_request_lock */
779 /****************************************************************************/
780 int ips_eh_abort(struct scsi_cmnd *SC)
781 {
782 ips_ha_t *ha;
783 ips_copp_wait_item_t *item;
784 int ret;
785 struct Scsi_Host *host;
786
787 METHOD_TRACE("ips_eh_abort", 1);
788
789 if (!SC)
790 return (FAILED);
791
792 host = SC->device->host;
793 ha = (ips_ha_t *) SC->device->host->hostdata;
794
795 if (!ha)
796 return (FAILED);
797
798 if (!ha->active)
799 return (FAILED);
800
801 spin_lock(host->host_lock);
802
803 /* See if the command is on the copp queue */
804 item = ha->copp_waitlist.head;
805 while ((item) && (item->scsi_cmd != SC))
806 item = item->next;
807
808 if (item) {
809 /* Found it */
810 ips_removeq_copp(&ha->copp_waitlist, item);
811 ret = (SUCCESS);
812
813 /* See if the command is on the wait queue */
814 } else if (ips_removeq_wait(&ha->scb_waitlist, SC)) {
815 /* command not sent yet */
816 ret = (SUCCESS);
817 } else {
818 /* command must have already been sent */
819 ret = (FAILED);
820 }
821
822 spin_unlock(host->host_lock);
823 return ret;
824 }
825
826 /****************************************************************************/
827 /* */
828 /* Routine Name: ips_eh_reset */
829 /* */
830 /* Routine Description: */
831 /* */
832 /* Reset the controller (with new eh error code) */
833 /* */
834 /* NOTE: this routine is called under the io_request_lock spinlock */
835 /* */
836 /****************************************************************************/
837 static int __ips_eh_reset(struct scsi_cmnd *SC)
838 {
839 int ret;
840 int i;
841 ips_ha_t *ha;
842 ips_scb_t *scb;
843 ips_copp_wait_item_t *item;
844
845 METHOD_TRACE("ips_eh_reset", 1);
846
847 #ifdef NO_IPS_RESET
848 return (FAILED);
849 #else
850
851 if (!SC) {
852 DEBUG(1, "Reset called with NULL scsi command");
853
854 return (FAILED);
855 }
856
857 ha = (ips_ha_t *) SC->device->host->hostdata;
858
859 if (!ha) {
860 DEBUG(1, "Reset called with NULL ha struct");
861
862 return (FAILED);
863 }
864
865 if (!ha->active)
866 return (FAILED);
867
868 /* See if the command is on the copp queue */
869 item = ha->copp_waitlist.head;
870 while ((item) && (item->scsi_cmd != SC))
871 item = item->next;
872
873 if (item) {
874 /* Found it */
875 ips_removeq_copp(&ha->copp_waitlist, item);
876 return (SUCCESS);
877 }
878
879 /* See if the command is on the wait queue */
880 if (ips_removeq_wait(&ha->scb_waitlist, SC)) {
881 /* command not sent yet */
882 return (SUCCESS);
883 }
884
885 /* An explanation for the casual observer: */
886 /* Part of the function of a RAID controller is automatic error */
887 /* detection and recovery. As such, the only problem that physically */
888 /* resetting an adapter will ever fix is when, for some reason, */
889 /* the driver is not successfully communicating with the adapter. */
890 /* Therefore, we will attempt to flush this adapter. If that succeeds, */
891 /* then there's no real purpose in a physical reset. This will complete */
892 /* much faster and avoids any problems that might be caused by a */
893 /* physical reset ( such as having to fail all the outstanding I/O's ). */
894
895 if (ha->ioctl_reset == 0) { /* IF Not an IOCTL Requested Reset */
896 scb = &ha->scbs[ha->max_cmds - 1];
897
898 ips_init_scb(ha, scb);
899
900 scb->timeout = ips_cmd_timeout;
901 scb->cdb[0] = IPS_CMD_FLUSH;
902
903 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
904 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
905 scb->cmd.flush_cache.state = IPS_NORM_STATE;
906 scb->cmd.flush_cache.reserved = 0;
907 scb->cmd.flush_cache.reserved2 = 0;
908 scb->cmd.flush_cache.reserved3 = 0;
909 scb->cmd.flush_cache.reserved4 = 0;
910
911 /* Attempt the flush command */
912 ret = ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_IORL);
913 if (ret == IPS_SUCCESS) {
914 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
915 "Reset Request - Flushed Cache\n");
916 return (SUCCESS);
917 }
918 }
919
920 /* Either we can't communicate with the adapter or it's an IOCTL request */
921 /* from a utility. A physical reset is needed at this point. */
922
923 ha->ioctl_reset = 0; /* Reset the IOCTL Requested Reset Flag */
924
925 /*
926 * command must have already been sent
927 * reset the controller
928 */
929 IPS_PRINTK(KERN_NOTICE, ha->pcidev, "Resetting controller.\n");
930 ret = (*ha->func.reset) (ha);
931
932 if (!ret) {
933 struct scsi_cmnd *scsi_cmd;
934
935 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
936 "Controller reset failed - controller now offline.\n");
937
938 /* Now fail all of the active commands */
939 DEBUG_VAR(1, "(%s%d) Failing active commands",
940 ips_name, ha->host_num);
941
942 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
943 scb->scsi_cmd->result = DID_ERROR << 16;
944 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
945 ips_freescb(ha, scb);
946 }
947
948 /* Now fail all of the pending commands */
949 DEBUG_VAR(1, "(%s%d) Failing pending commands",
950 ips_name, ha->host_num);
951
952 while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) {
953 scsi_cmd->result = DID_ERROR;
954 scsi_cmd->scsi_done(scsi_cmd);
955 }
956
957 ha->active = FALSE;
958 return (FAILED);
959 }
960
961 if (!ips_clear_adapter(ha, IPS_INTR_IORL)) {
962 struct scsi_cmnd *scsi_cmd;
963
964 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
965 "Controller reset failed - controller now offline.\n");
966
967 /* Now fail all of the active commands */
968 DEBUG_VAR(1, "(%s%d) Failing active commands",
969 ips_name, ha->host_num);
970
971 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
972 scb->scsi_cmd->result = DID_ERROR << 16;
973 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
974 ips_freescb(ha, scb);
975 }
976
977 /* Now fail all of the pending commands */
978 DEBUG_VAR(1, "(%s%d) Failing pending commands",
979 ips_name, ha->host_num);
980
981 while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) {
982 scsi_cmd->result = DID_ERROR << 16;
983 scsi_cmd->scsi_done(scsi_cmd);
984 }
985
986 ha->active = FALSE;
987 return (FAILED);
988 }
989
990 /* FFDC */
991 if (le32_to_cpu(ha->subsys->param[3]) & 0x300000) {
992 struct timeval tv;
993
994 do_gettimeofday(&tv);
995 ha->last_ffdc = tv.tv_sec;
996 ha->reset_count++;
997 ips_ffdc_reset(ha, IPS_INTR_IORL);
998 }
999
1000 /* Now fail all of the active commands */
1001 DEBUG_VAR(1, "(%s%d) Failing active commands", ips_name, ha->host_num);
1002
1003 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
1004 scb->scsi_cmd->result = DID_RESET << 16;
1005 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
1006 ips_freescb(ha, scb);
1007 }
1008
1009 /* Reset DCDB active command bits */
1010 for (i = 1; i < ha->nbus; i++)
1011 ha->dcdb_active[i - 1] = 0;
1012
1013 /* Reset the number of active IOCTLs */
1014 ha->num_ioctl = 0;
1015
1016 ips_next(ha, IPS_INTR_IORL);
1017
1018 return (SUCCESS);
1019 #endif /* NO_IPS_RESET */
1020
1021 }
1022
1023 static int ips_eh_reset(struct scsi_cmnd *SC)
1024 {
1025 int rc;
1026
1027 spin_lock_irq(SC->device->host->host_lock);
1028 rc = __ips_eh_reset(SC);
1029 spin_unlock_irq(SC->device->host->host_lock);
1030
1031 return rc;
1032 }
1033
1034 /****************************************************************************/
1035 /* */
1036 /* Routine Name: ips_queue */
1037 /* */
1038 /* Routine Description: */
1039 /* */
1040 /* Send a command to the controller */
1041 /* */
1042 /* NOTE: */
1043 /* Linux obtains io_request_lock before calling this function */
1044 /* */
1045 /****************************************************************************/
1046 static int ips_queue_lck(struct scsi_cmnd *SC, void (*done) (struct scsi_cmnd *))
1047 {
1048 ips_ha_t *ha;
1049 ips_passthru_t *pt;
1050
1051 METHOD_TRACE("ips_queue", 1);
1052
1053 ha = (ips_ha_t *) SC->device->host->hostdata;
1054
1055 if (!ha)
1056 return (1);
1057
1058 if (!ha->active)
1059 return (DID_ERROR);
1060
1061 if (ips_is_passthru(SC)) {
1062 if (ha->copp_waitlist.count == IPS_MAX_IOCTL_QUEUE) {
1063 SC->result = DID_BUS_BUSY << 16;
1064 done(SC);
1065
1066 return (0);
1067 }
1068 } else if (ha->scb_waitlist.count == IPS_MAX_QUEUE) {
1069 SC->result = DID_BUS_BUSY << 16;
1070 done(SC);
1071
1072 return (0);
1073 }
1074
1075 SC->scsi_done = done;
1076
1077 DEBUG_VAR(2, "(%s%d): ips_queue: cmd 0x%X (%d %d %d)",
1078 ips_name,
1079 ha->host_num,
1080 SC->cmnd[0],
1081 SC->device->channel, SC->device->id, SC->device->lun);
1082
1083 /* Check for command to initiator IDs */
1084 if ((scmd_channel(SC) > 0)
1085 && (scmd_id(SC) == ha->ha_id[scmd_channel(SC)])) {
1086 SC->result = DID_NO_CONNECT << 16;
1087 done(SC);
1088
1089 return (0);
1090 }
1091
1092 if (ips_is_passthru(SC)) {
1093
1094 ips_copp_wait_item_t *scratch;
1095
1096 /* A Reset IOCTL is only sent by the boot CD in extreme cases. */
1097 /* There can never be any system activity ( network or disk ), but check */
1098 /* anyway just as a good practice. */
1099 pt = (ips_passthru_t *) scsi_sglist(SC);
1100 if ((pt->CoppCP.cmd.reset.op_code == IPS_CMD_RESET_CHANNEL) &&
1101 (pt->CoppCP.cmd.reset.adapter_flag == 1)) {
1102 if (ha->scb_activelist.count != 0) {
1103 SC->result = DID_BUS_BUSY << 16;
1104 done(SC);
1105 return (0);
1106 }
1107 ha->ioctl_reset = 1; /* This reset request is from an IOCTL */
1108 __ips_eh_reset(SC);
1109 SC->result = DID_OK << 16;
1110 SC->scsi_done(SC);
1111 return (0);
1112 }
1113
1114 /* allocate space for the scribble */
1115 scratch = kmalloc(sizeof (ips_copp_wait_item_t), GFP_ATOMIC);
1116
1117 if (!scratch) {
1118 SC->result = DID_ERROR << 16;
1119 done(SC);
1120
1121 return (0);
1122 }
1123
1124 scratch->scsi_cmd = SC;
1125 scratch->next = NULL;
1126
1127 ips_putq_copp_tail(&ha->copp_waitlist, scratch);
1128 } else {
1129 ips_putq_wait_tail(&ha->scb_waitlist, SC);
1130 }
1131
1132 ips_next(ha, IPS_INTR_IORL);
1133
1134 return (0);
1135 }
1136
1137 static DEF_SCSI_QCMD(ips_queue)
1138
1139 /****************************************************************************/
1140 /* */
1141 /* Routine Name: ips_biosparam */
1142 /* */
1143 /* Routine Description: */
1144 /* */
1145 /* Set bios geometry for the controller */
1146 /* */
1147 /****************************************************************************/
1148 static int ips_biosparam(struct scsi_device *sdev, struct block_device *bdev,
1149 sector_t capacity, int geom[])
1150 {
1151 ips_ha_t *ha = (ips_ha_t *) sdev->host->hostdata;
1152 int heads;
1153 int sectors;
1154 int cylinders;
1155
1156 METHOD_TRACE("ips_biosparam", 1);
1157
1158 if (!ha)
1159 /* ?!?! host adater info invalid */
1160 return (0);
1161
1162 if (!ha->active)
1163 return (0);
1164
1165 if (!ips_read_adapter_status(ha, IPS_INTR_ON))
1166 /* ?!?! Enquiry command failed */
1167 return (0);
1168
1169 if ((capacity > 0x400000) && ((ha->enq->ucMiscFlag & 0x8) == 0)) {
1170 heads = IPS_NORM_HEADS;
1171 sectors = IPS_NORM_SECTORS;
1172 } else {
1173 heads = IPS_COMP_HEADS;
1174 sectors = IPS_COMP_SECTORS;
1175 }
1176
1177 cylinders = (unsigned long) capacity / (heads * sectors);
1178
1179 DEBUG_VAR(2, "Geometry: heads: %d, sectors: %d, cylinders: %d",
1180 heads, sectors, cylinders);
1181
1182 geom[0] = heads;
1183 geom[1] = sectors;
1184 geom[2] = cylinders;
1185
1186 return (0);
1187 }
1188
1189 /****************************************************************************/
1190 /* */
1191 /* Routine Name: ips_slave_configure */
1192 /* */
1193 /* Routine Description: */
1194 /* */
1195 /* Set queue depths on devices once scan is complete */
1196 /* */
1197 /****************************************************************************/
1198 static int
1199 ips_slave_configure(struct scsi_device * SDptr)
1200 {
1201 ips_ha_t *ha;
1202 int min;
1203
1204 ha = IPS_HA(SDptr->host);
1205 if (SDptr->tagged_supported && SDptr->type == TYPE_DISK) {
1206 min = ha->max_cmds / 2;
1207 if (ha->enq->ucLogDriveCount <= 2)
1208 min = ha->max_cmds - 1;
1209 scsi_change_queue_depth(SDptr, min);
1210 }
1211
1212 SDptr->skip_ms_page_8 = 1;
1213 SDptr->skip_ms_page_3f = 1;
1214 return 0;
1215 }
1216
1217 /****************************************************************************/
1218 /* */
1219 /* Routine Name: do_ipsintr */
1220 /* */
1221 /* Routine Description: */
1222 /* */
1223 /* Wrapper for the interrupt handler */
1224 /* */
1225 /****************************************************************************/
1226 static irqreturn_t
1227 do_ipsintr(int irq, void *dev_id)
1228 {
1229 ips_ha_t *ha;
1230 struct Scsi_Host *host;
1231 int irqstatus;
1232
1233 METHOD_TRACE("do_ipsintr", 2);
1234
1235 ha = (ips_ha_t *) dev_id;
1236 if (!ha)
1237 return IRQ_NONE;
1238 host = ips_sh[ha->host_num];
1239 /* interrupt during initialization */
1240 if (!host) {
1241 (*ha->func.intr) (ha);
1242 return IRQ_HANDLED;
1243 }
1244
1245 spin_lock(host->host_lock);
1246
1247 if (!ha->active) {
1248 spin_unlock(host->host_lock);
1249 return IRQ_HANDLED;
1250 }
1251
1252 irqstatus = (*ha->func.intr) (ha);
1253
1254 spin_unlock(host->host_lock);
1255
1256 /* start the next command */
1257 ips_next(ha, IPS_INTR_ON);
1258 return IRQ_RETVAL(irqstatus);
1259 }
1260
1261 /****************************************************************************/
1262 /* */
1263 /* Routine Name: ips_intr_copperhead */
1264 /* */
1265 /* Routine Description: */
1266 /* */
1267 /* Polling interrupt handler */
1268 /* */
1269 /* ASSUMES interrupts are disabled */
1270 /* */
1271 /****************************************************************************/
1272 int
1273 ips_intr_copperhead(ips_ha_t * ha)
1274 {
1275 ips_stat_t *sp;
1276 ips_scb_t *scb;
1277 IPS_STATUS cstatus;
1278 int intrstatus;
1279
1280 METHOD_TRACE("ips_intr", 2);
1281
1282 if (!ha)
1283 return 0;
1284
1285 if (!ha->active)
1286 return 0;
1287
1288 intrstatus = (*ha->func.isintr) (ha);
1289
1290 if (!intrstatus) {
1291 /*
1292 * Unexpected/Shared interrupt
1293 */
1294
1295 return 0;
1296 }
1297
1298 while (TRUE) {
1299 sp = &ha->sp;
1300
1301 intrstatus = (*ha->func.isintr) (ha);
1302
1303 if (!intrstatus)
1304 break;
1305 else
1306 cstatus.value = (*ha->func.statupd) (ha);
1307
1308 if (cstatus.fields.command_id > (IPS_MAX_CMDS - 1)) {
1309 /* Spurious Interrupt ? */
1310 continue;
1311 }
1312
1313 ips_chkstatus(ha, &cstatus);
1314 scb = (ips_scb_t *) sp->scb_addr;
1315
1316 /*
1317 * use the callback function to finish things up
1318 * NOTE: interrupts are OFF for this
1319 */
1320 (*scb->callback) (ha, scb);
1321 } /* end while */
1322 return 1;
1323 }
1324
1325 /****************************************************************************/
1326 /* */
1327 /* Routine Name: ips_intr_morpheus */
1328 /* */
1329 /* Routine Description: */
1330 /* */
1331 /* Polling interrupt handler */
1332 /* */
1333 /* ASSUMES interrupts are disabled */
1334 /* */
1335 /****************************************************************************/
1336 int
1337 ips_intr_morpheus(ips_ha_t * ha)
1338 {
1339 ips_stat_t *sp;
1340 ips_scb_t *scb;
1341 IPS_STATUS cstatus;
1342 int intrstatus;
1343
1344 METHOD_TRACE("ips_intr_morpheus", 2);
1345
1346 if (!ha)
1347 return 0;
1348
1349 if (!ha->active)
1350 return 0;
1351
1352 intrstatus = (*ha->func.isintr) (ha);
1353
1354 if (!intrstatus) {
1355 /*
1356 * Unexpected/Shared interrupt
1357 */
1358
1359 return 0;
1360 }
1361
1362 while (TRUE) {
1363 sp = &ha->sp;
1364
1365 intrstatus = (*ha->func.isintr) (ha);
1366
1367 if (!intrstatus)
1368 break;
1369 else
1370 cstatus.value = (*ha->func.statupd) (ha);
1371
1372 if (cstatus.value == 0xffffffff)
1373 /* No more to process */
1374 break;
1375
1376 if (cstatus.fields.command_id > (IPS_MAX_CMDS - 1)) {
1377 IPS_PRINTK(KERN_WARNING, ha->pcidev,
1378 "Spurious interrupt; no ccb.\n");
1379
1380 continue;
1381 }
1382
1383 ips_chkstatus(ha, &cstatus);
1384 scb = (ips_scb_t *) sp->scb_addr;
1385
1386 /*
1387 * use the callback function to finish things up
1388 * NOTE: interrupts are OFF for this
1389 */
1390 (*scb->callback) (ha, scb);
1391 } /* end while */
1392 return 1;
1393 }
1394
1395 /****************************************************************************/
1396 /* */
1397 /* Routine Name: ips_info */
1398 /* */
1399 /* Routine Description: */
1400 /* */
1401 /* Return info about the driver */
1402 /* */
1403 /****************************************************************************/
1404 static const char *
1405 ips_info(struct Scsi_Host *SH)
1406 {
1407 static char buffer[256];
1408 char *bp;
1409 ips_ha_t *ha;
1410
1411 METHOD_TRACE("ips_info", 1);
1412
1413 ha = IPS_HA(SH);
1414
1415 if (!ha)
1416 return (NULL);
1417
1418 bp = &buffer[0];
1419 memset(bp, 0, sizeof (buffer));
1420
1421 sprintf(bp, "%s%s%s Build %d", "IBM PCI ServeRAID ",
1422 IPS_VERSION_HIGH, IPS_VERSION_LOW, IPS_BUILD_IDENT);
1423
1424 if (ha->ad_type > 0 && ha->ad_type <= MAX_ADAPTER_NAME) {
1425 strcat(bp, " <");
1426 strcat(bp, ips_adapter_name[ha->ad_type - 1]);
1427 strcat(bp, ">");
1428 }
1429
1430 return (bp);
1431 }
1432
1433 static int
1434 ips_write_info(struct Scsi_Host *host, char *buffer, int length)
1435 {
1436 int i;
1437 ips_ha_t *ha = NULL;
1438
1439 /* Find our host structure */
1440 for (i = 0; i < ips_next_controller; i++) {
1441 if (ips_sh[i]) {
1442 if (ips_sh[i] == host) {
1443 ha = (ips_ha_t *) ips_sh[i]->hostdata;
1444 break;
1445 }
1446 }
1447 }
1448
1449 if (!ha)
1450 return (-EINVAL);
1451
1452 return 0;
1453 }
1454
1455 static int
1456 ips_show_info(struct seq_file *m, struct Scsi_Host *host)
1457 {
1458 int i;
1459 ips_ha_t *ha = NULL;
1460
1461 /* Find our host structure */
1462 for (i = 0; i < ips_next_controller; i++) {
1463 if (ips_sh[i]) {
1464 if (ips_sh[i] == host) {
1465 ha = (ips_ha_t *) ips_sh[i]->hostdata;
1466 break;
1467 }
1468 }
1469 }
1470
1471 if (!ha)
1472 return (-EINVAL);
1473
1474 return ips_host_info(ha, m);
1475 }
1476
1477 /*--------------------------------------------------------------------------*/
1478 /* Helper Functions */
1479 /*--------------------------------------------------------------------------*/
1480
1481 /****************************************************************************/
1482 /* */
1483 /* Routine Name: ips_is_passthru */
1484 /* */
1485 /* Routine Description: */
1486 /* */
1487 /* Determine if the specified SCSI command is really a passthru command */
1488 /* */
1489 /****************************************************************************/
1490 static int ips_is_passthru(struct scsi_cmnd *SC)
1491 {
1492 unsigned long flags;
1493
1494 METHOD_TRACE("ips_is_passthru", 1);
1495
1496 if (!SC)
1497 return (0);
1498
1499 if ((SC->cmnd[0] == IPS_IOCTL_COMMAND) &&
1500 (SC->device->channel == 0) &&
1501 (SC->device->id == IPS_ADAPTER_ID) &&
1502 (SC->device->lun == 0) && scsi_sglist(SC)) {
1503 struct scatterlist *sg = scsi_sglist(SC);
1504 char *buffer;
1505
1506 /* kmap_atomic() ensures addressability of the user buffer.*/
1507 /* local_irq_save() protects the KM_IRQ0 address slot. */
1508 local_irq_save(flags);
1509 buffer = kmap_atomic(sg_page(sg)) + sg->offset;
1510 if (buffer && buffer[0] == 'C' && buffer[1] == 'O' &&
1511 buffer[2] == 'P' && buffer[3] == 'P') {
1512 kunmap_atomic(buffer - sg->offset);
1513 local_irq_restore(flags);
1514 return 1;
1515 }
1516 kunmap_atomic(buffer - sg->offset);
1517 local_irq_restore(flags);
1518 }
1519 return 0;
1520 }
1521
1522 /****************************************************************************/
1523 /* */
1524 /* Routine Name: ips_alloc_passthru_buffer */
1525 /* */
1526 /* Routine Description: */
1527 /* allocate a buffer large enough for the ioctl data if the ioctl buffer */
1528 /* is too small or doesn't exist */
1529 /****************************************************************************/
1530 static int
1531 ips_alloc_passthru_buffer(ips_ha_t * ha, int length)
1532 {
1533 void *bigger_buf;
1534 dma_addr_t dma_busaddr;
1535
1536 if (ha->ioctl_data && length <= ha->ioctl_len)
1537 return 0;
1538 /* there is no buffer or it's not big enough, allocate a new one */
1539 bigger_buf = pci_alloc_consistent(ha->pcidev, length, &dma_busaddr);
1540 if (bigger_buf) {
1541 /* free the old memory */
1542 pci_free_consistent(ha->pcidev, ha->ioctl_len, ha->ioctl_data,
1543 ha->ioctl_busaddr);
1544 /* use the new memory */
1545 ha->ioctl_data = (char *) bigger_buf;
1546 ha->ioctl_len = length;
1547 ha->ioctl_busaddr = dma_busaddr;
1548 } else {
1549 return -1;
1550 }
1551 return 0;
1552 }
1553
1554 /****************************************************************************/
1555 /* */
1556 /* Routine Name: ips_make_passthru */
1557 /* */
1558 /* Routine Description: */
1559 /* */
1560 /* Make a passthru command out of the info in the Scsi block */
1561 /* */
1562 /****************************************************************************/
1563 static int
1564 ips_make_passthru(ips_ha_t *ha, struct scsi_cmnd *SC, ips_scb_t *scb, int intr)
1565 {
1566 ips_passthru_t *pt;
1567 int length = 0;
1568 int i, ret;
1569 struct scatterlist *sg = scsi_sglist(SC);
1570
1571 METHOD_TRACE("ips_make_passthru", 1);
1572
1573 scsi_for_each_sg(SC, sg, scsi_sg_count(SC), i)
1574 length += sg->length;
1575
1576 if (length < sizeof (ips_passthru_t)) {
1577 /* wrong size */
1578 DEBUG_VAR(1, "(%s%d) Passthru structure wrong size",
1579 ips_name, ha->host_num);
1580 return (IPS_FAILURE);
1581 }
1582 if (ips_alloc_passthru_buffer(ha, length)) {
1583 /* allocation failure! If ha->ioctl_data exists, use it to return
1584 some error codes. Return a failed command to the scsi layer. */
1585 if (ha->ioctl_data) {
1586 pt = (ips_passthru_t *) ha->ioctl_data;
1587 ips_scmd_buf_read(SC, pt, sizeof (ips_passthru_t));
1588 pt->BasicStatus = 0x0B;
1589 pt->ExtendedStatus = 0x00;
1590 ips_scmd_buf_write(SC, pt, sizeof (ips_passthru_t));
1591 }
1592 return IPS_FAILURE;
1593 }
1594 ha->ioctl_datasize = length;
1595
1596 ips_scmd_buf_read(SC, ha->ioctl_data, ha->ioctl_datasize);
1597 pt = (ips_passthru_t *) ha->ioctl_data;
1598
1599 /*
1600 * Some notes about the passthru interface used
1601 *
1602 * IF the scsi op_code == 0x0d then we assume
1603 * that the data came along with/goes with the
1604 * packet we received from the sg driver. In this
1605 * case the CmdBSize field of the pt structure is
1606 * used for the size of the buffer.
1607 */
1608
1609 switch (pt->CoppCmd) {
1610 case IPS_NUMCTRLS:
1611 memcpy(ha->ioctl_data + sizeof (ips_passthru_t),
1612 &ips_num_controllers, sizeof (int));
1613 ips_scmd_buf_write(SC, ha->ioctl_data,
1614 sizeof (ips_passthru_t) + sizeof (int));
1615 SC->result = DID_OK << 16;
1616
1617 return (IPS_SUCCESS_IMM);
1618
1619 case IPS_COPPUSRCMD:
1620 case IPS_COPPIOCCMD:
1621 if (SC->cmnd[0] == IPS_IOCTL_COMMAND) {
1622 if (length < (sizeof (ips_passthru_t) + pt->CmdBSize)) {
1623 /* wrong size */
1624 DEBUG_VAR(1,
1625 "(%s%d) Passthru structure wrong size",
1626 ips_name, ha->host_num);
1627
1628 return (IPS_FAILURE);
1629 }
1630
1631 if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD &&
1632 pt->CoppCP.cmd.flashfw.op_code ==
1633 IPS_CMD_RW_BIOSFW) {
1634 ret = ips_flash_copperhead(ha, pt, scb);
1635 ips_scmd_buf_write(SC, ha->ioctl_data,
1636 sizeof (ips_passthru_t));
1637 return ret;
1638 }
1639 if (ips_usrcmd(ha, pt, scb))
1640 return (IPS_SUCCESS);
1641 else
1642 return (IPS_FAILURE);
1643 }
1644
1645 break;
1646
1647 } /* end switch */
1648
1649 return (IPS_FAILURE);
1650 }
1651
1652 /****************************************************************************/
1653 /* Routine Name: ips_flash_copperhead */
1654 /* Routine Description: */
1655 /* Flash the BIOS/FW on a Copperhead style controller */
1656 /****************************************************************************/
1657 static int
1658 ips_flash_copperhead(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1659 {
1660 int datasize;
1661
1662 /* Trombone is the only copperhead that can do packet flash, but only
1663 * for firmware. No one said it had to make sense. */
1664 if (IPS_IS_TROMBONE(ha) && pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE) {
1665 if (ips_usrcmd(ha, pt, scb))
1666 return IPS_SUCCESS;
1667 else
1668 return IPS_FAILURE;
1669 }
1670 pt->BasicStatus = 0x0B;
1671 pt->ExtendedStatus = 0;
1672 scb->scsi_cmd->result = DID_OK << 16;
1673 /* IF it's OK to Use the "CD BOOT" Flash Buffer, then you can */
1674 /* avoid allocating a huge buffer per adapter ( which can fail ). */
1675 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
1676 pt->CoppCP.cmd.flashfw.direction == IPS_ERASE_BIOS) {
1677 pt->BasicStatus = 0;
1678 return ips_flash_bios(ha, pt, scb);
1679 } else if (pt->CoppCP.cmd.flashfw.packet_num == 0) {
1680 if (ips_FlashData && !test_and_set_bit(0, &ips_FlashDataInUse)){
1681 ha->flash_data = ips_FlashData;
1682 ha->flash_busaddr = ips_flashbusaddr;
1683 ha->flash_len = PAGE_SIZE << 7;
1684 ha->flash_datasize = 0;
1685 } else if (!ha->flash_data) {
1686 datasize = pt->CoppCP.cmd.flashfw.total_packets *
1687 pt->CoppCP.cmd.flashfw.count;
1688 ha->flash_data = pci_alloc_consistent(ha->pcidev,
1689 datasize,
1690 &ha->flash_busaddr);
1691 if (!ha->flash_data){
1692 printk(KERN_WARNING "Unable to allocate a flash buffer\n");
1693 return IPS_FAILURE;
1694 }
1695 ha->flash_datasize = 0;
1696 ha->flash_len = datasize;
1697 } else
1698 return IPS_FAILURE;
1699 } else {
1700 if (pt->CoppCP.cmd.flashfw.count + ha->flash_datasize >
1701 ha->flash_len) {
1702 ips_free_flash_copperhead(ha);
1703 IPS_PRINTK(KERN_WARNING, ha->pcidev,
1704 "failed size sanity check\n");
1705 return IPS_FAILURE;
1706 }
1707 }
1708 if (!ha->flash_data)
1709 return IPS_FAILURE;
1710 pt->BasicStatus = 0;
1711 memcpy(&ha->flash_data[ha->flash_datasize], pt + 1,
1712 pt->CoppCP.cmd.flashfw.count);
1713 ha->flash_datasize += pt->CoppCP.cmd.flashfw.count;
1714 if (pt->CoppCP.cmd.flashfw.packet_num ==
1715 pt->CoppCP.cmd.flashfw.total_packets - 1) {
1716 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE)
1717 return ips_flash_bios(ha, pt, scb);
1718 else if (pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE)
1719 return ips_flash_firmware(ha, pt, scb);
1720 }
1721 return IPS_SUCCESS_IMM;
1722 }
1723
1724 /****************************************************************************/
1725 /* Routine Name: ips_flash_bios */
1726 /* Routine Description: */
1727 /* flashes the bios of a copperhead adapter */
1728 /****************************************************************************/
1729 static int
1730 ips_flash_bios(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1731 {
1732
1733 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
1734 pt->CoppCP.cmd.flashfw.direction == IPS_WRITE_BIOS) {
1735 if ((!ha->func.programbios) || (!ha->func.erasebios) ||
1736 (!ha->func.verifybios))
1737 goto error;
1738 if ((*ha->func.erasebios) (ha)) {
1739 DEBUG_VAR(1,
1740 "(%s%d) flash bios failed - unable to erase flash",
1741 ips_name, ha->host_num);
1742 goto error;
1743 } else
1744 if ((*ha->func.programbios) (ha,
1745 ha->flash_data +
1746 IPS_BIOS_HEADER,
1747 ha->flash_datasize -
1748 IPS_BIOS_HEADER, 0)) {
1749 DEBUG_VAR(1,
1750 "(%s%d) flash bios failed - unable to flash",
1751 ips_name, ha->host_num);
1752 goto error;
1753 } else
1754 if ((*ha->func.verifybios) (ha,
1755 ha->flash_data +
1756 IPS_BIOS_HEADER,
1757 ha->flash_datasize -
1758 IPS_BIOS_HEADER, 0)) {
1759 DEBUG_VAR(1,
1760 "(%s%d) flash bios failed - unable to verify flash",
1761 ips_name, ha->host_num);
1762 goto error;
1763 }
1764 ips_free_flash_copperhead(ha);
1765 return IPS_SUCCESS_IMM;
1766 } else if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
1767 pt->CoppCP.cmd.flashfw.direction == IPS_ERASE_BIOS) {
1768 if (!ha->func.erasebios)
1769 goto error;
1770 if ((*ha->func.erasebios) (ha)) {
1771 DEBUG_VAR(1,
1772 "(%s%d) flash bios failed - unable to erase flash",
1773 ips_name, ha->host_num);
1774 goto error;
1775 }
1776 return IPS_SUCCESS_IMM;
1777 }
1778 error:
1779 pt->BasicStatus = 0x0B;
1780 pt->ExtendedStatus = 0x00;
1781 ips_free_flash_copperhead(ha);
1782 return IPS_FAILURE;
1783 }
1784
1785 /****************************************************************************/
1786 /* */
1787 /* Routine Name: ips_fill_scb_sg_single */
1788 /* */
1789 /* Routine Description: */
1790 /* Fill in a single scb sg_list element from an address */
1791 /* return a -1 if a breakup occurred */
1792 /****************************************************************************/
1793 static int
1794 ips_fill_scb_sg_single(ips_ha_t * ha, dma_addr_t busaddr,
1795 ips_scb_t * scb, int indx, unsigned int e_len)
1796 {
1797
1798 int ret_val = 0;
1799
1800 if ((scb->data_len + e_len) > ha->max_xfer) {
1801 e_len = ha->max_xfer - scb->data_len;
1802 scb->breakup = indx;
1803 ++scb->sg_break;
1804 ret_val = -1;
1805 } else {
1806 scb->breakup = 0;
1807 scb->sg_break = 0;
1808 }
1809 if (IPS_USE_ENH_SGLIST(ha)) {
1810 scb->sg_list.enh_list[indx].address_lo =
1811 cpu_to_le32(pci_dma_lo32(busaddr));
1812 scb->sg_list.enh_list[indx].address_hi =
1813 cpu_to_le32(pci_dma_hi32(busaddr));
1814 scb->sg_list.enh_list[indx].length = cpu_to_le32(e_len);
1815 } else {
1816 scb->sg_list.std_list[indx].address =
1817 cpu_to_le32(pci_dma_lo32(busaddr));
1818 scb->sg_list.std_list[indx].length = cpu_to_le32(e_len);
1819 }
1820
1821 ++scb->sg_len;
1822 scb->data_len += e_len;
1823 return ret_val;
1824 }
1825
1826 /****************************************************************************/
1827 /* Routine Name: ips_flash_firmware */
1828 /* Routine Description: */
1829 /* flashes the firmware of a copperhead adapter */
1830 /****************************************************************************/
1831 static int
1832 ips_flash_firmware(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1833 {
1834 IPS_SG_LIST sg_list;
1835 uint32_t cmd_busaddr;
1836
1837 if (pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE &&
1838 pt->CoppCP.cmd.flashfw.direction == IPS_WRITE_FW) {
1839 memset(&pt->CoppCP.cmd, 0, sizeof (IPS_HOST_COMMAND));
1840 pt->CoppCP.cmd.flashfw.op_code = IPS_CMD_DOWNLOAD;
1841 pt->CoppCP.cmd.flashfw.count = cpu_to_le32(ha->flash_datasize);
1842 } else {
1843 pt->BasicStatus = 0x0B;
1844 pt->ExtendedStatus = 0x00;
1845 ips_free_flash_copperhead(ha);
1846 return IPS_FAILURE;
1847 }
1848 /* Save the S/G list pointer so it doesn't get clobbered */
1849 sg_list.list = scb->sg_list.list;
1850 cmd_busaddr = scb->scb_busaddr;
1851 /* copy in the CP */
1852 memcpy(&scb->cmd, &pt->CoppCP.cmd, sizeof (IPS_IOCTL_CMD));
1853 /* FIX stuff that might be wrong */
1854 scb->sg_list.list = sg_list.list;
1855 scb->scb_busaddr = cmd_busaddr;
1856 scb->bus = scb->scsi_cmd->device->channel;
1857 scb->target_id = scb->scsi_cmd->device->id;
1858 scb->lun = scb->scsi_cmd->device->lun;
1859 scb->sg_len = 0;
1860 scb->data_len = 0;
1861 scb->flags = 0;
1862 scb->op_code = 0;
1863 scb->callback = ipsintr_done;
1864 scb->timeout = ips_cmd_timeout;
1865
1866 scb->data_len = ha->flash_datasize;
1867 scb->data_busaddr =
1868 pci_map_single(ha->pcidev, ha->flash_data, scb->data_len,
1869 IPS_DMA_DIR(scb));
1870 scb->flags |= IPS_SCB_MAP_SINGLE;
1871 scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb);
1872 scb->cmd.flashfw.buffer_addr = cpu_to_le32(scb->data_busaddr);
1873 if (pt->TimeOut)
1874 scb->timeout = pt->TimeOut;
1875 scb->scsi_cmd->result = DID_OK << 16;
1876 return IPS_SUCCESS;
1877 }
1878
1879 /****************************************************************************/
1880 /* Routine Name: ips_free_flash_copperhead */
1881 /* Routine Description: */
1882 /* release the memory resources used to hold the flash image */
1883 /****************************************************************************/
1884 static void
1885 ips_free_flash_copperhead(ips_ha_t * ha)
1886 {
1887 if (ha->flash_data == ips_FlashData)
1888 test_and_clear_bit(0, &ips_FlashDataInUse);
1889 else if (ha->flash_data)
1890 pci_free_consistent(ha->pcidev, ha->flash_len, ha->flash_data,
1891 ha->flash_busaddr);
1892 ha->flash_data = NULL;
1893 }
1894
1895 /****************************************************************************/
1896 /* */
1897 /* Routine Name: ips_usrcmd */
1898 /* */
1899 /* Routine Description: */
1900 /* */
1901 /* Process a user command and make it ready to send */
1902 /* */
1903 /****************************************************************************/
1904 static int
1905 ips_usrcmd(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1906 {
1907 IPS_SG_LIST sg_list;
1908 uint32_t cmd_busaddr;
1909
1910 METHOD_TRACE("ips_usrcmd", 1);
1911
1912 if ((!scb) || (!pt) || (!ha))
1913 return (0);
1914
1915 /* Save the S/G list pointer so it doesn't get clobbered */
1916 sg_list.list = scb->sg_list.list;
1917 cmd_busaddr = scb->scb_busaddr;
1918 /* copy in the CP */
1919 memcpy(&scb->cmd, &pt->CoppCP.cmd, sizeof (IPS_IOCTL_CMD));
1920 memcpy(&scb->dcdb, &pt->CoppCP.dcdb, sizeof (IPS_DCDB_TABLE));
1921
1922 /* FIX stuff that might be wrong */
1923 scb->sg_list.list = sg_list.list;
1924 scb->scb_busaddr = cmd_busaddr;
1925 scb->bus = scb->scsi_cmd->device->channel;
1926 scb->target_id = scb->scsi_cmd->device->id;
1927 scb->lun = scb->scsi_cmd->device->lun;
1928 scb->sg_len = 0;
1929 scb->data_len = 0;
1930 scb->flags = 0;
1931 scb->op_code = 0;
1932 scb->callback = ipsintr_done;
1933 scb->timeout = ips_cmd_timeout;
1934 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
1935
1936 /* we don't support DCDB/READ/WRITE Scatter Gather */
1937 if ((scb->cmd.basic_io.op_code == IPS_CMD_READ_SG) ||
1938 (scb->cmd.basic_io.op_code == IPS_CMD_WRITE_SG) ||
1939 (scb->cmd.basic_io.op_code == IPS_CMD_DCDB_SG))
1940 return (0);
1941
1942 if (pt->CmdBSize) {
1943 scb->data_len = pt->CmdBSize;
1944 scb->data_busaddr = ha->ioctl_busaddr + sizeof (ips_passthru_t);
1945 } else {
1946 scb->data_busaddr = 0L;
1947 }
1948
1949 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB)
1950 scb->cmd.dcdb.dcdb_address = cpu_to_le32(scb->scb_busaddr +
1951 (unsigned long) &scb->
1952 dcdb -
1953 (unsigned long) scb);
1954
1955 if (pt->CmdBSize) {
1956 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB)
1957 scb->dcdb.buffer_pointer =
1958 cpu_to_le32(scb->data_busaddr);
1959 else
1960 scb->cmd.basic_io.sg_addr =
1961 cpu_to_le32(scb->data_busaddr);
1962 }
1963
1964 /* set timeouts */
1965 if (pt->TimeOut) {
1966 scb->timeout = pt->TimeOut;
1967
1968 if (pt->TimeOut <= 10)
1969 scb->dcdb.cmd_attribute |= IPS_TIMEOUT10;
1970 else if (pt->TimeOut <= 60)
1971 scb->dcdb.cmd_attribute |= IPS_TIMEOUT60;
1972 else
1973 scb->dcdb.cmd_attribute |= IPS_TIMEOUT20M;
1974 }
1975
1976 /* assume success */
1977 scb->scsi_cmd->result = DID_OK << 16;
1978
1979 /* success */
1980 return (1);
1981 }
1982
1983 /****************************************************************************/
1984 /* */
1985 /* Routine Name: ips_cleanup_passthru */
1986 /* */
1987 /* Routine Description: */
1988 /* */
1989 /* Cleanup after a passthru command */
1990 /* */
1991 /****************************************************************************/
1992 static void
1993 ips_cleanup_passthru(ips_ha_t * ha, ips_scb_t * scb)
1994 {
1995 ips_passthru_t *pt;
1996
1997 METHOD_TRACE("ips_cleanup_passthru", 1);
1998
1999 if ((!scb) || (!scb->scsi_cmd) || (!scsi_sglist(scb->scsi_cmd))) {
2000 DEBUG_VAR(1, "(%s%d) couldn't cleanup after passthru",
2001 ips_name, ha->host_num);
2002
2003 return;
2004 }
2005 pt = (ips_passthru_t *) ha->ioctl_data;
2006
2007 /* Copy data back to the user */
2008 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB) /* Copy DCDB Back to Caller's Area */
2009 memcpy(&pt->CoppCP.dcdb, &scb->dcdb, sizeof (IPS_DCDB_TABLE));
2010
2011 pt->BasicStatus = scb->basic_status;
2012 pt->ExtendedStatus = scb->extended_status;
2013 pt->AdapterType = ha->ad_type;
2014
2015 if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD &&
2016 (scb->cmd.flashfw.op_code == IPS_CMD_DOWNLOAD ||
2017 scb->cmd.flashfw.op_code == IPS_CMD_RW_BIOSFW))
2018 ips_free_flash_copperhead(ha);
2019
2020 ips_scmd_buf_write(scb->scsi_cmd, ha->ioctl_data, ha->ioctl_datasize);
2021 }
2022
2023 /****************************************************************************/
2024 /* */
2025 /* Routine Name: ips_host_info */
2026 /* */
2027 /* Routine Description: */
2028 /* */
2029 /* The passthru interface for the driver */
2030 /* */
2031 /****************************************************************************/
2032 static int
2033 ips_host_info(ips_ha_t *ha, struct seq_file *m)
2034 {
2035 METHOD_TRACE("ips_host_info", 1);
2036
2037 seq_puts(m, "\nIBM ServeRAID General Information:\n\n");
2038
2039 if ((le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) &&
2040 (le16_to_cpu(ha->nvram->adapter_type) != 0))
2041 seq_printf(m, "\tController Type : %s\n",
2042 ips_adapter_name[ha->ad_type - 1]);
2043 else
2044 seq_puts(m, "\tController Type : Unknown\n");
2045
2046 if (ha->io_addr)
2047 seq_printf(m,
2048 "\tIO region : 0x%x (%d bytes)\n",
2049 ha->io_addr, ha->io_len);
2050
2051 if (ha->mem_addr) {
2052 seq_printf(m,
2053 "\tMemory region : 0x%x (%d bytes)\n",
2054 ha->mem_addr, ha->mem_len);
2055 seq_printf(m,
2056 "\tShared memory address : 0x%lx\n",
2057 (unsigned long)ha->mem_ptr);
2058 }
2059
2060 seq_printf(m, "\tIRQ number : %d\n", ha->pcidev->irq);
2061
2062 /* For the Next 3 lines Check for Binary 0 at the end and don't include it if it's there. */
2063 /* That keeps everything happy for "text" operations on the proc file. */
2064
2065 if (le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) {
2066 if (ha->nvram->bios_low[3] == 0) {
2067 seq_printf(m,
2068 "\tBIOS Version : %c%c%c%c%c%c%c\n",
2069 ha->nvram->bios_high[0], ha->nvram->bios_high[1],
2070 ha->nvram->bios_high[2], ha->nvram->bios_high[3],
2071 ha->nvram->bios_low[0], ha->nvram->bios_low[1],
2072 ha->nvram->bios_low[2]);
2073
2074 } else {
2075 seq_printf(m,
2076 "\tBIOS Version : %c%c%c%c%c%c%c%c\n",
2077 ha->nvram->bios_high[0], ha->nvram->bios_high[1],
2078 ha->nvram->bios_high[2], ha->nvram->bios_high[3],
2079 ha->nvram->bios_low[0], ha->nvram->bios_low[1],
2080 ha->nvram->bios_low[2], ha->nvram->bios_low[3]);
2081 }
2082
2083 }
2084
2085 if (ha->enq->CodeBlkVersion[7] == 0) {
2086 seq_printf(m,
2087 "\tFirmware Version : %c%c%c%c%c%c%c\n",
2088 ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1],
2089 ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3],
2090 ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5],
2091 ha->enq->CodeBlkVersion[6]);
2092 } else {
2093 seq_printf(m,
2094 "\tFirmware Version : %c%c%c%c%c%c%c%c\n",
2095 ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1],
2096 ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3],
2097 ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5],
2098 ha->enq->CodeBlkVersion[6], ha->enq->CodeBlkVersion[7]);
2099 }
2100
2101 if (ha->enq->BootBlkVersion[7] == 0) {
2102 seq_printf(m,
2103 "\tBoot Block Version : %c%c%c%c%c%c%c\n",
2104 ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1],
2105 ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3],
2106 ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5],
2107 ha->enq->BootBlkVersion[6]);
2108 } else {
2109 seq_printf(m,
2110 "\tBoot Block Version : %c%c%c%c%c%c%c%c\n",
2111 ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1],
2112 ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3],
2113 ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5],
2114 ha->enq->BootBlkVersion[6], ha->enq->BootBlkVersion[7]);
2115 }
2116
2117 seq_printf(m, "\tDriver Version : %s%s\n",
2118 IPS_VERSION_HIGH, IPS_VERSION_LOW);
2119
2120 seq_printf(m, "\tDriver Build : %d\n",
2121 IPS_BUILD_IDENT);
2122
2123 seq_printf(m, "\tMax Physical Devices : %d\n",
2124 ha->enq->ucMaxPhysicalDevices);
2125 seq_printf(m, "\tMax Active Commands : %d\n",
2126 ha->max_cmds);
2127 seq_printf(m, "\tCurrent Queued Commands : %d\n",
2128 ha->scb_waitlist.count);
2129 seq_printf(m, "\tCurrent Active Commands : %d\n",
2130 ha->scb_activelist.count - ha->num_ioctl);
2131 seq_printf(m, "\tCurrent Queued PT Commands : %d\n",
2132 ha->copp_waitlist.count);
2133 seq_printf(m, "\tCurrent Active PT Commands : %d\n",
2134 ha->num_ioctl);
2135
2136 seq_putc(m, '\n');
2137
2138 return 0;
2139 }
2140
2141 /****************************************************************************/
2142 /* */
2143 /* Routine Name: ips_identify_controller */
2144 /* */
2145 /* Routine Description: */
2146 /* */
2147 /* Identify this controller */
2148 /* */
2149 /****************************************************************************/
2150 static void
2151 ips_identify_controller(ips_ha_t * ha)
2152 {
2153 METHOD_TRACE("ips_identify_controller", 1);
2154
2155 switch (ha->pcidev->device) {
2156 case IPS_DEVICEID_COPPERHEAD:
2157 if (ha->pcidev->revision <= IPS_REVID_SERVERAID) {
2158 ha->ad_type = IPS_ADTYPE_SERVERAID;
2159 } else if (ha->pcidev->revision == IPS_REVID_SERVERAID2) {
2160 ha->ad_type = IPS_ADTYPE_SERVERAID2;
2161 } else if (ha->pcidev->revision == IPS_REVID_NAVAJO) {
2162 ha->ad_type = IPS_ADTYPE_NAVAJO;
2163 } else if ((ha->pcidev->revision == IPS_REVID_SERVERAID2)
2164 && (ha->slot_num == 0)) {
2165 ha->ad_type = IPS_ADTYPE_KIOWA;
2166 } else if ((ha->pcidev->revision >= IPS_REVID_CLARINETP1) &&
2167 (ha->pcidev->revision <= IPS_REVID_CLARINETP3)) {
2168 if (ha->enq->ucMaxPhysicalDevices == 15)
2169 ha->ad_type = IPS_ADTYPE_SERVERAID3L;
2170 else
2171 ha->ad_type = IPS_ADTYPE_SERVERAID3;
2172 } else if ((ha->pcidev->revision >= IPS_REVID_TROMBONE32) &&
2173 (ha->pcidev->revision <= IPS_REVID_TROMBONE64)) {
2174 ha->ad_type = IPS_ADTYPE_SERVERAID4H;
2175 }
2176 break;
2177
2178 case IPS_DEVICEID_MORPHEUS:
2179 switch (ha->pcidev->subsystem_device) {
2180 case IPS_SUBDEVICEID_4L:
2181 ha->ad_type = IPS_ADTYPE_SERVERAID4L;
2182 break;
2183
2184 case IPS_SUBDEVICEID_4M:
2185 ha->ad_type = IPS_ADTYPE_SERVERAID4M;
2186 break;
2187
2188 case IPS_SUBDEVICEID_4MX:
2189 ha->ad_type = IPS_ADTYPE_SERVERAID4MX;
2190 break;
2191
2192 case IPS_SUBDEVICEID_4LX:
2193 ha->ad_type = IPS_ADTYPE_SERVERAID4LX;
2194 break;
2195
2196 case IPS_SUBDEVICEID_5I2:
2197 ha->ad_type = IPS_ADTYPE_SERVERAID5I2;
2198 break;
2199
2200 case IPS_SUBDEVICEID_5I1:
2201 ha->ad_type = IPS_ADTYPE_SERVERAID5I1;
2202 break;
2203 }
2204
2205 break;
2206
2207 case IPS_DEVICEID_MARCO:
2208 switch (ha->pcidev->subsystem_device) {
2209 case IPS_SUBDEVICEID_6M:
2210 ha->ad_type = IPS_ADTYPE_SERVERAID6M;
2211 break;
2212 case IPS_SUBDEVICEID_6I:
2213 ha->ad_type = IPS_ADTYPE_SERVERAID6I;
2214 break;
2215 case IPS_SUBDEVICEID_7k:
2216 ha->ad_type = IPS_ADTYPE_SERVERAID7k;
2217 break;
2218 case IPS_SUBDEVICEID_7M:
2219 ha->ad_type = IPS_ADTYPE_SERVERAID7M;
2220 break;
2221 }
2222 break;
2223 }
2224 }
2225
2226 /****************************************************************************/
2227 /* */
2228 /* Routine Name: ips_get_bios_version */
2229 /* */
2230 /* Routine Description: */
2231 /* */
2232 /* Get the BIOS revision number */
2233 /* */
2234 /****************************************************************************/
2235 static void
2236 ips_get_bios_version(ips_ha_t * ha, int intr)
2237 {
2238 ips_scb_t *scb;
2239 int ret;
2240 uint8_t major;
2241 uint8_t minor;
2242 uint8_t subminor;
2243 uint8_t *buffer;
2244
2245 METHOD_TRACE("ips_get_bios_version", 1);
2246
2247 major = 0;
2248 minor = 0;
2249
2250 strncpy(ha->bios_version, " ?", 8);
2251
2252 if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD) {
2253 if (IPS_USE_MEMIO(ha)) {
2254 /* Memory Mapped I/O */
2255
2256 /* test 1st byte */
2257 writel(0, ha->mem_ptr + IPS_REG_FLAP);
2258 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2259 udelay(25); /* 25 us */
2260
2261 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55)
2262 return;
2263
2264 writel(1, ha->mem_ptr + IPS_REG_FLAP);
2265 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2266 udelay(25); /* 25 us */
2267
2268 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA)
2269 return;
2270
2271 /* Get Major version */
2272 writel(0x1FF, ha->mem_ptr + IPS_REG_FLAP);
2273 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2274 udelay(25); /* 25 us */
2275
2276 major = readb(ha->mem_ptr + IPS_REG_FLDP);
2277
2278 /* Get Minor version */
2279 writel(0x1FE, ha->mem_ptr + IPS_REG_FLAP);
2280 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2281 udelay(25); /* 25 us */
2282 minor = readb(ha->mem_ptr + IPS_REG_FLDP);
2283
2284 /* Get SubMinor version */
2285 writel(0x1FD, ha->mem_ptr + IPS_REG_FLAP);
2286 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2287 udelay(25); /* 25 us */
2288 subminor = readb(ha->mem_ptr + IPS_REG_FLDP);
2289
2290 } else {
2291 /* Programmed I/O */
2292
2293 /* test 1st byte */
2294 outl(0, ha->io_addr + IPS_REG_FLAP);
2295 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2296 udelay(25); /* 25 us */
2297
2298 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55)
2299 return;
2300
2301 outl(1, ha->io_addr + IPS_REG_FLAP);
2302 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2303 udelay(25); /* 25 us */
2304
2305 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA)
2306 return;
2307
2308 /* Get Major version */
2309 outl(0x1FF, ha->io_addr + IPS_REG_FLAP);
2310 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2311 udelay(25); /* 25 us */
2312
2313 major = inb(ha->io_addr + IPS_REG_FLDP);
2314
2315 /* Get Minor version */
2316 outl(0x1FE, ha->io_addr + IPS_REG_FLAP);
2317 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2318 udelay(25); /* 25 us */
2319
2320 minor = inb(ha->io_addr + IPS_REG_FLDP);
2321
2322 /* Get SubMinor version */
2323 outl(0x1FD, ha->io_addr + IPS_REG_FLAP);
2324 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2325 udelay(25); /* 25 us */
2326
2327 subminor = inb(ha->io_addr + IPS_REG_FLDP);
2328
2329 }
2330 } else {
2331 /* Morpheus Family - Send Command to the card */
2332
2333 buffer = ha->ioctl_data;
2334
2335 memset(buffer, 0, 0x1000);
2336
2337 scb = &ha->scbs[ha->max_cmds - 1];
2338
2339 ips_init_scb(ha, scb);
2340
2341 scb->timeout = ips_cmd_timeout;
2342 scb->cdb[0] = IPS_CMD_RW_BIOSFW;
2343
2344 scb->cmd.flashfw.op_code = IPS_CMD_RW_BIOSFW;
2345 scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb);
2346 scb->cmd.flashfw.type = 1;
2347 scb->cmd.flashfw.direction = 0;
2348 scb->cmd.flashfw.count = cpu_to_le32(0x800);
2349 scb->cmd.flashfw.total_packets = 1;
2350 scb->cmd.flashfw.packet_num = 0;
2351 scb->data_len = 0x1000;
2352 scb->cmd.flashfw.buffer_addr = ha->ioctl_busaddr;
2353
2354 /* issue the command */
2355 if (((ret =
2356 ips_send_wait(ha, scb, ips_cmd_timeout,
2357 intr)) == IPS_FAILURE)
2358 || (ret == IPS_SUCCESS_IMM)
2359 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
2360 /* Error occurred */
2361
2362 return;
2363 }
2364
2365 if ((buffer[0xC0] == 0x55) && (buffer[0xC1] == 0xAA)) {
2366 major = buffer[0x1ff + 0xC0]; /* Offset 0x1ff after the header (0xc0) */
2367 minor = buffer[0x1fe + 0xC0]; /* Offset 0x1fe after the header (0xc0) */
2368 subminor = buffer[0x1fd + 0xC0]; /* Offset 0x1fd after the header (0xc0) */
2369 } else {
2370 return;
2371 }
2372 }
2373
2374 ha->bios_version[0] = hex_asc_upper_hi(major);
2375 ha->bios_version[1] = '.';
2376 ha->bios_version[2] = hex_asc_upper_lo(major);
2377 ha->bios_version[3] = hex_asc_upper_lo(subminor);
2378 ha->bios_version[4] = '.';
2379 ha->bios_version[5] = hex_asc_upper_hi(minor);
2380 ha->bios_version[6] = hex_asc_upper_lo(minor);
2381 ha->bios_version[7] = 0;
2382 }
2383
2384 /****************************************************************************/
2385 /* */
2386 /* Routine Name: ips_hainit */
2387 /* */
2388 /* Routine Description: */
2389 /* */
2390 /* Initialize the controller */
2391 /* */
2392 /* NOTE: Assumes to be called from with a lock */
2393 /* */
2394 /****************************************************************************/
2395 static int
2396 ips_hainit(ips_ha_t * ha)
2397 {
2398 int i;
2399 struct timeval tv;
2400
2401 METHOD_TRACE("ips_hainit", 1);
2402
2403 if (!ha)
2404 return (0);
2405
2406 if (ha->func.statinit)
2407 (*ha->func.statinit) (ha);
2408
2409 if (ha->func.enableint)
2410 (*ha->func.enableint) (ha);
2411
2412 /* Send FFDC */
2413 ha->reset_count = 1;
2414 do_gettimeofday(&tv);
2415 ha->last_ffdc = tv.tv_sec;
2416 ips_ffdc_reset(ha, IPS_INTR_IORL);
2417
2418 if (!ips_read_config(ha, IPS_INTR_IORL)) {
2419 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2420 "unable to read config from controller.\n");
2421
2422 return (0);
2423 }
2424 /* end if */
2425 if (!ips_read_adapter_status(ha, IPS_INTR_IORL)) {
2426 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2427 "unable to read controller status.\n");
2428
2429 return (0);
2430 }
2431
2432 /* Identify this controller */
2433 ips_identify_controller(ha);
2434
2435 if (!ips_read_subsystem_parameters(ha, IPS_INTR_IORL)) {
2436 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2437 "unable to read subsystem parameters.\n");
2438
2439 return (0);
2440 }
2441
2442 /* write nvram user page 5 */
2443 if (!ips_write_driver_status(ha, IPS_INTR_IORL)) {
2444 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2445 "unable to write driver info to controller.\n");
2446
2447 return (0);
2448 }
2449
2450 /* If there are Logical Drives and a Reset Occurred, then an EraseStripeLock is Needed */
2451 if ((ha->conf->ucLogDriveCount > 0) && (ha->requires_esl == 1))
2452 ips_clear_adapter(ha, IPS_INTR_IORL);
2453
2454 /* set limits on SID, LUN, BUS */
2455 ha->ntargets = IPS_MAX_TARGETS + 1;
2456 ha->nlun = 1;
2457 ha->nbus = (ha->enq->ucMaxPhysicalDevices / IPS_MAX_TARGETS) + 1;
2458
2459 switch (ha->conf->logical_drive[0].ucStripeSize) {
2460 case 4:
2461 ha->max_xfer = 0x10000;
2462 break;
2463
2464 case 5:
2465 ha->max_xfer = 0x20000;
2466 break;
2467
2468 case 6:
2469 ha->max_xfer = 0x40000;
2470 break;
2471
2472 case 7:
2473 default:
2474 ha->max_xfer = 0x80000;
2475 break;
2476 }
2477
2478 /* setup max concurrent commands */
2479 if (le32_to_cpu(ha->subsys->param[4]) & 0x1) {
2480 /* Use the new method */
2481 ha->max_cmds = ha->enq->ucConcurrentCmdCount;
2482 } else {
2483 /* use the old method */
2484 switch (ha->conf->logical_drive[0].ucStripeSize) {
2485 case 4:
2486 ha->max_cmds = 32;
2487 break;
2488
2489 case 5:
2490 ha->max_cmds = 16;
2491 break;
2492
2493 case 6:
2494 ha->max_cmds = 8;
2495 break;
2496
2497 case 7:
2498 default:
2499 ha->max_cmds = 4;
2500 break;
2501 }
2502 }
2503
2504 /* Limit the Active Commands on a Lite Adapter */
2505 if ((ha->ad_type == IPS_ADTYPE_SERVERAID3L) ||
2506 (ha->ad_type == IPS_ADTYPE_SERVERAID4L) ||
2507 (ha->ad_type == IPS_ADTYPE_SERVERAID4LX)) {
2508 if ((ha->max_cmds > MaxLiteCmds) && (MaxLiteCmds))
2509 ha->max_cmds = MaxLiteCmds;
2510 }
2511
2512 /* set controller IDs */
2513 ha->ha_id[0] = IPS_ADAPTER_ID;
2514 for (i = 1; i < ha->nbus; i++) {
2515 ha->ha_id[i] = ha->conf->init_id[i - 1] & 0x1f;
2516 ha->dcdb_active[i - 1] = 0;
2517 }
2518
2519 return (1);
2520 }
2521
2522 /****************************************************************************/
2523 /* */
2524 /* Routine Name: ips_next */
2525 /* */
2526 /* Routine Description: */
2527 /* */
2528 /* Take the next command off the queue and send it to the controller */
2529 /* */
2530 /****************************************************************************/
2531 static void
2532 ips_next(ips_ha_t * ha, int intr)
2533 {
2534 ips_scb_t *scb;
2535 struct scsi_cmnd *SC;
2536 struct scsi_cmnd *p;
2537 struct scsi_cmnd *q;
2538 ips_copp_wait_item_t *item;
2539 int ret;
2540 struct Scsi_Host *host;
2541 METHOD_TRACE("ips_next", 1);
2542
2543 if (!ha)
2544 return;
2545 host = ips_sh[ha->host_num];
2546 /*
2547 * Block access to the queue function so
2548 * this command won't time out
2549 */
2550 if (intr == IPS_INTR_ON)
2551 spin_lock(host->host_lock);
2552
2553 if ((ha->subsys->param[3] & 0x300000)
2554 && (ha->scb_activelist.count == 0)) {
2555 struct timeval tv;
2556
2557 do_gettimeofday(&tv);
2558
2559 if (tv.tv_sec - ha->last_ffdc > IPS_SECS_8HOURS) {
2560 ha->last_ffdc = tv.tv_sec;
2561 ips_ffdc_time(ha);
2562 }
2563 }
2564
2565 /*
2566 * Send passthru commands
2567 * These have priority over normal I/O
2568 * but shouldn't affect performance too much
2569 * since we limit the number that can be active
2570 * on the card at any one time
2571 */
2572 while ((ha->num_ioctl < IPS_MAX_IOCTL) &&
2573 (ha->copp_waitlist.head) && (scb = ips_getscb(ha))) {
2574
2575 item = ips_removeq_copp_head(&ha->copp_waitlist);
2576 ha->num_ioctl++;
2577 if (intr == IPS_INTR_ON)
2578 spin_unlock(host->host_lock);
2579 scb->scsi_cmd = item->scsi_cmd;
2580 kfree(item);
2581
2582 ret = ips_make_passthru(ha, scb->scsi_cmd, scb, intr);
2583
2584 if (intr == IPS_INTR_ON)
2585 spin_lock(host->host_lock);
2586 switch (ret) {
2587 case IPS_FAILURE:
2588 if (scb->scsi_cmd) {
2589 scb->scsi_cmd->result = DID_ERROR << 16;
2590 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2591 }
2592
2593 ips_freescb(ha, scb);
2594 break;
2595 case IPS_SUCCESS_IMM:
2596 if (scb->scsi_cmd) {
2597 scb->scsi_cmd->result = DID_OK << 16;
2598 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2599 }
2600
2601 ips_freescb(ha, scb);
2602 break;
2603 default:
2604 break;
2605 } /* end case */
2606
2607 if (ret != IPS_SUCCESS) {
2608 ha->num_ioctl--;
2609 continue;
2610 }
2611
2612 ret = ips_send_cmd(ha, scb);
2613
2614 if (ret == IPS_SUCCESS)
2615 ips_putq_scb_head(&ha->scb_activelist, scb);
2616 else
2617 ha->num_ioctl--;
2618
2619 switch (ret) {
2620 case IPS_FAILURE:
2621 if (scb->scsi_cmd) {
2622 scb->scsi_cmd->result = DID_ERROR << 16;
2623 }
2624
2625 ips_freescb(ha, scb);
2626 break;
2627 case IPS_SUCCESS_IMM:
2628 ips_freescb(ha, scb);
2629 break;
2630 default:
2631 break;
2632 } /* end case */
2633
2634 }
2635
2636 /*
2637 * Send "Normal" I/O commands
2638 */
2639
2640 p = ha->scb_waitlist.head;
2641 while ((p) && (scb = ips_getscb(ha))) {
2642 if ((scmd_channel(p) > 0)
2643 && (ha->
2644 dcdb_active[scmd_channel(p) -
2645 1] & (1 << scmd_id(p)))) {
2646 ips_freescb(ha, scb);
2647 p = (struct scsi_cmnd *) p->host_scribble;
2648 continue;
2649 }
2650
2651 q = p;
2652 SC = ips_removeq_wait(&ha->scb_waitlist, q);
2653
2654 if (intr == IPS_INTR_ON)
2655 spin_unlock(host->host_lock); /* Unlock HA after command is taken off queue */
2656
2657 SC->result = DID_OK;
2658 SC->host_scribble = NULL;
2659
2660 scb->target_id = SC->device->id;
2661 scb->lun = SC->device->lun;
2662 scb->bus = SC->device->channel;
2663 scb->scsi_cmd = SC;
2664 scb->breakup = 0;
2665 scb->data_len = 0;
2666 scb->callback = ipsintr_done;
2667 scb->timeout = ips_cmd_timeout;
2668 memset(&scb->cmd, 0, 16);
2669
2670 /* copy in the CDB */
2671 memcpy(scb->cdb, SC->cmnd, SC->cmd_len);
2672
2673 scb->sg_count = scsi_dma_map(SC);
2674 BUG_ON(scb->sg_count < 0);
2675 if (scb->sg_count) {
2676 struct scatterlist *sg;
2677 int i;
2678
2679 scb->flags |= IPS_SCB_MAP_SG;
2680
2681 scsi_for_each_sg(SC, sg, scb->sg_count, i) {
2682 if (ips_fill_scb_sg_single
2683 (ha, sg_dma_address(sg), scb, i,
2684 sg_dma_len(sg)) < 0)
2685 break;
2686 }
2687 scb->dcdb.transfer_length = scb->data_len;
2688 } else {
2689 scb->data_busaddr = 0L;
2690 scb->sg_len = 0;
2691 scb->data_len = 0;
2692 scb->dcdb.transfer_length = 0;
2693 }
2694
2695 scb->dcdb.cmd_attribute =
2696 ips_command_direction[scb->scsi_cmd->cmnd[0]];
2697
2698 /* Allow a WRITE BUFFER Command to Have no Data */
2699 /* This is Used by Tape Flash Utilites */
2700 if ((scb->scsi_cmd->cmnd[0] == WRITE_BUFFER) &&
2701 (scb->data_len == 0))
2702 scb->dcdb.cmd_attribute = 0;
2703
2704 if (!(scb->dcdb.cmd_attribute & 0x3))
2705 scb->dcdb.transfer_length = 0;
2706
2707 if (scb->data_len >= IPS_MAX_XFER) {
2708 scb->dcdb.cmd_attribute |= IPS_TRANSFER64K;
2709 scb->dcdb.transfer_length = 0;
2710 }
2711 if (intr == IPS_INTR_ON)
2712 spin_lock(host->host_lock);
2713
2714 ret = ips_send_cmd(ha, scb);
2715
2716 switch (ret) {
2717 case IPS_SUCCESS:
2718 ips_putq_scb_head(&ha->scb_activelist, scb);
2719 break;
2720 case IPS_FAILURE:
2721 if (scb->scsi_cmd) {
2722 scb->scsi_cmd->result = DID_ERROR << 16;
2723 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2724 }
2725
2726 if (scb->bus)
2727 ha->dcdb_active[scb->bus - 1] &=
2728 ~(1 << scb->target_id);
2729
2730 ips_freescb(ha, scb);
2731 break;
2732 case IPS_SUCCESS_IMM:
2733 if (scb->scsi_cmd)
2734 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2735
2736 if (scb->bus)
2737 ha->dcdb_active[scb->bus - 1] &=
2738 ~(1 << scb->target_id);
2739
2740 ips_freescb(ha, scb);
2741 break;
2742 default:
2743 break;
2744 } /* end case */
2745
2746 p = (struct scsi_cmnd *) p->host_scribble;
2747
2748 } /* end while */
2749
2750 if (intr == IPS_INTR_ON)
2751 spin_unlock(host->host_lock);
2752 }
2753
2754 /****************************************************************************/
2755 /* */
2756 /* Routine Name: ips_putq_scb_head */
2757 /* */
2758 /* Routine Description: */
2759 /* */
2760 /* Add an item to the head of the queue */
2761 /* */
2762 /* ASSUMED to be called from within the HA lock */
2763 /* */
2764 /****************************************************************************/
2765 static void
2766 ips_putq_scb_head(ips_scb_queue_t * queue, ips_scb_t * item)
2767 {
2768 METHOD_TRACE("ips_putq_scb_head", 1);
2769
2770 if (!item)
2771 return;
2772
2773 item->q_next = queue->head;
2774 queue->head = item;
2775
2776 if (!queue->tail)
2777 queue->tail = item;
2778
2779 queue->count++;
2780 }
2781
2782 /****************************************************************************/
2783 /* */
2784 /* Routine Name: ips_removeq_scb_head */
2785 /* */
2786 /* Routine Description: */
2787 /* */
2788 /* Remove the head of the queue */
2789 /* */
2790 /* ASSUMED to be called from within the HA lock */
2791 /* */
2792 /****************************************************************************/
2793 static ips_scb_t *
2794 ips_removeq_scb_head(ips_scb_queue_t * queue)
2795 {
2796 ips_scb_t *item;
2797
2798 METHOD_TRACE("ips_removeq_scb_head", 1);
2799
2800 item = queue->head;
2801
2802 if (!item) {
2803 return (NULL);
2804 }
2805
2806 queue->head = item->q_next;
2807 item->q_next = NULL;
2808
2809 if (queue->tail == item)
2810 queue->tail = NULL;
2811
2812 queue->count--;
2813
2814 return (item);
2815 }
2816
2817 /****************************************************************************/
2818 /* */
2819 /* Routine Name: ips_removeq_scb */
2820 /* */
2821 /* Routine Description: */
2822 /* */
2823 /* Remove an item from a queue */
2824 /* */
2825 /* ASSUMED to be called from within the HA lock */
2826 /* */
2827 /****************************************************************************/
2828 static ips_scb_t *
2829 ips_removeq_scb(ips_scb_queue_t * queue, ips_scb_t * item)
2830 {
2831 ips_scb_t *p;
2832
2833 METHOD_TRACE("ips_removeq_scb", 1);
2834
2835 if (!item)
2836 return (NULL);
2837
2838 if (item == queue->head) {
2839 return (ips_removeq_scb_head(queue));
2840 }
2841
2842 p = queue->head;
2843
2844 while ((p) && (item != p->q_next))
2845 p = p->q_next;
2846
2847 if (p) {
2848 /* found a match */
2849 p->q_next = item->q_next;
2850
2851 if (!item->q_next)
2852 queue->tail = p;
2853
2854 item->q_next = NULL;
2855 queue->count--;
2856
2857 return (item);
2858 }
2859
2860 return (NULL);
2861 }
2862
2863 /****************************************************************************/
2864 /* */
2865 /* Routine Name: ips_putq_wait_tail */
2866 /* */
2867 /* Routine Description: */
2868 /* */
2869 /* Add an item to the tail of the queue */
2870 /* */
2871 /* ASSUMED to be called from within the HA lock */
2872 /* */
2873 /****************************************************************************/
2874 static void ips_putq_wait_tail(ips_wait_queue_entry_t *queue, struct scsi_cmnd *item)
2875 {
2876 METHOD_TRACE("ips_putq_wait_tail", 1);
2877
2878 if (!item)
2879 return;
2880
2881 item->host_scribble = NULL;
2882
2883 if (queue->tail)
2884 queue->tail->host_scribble = (char *) item;
2885
2886 queue->tail = item;
2887
2888 if (!queue->head)
2889 queue->head = item;
2890
2891 queue->count++;
2892 }
2893
2894 /****************************************************************************/
2895 /* */
2896 /* Routine Name: ips_removeq_wait_head */
2897 /* */
2898 /* Routine Description: */
2899 /* */
2900 /* Remove the head of the queue */
2901 /* */
2902 /* ASSUMED to be called from within the HA lock */
2903 /* */
2904 /****************************************************************************/
2905 static struct scsi_cmnd *ips_removeq_wait_head(ips_wait_queue_entry_t *queue)
2906 {
2907 struct scsi_cmnd *item;
2908
2909 METHOD_TRACE("ips_removeq_wait_head", 1);
2910
2911 item = queue->head;
2912
2913 if (!item) {
2914 return (NULL);
2915 }
2916
2917 queue->head = (struct scsi_cmnd *) item->host_scribble;
2918 item->host_scribble = NULL;
2919
2920 if (queue->tail == item)
2921 queue->tail = NULL;
2922
2923 queue->count--;
2924
2925 return (item);
2926 }
2927
2928 /****************************************************************************/
2929 /* */
2930 /* Routine Name: ips_removeq_wait */
2931 /* */
2932 /* Routine Description: */
2933 /* */
2934 /* Remove an item from a queue */
2935 /* */
2936 /* ASSUMED to be called from within the HA lock */
2937 /* */
2938 /****************************************************************************/
2939 static struct scsi_cmnd *ips_removeq_wait(ips_wait_queue_entry_t *queue,
2940 struct scsi_cmnd *item)
2941 {
2942 struct scsi_cmnd *p;
2943
2944 METHOD_TRACE("ips_removeq_wait", 1);
2945
2946 if (!item)
2947 return (NULL);
2948
2949 if (item == queue->head) {
2950 return (ips_removeq_wait_head(queue));
2951 }
2952
2953 p = queue->head;
2954
2955 while ((p) && (item != (struct scsi_cmnd *) p->host_scribble))
2956 p = (struct scsi_cmnd *) p->host_scribble;
2957
2958 if (p) {
2959 /* found a match */
2960 p->host_scribble = item->host_scribble;
2961
2962 if (!item->host_scribble)
2963 queue->tail = p;
2964
2965 item->host_scribble = NULL;
2966 queue->count--;
2967
2968 return (item);
2969 }
2970
2971 return (NULL);
2972 }
2973
2974 /****************************************************************************/
2975 /* */
2976 /* Routine Name: ips_putq_copp_tail */
2977 /* */
2978 /* Routine Description: */
2979 /* */
2980 /* Add an item to the tail of the queue */
2981 /* */
2982 /* ASSUMED to be called from within the HA lock */
2983 /* */
2984 /****************************************************************************/
2985 static void
2986 ips_putq_copp_tail(ips_copp_queue_t * queue, ips_copp_wait_item_t * item)
2987 {
2988 METHOD_TRACE("ips_putq_copp_tail", 1);
2989
2990 if (!item)
2991 return;
2992
2993 item->next = NULL;
2994
2995 if (queue->tail)
2996 queue->tail->next = item;
2997
2998 queue->tail = item;
2999
3000 if (!queue->head)
3001 queue->head = item;
3002
3003 queue->count++;
3004 }
3005
3006 /****************************************************************************/
3007 /* */
3008 /* Routine Name: ips_removeq_copp_head */
3009 /* */
3010 /* Routine Description: */
3011 /* */
3012 /* Remove the head of the queue */
3013 /* */
3014 /* ASSUMED to be called from within the HA lock */
3015 /* */
3016 /****************************************************************************/
3017 static ips_copp_wait_item_t *
3018 ips_removeq_copp_head(ips_copp_queue_t * queue)
3019 {
3020 ips_copp_wait_item_t *item;
3021
3022 METHOD_TRACE("ips_removeq_copp_head", 1);
3023
3024 item = queue->head;
3025
3026 if (!item) {
3027 return (NULL);
3028 }
3029
3030 queue->head = item->next;
3031 item->next = NULL;
3032
3033 if (queue->tail == item)
3034 queue->tail = NULL;
3035
3036 queue->count--;
3037
3038 return (item);
3039 }
3040
3041 /****************************************************************************/
3042 /* */
3043 /* Routine Name: ips_removeq_copp */
3044 /* */
3045 /* Routine Description: */
3046 /* */
3047 /* Remove an item from a queue */
3048 /* */
3049 /* ASSUMED to be called from within the HA lock */
3050 /* */
3051 /****************************************************************************/
3052 static ips_copp_wait_item_t *
3053 ips_removeq_copp(ips_copp_queue_t * queue, ips_copp_wait_item_t * item)
3054 {
3055 ips_copp_wait_item_t *p;
3056
3057 METHOD_TRACE("ips_removeq_copp", 1);
3058
3059 if (!item)
3060 return (NULL);
3061
3062 if (item == queue->head) {
3063 return (ips_removeq_copp_head(queue));
3064 }
3065
3066 p = queue->head;
3067
3068 while ((p) && (item != p->next))
3069 p = p->next;
3070
3071 if (p) {
3072 /* found a match */
3073 p->next = item->next;
3074
3075 if (!item->next)
3076 queue->tail = p;
3077
3078 item->next = NULL;
3079 queue->count--;
3080
3081 return (item);
3082 }
3083
3084 return (NULL);
3085 }
3086
3087 /****************************************************************************/
3088 /* */
3089 /* Routine Name: ipsintr_blocking */
3090 /* */
3091 /* Routine Description: */
3092 /* */
3093 /* Finalize an interrupt for internal commands */
3094 /* */
3095 /****************************************************************************/
3096 static void
3097 ipsintr_blocking(ips_ha_t * ha, ips_scb_t * scb)
3098 {
3099 METHOD_TRACE("ipsintr_blocking", 2);
3100
3101 ips_freescb(ha, scb);
3102 if ((ha->waitflag == TRUE) && (ha->cmd_in_progress == scb->cdb[0])) {
3103 ha->waitflag = FALSE;
3104
3105 return;
3106 }
3107 }
3108
3109 /****************************************************************************/
3110 /* */
3111 /* Routine Name: ipsintr_done */
3112 /* */
3113 /* Routine Description: */
3114 /* */
3115 /* Finalize an interrupt for non-internal commands */
3116 /* */
3117 /****************************************************************************/
3118 static void
3119 ipsintr_done(ips_ha_t * ha, ips_scb_t * scb)
3120 {
3121 METHOD_TRACE("ipsintr_done", 2);
3122
3123 if (!scb) {
3124 IPS_PRINTK(KERN_WARNING, ha->pcidev,
3125 "Spurious interrupt; scb NULL.\n");
3126
3127 return;
3128 }
3129
3130 if (scb->scsi_cmd == NULL) {
3131 /* unexpected interrupt */
3132 IPS_PRINTK(KERN_WARNING, ha->pcidev,
3133 "Spurious interrupt; scsi_cmd not set.\n");
3134
3135 return;
3136 }
3137
3138 ips_done(ha, scb);
3139 }
3140
3141 /****************************************************************************/
3142 /* */
3143 /* Routine Name: ips_done */
3144 /* */
3145 /* Routine Description: */
3146 /* */
3147 /* Do housekeeping on completed commands */
3148 /* ASSUMED to be called form within the request lock */
3149 /****************************************************************************/
3150 static void
3151 ips_done(ips_ha_t * ha, ips_scb_t * scb)
3152 {
3153 int ret;
3154
3155 METHOD_TRACE("ips_done", 1);
3156
3157 if (!scb)
3158 return;
3159
3160 if ((scb->scsi_cmd) && (ips_is_passthru(scb->scsi_cmd))) {
3161 ips_cleanup_passthru(ha, scb);
3162 ha->num_ioctl--;
3163 } else {
3164 /*
3165 * Check to see if this command had too much
3166 * data and had to be broke up. If so, queue
3167 * the rest of the data and continue.
3168 */
3169 if ((scb->breakup) || (scb->sg_break)) {
3170 struct scatterlist *sg;
3171 int i, sg_dma_index, ips_sg_index = 0;
3172
3173 /* we had a data breakup */
3174 scb->data_len = 0;
3175
3176 sg = scsi_sglist(scb->scsi_cmd);
3177
3178 /* Spin forward to last dma chunk */
3179 sg_dma_index = scb->breakup;
3180 for (i = 0; i < scb->breakup; i++)
3181 sg = sg_next(sg);
3182
3183 /* Take care of possible partial on last chunk */
3184 ips_fill_scb_sg_single(ha,
3185 sg_dma_address(sg),
3186 scb, ips_sg_index++,
3187 sg_dma_len(sg));
3188
3189 for (; sg_dma_index < scsi_sg_count(scb->scsi_cmd);
3190 sg_dma_index++, sg = sg_next(sg)) {
3191 if (ips_fill_scb_sg_single
3192 (ha,
3193 sg_dma_address(sg),
3194 scb, ips_sg_index++,
3195 sg_dma_len(sg)) < 0)
3196 break;
3197 }
3198
3199 scb->dcdb.transfer_length = scb->data_len;
3200 scb->dcdb.cmd_attribute |=
3201 ips_command_direction[scb->scsi_cmd->cmnd[0]];
3202
3203 if (!(scb->dcdb.cmd_attribute & 0x3))
3204 scb->dcdb.transfer_length = 0;
3205
3206 if (scb->data_len >= IPS_MAX_XFER) {
3207 scb->dcdb.cmd_attribute |= IPS_TRANSFER64K;
3208 scb->dcdb.transfer_length = 0;
3209 }
3210
3211 ret = ips_send_cmd(ha, scb);
3212
3213 switch (ret) {
3214 case IPS_FAILURE:
3215 if (scb->scsi_cmd) {
3216 scb->scsi_cmd->result = DID_ERROR << 16;
3217 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
3218 }
3219
3220 ips_freescb(ha, scb);
3221 break;
3222 case IPS_SUCCESS_IMM:
3223 if (scb->scsi_cmd) {
3224 scb->scsi_cmd->result = DID_ERROR << 16;
3225 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
3226 }
3227
3228 ips_freescb(ha, scb);
3229 break;
3230 default:
3231 break;
3232 } /* end case */
3233
3234 return;
3235 }
3236 } /* end if passthru */
3237
3238 if (scb->bus) {
3239 ha->dcdb_active[scb->bus - 1] &= ~(1 << scb->target_id);
3240 }
3241
3242 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
3243
3244 ips_freescb(ha, scb);
3245 }
3246
3247 /****************************************************************************/
3248 /* */
3249 /* Routine Name: ips_map_status */
3250 /* */
3251 /* Routine Description: */
3252 /* */
3253 /* Map Controller Error codes to Linux Error Codes */
3254 /* */
3255 /****************************************************************************/
3256 static int
3257 ips_map_status(ips_ha_t * ha, ips_scb_t * scb, ips_stat_t * sp)
3258 {
3259 int errcode;
3260 int device_error;
3261 uint32_t transfer_len;
3262 IPS_DCDB_TABLE_TAPE *tapeDCDB;
3263 IPS_SCSI_INQ_DATA inquiryData;
3264
3265 METHOD_TRACE("ips_map_status", 1);
3266
3267 if (scb->bus) {
3268 DEBUG_VAR(2,
3269 "(%s%d) Physical device error (%d %d %d): %x %x, Sense Key: %x, ASC: %x, ASCQ: %x",
3270 ips_name, ha->host_num,
3271 scb->scsi_cmd->device->channel,
3272 scb->scsi_cmd->device->id, scb->scsi_cmd->device->lun,
3273 scb->basic_status, scb->extended_status,
3274 scb->extended_status ==
3275 IPS_ERR_CKCOND ? scb->dcdb.sense_info[2] & 0xf : 0,
3276 scb->extended_status ==
3277 IPS_ERR_CKCOND ? scb->dcdb.sense_info[12] : 0,
3278 scb->extended_status ==
3279 IPS_ERR_CKCOND ? scb->dcdb.sense_info[13] : 0);
3280 }
3281
3282 /* default driver error */
3283 errcode = DID_ERROR;
3284 device_error = 0;
3285
3286 switch (scb->basic_status & IPS_GSC_STATUS_MASK) {
3287 case IPS_CMD_TIMEOUT:
3288 errcode = DID_TIME_OUT;
3289 break;
3290
3291 case IPS_INVAL_OPCO:
3292 case IPS_INVAL_CMD_BLK:
3293 case IPS_INVAL_PARM_BLK:
3294 case IPS_LD_ERROR:
3295 case IPS_CMD_CMPLT_WERROR:
3296 break;
3297
3298 case IPS_PHYS_DRV_ERROR:
3299 switch (scb->extended_status) {
3300 case IPS_ERR_SEL_TO:
3301 if (scb->bus)
3302 errcode = DID_NO_CONNECT;
3303
3304 break;
3305
3306 case IPS_ERR_OU_RUN:
3307 if ((scb->cmd.dcdb.op_code == IPS_CMD_EXTENDED_DCDB) ||
3308 (scb->cmd.dcdb.op_code ==
3309 IPS_CMD_EXTENDED_DCDB_SG)) {
3310 tapeDCDB = (IPS_DCDB_TABLE_TAPE *) & scb->dcdb;
3311 transfer_len = tapeDCDB->transfer_length;
3312 } else {
3313 transfer_len =
3314 (uint32_t) scb->dcdb.transfer_length;
3315 }
3316
3317 if ((scb->bus) && (transfer_len < scb->data_len)) {
3318 /* Underrun - set default to no error */
3319 errcode = DID_OK;
3320
3321 /* Restrict access to physical DASD */
3322 if (scb->scsi_cmd->cmnd[0] == INQUIRY) {
3323 ips_scmd_buf_read(scb->scsi_cmd,
3324 &inquiryData, sizeof (inquiryData));
3325 if ((inquiryData.DeviceType & 0x1f) == TYPE_DISK) {
3326 errcode = DID_TIME_OUT;
3327 break;
3328 }
3329 }
3330 } else
3331 errcode = DID_ERROR;
3332
3333 break;
3334
3335 case IPS_ERR_RECOVERY:
3336 /* don't fail recovered errors */
3337 if (scb->bus)
3338 errcode = DID_OK;
3339
3340 break;
3341
3342 case IPS_ERR_HOST_RESET:
3343 case IPS_ERR_DEV_RESET:
3344 errcode = DID_RESET;
3345 break;
3346
3347 case IPS_ERR_CKCOND:
3348 if (scb->bus) {
3349 if ((scb->cmd.dcdb.op_code ==
3350 IPS_CMD_EXTENDED_DCDB)
3351 || (scb->cmd.dcdb.op_code ==
3352 IPS_CMD_EXTENDED_DCDB_SG)) {
3353 tapeDCDB =
3354 (IPS_DCDB_TABLE_TAPE *) & scb->dcdb;
3355 memcpy(scb->scsi_cmd->sense_buffer,
3356 tapeDCDB->sense_info,
3357 SCSI_SENSE_BUFFERSIZE);
3358 } else {
3359 memcpy(scb->scsi_cmd->sense_buffer,
3360 scb->dcdb.sense_info,
3361 SCSI_SENSE_BUFFERSIZE);
3362 }
3363 device_error = 2; /* check condition */
3364 }
3365
3366 errcode = DID_OK;
3367
3368 break;
3369
3370 default:
3371 errcode = DID_ERROR;
3372 break;
3373
3374 } /* end switch */
3375 } /* end switch */
3376
3377 scb->scsi_cmd->result = device_error | (errcode << 16);
3378
3379 return (1);
3380 }
3381
3382 /****************************************************************************/
3383 /* */
3384 /* Routine Name: ips_send_wait */
3385 /* */
3386 /* Routine Description: */
3387 /* */
3388 /* Send a command to the controller and wait for it to return */
3389 /* */
3390 /* The FFDC Time Stamp use this function for the callback, but doesn't */
3391 /* actually need to wait. */
3392 /****************************************************************************/
3393 static int
3394 ips_send_wait(ips_ha_t * ha, ips_scb_t * scb, int timeout, int intr)
3395 {
3396 int ret;
3397
3398 METHOD_TRACE("ips_send_wait", 1);
3399
3400 if (intr != IPS_FFDC) { /* Won't be Waiting if this is a Time Stamp */
3401 ha->waitflag = TRUE;
3402 ha->cmd_in_progress = scb->cdb[0];
3403 }
3404 scb->callback = ipsintr_blocking;
3405 ret = ips_send_cmd(ha, scb);
3406
3407 if ((ret == IPS_FAILURE) || (ret == IPS_SUCCESS_IMM))
3408 return (ret);
3409
3410 if (intr != IPS_FFDC) /* Don't Wait around if this is a Time Stamp */
3411 ret = ips_wait(ha, timeout, intr);
3412
3413 return (ret);
3414 }
3415
3416 /****************************************************************************/
3417 /* */
3418 /* Routine Name: ips_scmd_buf_write */
3419 /* */
3420 /* Routine Description: */
3421 /* Write data to struct scsi_cmnd request_buffer at proper offsets */
3422 /****************************************************************************/
3423 static void
3424 ips_scmd_buf_write(struct scsi_cmnd *scmd, void *data, unsigned int count)
3425 {
3426 unsigned long flags;
3427
3428 local_irq_save(flags);
3429 scsi_sg_copy_from_buffer(scmd, data, count);
3430 local_irq_restore(flags);
3431 }
3432
3433 /****************************************************************************/
3434 /* */
3435 /* Routine Name: ips_scmd_buf_read */
3436 /* */
3437 /* Routine Description: */
3438 /* Copy data from a struct scsi_cmnd to a new, linear buffer */
3439 /****************************************************************************/
3440 static void
3441 ips_scmd_buf_read(struct scsi_cmnd *scmd, void *data, unsigned int count)
3442 {
3443 unsigned long flags;
3444
3445 local_irq_save(flags);
3446 scsi_sg_copy_to_buffer(scmd, data, count);
3447 local_irq_restore(flags);
3448 }
3449
3450 /****************************************************************************/
3451 /* */
3452 /* Routine Name: ips_send_cmd */
3453 /* */
3454 /* Routine Description: */
3455 /* */
3456 /* Map SCSI commands to ServeRAID commands for logical drives */
3457 /* */
3458 /****************************************************************************/
3459 static int
3460 ips_send_cmd(ips_ha_t * ha, ips_scb_t * scb)
3461 {
3462 int ret;
3463 char *sp;
3464 int device_error;
3465 IPS_DCDB_TABLE_TAPE *tapeDCDB;
3466 int TimeOut;
3467
3468 METHOD_TRACE("ips_send_cmd", 1);
3469
3470 ret = IPS_SUCCESS;
3471
3472 if (!scb->scsi_cmd) {
3473 /* internal command */
3474
3475 if (scb->bus > 0) {
3476 /* Controller commands can't be issued */
3477 /* to real devices -- fail them */
3478 if ((ha->waitflag == TRUE) &&
3479 (ha->cmd_in_progress == scb->cdb[0])) {
3480 ha->waitflag = FALSE;
3481 }
3482
3483 return (1);
3484 }
3485 } else if ((scb->bus == 0) && (!ips_is_passthru(scb->scsi_cmd))) {
3486 /* command to logical bus -- interpret */
3487 ret = IPS_SUCCESS_IMM;
3488
3489 switch (scb->scsi_cmd->cmnd[0]) {
3490 case ALLOW_MEDIUM_REMOVAL:
3491 case REZERO_UNIT:
3492 case ERASE:
3493 case WRITE_FILEMARKS:
3494 case SPACE:
3495 scb->scsi_cmd->result = DID_ERROR << 16;
3496 break;
3497
3498 case START_STOP:
3499 scb->scsi_cmd->result = DID_OK << 16;
3500 break;
3501
3502 case TEST_UNIT_READY:
3503 case INQUIRY:
3504 if (scb->target_id == IPS_ADAPTER_ID) {
3505 /*
3506 * Either we have a TUR
3507 * or we have a SCSI inquiry
3508 */
3509 if (scb->scsi_cmd->cmnd[0] == TEST_UNIT_READY)
3510 scb->scsi_cmd->result = DID_OK << 16;
3511
3512 if (scb->scsi_cmd->cmnd[0] == INQUIRY) {
3513 IPS_SCSI_INQ_DATA inquiry;
3514
3515 memset(&inquiry, 0,
3516 sizeof (IPS_SCSI_INQ_DATA));
3517
3518 inquiry.DeviceType =
3519 IPS_SCSI_INQ_TYPE_PROCESSOR;
3520 inquiry.DeviceTypeQualifier =
3521 IPS_SCSI_INQ_LU_CONNECTED;
3522 inquiry.Version = IPS_SCSI_INQ_REV2;
3523 inquiry.ResponseDataFormat =
3524 IPS_SCSI_INQ_RD_REV2;
3525 inquiry.AdditionalLength = 31;
3526 inquiry.Flags[0] =
3527 IPS_SCSI_INQ_Address16;
3528 inquiry.Flags[1] =
3529 IPS_SCSI_INQ_WBus16 |
3530 IPS_SCSI_INQ_Sync;
3531 strncpy(inquiry.VendorId, "IBM ",
3532 8);
3533 strncpy(inquiry.ProductId,
3534 "SERVERAID ", 16);
3535 strncpy(inquiry.ProductRevisionLevel,
3536 "1.00", 4);
3537
3538 ips_scmd_buf_write(scb->scsi_cmd,
3539 &inquiry,
3540 sizeof (inquiry));
3541
3542 scb->scsi_cmd->result = DID_OK << 16;
3543 }
3544 } else {
3545 scb->cmd.logical_info.op_code = IPS_CMD_GET_LD_INFO;
3546 scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb);
3547 scb->cmd.logical_info.reserved = 0;
3548 scb->cmd.logical_info.reserved2 = 0;
3549 scb->data_len = sizeof (IPS_LD_INFO);
3550 scb->data_busaddr = ha->logical_drive_info_dma_addr;
3551 scb->flags = 0;
3552 scb->cmd.logical_info.buffer_addr = scb->data_busaddr;
3553 ret = IPS_SUCCESS;
3554 }
3555
3556 break;
3557
3558 case REQUEST_SENSE:
3559 ips_reqsen(ha, scb);
3560 scb->scsi_cmd->result = DID_OK << 16;
3561 break;
3562
3563 case READ_6:
3564 case WRITE_6:
3565 if (!scb->sg_len) {
3566 scb->cmd.basic_io.op_code =
3567 (scb->scsi_cmd->cmnd[0] ==
3568 READ_6) ? IPS_CMD_READ : IPS_CMD_WRITE;
3569 scb->cmd.basic_io.enhanced_sg = 0;
3570 scb->cmd.basic_io.sg_addr =
3571 cpu_to_le32(scb->data_busaddr);
3572 } else {
3573 scb->cmd.basic_io.op_code =
3574 (scb->scsi_cmd->cmnd[0] ==
3575 READ_6) ? IPS_CMD_READ_SG :
3576 IPS_CMD_WRITE_SG;
3577 scb->cmd.basic_io.enhanced_sg =
3578 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3579 scb->cmd.basic_io.sg_addr =
3580 cpu_to_le32(scb->sg_busaddr);
3581 }
3582
3583 scb->cmd.basic_io.segment_4G = 0;
3584 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3585 scb->cmd.basic_io.log_drv = scb->target_id;
3586 scb->cmd.basic_io.sg_count = scb->sg_len;
3587
3588 if (scb->cmd.basic_io.lba)
3589 le32_add_cpu(&scb->cmd.basic_io.lba,
3590 le16_to_cpu(scb->cmd.basic_io.
3591 sector_count));
3592 else
3593 scb->cmd.basic_io.lba =
3594 (((scb->scsi_cmd->
3595 cmnd[1] & 0x1f) << 16) | (scb->scsi_cmd->
3596 cmnd[2] << 8) |
3597 (scb->scsi_cmd->cmnd[3]));
3598
3599 scb->cmd.basic_io.sector_count =
3600 cpu_to_le16(scb->data_len / IPS_BLKSIZE);
3601
3602 if (le16_to_cpu(scb->cmd.basic_io.sector_count) == 0)
3603 scb->cmd.basic_io.sector_count =
3604 cpu_to_le16(256);
3605
3606 ret = IPS_SUCCESS;
3607 break;
3608
3609 case READ_10:
3610 case WRITE_10:
3611 if (!scb->sg_len) {
3612 scb->cmd.basic_io.op_code =
3613 (scb->scsi_cmd->cmnd[0] ==
3614 READ_10) ? IPS_CMD_READ : IPS_CMD_WRITE;
3615 scb->cmd.basic_io.enhanced_sg = 0;
3616 scb->cmd.basic_io.sg_addr =
3617 cpu_to_le32(scb->data_busaddr);
3618 } else {
3619 scb->cmd.basic_io.op_code =
3620 (scb->scsi_cmd->cmnd[0] ==
3621 READ_10) ? IPS_CMD_READ_SG :
3622 IPS_CMD_WRITE_SG;
3623 scb->cmd.basic_io.enhanced_sg =
3624 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3625 scb->cmd.basic_io.sg_addr =
3626 cpu_to_le32(scb->sg_busaddr);
3627 }
3628
3629 scb->cmd.basic_io.segment_4G = 0;
3630 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3631 scb->cmd.basic_io.log_drv = scb->target_id;
3632 scb->cmd.basic_io.sg_count = scb->sg_len;
3633
3634 if (scb->cmd.basic_io.lba)
3635 le32_add_cpu(&scb->cmd.basic_io.lba,
3636 le16_to_cpu(scb->cmd.basic_io.
3637 sector_count));
3638 else
3639 scb->cmd.basic_io.lba =
3640 ((scb->scsi_cmd->cmnd[2] << 24) | (scb->
3641 scsi_cmd->
3642 cmnd[3]
3643 << 16) |
3644 (scb->scsi_cmd->cmnd[4] << 8) | scb->
3645 scsi_cmd->cmnd[5]);
3646
3647 scb->cmd.basic_io.sector_count =
3648 cpu_to_le16(scb->data_len / IPS_BLKSIZE);
3649
3650 if (cpu_to_le16(scb->cmd.basic_io.sector_count) == 0) {
3651 /*
3652 * This is a null condition
3653 * we don't have to do anything
3654 * so just return
3655 */
3656 scb->scsi_cmd->result = DID_OK << 16;
3657 } else
3658 ret = IPS_SUCCESS;
3659
3660 break;
3661
3662 case RESERVE:
3663 case RELEASE:
3664 scb->scsi_cmd->result = DID_OK << 16;
3665 break;
3666
3667 case MODE_SENSE:
3668 scb->cmd.basic_io.op_code = IPS_CMD_ENQUIRY;
3669 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3670 scb->cmd.basic_io.segment_4G = 0;
3671 scb->cmd.basic_io.enhanced_sg = 0;
3672 scb->data_len = sizeof (*ha->enq);
3673 scb->cmd.basic_io.sg_addr = ha->enq_busaddr;
3674 ret = IPS_SUCCESS;
3675 break;
3676
3677 case READ_CAPACITY:
3678 scb->cmd.logical_info.op_code = IPS_CMD_GET_LD_INFO;
3679 scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb);
3680 scb->cmd.logical_info.reserved = 0;
3681 scb->cmd.logical_info.reserved2 = 0;
3682 scb->cmd.logical_info.reserved3 = 0;
3683 scb->data_len = sizeof (IPS_LD_INFO);
3684 scb->data_busaddr = ha->logical_drive_info_dma_addr;
3685 scb->flags = 0;
3686 scb->cmd.logical_info.buffer_addr = scb->data_busaddr;
3687 ret = IPS_SUCCESS;
3688 break;
3689
3690 case SEND_DIAGNOSTIC:
3691 case REASSIGN_BLOCKS:
3692 case FORMAT_UNIT:
3693 case SEEK_10:
3694 case VERIFY:
3695 case READ_DEFECT_DATA:
3696 case READ_BUFFER:
3697 case WRITE_BUFFER:
3698 scb->scsi_cmd->result = DID_OK << 16;
3699 break;
3700
3701 default:
3702 /* Set the Return Info to appear like the Command was */
3703 /* attempted, a Check Condition occurred, and Sense */
3704 /* Data indicating an Invalid CDB OpCode is returned. */
3705 sp = (char *) scb->scsi_cmd->sense_buffer;
3706
3707 sp[0] = 0x70; /* Error Code */
3708 sp[2] = ILLEGAL_REQUEST; /* Sense Key 5 Illegal Req. */
3709 sp[7] = 0x0A; /* Additional Sense Length */
3710 sp[12] = 0x20; /* ASC = Invalid OpCode */
3711 sp[13] = 0x00; /* ASCQ */
3712
3713 device_error = 2; /* Indicate Check Condition */
3714 scb->scsi_cmd->result = device_error | (DID_OK << 16);
3715 break;
3716 } /* end switch */
3717 }
3718 /* end if */
3719 if (ret == IPS_SUCCESS_IMM)
3720 return (ret);
3721
3722 /* setup DCDB */
3723 if (scb->bus > 0) {
3724
3725 /* If we already know the Device is Not there, no need to attempt a Command */
3726 /* This also protects an NT FailOver Controller from getting CDB's sent to it */
3727 if (ha->conf->dev[scb->bus - 1][scb->target_id].ucState == 0) {
3728 scb->scsi_cmd->result = DID_NO_CONNECT << 16;
3729 return (IPS_SUCCESS_IMM);
3730 }
3731
3732 ha->dcdb_active[scb->bus - 1] |= (1 << scb->target_id);
3733 scb->cmd.dcdb.command_id = IPS_COMMAND_ID(ha, scb);
3734 scb->cmd.dcdb.dcdb_address = cpu_to_le32(scb->scb_busaddr +
3735 (unsigned long) &scb->
3736 dcdb -
3737 (unsigned long) scb);
3738 scb->cmd.dcdb.reserved = 0;
3739 scb->cmd.dcdb.reserved2 = 0;
3740 scb->cmd.dcdb.reserved3 = 0;
3741 scb->cmd.dcdb.segment_4G = 0;
3742 scb->cmd.dcdb.enhanced_sg = 0;
3743
3744 TimeOut = scb->scsi_cmd->request->timeout;
3745
3746 if (ha->subsys->param[4] & 0x00100000) { /* If NEW Tape DCDB is Supported */
3747 if (!scb->sg_len) {
3748 scb->cmd.dcdb.op_code = IPS_CMD_EXTENDED_DCDB;
3749 } else {
3750 scb->cmd.dcdb.op_code =
3751 IPS_CMD_EXTENDED_DCDB_SG;
3752 scb->cmd.dcdb.enhanced_sg =
3753 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3754 }
3755
3756 tapeDCDB = (IPS_DCDB_TABLE_TAPE *) & scb->dcdb; /* Use Same Data Area as Old DCDB Struct */
3757 tapeDCDB->device_address =
3758 ((scb->bus - 1) << 4) | scb->target_id;
3759 tapeDCDB->cmd_attribute |= IPS_DISCONNECT_ALLOWED;
3760 tapeDCDB->cmd_attribute &= ~IPS_TRANSFER64K; /* Always Turn OFF 64K Size Flag */
3761
3762 if (TimeOut) {
3763 if (TimeOut < (10 * HZ))
3764 tapeDCDB->cmd_attribute |= IPS_TIMEOUT10; /* TimeOut is 10 Seconds */
3765 else if (TimeOut < (60 * HZ))
3766 tapeDCDB->cmd_attribute |= IPS_TIMEOUT60; /* TimeOut is 60 Seconds */
3767 else if (TimeOut < (1200 * HZ))
3768 tapeDCDB->cmd_attribute |= IPS_TIMEOUT20M; /* TimeOut is 20 Minutes */
3769 }
3770
3771 tapeDCDB->cdb_length = scb->scsi_cmd->cmd_len;
3772 tapeDCDB->reserved_for_LUN = 0;
3773 tapeDCDB->transfer_length = scb->data_len;
3774 if (scb->cmd.dcdb.op_code == IPS_CMD_EXTENDED_DCDB_SG)
3775 tapeDCDB->buffer_pointer =
3776 cpu_to_le32(scb->sg_busaddr);
3777 else
3778 tapeDCDB->buffer_pointer =
3779 cpu_to_le32(scb->data_busaddr);
3780 tapeDCDB->sg_count = scb->sg_len;
3781 tapeDCDB->sense_length = sizeof (tapeDCDB->sense_info);
3782 tapeDCDB->scsi_status = 0;
3783 tapeDCDB->reserved = 0;
3784 memcpy(tapeDCDB->scsi_cdb, scb->scsi_cmd->cmnd,
3785 scb->scsi_cmd->cmd_len);
3786 } else {
3787 if (!scb->sg_len) {
3788 scb->cmd.dcdb.op_code = IPS_CMD_DCDB;
3789 } else {
3790 scb->cmd.dcdb.op_code = IPS_CMD_DCDB_SG;
3791 scb->cmd.dcdb.enhanced_sg =
3792 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3793 }
3794
3795 scb->dcdb.device_address =
3796 ((scb->bus - 1) << 4) | scb->target_id;
3797 scb->dcdb.cmd_attribute |= IPS_DISCONNECT_ALLOWED;
3798
3799 if (TimeOut) {
3800 if (TimeOut < (10 * HZ))
3801 scb->dcdb.cmd_attribute |= IPS_TIMEOUT10; /* TimeOut is 10 Seconds */
3802 else if (TimeOut < (60 * HZ))
3803 scb->dcdb.cmd_attribute |= IPS_TIMEOUT60; /* TimeOut is 60 Seconds */
3804 else if (TimeOut < (1200 * HZ))
3805 scb->dcdb.cmd_attribute |= IPS_TIMEOUT20M; /* TimeOut is 20 Minutes */
3806 }
3807
3808 scb->dcdb.transfer_length = scb->data_len;
3809 if (scb->dcdb.cmd_attribute & IPS_TRANSFER64K)
3810 scb->dcdb.transfer_length = 0;
3811 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB_SG)
3812 scb->dcdb.buffer_pointer =
3813 cpu_to_le32(scb->sg_busaddr);
3814 else
3815 scb->dcdb.buffer_pointer =
3816 cpu_to_le32(scb->data_busaddr);
3817 scb->dcdb.cdb_length = scb->scsi_cmd->cmd_len;
3818 scb->dcdb.sense_length = sizeof (scb->dcdb.sense_info);
3819 scb->dcdb.sg_count = scb->sg_len;
3820 scb->dcdb.reserved = 0;
3821 memcpy(scb->dcdb.scsi_cdb, scb->scsi_cmd->cmnd,
3822 scb->scsi_cmd->cmd_len);
3823 scb->dcdb.scsi_status = 0;
3824 scb->dcdb.reserved2[0] = 0;
3825 scb->dcdb.reserved2[1] = 0;
3826 scb->dcdb.reserved2[2] = 0;
3827 }
3828 }
3829
3830 return ((*ha->func.issue) (ha, scb));
3831 }
3832
3833 /****************************************************************************/
3834 /* */
3835 /* Routine Name: ips_chk_status */
3836 /* */
3837 /* Routine Description: */
3838 /* */
3839 /* Check the status of commands to logical drives */
3840 /* Assumed to be called with the HA lock */
3841 /****************************************************************************/
3842 static void
3843 ips_chkstatus(ips_ha_t * ha, IPS_STATUS * pstatus)
3844 {
3845 ips_scb_t *scb;
3846 ips_stat_t *sp;
3847 uint8_t basic_status;
3848 uint8_t ext_status;
3849 int errcode;
3850 IPS_SCSI_INQ_DATA inquiryData;
3851
3852 METHOD_TRACE("ips_chkstatus", 1);
3853
3854 scb = &ha->scbs[pstatus->fields.command_id];
3855 scb->basic_status = basic_status =
3856 pstatus->fields.basic_status & IPS_BASIC_STATUS_MASK;
3857 scb->extended_status = ext_status = pstatus->fields.extended_status;
3858
3859 sp = &ha->sp;
3860 sp->residue_len = 0;
3861 sp->scb_addr = (void *) scb;
3862
3863 /* Remove the item from the active queue */
3864 ips_removeq_scb(&ha->scb_activelist, scb);
3865
3866 if (!scb->scsi_cmd)
3867 /* internal commands are handled in do_ipsintr */
3868 return;
3869
3870 DEBUG_VAR(2, "(%s%d) ips_chkstatus: cmd 0x%X id %d (%d %d %d)",
3871 ips_name,
3872 ha->host_num,
3873 scb->cdb[0],
3874 scb->cmd.basic_io.command_id,
3875 scb->bus, scb->target_id, scb->lun);
3876
3877 if ((scb->scsi_cmd) && (ips_is_passthru(scb->scsi_cmd)))
3878 /* passthru - just returns the raw result */
3879 return;
3880
3881 errcode = DID_OK;
3882
3883 if (((basic_status & IPS_GSC_STATUS_MASK) == IPS_CMD_SUCCESS) ||
3884 ((basic_status & IPS_GSC_STATUS_MASK) == IPS_CMD_RECOVERED_ERROR)) {
3885
3886 if (scb->bus == 0) {
3887 if ((basic_status & IPS_GSC_STATUS_MASK) ==
3888 IPS_CMD_RECOVERED_ERROR) {
3889 DEBUG_VAR(1,
3890 "(%s%d) Recovered Logical Drive Error OpCode: %x, BSB: %x, ESB: %x",
3891 ips_name, ha->host_num,
3892 scb->cmd.basic_io.op_code,
3893 basic_status, ext_status);
3894 }
3895
3896 switch (scb->scsi_cmd->cmnd[0]) {
3897 case ALLOW_MEDIUM_REMOVAL:
3898 case REZERO_UNIT:
3899 case ERASE:
3900 case WRITE_FILEMARKS:
3901 case SPACE:
3902 errcode = DID_ERROR;
3903 break;
3904
3905 case START_STOP:
3906 break;
3907
3908 case TEST_UNIT_READY:
3909 if (!ips_online(ha, scb)) {
3910 errcode = DID_TIME_OUT;
3911 }
3912 break;
3913
3914 case INQUIRY:
3915 if (ips_online(ha, scb)) {
3916 ips_inquiry(ha, scb);
3917 } else {
3918 errcode = DID_TIME_OUT;
3919 }
3920 break;
3921
3922 case REQUEST_SENSE:
3923 ips_reqsen(ha, scb);
3924 break;
3925
3926 case READ_6:
3927 case WRITE_6:
3928 case READ_10:
3929 case WRITE_10:
3930 case RESERVE:
3931 case RELEASE:
3932 break;
3933
3934 case MODE_SENSE:
3935 if (!ips_online(ha, scb)
3936 || !ips_msense(ha, scb)) {
3937 errcode = DID_ERROR;
3938 }
3939 break;
3940
3941 case READ_CAPACITY:
3942 if (ips_online(ha, scb))
3943 ips_rdcap(ha, scb);
3944 else {
3945 errcode = DID_TIME_OUT;
3946 }
3947 break;
3948
3949 case SEND_DIAGNOSTIC:
3950 case REASSIGN_BLOCKS:
3951 break;
3952
3953 case FORMAT_UNIT:
3954 errcode = DID_ERROR;
3955 break;
3956
3957 case SEEK_10:
3958 case VERIFY:
3959 case READ_DEFECT_DATA:
3960 case READ_BUFFER:
3961 case WRITE_BUFFER:
3962 break;
3963
3964 default:
3965 errcode = DID_ERROR;
3966 } /* end switch */
3967
3968 scb->scsi_cmd->result = errcode << 16;
3969 } else { /* bus == 0 */
3970 /* restrict access to physical drives */
3971 if (scb->scsi_cmd->cmnd[0] == INQUIRY) {
3972 ips_scmd_buf_read(scb->scsi_cmd,
3973 &inquiryData, sizeof (inquiryData));
3974 if ((inquiryData.DeviceType & 0x1f) == TYPE_DISK)
3975 scb->scsi_cmd->result = DID_TIME_OUT << 16;
3976 }
3977 } /* else */
3978 } else { /* recovered error / success */
3979 if (scb->bus == 0) {
3980 DEBUG_VAR(1,
3981 "(%s%d) Unrecovered Logical Drive Error OpCode: %x, BSB: %x, ESB: %x",
3982 ips_name, ha->host_num,
3983 scb->cmd.basic_io.op_code, basic_status,
3984 ext_status);
3985 }
3986
3987 ips_map_status(ha, scb, sp);
3988 } /* else */
3989 }
3990
3991 /****************************************************************************/
3992 /* */
3993 /* Routine Name: ips_online */
3994 /* */
3995 /* Routine Description: */
3996 /* */
3997 /* Determine if a logical drive is online */
3998 /* */
3999 /****************************************************************************/
4000 static int
4001 ips_online(ips_ha_t * ha, ips_scb_t * scb)
4002 {
4003 METHOD_TRACE("ips_online", 1);
4004
4005 if (scb->target_id >= IPS_MAX_LD)
4006 return (0);
4007
4008 if ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1) {
4009 memset(ha->logical_drive_info, 0, sizeof (IPS_LD_INFO));
4010 return (0);
4011 }
4012
4013 if (ha->logical_drive_info->drive_info[scb->target_id].state !=
4014 IPS_LD_OFFLINE
4015 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4016 IPS_LD_FREE
4017 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4018 IPS_LD_CRS
4019 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4020 IPS_LD_SYS)
4021 return (1);
4022 else
4023 return (0);
4024 }
4025
4026 /****************************************************************************/
4027 /* */
4028 /* Routine Name: ips_inquiry */
4029 /* */
4030 /* Routine Description: */
4031 /* */
4032 /* Simulate an inquiry command to a logical drive */
4033 /* */
4034 /****************************************************************************/
4035 static int
4036 ips_inquiry(ips_ha_t * ha, ips_scb_t * scb)
4037 {
4038 IPS_SCSI_INQ_DATA inquiry;
4039
4040 METHOD_TRACE("ips_inquiry", 1);
4041
4042 memset(&inquiry, 0, sizeof (IPS_SCSI_INQ_DATA));
4043
4044 inquiry.DeviceType = IPS_SCSI_INQ_TYPE_DASD;
4045 inquiry.DeviceTypeQualifier = IPS_SCSI_INQ_LU_CONNECTED;
4046 inquiry.Version = IPS_SCSI_INQ_REV2;
4047 inquiry.ResponseDataFormat = IPS_SCSI_INQ_RD_REV2;
4048 inquiry.AdditionalLength = 31;
4049 inquiry.Flags[0] = IPS_SCSI_INQ_Address16;
4050 inquiry.Flags[1] =
4051 IPS_SCSI_INQ_WBus16 | IPS_SCSI_INQ_Sync | IPS_SCSI_INQ_CmdQue;
4052 strncpy(inquiry.VendorId, "IBM ", 8);
4053 strncpy(inquiry.ProductId, "SERVERAID ", 16);
4054 strncpy(inquiry.ProductRevisionLevel, "1.00", 4);
4055
4056 ips_scmd_buf_write(scb->scsi_cmd, &inquiry, sizeof (inquiry));
4057
4058 return (1);
4059 }
4060
4061 /****************************************************************************/
4062 /* */
4063 /* Routine Name: ips_rdcap */
4064 /* */
4065 /* Routine Description: */
4066 /* */
4067 /* Simulate a read capacity command to a logical drive */
4068 /* */
4069 /****************************************************************************/
4070 static int
4071 ips_rdcap(ips_ha_t * ha, ips_scb_t * scb)
4072 {
4073 IPS_SCSI_CAPACITY cap;
4074
4075 METHOD_TRACE("ips_rdcap", 1);
4076
4077 if (scsi_bufflen(scb->scsi_cmd) < 8)
4078 return (0);
4079
4080 cap.lba =
4081 cpu_to_be32(le32_to_cpu
4082 (ha->logical_drive_info->
4083 drive_info[scb->target_id].sector_count) - 1);
4084 cap.len = cpu_to_be32((uint32_t) IPS_BLKSIZE);
4085
4086 ips_scmd_buf_write(scb->scsi_cmd, &cap, sizeof (cap));
4087
4088 return (1);
4089 }
4090
4091 /****************************************************************************/
4092 /* */
4093 /* Routine Name: ips_msense */
4094 /* */
4095 /* Routine Description: */
4096 /* */
4097 /* Simulate a mode sense command to a logical drive */
4098 /* */
4099 /****************************************************************************/
4100 static int
4101 ips_msense(ips_ha_t * ha, ips_scb_t * scb)
4102 {
4103 uint16_t heads;
4104 uint16_t sectors;
4105 uint32_t cylinders;
4106 IPS_SCSI_MODE_PAGE_DATA mdata;
4107
4108 METHOD_TRACE("ips_msense", 1);
4109
4110 if (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) > 0x400000 &&
4111 (ha->enq->ucMiscFlag & 0x8) == 0) {
4112 heads = IPS_NORM_HEADS;
4113 sectors = IPS_NORM_SECTORS;
4114 } else {
4115 heads = IPS_COMP_HEADS;
4116 sectors = IPS_COMP_SECTORS;
4117 }
4118
4119 cylinders =
4120 (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) -
4121 1) / (heads * sectors);
4122
4123 memset(&mdata, 0, sizeof (IPS_SCSI_MODE_PAGE_DATA));
4124
4125 mdata.hdr.BlockDescLength = 8;
4126
4127 switch (scb->scsi_cmd->cmnd[2] & 0x3f) {
4128 case 0x03: /* page 3 */
4129 mdata.pdata.pg3.PageCode = 3;
4130 mdata.pdata.pg3.PageLength = sizeof (IPS_SCSI_MODE_PAGE3);
4131 mdata.hdr.DataLength =
4132 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg3.PageLength;
4133 mdata.pdata.pg3.TracksPerZone = 0;
4134 mdata.pdata.pg3.AltSectorsPerZone = 0;
4135 mdata.pdata.pg3.AltTracksPerZone = 0;
4136 mdata.pdata.pg3.AltTracksPerVolume = 0;
4137 mdata.pdata.pg3.SectorsPerTrack = cpu_to_be16(sectors);
4138 mdata.pdata.pg3.BytesPerSector = cpu_to_be16(IPS_BLKSIZE);
4139 mdata.pdata.pg3.Interleave = cpu_to_be16(1);
4140 mdata.pdata.pg3.TrackSkew = 0;
4141 mdata.pdata.pg3.CylinderSkew = 0;
4142 mdata.pdata.pg3.flags = IPS_SCSI_MP3_SoftSector;
4143 break;
4144
4145 case 0x4:
4146 mdata.pdata.pg4.PageCode = 4;
4147 mdata.pdata.pg4.PageLength = sizeof (IPS_SCSI_MODE_PAGE4);
4148 mdata.hdr.DataLength =
4149 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg4.PageLength;
4150 mdata.pdata.pg4.CylindersHigh =
4151 cpu_to_be16((cylinders >> 8) & 0xFFFF);
4152 mdata.pdata.pg4.CylindersLow = (cylinders & 0xFF);
4153 mdata.pdata.pg4.Heads = heads;
4154 mdata.pdata.pg4.WritePrecompHigh = 0;
4155 mdata.pdata.pg4.WritePrecompLow = 0;
4156 mdata.pdata.pg4.ReducedWriteCurrentHigh = 0;
4157 mdata.pdata.pg4.ReducedWriteCurrentLow = 0;
4158 mdata.pdata.pg4.StepRate = cpu_to_be16(1);
4159 mdata.pdata.pg4.LandingZoneHigh = 0;
4160 mdata.pdata.pg4.LandingZoneLow = 0;
4161 mdata.pdata.pg4.flags = 0;
4162 mdata.pdata.pg4.RotationalOffset = 0;
4163 mdata.pdata.pg4.MediumRotationRate = 0;
4164 break;
4165 case 0x8:
4166 mdata.pdata.pg8.PageCode = 8;
4167 mdata.pdata.pg8.PageLength = sizeof (IPS_SCSI_MODE_PAGE8);
4168 mdata.hdr.DataLength =
4169 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg8.PageLength;
4170 /* everything else is left set to 0 */
4171 break;
4172
4173 default:
4174 return (0);
4175 } /* end switch */
4176
4177 ips_scmd_buf_write(scb->scsi_cmd, &mdata, sizeof (mdata));
4178
4179 return (1);
4180 }
4181
4182 /****************************************************************************/
4183 /* */
4184 /* Routine Name: ips_reqsen */
4185 /* */
4186 /* Routine Description: */
4187 /* */
4188 /* Simulate a request sense command to a logical drive */
4189 /* */
4190 /****************************************************************************/
4191 static int
4192 ips_reqsen(ips_ha_t * ha, ips_scb_t * scb)
4193 {
4194 IPS_SCSI_REQSEN reqsen;
4195
4196 METHOD_TRACE("ips_reqsen", 1);
4197
4198 memset(&reqsen, 0, sizeof (IPS_SCSI_REQSEN));
4199
4200 reqsen.ResponseCode =
4201 IPS_SCSI_REQSEN_VALID | IPS_SCSI_REQSEN_CURRENT_ERR;
4202 reqsen.AdditionalLength = 10;
4203 reqsen.AdditionalSenseCode = IPS_SCSI_REQSEN_NO_SENSE;
4204 reqsen.AdditionalSenseCodeQual = IPS_SCSI_REQSEN_NO_SENSE;
4205
4206 ips_scmd_buf_write(scb->scsi_cmd, &reqsen, sizeof (reqsen));
4207
4208 return (1);
4209 }
4210
4211 /****************************************************************************/
4212 /* */
4213 /* Routine Name: ips_free */
4214 /* */
4215 /* Routine Description: */
4216 /* */
4217 /* Free any allocated space for this controller */
4218 /* */
4219 /****************************************************************************/
4220 static void
4221 ips_free(ips_ha_t * ha)
4222 {
4223
4224 METHOD_TRACE("ips_free", 1);
4225
4226 if (ha) {
4227 if (ha->enq) {
4228 pci_free_consistent(ha->pcidev, sizeof(IPS_ENQ),
4229 ha->enq, ha->enq_busaddr);
4230 ha->enq = NULL;
4231 }
4232
4233 kfree(ha->conf);
4234 ha->conf = NULL;
4235
4236 if (ha->adapt) {
4237 pci_free_consistent(ha->pcidev,
4238 sizeof (IPS_ADAPTER) +
4239 sizeof (IPS_IO_CMD), ha->adapt,
4240 ha->adapt->hw_status_start);
4241 ha->adapt = NULL;
4242 }
4243
4244 if (ha->logical_drive_info) {
4245 pci_free_consistent(ha->pcidev,
4246 sizeof (IPS_LD_INFO),
4247 ha->logical_drive_info,
4248 ha->logical_drive_info_dma_addr);
4249 ha->logical_drive_info = NULL;
4250 }
4251
4252 kfree(ha->nvram);
4253 ha->nvram = NULL;
4254
4255 kfree(ha->subsys);
4256 ha->subsys = NULL;
4257
4258 if (ha->ioctl_data) {
4259 pci_free_consistent(ha->pcidev, ha->ioctl_len,
4260 ha->ioctl_data, ha->ioctl_busaddr);
4261 ha->ioctl_data = NULL;
4262 ha->ioctl_datasize = 0;
4263 ha->ioctl_len = 0;
4264 }
4265 ips_deallocatescbs(ha, ha->max_cmds);
4266
4267 /* free memory mapped (if applicable) */
4268 if (ha->mem_ptr) {
4269 iounmap(ha->ioremap_ptr);
4270 ha->ioremap_ptr = NULL;
4271 ha->mem_ptr = NULL;
4272 }
4273
4274 ha->mem_addr = 0;
4275
4276 }
4277 }
4278
4279 /****************************************************************************/
4280 /* */
4281 /* Routine Name: ips_deallocatescbs */
4282 /* */
4283 /* Routine Description: */
4284 /* */
4285 /* Free the command blocks */
4286 /* */
4287 /****************************************************************************/
4288 static int
4289 ips_deallocatescbs(ips_ha_t * ha, int cmds)
4290 {
4291 if (ha->scbs) {
4292 pci_free_consistent(ha->pcidev,
4293 IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * cmds,
4294 ha->scbs->sg_list.list,
4295 ha->scbs->sg_busaddr);
4296 pci_free_consistent(ha->pcidev, sizeof (ips_scb_t) * cmds,
4297 ha->scbs, ha->scbs->scb_busaddr);
4298 ha->scbs = NULL;
4299 } /* end if */
4300 return 1;
4301 }
4302
4303 /****************************************************************************/
4304 /* */
4305 /* Routine Name: ips_allocatescbs */
4306 /* */
4307 /* Routine Description: */
4308 /* */
4309 /* Allocate the command blocks */
4310 /* */
4311 /****************************************************************************/
4312 static int
4313 ips_allocatescbs(ips_ha_t * ha)
4314 {
4315 ips_scb_t *scb_p;
4316 IPS_SG_LIST ips_sg;
4317 int i;
4318 dma_addr_t command_dma, sg_dma;
4319
4320 METHOD_TRACE("ips_allocatescbs", 1);
4321
4322 /* Allocate memory for the SCBs */
4323 ha->scbs =
4324 pci_alloc_consistent(ha->pcidev, ha->max_cmds * sizeof (ips_scb_t),
4325 &command_dma);
4326 if (ha->scbs == NULL)
4327 return 0;
4328 ips_sg.list =
4329 pci_alloc_consistent(ha->pcidev,
4330 IPS_SGLIST_SIZE(ha) * IPS_MAX_SG *
4331 ha->max_cmds, &sg_dma);
4332 if (ips_sg.list == NULL) {
4333 pci_free_consistent(ha->pcidev,
4334 ha->max_cmds * sizeof (ips_scb_t), ha->scbs,
4335 command_dma);
4336 return 0;
4337 }
4338
4339 memset(ha->scbs, 0, ha->max_cmds * sizeof (ips_scb_t));
4340
4341 for (i = 0; i < ha->max_cmds; i++) {
4342 scb_p = &ha->scbs[i];
4343 scb_p->scb_busaddr = command_dma + sizeof (ips_scb_t) * i;
4344 /* set up S/G list */
4345 if (IPS_USE_ENH_SGLIST(ha)) {
4346 scb_p->sg_list.enh_list =
4347 ips_sg.enh_list + i * IPS_MAX_SG;
4348 scb_p->sg_busaddr =
4349 sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i;
4350 } else {
4351 scb_p->sg_list.std_list =
4352 ips_sg.std_list + i * IPS_MAX_SG;
4353 scb_p->sg_busaddr =
4354 sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i;
4355 }
4356
4357 /* add to the free list */
4358 if (i < ha->max_cmds - 1) {
4359 scb_p->q_next = ha->scb_freelist;
4360 ha->scb_freelist = scb_p;
4361 }
4362 }
4363
4364 /* success */
4365 return (1);
4366 }
4367
4368 /****************************************************************************/
4369 /* */
4370 /* Routine Name: ips_init_scb */
4371 /* */
4372 /* Routine Description: */
4373 /* */
4374 /* Initialize a CCB to default values */
4375 /* */
4376 /****************************************************************************/
4377 static void
4378 ips_init_scb(ips_ha_t * ha, ips_scb_t * scb)
4379 {
4380 IPS_SG_LIST sg_list;
4381 uint32_t cmd_busaddr, sg_busaddr;
4382 METHOD_TRACE("ips_init_scb", 1);
4383
4384 if (scb == NULL)
4385 return;
4386
4387 sg_list.list = scb->sg_list.list;
4388 cmd_busaddr = scb->scb_busaddr;
4389 sg_busaddr = scb->sg_busaddr;
4390 /* zero fill */
4391 memset(scb, 0, sizeof (ips_scb_t));
4392 memset(ha->dummy, 0, sizeof (IPS_IO_CMD));
4393
4394 /* Initialize dummy command bucket */
4395 ha->dummy->op_code = 0xFF;
4396 ha->dummy->ccsar = cpu_to_le32(ha->adapt->hw_status_start
4397 + sizeof (IPS_ADAPTER));
4398 ha->dummy->command_id = IPS_MAX_CMDS;
4399
4400 /* set bus address of scb */
4401 scb->scb_busaddr = cmd_busaddr;
4402 scb->sg_busaddr = sg_busaddr;
4403 scb->sg_list.list = sg_list.list;
4404
4405 /* Neptune Fix */
4406 scb->cmd.basic_io.cccr = cpu_to_le32((uint32_t) IPS_BIT_ILE);
4407 scb->cmd.basic_io.ccsar = cpu_to_le32(ha->adapt->hw_status_start
4408 + sizeof (IPS_ADAPTER));
4409 }
4410
4411 /****************************************************************************/
4412 /* */
4413 /* Routine Name: ips_get_scb */
4414 /* */
4415 /* Routine Description: */
4416 /* */
4417 /* Initialize a CCB to default values */
4418 /* */
4419 /* ASSUMED to be called from within a lock */
4420 /* */
4421 /****************************************************************************/
4422 static ips_scb_t *
4423 ips_getscb(ips_ha_t * ha)
4424 {
4425 ips_scb_t *scb;
4426
4427 METHOD_TRACE("ips_getscb", 1);
4428
4429 if ((scb = ha->scb_freelist) == NULL) {
4430
4431 return (NULL);
4432 }
4433
4434 ha->scb_freelist = scb->q_next;
4435 scb->flags = 0;
4436 scb->q_next = NULL;
4437
4438 ips_init_scb(ha, scb);
4439
4440 return (scb);
4441 }
4442
4443 /****************************************************************************/
4444 /* */
4445 /* Routine Name: ips_free_scb */
4446 /* */
4447 /* Routine Description: */
4448 /* */
4449 /* Return an unused CCB back to the free list */
4450 /* */
4451 /* ASSUMED to be called from within a lock */
4452 /* */
4453 /****************************************************************************/
4454 static void
4455 ips_freescb(ips_ha_t * ha, ips_scb_t * scb)
4456 {
4457
4458 METHOD_TRACE("ips_freescb", 1);
4459 if (scb->flags & IPS_SCB_MAP_SG)
4460 scsi_dma_unmap(scb->scsi_cmd);
4461 else if (scb->flags & IPS_SCB_MAP_SINGLE)
4462 pci_unmap_single(ha->pcidev, scb->data_busaddr, scb->data_len,
4463 IPS_DMA_DIR(scb));
4464
4465 /* check to make sure this is not our "special" scb */
4466 if (IPS_COMMAND_ID(ha, scb) < (ha->max_cmds - 1)) {
4467 scb->q_next = ha->scb_freelist;
4468 ha->scb_freelist = scb;
4469 }
4470 }
4471
4472 /****************************************************************************/
4473 /* */
4474 /* Routine Name: ips_isinit_copperhead */
4475 /* */
4476 /* Routine Description: */
4477 /* */
4478 /* Is controller initialized ? */
4479 /* */
4480 /****************************************************************************/
4481 static int
4482 ips_isinit_copperhead(ips_ha_t * ha)
4483 {
4484 uint8_t scpr;
4485 uint8_t isr;
4486
4487 METHOD_TRACE("ips_isinit_copperhead", 1);
4488
4489 isr = inb(ha->io_addr + IPS_REG_HISR);
4490 scpr = inb(ha->io_addr + IPS_REG_SCPR);
4491
4492 if (((isr & IPS_BIT_EI) == 0) && ((scpr & IPS_BIT_EBM) == 0))
4493 return (0);
4494 else
4495 return (1);
4496 }
4497
4498 /****************************************************************************/
4499 /* */
4500 /* Routine Name: ips_isinit_copperhead_memio */
4501 /* */
4502 /* Routine Description: */
4503 /* */
4504 /* Is controller initialized ? */
4505 /* */
4506 /****************************************************************************/
4507 static int
4508 ips_isinit_copperhead_memio(ips_ha_t * ha)
4509 {
4510 uint8_t isr = 0;
4511 uint8_t scpr;
4512
4513 METHOD_TRACE("ips_is_init_copperhead_memio", 1);
4514
4515 isr = readb(ha->mem_ptr + IPS_REG_HISR);
4516 scpr = readb(ha->mem_ptr + IPS_REG_SCPR);
4517
4518 if (((isr & IPS_BIT_EI) == 0) && ((scpr & IPS_BIT_EBM) == 0))
4519 return (0);
4520 else
4521 return (1);
4522 }
4523
4524 /****************************************************************************/
4525 /* */
4526 /* Routine Name: ips_isinit_morpheus */
4527 /* */
4528 /* Routine Description: */
4529 /* */
4530 /* Is controller initialized ? */
4531 /* */
4532 /****************************************************************************/
4533 static int
4534 ips_isinit_morpheus(ips_ha_t * ha)
4535 {
4536 uint32_t post;
4537 uint32_t bits;
4538
4539 METHOD_TRACE("ips_is_init_morpheus", 1);
4540
4541 if (ips_isintr_morpheus(ha))
4542 ips_flush_and_reset(ha);
4543
4544 post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
4545 bits = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
4546
4547 if (post == 0)
4548 return (0);
4549 else if (bits & 0x3)
4550 return (0);
4551 else
4552 return (1);
4553 }
4554
4555 /****************************************************************************/
4556 /* */
4557 /* Routine Name: ips_flush_and_reset */
4558 /* */
4559 /* Routine Description: */
4560 /* */
4561 /* Perform cleanup ( FLUSH and RESET ) when the adapter is in an unknown */
4562 /* state ( was trying to INIT and an interrupt was already pending ) ... */
4563 /* */
4564 /****************************************************************************/
4565 static void
4566 ips_flush_and_reset(ips_ha_t *ha)
4567 {
4568 ips_scb_t *scb;
4569 int ret;
4570 int time;
4571 int done;
4572 dma_addr_t command_dma;
4573
4574 /* Create a usuable SCB */
4575 scb = pci_alloc_consistent(ha->pcidev, sizeof(ips_scb_t), &command_dma);
4576 if (scb) {
4577 memset(scb, 0, sizeof(ips_scb_t));
4578 ips_init_scb(ha, scb);
4579 scb->scb_busaddr = command_dma;
4580
4581 scb->timeout = ips_cmd_timeout;
4582 scb->cdb[0] = IPS_CMD_FLUSH;
4583
4584 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
4585 scb->cmd.flush_cache.command_id = IPS_MAX_CMDS; /* Use an ID that would otherwise not exist */
4586 scb->cmd.flush_cache.state = IPS_NORM_STATE;
4587 scb->cmd.flush_cache.reserved = 0;
4588 scb->cmd.flush_cache.reserved2 = 0;
4589 scb->cmd.flush_cache.reserved3 = 0;
4590 scb->cmd.flush_cache.reserved4 = 0;
4591
4592 ret = ips_send_cmd(ha, scb); /* Send the Flush Command */
4593
4594 if (ret == IPS_SUCCESS) {
4595 time = 60 * IPS_ONE_SEC; /* Max Wait time is 60 seconds */
4596 done = 0;
4597
4598 while ((time > 0) && (!done)) {
4599 done = ips_poll_for_flush_complete(ha);
4600 /* This may look evil, but it's only done during extremely rare start-up conditions ! */
4601 udelay(1000);
4602 time--;
4603 }
4604 }
4605 }
4606
4607 /* Now RESET and INIT the adapter */
4608 (*ha->func.reset) (ha);
4609
4610 pci_free_consistent(ha->pcidev, sizeof(ips_scb_t), scb, command_dma);
4611 return;
4612 }
4613
4614 /****************************************************************************/
4615 /* */
4616 /* Routine Name: ips_poll_for_flush_complete */
4617 /* */
4618 /* Routine Description: */
4619 /* */
4620 /* Poll for the Flush Command issued by ips_flush_and_reset() to complete */
4621 /* All other responses are just taken off the queue and ignored */
4622 /* */
4623 /****************************************************************************/
4624 static int
4625 ips_poll_for_flush_complete(ips_ha_t * ha)
4626 {
4627 IPS_STATUS cstatus;
4628
4629 while (TRUE) {
4630 cstatus.value = (*ha->func.statupd) (ha);
4631
4632 if (cstatus.value == 0xffffffff) /* If No Interrupt to process */
4633 break;
4634
4635 /* Success is when we see the Flush Command ID */
4636 if (cstatus.fields.command_id == IPS_MAX_CMDS)
4637 return 1;
4638 }
4639
4640 return 0;
4641 }
4642
4643 /****************************************************************************/
4644 /* */
4645 /* Routine Name: ips_enable_int_copperhead */
4646 /* */
4647 /* Routine Description: */
4648 /* Turn on interrupts */
4649 /* */
4650 /****************************************************************************/
4651 static void
4652 ips_enable_int_copperhead(ips_ha_t * ha)
4653 {
4654 METHOD_TRACE("ips_enable_int_copperhead", 1);
4655
4656 outb(ha->io_addr + IPS_REG_HISR, IPS_BIT_EI);
4657 inb(ha->io_addr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/
4658 }
4659
4660 /****************************************************************************/
4661 /* */
4662 /* Routine Name: ips_enable_int_copperhead_memio */
4663 /* */
4664 /* Routine Description: */
4665 /* Turn on interrupts */
4666 /* */
4667 /****************************************************************************/
4668 static void
4669 ips_enable_int_copperhead_memio(ips_ha_t * ha)
4670 {
4671 METHOD_TRACE("ips_enable_int_copperhead_memio", 1);
4672
4673 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR);
4674 readb(ha->mem_ptr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/
4675 }
4676
4677 /****************************************************************************/
4678 /* */
4679 /* Routine Name: ips_enable_int_morpheus */
4680 /* */
4681 /* Routine Description: */
4682 /* Turn on interrupts */
4683 /* */
4684 /****************************************************************************/
4685 static void
4686 ips_enable_int_morpheus(ips_ha_t * ha)
4687 {
4688 uint32_t Oimr;
4689
4690 METHOD_TRACE("ips_enable_int_morpheus", 1);
4691
4692 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR);
4693 Oimr &= ~0x08;
4694 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR);
4695 readl(ha->mem_ptr + IPS_REG_I960_OIMR); /*Ensure PCI Posting Completes*/
4696 }
4697
4698 /****************************************************************************/
4699 /* */
4700 /* Routine Name: ips_init_copperhead */
4701 /* */
4702 /* Routine Description: */
4703 /* */
4704 /* Initialize a copperhead controller */
4705 /* */
4706 /****************************************************************************/
4707 static int
4708 ips_init_copperhead(ips_ha_t * ha)
4709 {
4710 uint8_t Isr;
4711 uint8_t Cbsp;
4712 uint8_t PostByte[IPS_MAX_POST_BYTES];
4713 uint8_t ConfigByte[IPS_MAX_CONFIG_BYTES];
4714 int i, j;
4715
4716 METHOD_TRACE("ips_init_copperhead", 1);
4717
4718 for (i = 0; i < IPS_MAX_POST_BYTES; i++) {
4719 for (j = 0; j < 45; j++) {
4720 Isr = inb(ha->io_addr + IPS_REG_HISR);
4721 if (Isr & IPS_BIT_GHI)
4722 break;
4723
4724 /* Delay for 1 Second */
4725 MDELAY(IPS_ONE_SEC);
4726 }
4727
4728 if (j >= 45)
4729 /* error occurred */
4730 return (0);
4731
4732 PostByte[i] = inb(ha->io_addr + IPS_REG_ISPR);
4733 outb(Isr, ha->io_addr + IPS_REG_HISR);
4734 }
4735
4736 if (PostByte[0] < IPS_GOOD_POST_STATUS) {
4737 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4738 "reset controller fails (post status %x %x).\n",
4739 PostByte[0], PostByte[1]);
4740
4741 return (0);
4742 }
4743
4744 for (i = 0; i < IPS_MAX_CONFIG_BYTES; i++) {
4745 for (j = 0; j < 240; j++) {
4746 Isr = inb(ha->io_addr + IPS_REG_HISR);
4747 if (Isr & IPS_BIT_GHI)
4748 break;
4749
4750 /* Delay for 1 Second */
4751 MDELAY(IPS_ONE_SEC);
4752 }
4753
4754 if (j >= 240)
4755 /* error occurred */
4756 return (0);
4757
4758 ConfigByte[i] = inb(ha->io_addr + IPS_REG_ISPR);
4759 outb(Isr, ha->io_addr + IPS_REG_HISR);
4760 }
4761
4762 for (i = 0; i < 240; i++) {
4763 Cbsp = inb(ha->io_addr + IPS_REG_CBSP);
4764
4765 if ((Cbsp & IPS_BIT_OP) == 0)
4766 break;
4767
4768 /* Delay for 1 Second */
4769 MDELAY(IPS_ONE_SEC);
4770 }
4771
4772 if (i >= 240)
4773 /* reset failed */
4774 return (0);
4775
4776 /* setup CCCR */
4777 outl(0x1010, ha->io_addr + IPS_REG_CCCR);
4778
4779 /* Enable busmastering */
4780 outb(IPS_BIT_EBM, ha->io_addr + IPS_REG_SCPR);
4781
4782 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
4783 /* fix for anaconda64 */
4784 outl(0, ha->io_addr + IPS_REG_NDAE);
4785
4786 /* Enable interrupts */
4787 outb(IPS_BIT_EI, ha->io_addr + IPS_REG_HISR);
4788
4789 return (1);
4790 }
4791
4792 /****************************************************************************/
4793 /* */
4794 /* Routine Name: ips_init_copperhead_memio */
4795 /* */
4796 /* Routine Description: */
4797 /* */
4798 /* Initialize a copperhead controller with memory mapped I/O */
4799 /* */
4800 /****************************************************************************/
4801 static int
4802 ips_init_copperhead_memio(ips_ha_t * ha)
4803 {
4804 uint8_t Isr = 0;
4805 uint8_t Cbsp;
4806 uint8_t PostByte[IPS_MAX_POST_BYTES];
4807 uint8_t ConfigByte[IPS_MAX_CONFIG_BYTES];
4808 int i, j;
4809
4810 METHOD_TRACE("ips_init_copperhead_memio", 1);
4811
4812 for (i = 0; i < IPS_MAX_POST_BYTES; i++) {
4813 for (j = 0; j < 45; j++) {
4814 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
4815 if (Isr & IPS_BIT_GHI)
4816 break;
4817
4818 /* Delay for 1 Second */
4819 MDELAY(IPS_ONE_SEC);
4820 }
4821
4822 if (j >= 45)
4823 /* error occurred */
4824 return (0);
4825
4826 PostByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR);
4827 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
4828 }
4829
4830 if (PostByte[0] < IPS_GOOD_POST_STATUS) {
4831 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4832 "reset controller fails (post status %x %x).\n",
4833 PostByte[0], PostByte[1]);
4834
4835 return (0);
4836 }
4837
4838 for (i = 0; i < IPS_MAX_CONFIG_BYTES; i++) {
4839 for (j = 0; j < 240; j++) {
4840 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
4841 if (Isr & IPS_BIT_GHI)
4842 break;
4843
4844 /* Delay for 1 Second */
4845 MDELAY(IPS_ONE_SEC);
4846 }
4847
4848 if (j >= 240)
4849 /* error occurred */
4850 return (0);
4851
4852 ConfigByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR);
4853 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
4854 }
4855
4856 for (i = 0; i < 240; i++) {
4857 Cbsp = readb(ha->mem_ptr + IPS_REG_CBSP);
4858
4859 if ((Cbsp & IPS_BIT_OP) == 0)
4860 break;
4861
4862 /* Delay for 1 Second */
4863 MDELAY(IPS_ONE_SEC);
4864 }
4865
4866 if (i >= 240)
4867 /* error occurred */
4868 return (0);
4869
4870 /* setup CCCR */
4871 writel(0x1010, ha->mem_ptr + IPS_REG_CCCR);
4872
4873 /* Enable busmastering */
4874 writeb(IPS_BIT_EBM, ha->mem_ptr + IPS_REG_SCPR);
4875
4876 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
4877 /* fix for anaconda64 */
4878 writel(0, ha->mem_ptr + IPS_REG_NDAE);
4879
4880 /* Enable interrupts */
4881 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR);
4882
4883 /* if we get here then everything went OK */
4884 return (1);
4885 }
4886
4887 /****************************************************************************/
4888 /* */
4889 /* Routine Name: ips_init_morpheus */
4890 /* */
4891 /* Routine Description: */
4892 /* */
4893 /* Initialize a morpheus controller */
4894 /* */
4895 /****************************************************************************/
4896 static int
4897 ips_init_morpheus(ips_ha_t * ha)
4898 {
4899 uint32_t Post;
4900 uint32_t Config;
4901 uint32_t Isr;
4902 uint32_t Oimr;
4903 int i;
4904
4905 METHOD_TRACE("ips_init_morpheus", 1);
4906
4907 /* Wait up to 45 secs for Post */
4908 for (i = 0; i < 45; i++) {
4909 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
4910
4911 if (Isr & IPS_BIT_I960_MSG0I)
4912 break;
4913
4914 /* Delay for 1 Second */
4915 MDELAY(IPS_ONE_SEC);
4916 }
4917
4918 if (i >= 45) {
4919 /* error occurred */
4920 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4921 "timeout waiting for post.\n");
4922
4923 return (0);
4924 }
4925
4926 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
4927
4928 if (Post == 0x4F00) { /* If Flashing the Battery PIC */
4929 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4930 "Flashing Battery PIC, Please wait ...\n");
4931
4932 /* Clear the interrupt bit */
4933 Isr = (uint32_t) IPS_BIT_I960_MSG0I;
4934 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
4935
4936 for (i = 0; i < 120; i++) { /* Wait Up to 2 Min. for Completion */
4937 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
4938 if (Post != 0x4F00)
4939 break;
4940 /* Delay for 1 Second */
4941 MDELAY(IPS_ONE_SEC);
4942 }
4943
4944 if (i >= 120) {
4945 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4946 "timeout waiting for Battery PIC Flash\n");
4947 return (0);
4948 }
4949
4950 }
4951
4952 /* Clear the interrupt bit */
4953 Isr = (uint32_t) IPS_BIT_I960_MSG0I;
4954 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
4955
4956 if (Post < (IPS_GOOD_POST_STATUS << 8)) {
4957 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4958 "reset controller fails (post status %x).\n", Post);
4959
4960 return (0);
4961 }
4962
4963 /* Wait up to 240 secs for config bytes */
4964 for (i = 0; i < 240; i++) {
4965 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
4966
4967 if (Isr & IPS_BIT_I960_MSG1I)
4968 break;
4969
4970 /* Delay for 1 Second */
4971 MDELAY(IPS_ONE_SEC);
4972 }
4973
4974 if (i >= 240) {
4975 /* error occurred */
4976 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4977 "timeout waiting for config.\n");
4978
4979 return (0);
4980 }
4981
4982 Config = readl(ha->mem_ptr + IPS_REG_I960_MSG1);
4983
4984 /* Clear interrupt bit */
4985 Isr = (uint32_t) IPS_BIT_I960_MSG1I;
4986 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
4987
4988 /* Turn on the interrupts */
4989 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR);
4990 Oimr &= ~0x8;
4991 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR);
4992
4993 /* if we get here then everything went OK */
4994
4995 /* Since we did a RESET, an EraseStripeLock may be needed */
4996 if (Post == 0xEF10) {
4997 if ((Config == 0x000F) || (Config == 0x0009))
4998 ha->requires_esl = 1;
4999 }
5000
5001 return (1);
5002 }
5003
5004 /****************************************************************************/
5005 /* */
5006 /* Routine Name: ips_reset_copperhead */
5007 /* */
5008 /* Routine Description: */
5009 /* */
5010 /* Reset the controller */
5011 /* */
5012 /****************************************************************************/
5013 static int
5014 ips_reset_copperhead(ips_ha_t * ha)
5015 {
5016 int reset_counter;
5017
5018 METHOD_TRACE("ips_reset_copperhead", 1);
5019
5020 DEBUG_VAR(1, "(%s%d) ips_reset_copperhead: io addr: %x, irq: %d",
5021 ips_name, ha->host_num, ha->io_addr, ha->pcidev->irq);
5022
5023 reset_counter = 0;
5024
5025 while (reset_counter < 2) {
5026 reset_counter++;
5027
5028 outb(IPS_BIT_RST, ha->io_addr + IPS_REG_SCPR);
5029
5030 /* Delay for 1 Second */
5031 MDELAY(IPS_ONE_SEC);
5032
5033 outb(0, ha->io_addr + IPS_REG_SCPR);
5034
5035 /* Delay for 1 Second */
5036 MDELAY(IPS_ONE_SEC);
5037
5038 if ((*ha->func.init) (ha))
5039 break;
5040 else if (reset_counter >= 2) {
5041
5042 return (0);
5043 }
5044 }
5045
5046 return (1);
5047 }
5048
5049 /****************************************************************************/
5050 /* */
5051 /* Routine Name: ips_reset_copperhead_memio */
5052 /* */
5053 /* Routine Description: */
5054 /* */
5055 /* Reset the controller */
5056 /* */
5057 /****************************************************************************/
5058 static int
5059 ips_reset_copperhead_memio(ips_ha_t * ha)
5060 {
5061 int reset_counter;
5062
5063 METHOD_TRACE("ips_reset_copperhead_memio", 1);
5064
5065 DEBUG_VAR(1, "(%s%d) ips_reset_copperhead_memio: mem addr: %x, irq: %d",
5066 ips_name, ha->host_num, ha->mem_addr, ha->pcidev->irq);
5067
5068 reset_counter = 0;
5069
5070 while (reset_counter < 2) {
5071 reset_counter++;
5072
5073 writeb(IPS_BIT_RST, ha->mem_ptr + IPS_REG_SCPR);
5074
5075 /* Delay for 1 Second */
5076 MDELAY(IPS_ONE_SEC);
5077
5078 writeb(0, ha->mem_ptr + IPS_REG_SCPR);
5079
5080 /* Delay for 1 Second */
5081 MDELAY(IPS_ONE_SEC);
5082
5083 if ((*ha->func.init) (ha))
5084 break;
5085 else if (reset_counter >= 2) {
5086
5087 return (0);
5088 }
5089 }
5090
5091 return (1);
5092 }
5093
5094 /****************************************************************************/
5095 /* */
5096 /* Routine Name: ips_reset_morpheus */
5097 /* */
5098 /* Routine Description: */
5099 /* */
5100 /* Reset the controller */
5101 /* */
5102 /****************************************************************************/
5103 static int
5104 ips_reset_morpheus(ips_ha_t * ha)
5105 {
5106 int reset_counter;
5107 uint8_t junk;
5108
5109 METHOD_TRACE("ips_reset_morpheus", 1);
5110
5111 DEBUG_VAR(1, "(%s%d) ips_reset_morpheus: mem addr: %x, irq: %d",
5112 ips_name, ha->host_num, ha->mem_addr, ha->pcidev->irq);
5113
5114 reset_counter = 0;
5115
5116 while (reset_counter < 2) {
5117 reset_counter++;
5118
5119 writel(0x80000000, ha->mem_ptr + IPS_REG_I960_IDR);
5120
5121 /* Delay for 5 Seconds */
5122 MDELAY(5 * IPS_ONE_SEC);
5123
5124 /* Do a PCI config read to wait for adapter */
5125 pci_read_config_byte(ha->pcidev, 4, &junk);
5126
5127 if ((*ha->func.init) (ha))
5128 break;
5129 else if (reset_counter >= 2) {
5130
5131 return (0);
5132 }
5133 }
5134
5135 return (1);
5136 }
5137
5138 /****************************************************************************/
5139 /* */
5140 /* Routine Name: ips_statinit */
5141 /* */
5142 /* Routine Description: */
5143 /* */
5144 /* Initialize the status queues on the controller */
5145 /* */
5146 /****************************************************************************/
5147 static void
5148 ips_statinit(ips_ha_t * ha)
5149 {
5150 uint32_t phys_status_start;
5151
5152 METHOD_TRACE("ips_statinit", 1);
5153
5154 ha->adapt->p_status_start = ha->adapt->status;
5155 ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS;
5156 ha->adapt->p_status_tail = ha->adapt->status;
5157
5158 phys_status_start = ha->adapt->hw_status_start;
5159 outl(phys_status_start, ha->io_addr + IPS_REG_SQSR);
5160 outl(phys_status_start + IPS_STATUS_Q_SIZE,
5161 ha->io_addr + IPS_REG_SQER);
5162 outl(phys_status_start + IPS_STATUS_SIZE,
5163 ha->io_addr + IPS_REG_SQHR);
5164 outl(phys_status_start, ha->io_addr + IPS_REG_SQTR);
5165
5166 ha->adapt->hw_status_tail = phys_status_start;
5167 }
5168
5169 /****************************************************************************/
5170 /* */
5171 /* Routine Name: ips_statinit_memio */
5172 /* */
5173 /* Routine Description: */
5174 /* */
5175 /* Initialize the status queues on the controller */
5176 /* */
5177 /****************************************************************************/
5178 static void
5179 ips_statinit_memio(ips_ha_t * ha)
5180 {
5181 uint32_t phys_status_start;
5182
5183 METHOD_TRACE("ips_statinit_memio", 1);
5184
5185 ha->adapt->p_status_start = ha->adapt->status;
5186 ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS;
5187 ha->adapt->p_status_tail = ha->adapt->status;
5188
5189 phys_status_start = ha->adapt->hw_status_start;
5190 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQSR);
5191 writel(phys_status_start + IPS_STATUS_Q_SIZE,
5192 ha->mem_ptr + IPS_REG_SQER);
5193 writel(phys_status_start + IPS_STATUS_SIZE, ha->mem_ptr + IPS_REG_SQHR);
5194 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQTR);
5195
5196 ha->adapt->hw_status_tail = phys_status_start;
5197 }
5198
5199 /****************************************************************************/
5200 /* */
5201 /* Routine Name: ips_statupd_copperhead */
5202 /* */
5203 /* Routine Description: */
5204 /* */
5205 /* Remove an element from the status queue */
5206 /* */
5207 /****************************************************************************/
5208 static uint32_t
5209 ips_statupd_copperhead(ips_ha_t * ha)
5210 {
5211 METHOD_TRACE("ips_statupd_copperhead", 1);
5212
5213 if (ha->adapt->p_status_tail != ha->adapt->p_status_end) {
5214 ha->adapt->p_status_tail++;
5215 ha->adapt->hw_status_tail += sizeof (IPS_STATUS);
5216 } else {
5217 ha->adapt->p_status_tail = ha->adapt->p_status_start;
5218 ha->adapt->hw_status_tail = ha->adapt->hw_status_start;
5219 }
5220
5221 outl(ha->adapt->hw_status_tail,
5222 ha->io_addr + IPS_REG_SQTR);
5223
5224 return (ha->adapt->p_status_tail->value);
5225 }
5226
5227 /****************************************************************************/
5228 /* */
5229 /* Routine Name: ips_statupd_copperhead_memio */
5230 /* */
5231 /* Routine Description: */
5232 /* */
5233 /* Remove an element from the status queue */
5234 /* */
5235 /****************************************************************************/
5236 static uint32_t
5237 ips_statupd_copperhead_memio(ips_ha_t * ha)
5238 {
5239 METHOD_TRACE("ips_statupd_copperhead_memio", 1);
5240
5241 if (ha->adapt->p_status_tail != ha->adapt->p_status_end) {
5242 ha->adapt->p_status_tail++;
5243 ha->adapt->hw_status_tail += sizeof (IPS_STATUS);
5244 } else {
5245 ha->adapt->p_status_tail = ha->adapt->p_status_start;
5246 ha->adapt->hw_status_tail = ha->adapt->hw_status_start;
5247 }
5248
5249 writel(ha->adapt->hw_status_tail, ha->mem_ptr + IPS_REG_SQTR);
5250
5251 return (ha->adapt->p_status_tail->value);
5252 }
5253
5254 /****************************************************************************/
5255 /* */
5256 /* Routine Name: ips_statupd_morpheus */
5257 /* */
5258 /* Routine Description: */
5259 /* */
5260 /* Remove an element from the status queue */
5261 /* */
5262 /****************************************************************************/
5263 static uint32_t
5264 ips_statupd_morpheus(ips_ha_t * ha)
5265 {
5266 uint32_t val;
5267
5268 METHOD_TRACE("ips_statupd_morpheus", 1);
5269
5270 val = readl(ha->mem_ptr + IPS_REG_I2O_OUTMSGQ);
5271
5272 return (val);
5273 }
5274
5275 /****************************************************************************/
5276 /* */
5277 /* Routine Name: ips_issue_copperhead */
5278 /* */
5279 /* Routine Description: */
5280 /* */
5281 /* Send a command down to the controller */
5282 /* */
5283 /****************************************************************************/
5284 static int
5285 ips_issue_copperhead(ips_ha_t * ha, ips_scb_t * scb)
5286 {
5287 uint32_t TimeOut;
5288 uint32_t val;
5289
5290 METHOD_TRACE("ips_issue_copperhead", 1);
5291
5292 if (scb->scsi_cmd) {
5293 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5294 ips_name,
5295 ha->host_num,
5296 scb->cdb[0],
5297 scb->cmd.basic_io.command_id,
5298 scb->bus, scb->target_id, scb->lun);
5299 } else {
5300 DEBUG_VAR(2, KERN_NOTICE "(%s%d) ips_issue: logical cmd id %d",
5301 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5302 }
5303
5304 TimeOut = 0;
5305
5306 while ((val =
5307 le32_to_cpu(inl(ha->io_addr + IPS_REG_CCCR))) & IPS_BIT_SEM) {
5308 udelay(1000);
5309
5310 if (++TimeOut >= IPS_SEM_TIMEOUT) {
5311 if (!(val & IPS_BIT_START_STOP))
5312 break;
5313
5314 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5315 "ips_issue val [0x%x].\n", val);
5316 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5317 "ips_issue semaphore chk timeout.\n");
5318
5319 return (IPS_FAILURE);
5320 } /* end if */
5321 } /* end while */
5322
5323 outl(scb->scb_busaddr, ha->io_addr + IPS_REG_CCSAR);
5324 outw(IPS_BIT_START_CMD, ha->io_addr + IPS_REG_CCCR);
5325
5326 return (IPS_SUCCESS);
5327 }
5328
5329 /****************************************************************************/
5330 /* */
5331 /* Routine Name: ips_issue_copperhead_memio */
5332 /* */
5333 /* Routine Description: */
5334 /* */
5335 /* Send a command down to the controller */
5336 /* */
5337 /****************************************************************************/
5338 static int
5339 ips_issue_copperhead_memio(ips_ha_t * ha, ips_scb_t * scb)
5340 {
5341 uint32_t TimeOut;
5342 uint32_t val;
5343
5344 METHOD_TRACE("ips_issue_copperhead_memio", 1);
5345
5346 if (scb->scsi_cmd) {
5347 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5348 ips_name,
5349 ha->host_num,
5350 scb->cdb[0],
5351 scb->cmd.basic_io.command_id,
5352 scb->bus, scb->target_id, scb->lun);
5353 } else {
5354 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
5355 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5356 }
5357
5358 TimeOut = 0;
5359
5360 while ((val = readl(ha->mem_ptr + IPS_REG_CCCR)) & IPS_BIT_SEM) {
5361 udelay(1000);
5362
5363 if (++TimeOut >= IPS_SEM_TIMEOUT) {
5364 if (!(val & IPS_BIT_START_STOP))
5365 break;
5366
5367 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5368 "ips_issue val [0x%x].\n", val);
5369 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5370 "ips_issue semaphore chk timeout.\n");
5371
5372 return (IPS_FAILURE);
5373 } /* end if */
5374 } /* end while */
5375
5376 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_CCSAR);
5377 writel(IPS_BIT_START_CMD, ha->mem_ptr + IPS_REG_CCCR);
5378
5379 return (IPS_SUCCESS);
5380 }
5381
5382 /****************************************************************************/
5383 /* */
5384 /* Routine Name: ips_issue_i2o */
5385 /* */
5386 /* Routine Description: */
5387 /* */
5388 /* Send a command down to the controller */
5389 /* */
5390 /****************************************************************************/
5391 static int
5392 ips_issue_i2o(ips_ha_t * ha, ips_scb_t * scb)
5393 {
5394
5395 METHOD_TRACE("ips_issue_i2o", 1);
5396
5397 if (scb->scsi_cmd) {
5398 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5399 ips_name,
5400 ha->host_num,
5401 scb->cdb[0],
5402 scb->cmd.basic_io.command_id,
5403 scb->bus, scb->target_id, scb->lun);
5404 } else {
5405 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
5406 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5407 }
5408
5409 outl(scb->scb_busaddr, ha->io_addr + IPS_REG_I2O_INMSGQ);
5410
5411 return (IPS_SUCCESS);
5412 }
5413
5414 /****************************************************************************/
5415 /* */
5416 /* Routine Name: ips_issue_i2o_memio */
5417 /* */
5418 /* Routine Description: */
5419 /* */
5420 /* Send a command down to the controller */
5421 /* */
5422 /****************************************************************************/
5423 static int
5424 ips_issue_i2o_memio(ips_ha_t * ha, ips_scb_t * scb)
5425 {
5426
5427 METHOD_TRACE("ips_issue_i2o_memio", 1);
5428
5429 if (scb->scsi_cmd) {
5430 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5431 ips_name,
5432 ha->host_num,
5433 scb->cdb[0],
5434 scb->cmd.basic_io.command_id,
5435 scb->bus, scb->target_id, scb->lun);
5436 } else {
5437 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
5438 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5439 }
5440
5441 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_I2O_INMSGQ);
5442
5443 return (IPS_SUCCESS);
5444 }
5445
5446 /****************************************************************************/
5447 /* */
5448 /* Routine Name: ips_isintr_copperhead */
5449 /* */
5450 /* Routine Description: */
5451 /* */
5452 /* Test to see if an interrupt is for us */
5453 /* */
5454 /****************************************************************************/
5455 static int
5456 ips_isintr_copperhead(ips_ha_t * ha)
5457 {
5458 uint8_t Isr;
5459
5460 METHOD_TRACE("ips_isintr_copperhead", 2);
5461
5462 Isr = inb(ha->io_addr + IPS_REG_HISR);
5463
5464 if (Isr == 0xFF)
5465 /* ?!?! Nothing really there */
5466 return (0);
5467
5468 if (Isr & IPS_BIT_SCE)
5469 return (1);
5470 else if (Isr & (IPS_BIT_SQO | IPS_BIT_GHI)) {
5471 /* status queue overflow or GHI */
5472 /* just clear the interrupt */
5473 outb(Isr, ha->io_addr + IPS_REG_HISR);
5474 }
5475
5476 return (0);
5477 }
5478
5479 /****************************************************************************/
5480 /* */
5481 /* Routine Name: ips_isintr_copperhead_memio */
5482 /* */
5483 /* Routine Description: */
5484 /* */
5485 /* Test to see if an interrupt is for us */
5486 /* */
5487 /****************************************************************************/
5488 static int
5489 ips_isintr_copperhead_memio(ips_ha_t * ha)
5490 {
5491 uint8_t Isr;
5492
5493 METHOD_TRACE("ips_isintr_memio", 2);
5494
5495 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
5496
5497 if (Isr == 0xFF)
5498 /* ?!?! Nothing really there */
5499 return (0);
5500
5501 if (Isr & IPS_BIT_SCE)
5502 return (1);
5503 else if (Isr & (IPS_BIT_SQO | IPS_BIT_GHI)) {
5504 /* status queue overflow or GHI */
5505 /* just clear the interrupt */
5506 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
5507 }
5508
5509 return (0);
5510 }
5511
5512 /****************************************************************************/
5513 /* */
5514 /* Routine Name: ips_isintr_morpheus */
5515 /* */
5516 /* Routine Description: */
5517 /* */
5518 /* Test to see if an interrupt is for us */
5519 /* */
5520 /****************************************************************************/
5521 static int
5522 ips_isintr_morpheus(ips_ha_t * ha)
5523 {
5524 uint32_t Isr;
5525
5526 METHOD_TRACE("ips_isintr_morpheus", 2);
5527
5528 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
5529
5530 if (Isr & IPS_BIT_I2O_OPQI)
5531 return (1);
5532 else
5533 return (0);
5534 }
5535
5536 /****************************************************************************/
5537 /* */
5538 /* Routine Name: ips_wait */
5539 /* */
5540 /* Routine Description: */
5541 /* */
5542 /* Wait for a command to complete */
5543 /* */
5544 /****************************************************************************/
5545 static int
5546 ips_wait(ips_ha_t * ha, int time, int intr)
5547 {
5548 int ret;
5549 int done;
5550
5551 METHOD_TRACE("ips_wait", 1);
5552
5553 ret = IPS_FAILURE;
5554 done = FALSE;
5555
5556 time *= IPS_ONE_SEC; /* convert seconds */
5557
5558 while ((time > 0) && (!done)) {
5559 if (intr == IPS_INTR_ON) {
5560 if (ha->waitflag == FALSE) {
5561 ret = IPS_SUCCESS;
5562 done = TRUE;
5563 break;
5564 }
5565 } else if (intr == IPS_INTR_IORL) {
5566 if (ha->waitflag == FALSE) {
5567 /*
5568 * controller generated an interrupt to
5569 * acknowledge completion of the command
5570 * and ips_intr() has serviced the interrupt.
5571 */
5572 ret = IPS_SUCCESS;
5573 done = TRUE;
5574 break;
5575 }
5576
5577 /*
5578 * NOTE: we already have the io_request_lock so
5579 * even if we get an interrupt it won't get serviced
5580 * until after we finish.
5581 */
5582
5583 (*ha->func.intr) (ha);
5584 }
5585
5586 /* This looks like a very evil loop, but it only does this during start-up */
5587 udelay(1000);
5588 time--;
5589 }
5590
5591 return (ret);
5592 }
5593
5594 /****************************************************************************/
5595 /* */
5596 /* Routine Name: ips_write_driver_status */
5597 /* */
5598 /* Routine Description: */
5599 /* */
5600 /* Write OS/Driver version to Page 5 of the nvram on the controller */
5601 /* */
5602 /****************************************************************************/
5603 static int
5604 ips_write_driver_status(ips_ha_t * ha, int intr)
5605 {
5606 METHOD_TRACE("ips_write_driver_status", 1);
5607
5608 if (!ips_readwrite_page5(ha, FALSE, intr)) {
5609 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5610 "unable to read NVRAM page 5.\n");
5611
5612 return (0);
5613 }
5614
5615 /* check to make sure the page has a valid */
5616 /* signature */
5617 if (le32_to_cpu(ha->nvram->signature) != IPS_NVRAM_P5_SIG) {
5618 DEBUG_VAR(1,
5619 "(%s%d) NVRAM page 5 has an invalid signature: %X.",
5620 ips_name, ha->host_num, ha->nvram->signature);
5621 ha->nvram->signature = IPS_NVRAM_P5_SIG;
5622 }
5623
5624 DEBUG_VAR(2,
5625 "(%s%d) Ad Type: %d, Ad Slot: %d, BIOS: %c%c%c%c %c%c%c%c.",
5626 ips_name, ha->host_num, le16_to_cpu(ha->nvram->adapter_type),
5627 ha->nvram->adapter_slot, ha->nvram->bios_high[0],
5628 ha->nvram->bios_high[1], ha->nvram->bios_high[2],
5629 ha->nvram->bios_high[3], ha->nvram->bios_low[0],
5630 ha->nvram->bios_low[1], ha->nvram->bios_low[2],
5631 ha->nvram->bios_low[3]);
5632
5633 ips_get_bios_version(ha, intr);
5634
5635 /* change values (as needed) */
5636 ha->nvram->operating_system = IPS_OS_LINUX;
5637 ha->nvram->adapter_type = ha->ad_type;
5638 strncpy((char *) ha->nvram->driver_high, IPS_VERSION_HIGH, 4);
5639 strncpy((char *) ha->nvram->driver_low, IPS_VERSION_LOW, 4);
5640 strncpy((char *) ha->nvram->bios_high, ha->bios_version, 4);
5641 strncpy((char *) ha->nvram->bios_low, ha->bios_version + 4, 4);
5642
5643 ha->nvram->versioning = 0; /* Indicate the Driver Does Not Support Versioning */
5644
5645 /* now update the page */
5646 if (!ips_readwrite_page5(ha, TRUE, intr)) {
5647 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5648 "unable to write NVRAM page 5.\n");
5649
5650 return (0);
5651 }
5652
5653 /* IF NVRAM Page 5 is OK, Use it for Slot Number Info Because Linux Doesn't Do Slots */
5654 ha->slot_num = ha->nvram->adapter_slot;
5655
5656 return (1);
5657 }
5658
5659 /****************************************************************************/
5660 /* */
5661 /* Routine Name: ips_read_adapter_status */
5662 /* */
5663 /* Routine Description: */
5664 /* */
5665 /* Do an Inquiry command to the adapter */
5666 /* */
5667 /****************************************************************************/
5668 static int
5669 ips_read_adapter_status(ips_ha_t * ha, int intr)
5670 {
5671 ips_scb_t *scb;
5672 int ret;
5673
5674 METHOD_TRACE("ips_read_adapter_status", 1);
5675
5676 scb = &ha->scbs[ha->max_cmds - 1];
5677
5678 ips_init_scb(ha, scb);
5679
5680 scb->timeout = ips_cmd_timeout;
5681 scb->cdb[0] = IPS_CMD_ENQUIRY;
5682
5683 scb->cmd.basic_io.op_code = IPS_CMD_ENQUIRY;
5684 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5685 scb->cmd.basic_io.sg_count = 0;
5686 scb->cmd.basic_io.lba = 0;
5687 scb->cmd.basic_io.sector_count = 0;
5688 scb->cmd.basic_io.log_drv = 0;
5689 scb->data_len = sizeof (*ha->enq);
5690 scb->cmd.basic_io.sg_addr = ha->enq_busaddr;
5691
5692 /* send command */
5693 if (((ret =
5694 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5695 || (ret == IPS_SUCCESS_IMM)
5696 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5697 return (0);
5698
5699 return (1);
5700 }
5701
5702 /****************************************************************************/
5703 /* */
5704 /* Routine Name: ips_read_subsystem_parameters */
5705 /* */
5706 /* Routine Description: */
5707 /* */
5708 /* Read subsystem parameters from the adapter */
5709 /* */
5710 /****************************************************************************/
5711 static int
5712 ips_read_subsystem_parameters(ips_ha_t * ha, int intr)
5713 {
5714 ips_scb_t *scb;
5715 int ret;
5716
5717 METHOD_TRACE("ips_read_subsystem_parameters", 1);
5718
5719 scb = &ha->scbs[ha->max_cmds - 1];
5720
5721 ips_init_scb(ha, scb);
5722
5723 scb->timeout = ips_cmd_timeout;
5724 scb->cdb[0] = IPS_CMD_GET_SUBSYS;
5725
5726 scb->cmd.basic_io.op_code = IPS_CMD_GET_SUBSYS;
5727 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5728 scb->cmd.basic_io.sg_count = 0;
5729 scb->cmd.basic_io.lba = 0;
5730 scb->cmd.basic_io.sector_count = 0;
5731 scb->cmd.basic_io.log_drv = 0;
5732 scb->data_len = sizeof (*ha->subsys);
5733 scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr;
5734
5735 /* send command */
5736 if (((ret =
5737 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5738 || (ret == IPS_SUCCESS_IMM)
5739 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5740 return (0);
5741
5742 memcpy(ha->subsys, ha->ioctl_data, sizeof(*ha->subsys));
5743 return (1);
5744 }
5745
5746 /****************************************************************************/
5747 /* */
5748 /* Routine Name: ips_read_config */
5749 /* */
5750 /* Routine Description: */
5751 /* */
5752 /* Read the configuration on the adapter */
5753 /* */
5754 /****************************************************************************/
5755 static int
5756 ips_read_config(ips_ha_t * ha, int intr)
5757 {
5758 ips_scb_t *scb;
5759 int i;
5760 int ret;
5761
5762 METHOD_TRACE("ips_read_config", 1);
5763
5764 /* set defaults for initiator IDs */
5765 for (i = 0; i < 4; i++)
5766 ha->conf->init_id[i] = 7;
5767
5768 scb = &ha->scbs[ha->max_cmds - 1];
5769
5770 ips_init_scb(ha, scb);
5771
5772 scb->timeout = ips_cmd_timeout;
5773 scb->cdb[0] = IPS_CMD_READ_CONF;
5774
5775 scb->cmd.basic_io.op_code = IPS_CMD_READ_CONF;
5776 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5777 scb->data_len = sizeof (*ha->conf);
5778 scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr;
5779
5780 /* send command */
5781 if (((ret =
5782 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5783 || (ret == IPS_SUCCESS_IMM)
5784 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
5785
5786 memset(ha->conf, 0, sizeof (IPS_CONF));
5787
5788 /* reset initiator IDs */
5789 for (i = 0; i < 4; i++)
5790 ha->conf->init_id[i] = 7;
5791
5792 /* Allow Completed with Errors, so JCRM can access the Adapter to fix the problems */
5793 if ((scb->basic_status & IPS_GSC_STATUS_MASK) ==
5794 IPS_CMD_CMPLT_WERROR)
5795 return (1);
5796
5797 return (0);
5798 }
5799
5800 memcpy(ha->conf, ha->ioctl_data, sizeof(*ha->conf));
5801 return (1);
5802 }
5803
5804 /****************************************************************************/
5805 /* */
5806 /* Routine Name: ips_readwrite_page5 */
5807 /* */
5808 /* Routine Description: */
5809 /* */
5810 /* Read nvram page 5 from the adapter */
5811 /* */
5812 /****************************************************************************/
5813 static int
5814 ips_readwrite_page5(ips_ha_t * ha, int write, int intr)
5815 {
5816 ips_scb_t *scb;
5817 int ret;
5818
5819 METHOD_TRACE("ips_readwrite_page5", 1);
5820
5821 scb = &ha->scbs[ha->max_cmds - 1];
5822
5823 ips_init_scb(ha, scb);
5824
5825 scb->timeout = ips_cmd_timeout;
5826 scb->cdb[0] = IPS_CMD_RW_NVRAM_PAGE;
5827
5828 scb->cmd.nvram.op_code = IPS_CMD_RW_NVRAM_PAGE;
5829 scb->cmd.nvram.command_id = IPS_COMMAND_ID(ha, scb);
5830 scb->cmd.nvram.page = 5;
5831 scb->cmd.nvram.write = write;
5832 scb->cmd.nvram.reserved = 0;
5833 scb->cmd.nvram.reserved2 = 0;
5834 scb->data_len = sizeof (*ha->nvram);
5835 scb->cmd.nvram.buffer_addr = ha->ioctl_busaddr;
5836 if (write)
5837 memcpy(ha->ioctl_data, ha->nvram, sizeof(*ha->nvram));
5838
5839 /* issue the command */
5840 if (((ret =
5841 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5842 || (ret == IPS_SUCCESS_IMM)
5843 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
5844
5845 memset(ha->nvram, 0, sizeof (IPS_NVRAM_P5));
5846
5847 return (0);
5848 }
5849 if (!write)
5850 memcpy(ha->nvram, ha->ioctl_data, sizeof(*ha->nvram));
5851 return (1);
5852 }
5853
5854 /****************************************************************************/
5855 /* */
5856 /* Routine Name: ips_clear_adapter */
5857 /* */
5858 /* Routine Description: */
5859 /* */
5860 /* Clear the stripe lock tables */
5861 /* */
5862 /****************************************************************************/
5863 static int
5864 ips_clear_adapter(ips_ha_t * ha, int intr)
5865 {
5866 ips_scb_t *scb;
5867 int ret;
5868
5869 METHOD_TRACE("ips_clear_adapter", 1);
5870
5871 scb = &ha->scbs[ha->max_cmds - 1];
5872
5873 ips_init_scb(ha, scb);
5874
5875 scb->timeout = ips_reset_timeout;
5876 scb->cdb[0] = IPS_CMD_CONFIG_SYNC;
5877
5878 scb->cmd.config_sync.op_code = IPS_CMD_CONFIG_SYNC;
5879 scb->cmd.config_sync.command_id = IPS_COMMAND_ID(ha, scb);
5880 scb->cmd.config_sync.channel = 0;
5881 scb->cmd.config_sync.source_target = IPS_POCL;
5882 scb->cmd.config_sync.reserved = 0;
5883 scb->cmd.config_sync.reserved2 = 0;
5884 scb->cmd.config_sync.reserved3 = 0;
5885
5886 /* issue command */
5887 if (((ret =
5888 ips_send_wait(ha, scb, ips_reset_timeout, intr)) == IPS_FAILURE)
5889 || (ret == IPS_SUCCESS_IMM)
5890 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5891 return (0);
5892
5893 /* send unlock stripe command */
5894 ips_init_scb(ha, scb);
5895
5896 scb->cdb[0] = IPS_CMD_ERROR_TABLE;
5897 scb->timeout = ips_reset_timeout;
5898
5899 scb->cmd.unlock_stripe.op_code = IPS_CMD_ERROR_TABLE;
5900 scb->cmd.unlock_stripe.command_id = IPS_COMMAND_ID(ha, scb);
5901 scb->cmd.unlock_stripe.log_drv = 0;
5902 scb->cmd.unlock_stripe.control = IPS_CSL;
5903 scb->cmd.unlock_stripe.reserved = 0;
5904 scb->cmd.unlock_stripe.reserved2 = 0;
5905 scb->cmd.unlock_stripe.reserved3 = 0;
5906
5907 /* issue command */
5908 if (((ret =
5909 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5910 || (ret == IPS_SUCCESS_IMM)
5911 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5912 return (0);
5913
5914 return (1);
5915 }
5916
5917 /****************************************************************************/
5918 /* */
5919 /* Routine Name: ips_ffdc_reset */
5920 /* */
5921 /* Routine Description: */
5922 /* */
5923 /* FFDC: write reset info */
5924 /* */
5925 /****************************************************************************/
5926 static void
5927 ips_ffdc_reset(ips_ha_t * ha, int intr)
5928 {
5929 ips_scb_t *scb;
5930
5931 METHOD_TRACE("ips_ffdc_reset", 1);
5932
5933 scb = &ha->scbs[ha->max_cmds - 1];
5934
5935 ips_init_scb(ha, scb);
5936
5937 scb->timeout = ips_cmd_timeout;
5938 scb->cdb[0] = IPS_CMD_FFDC;
5939 scb->cmd.ffdc.op_code = IPS_CMD_FFDC;
5940 scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb);
5941 scb->cmd.ffdc.reset_count = ha->reset_count;
5942 scb->cmd.ffdc.reset_type = 0x80;
5943
5944 /* convert time to what the card wants */
5945 ips_fix_ffdc_time(ha, scb, ha->last_ffdc);
5946
5947 /* issue command */
5948 ips_send_wait(ha, scb, ips_cmd_timeout, intr);
5949 }
5950
5951 /****************************************************************************/
5952 /* */
5953 /* Routine Name: ips_ffdc_time */
5954 /* */
5955 /* Routine Description: */
5956 /* */
5957 /* FFDC: write time info */
5958 /* */
5959 /****************************************************************************/
5960 static void
5961 ips_ffdc_time(ips_ha_t * ha)
5962 {
5963 ips_scb_t *scb;
5964
5965 METHOD_TRACE("ips_ffdc_time", 1);
5966
5967 DEBUG_VAR(1, "(%s%d) Sending time update.", ips_name, ha->host_num);
5968
5969 scb = &ha->scbs[ha->max_cmds - 1];
5970
5971 ips_init_scb(ha, scb);
5972
5973 scb->timeout = ips_cmd_timeout;
5974 scb->cdb[0] = IPS_CMD_FFDC;
5975 scb->cmd.ffdc.op_code = IPS_CMD_FFDC;
5976 scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb);
5977 scb->cmd.ffdc.reset_count = 0;
5978 scb->cmd.ffdc.reset_type = 0;
5979
5980 /* convert time to what the card wants */
5981 ips_fix_ffdc_time(ha, scb, ha->last_ffdc);
5982
5983 /* issue command */
5984 ips_send_wait(ha, scb, ips_cmd_timeout, IPS_FFDC);
5985 }
5986
5987 /****************************************************************************/
5988 /* */
5989 /* Routine Name: ips_fix_ffdc_time */
5990 /* */
5991 /* Routine Description: */
5992 /* Adjust time_t to what the card wants */
5993 /* */
5994 /****************************************************************************/
5995 static void
5996 ips_fix_ffdc_time(ips_ha_t * ha, ips_scb_t * scb, time_t current_time)
5997 {
5998 long days;
5999 long rem;
6000 int i;
6001 int year;
6002 int yleap;
6003 int year_lengths[2] = { IPS_DAYS_NORMAL_YEAR, IPS_DAYS_LEAP_YEAR };
6004 int month_lengths[12][2] = { {31, 31},
6005 {28, 29},
6006 {31, 31},
6007 {30, 30},
6008 {31, 31},
6009 {30, 30},
6010 {31, 31},
6011 {31, 31},
6012 {30, 30},
6013 {31, 31},
6014 {30, 30},
6015 {31, 31}
6016 };
6017
6018 METHOD_TRACE("ips_fix_ffdc_time", 1);
6019
6020 days = current_time / IPS_SECS_DAY;
6021 rem = current_time % IPS_SECS_DAY;
6022
6023 scb->cmd.ffdc.hour = (rem / IPS_SECS_HOUR);
6024 rem = rem % IPS_SECS_HOUR;
6025 scb->cmd.ffdc.minute = (rem / IPS_SECS_MIN);
6026 scb->cmd.ffdc.second = (rem % IPS_SECS_MIN);
6027
6028 year = IPS_EPOCH_YEAR;
6029 while (days < 0 || days >= year_lengths[yleap = IPS_IS_LEAP_YEAR(year)]) {
6030 int newy;
6031
6032 newy = year + (days / IPS_DAYS_NORMAL_YEAR);
6033 if (days < 0)
6034 --newy;
6035 days -= (newy - year) * IPS_DAYS_NORMAL_YEAR +
6036 IPS_NUM_LEAP_YEARS_THROUGH(newy - 1) -
6037 IPS_NUM_LEAP_YEARS_THROUGH(year - 1);
6038 year = newy;
6039 }
6040
6041 scb->cmd.ffdc.yearH = year / 100;
6042 scb->cmd.ffdc.yearL = year % 100;
6043
6044 for (i = 0; days >= month_lengths[i][yleap]; ++i)
6045 days -= month_lengths[i][yleap];
6046
6047 scb->cmd.ffdc.month = i + 1;
6048 scb->cmd.ffdc.day = days + 1;
6049 }
6050
6051 /****************************************************************************
6052 * BIOS Flash Routines *
6053 ****************************************************************************/
6054
6055 /****************************************************************************/
6056 /* */
6057 /* Routine Name: ips_erase_bios */
6058 /* */
6059 /* Routine Description: */
6060 /* Erase the BIOS on the adapter */
6061 /* */
6062 /****************************************************************************/
6063 static int
6064 ips_erase_bios(ips_ha_t * ha)
6065 {
6066 int timeout;
6067 uint8_t status = 0;
6068
6069 METHOD_TRACE("ips_erase_bios", 1);
6070
6071 status = 0;
6072
6073 /* Clear the status register */
6074 outl(0, ha->io_addr + IPS_REG_FLAP);
6075 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6076 udelay(25); /* 25 us */
6077
6078 outb(0x50, ha->io_addr + IPS_REG_FLDP);
6079 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6080 udelay(25); /* 25 us */
6081
6082 /* Erase Setup */
6083 outb(0x20, ha->io_addr + IPS_REG_FLDP);
6084 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6085 udelay(25); /* 25 us */
6086
6087 /* Erase Confirm */
6088 outb(0xD0, ha->io_addr + IPS_REG_FLDP);
6089 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6090 udelay(25); /* 25 us */
6091
6092 /* Erase Status */
6093 outb(0x70, ha->io_addr + IPS_REG_FLDP);
6094 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6095 udelay(25); /* 25 us */
6096
6097 timeout = 80000; /* 80 seconds */
6098
6099 while (timeout > 0) {
6100 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6101 outl(0, ha->io_addr + IPS_REG_FLAP);
6102 udelay(25); /* 25 us */
6103 }
6104
6105 status = inb(ha->io_addr + IPS_REG_FLDP);
6106
6107 if (status & 0x80)
6108 break;
6109
6110 MDELAY(1);
6111 timeout--;
6112 }
6113
6114 /* check for timeout */
6115 if (timeout <= 0) {
6116 /* timeout */
6117
6118 /* try to suspend the erase */
6119 outb(0xB0, ha->io_addr + IPS_REG_FLDP);
6120 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6121 udelay(25); /* 25 us */
6122
6123 /* wait for 10 seconds */
6124 timeout = 10000;
6125 while (timeout > 0) {
6126 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6127 outl(0, ha->io_addr + IPS_REG_FLAP);
6128 udelay(25); /* 25 us */
6129 }
6130
6131 status = inb(ha->io_addr + IPS_REG_FLDP);
6132
6133 if (status & 0xC0)
6134 break;
6135
6136 MDELAY(1);
6137 timeout--;
6138 }
6139
6140 return (1);
6141 }
6142
6143 /* check for valid VPP */
6144 if (status & 0x08)
6145 /* VPP failure */
6146 return (1);
6147
6148 /* check for successful flash */
6149 if (status & 0x30)
6150 /* sequence error */
6151 return (1);
6152
6153 /* Otherwise, we were successful */
6154 /* clear status */
6155 outb(0x50, ha->io_addr + IPS_REG_FLDP);
6156 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6157 udelay(25); /* 25 us */
6158
6159 /* enable reads */
6160 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6161 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6162 udelay(25); /* 25 us */
6163
6164 return (0);
6165 }
6166
6167 /****************************************************************************/
6168 /* */
6169 /* Routine Name: ips_erase_bios_memio */
6170 /* */
6171 /* Routine Description: */
6172 /* Erase the BIOS on the adapter */
6173 /* */
6174 /****************************************************************************/
6175 static int
6176 ips_erase_bios_memio(ips_ha_t * ha)
6177 {
6178 int timeout;
6179 uint8_t status;
6180
6181 METHOD_TRACE("ips_erase_bios_memio", 1);
6182
6183 status = 0;
6184
6185 /* Clear the status register */
6186 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6187 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6188 udelay(25); /* 25 us */
6189
6190 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP);
6191 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6192 udelay(25); /* 25 us */
6193
6194 /* Erase Setup */
6195 writeb(0x20, ha->mem_ptr + IPS_REG_FLDP);
6196 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6197 udelay(25); /* 25 us */
6198
6199 /* Erase Confirm */
6200 writeb(0xD0, ha->mem_ptr + IPS_REG_FLDP);
6201 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6202 udelay(25); /* 25 us */
6203
6204 /* Erase Status */
6205 writeb(0x70, ha->mem_ptr + IPS_REG_FLDP);
6206 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6207 udelay(25); /* 25 us */
6208
6209 timeout = 80000; /* 80 seconds */
6210
6211 while (timeout > 0) {
6212 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6213 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6214 udelay(25); /* 25 us */
6215 }
6216
6217 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6218
6219 if (status & 0x80)
6220 break;
6221
6222 MDELAY(1);
6223 timeout--;
6224 }
6225
6226 /* check for timeout */
6227 if (timeout <= 0) {
6228 /* timeout */
6229
6230 /* try to suspend the erase */
6231 writeb(0xB0, ha->mem_ptr + IPS_REG_FLDP);
6232 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6233 udelay(25); /* 25 us */
6234
6235 /* wait for 10 seconds */
6236 timeout = 10000;
6237 while (timeout > 0) {
6238 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6239 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6240 udelay(25); /* 25 us */
6241 }
6242
6243 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6244
6245 if (status & 0xC0)
6246 break;
6247
6248 MDELAY(1);
6249 timeout--;
6250 }
6251
6252 return (1);
6253 }
6254
6255 /* check for valid VPP */
6256 if (status & 0x08)
6257 /* VPP failure */
6258 return (1);
6259
6260 /* check for successful flash */
6261 if (status & 0x30)
6262 /* sequence error */
6263 return (1);
6264
6265 /* Otherwise, we were successful */
6266 /* clear status */
6267 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP);
6268 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6269 udelay(25); /* 25 us */
6270
6271 /* enable reads */
6272 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6273 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6274 udelay(25); /* 25 us */
6275
6276 return (0);
6277 }
6278
6279 /****************************************************************************/
6280 /* */
6281 /* Routine Name: ips_program_bios */
6282 /* */
6283 /* Routine Description: */
6284 /* Program the BIOS on the adapter */
6285 /* */
6286 /****************************************************************************/
6287 static int
6288 ips_program_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6289 uint32_t offset)
6290 {
6291 int i;
6292 int timeout;
6293 uint8_t status = 0;
6294
6295 METHOD_TRACE("ips_program_bios", 1);
6296
6297 status = 0;
6298
6299 for (i = 0; i < buffersize; i++) {
6300 /* write a byte */
6301 outl(i + offset, ha->io_addr + IPS_REG_FLAP);
6302 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6303 udelay(25); /* 25 us */
6304
6305 outb(0x40, ha->io_addr + IPS_REG_FLDP);
6306 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6307 udelay(25); /* 25 us */
6308
6309 outb(buffer[i], ha->io_addr + IPS_REG_FLDP);
6310 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6311 udelay(25); /* 25 us */
6312
6313 /* wait up to one second */
6314 timeout = 1000;
6315 while (timeout > 0) {
6316 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6317 outl(0, ha->io_addr + IPS_REG_FLAP);
6318 udelay(25); /* 25 us */
6319 }
6320
6321 status = inb(ha->io_addr + IPS_REG_FLDP);
6322
6323 if (status & 0x80)
6324 break;
6325
6326 MDELAY(1);
6327 timeout--;
6328 }
6329
6330 if (timeout == 0) {
6331 /* timeout error */
6332 outl(0, ha->io_addr + IPS_REG_FLAP);
6333 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6334 udelay(25); /* 25 us */
6335
6336 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6337 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6338 udelay(25); /* 25 us */
6339
6340 return (1);
6341 }
6342
6343 /* check the status */
6344 if (status & 0x18) {
6345 /* programming error */
6346 outl(0, ha->io_addr + IPS_REG_FLAP);
6347 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6348 udelay(25); /* 25 us */
6349
6350 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6351 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6352 udelay(25); /* 25 us */
6353
6354 return (1);
6355 }
6356 } /* end for */
6357
6358 /* Enable reading */
6359 outl(0, ha->io_addr + IPS_REG_FLAP);
6360 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6361 udelay(25); /* 25 us */
6362
6363 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6364 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6365 udelay(25); /* 25 us */
6366
6367 return (0);
6368 }
6369
6370 /****************************************************************************/
6371 /* */
6372 /* Routine Name: ips_program_bios_memio */
6373 /* */
6374 /* Routine Description: */
6375 /* Program the BIOS on the adapter */
6376 /* */
6377 /****************************************************************************/
6378 static int
6379 ips_program_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6380 uint32_t offset)
6381 {
6382 int i;
6383 int timeout;
6384 uint8_t status = 0;
6385
6386 METHOD_TRACE("ips_program_bios_memio", 1);
6387
6388 status = 0;
6389
6390 for (i = 0; i < buffersize; i++) {
6391 /* write a byte */
6392 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);
6393 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6394 udelay(25); /* 25 us */
6395
6396 writeb(0x40, ha->mem_ptr + IPS_REG_FLDP);
6397 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6398 udelay(25); /* 25 us */
6399
6400 writeb(buffer[i], ha->mem_ptr + IPS_REG_FLDP);
6401 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6402 udelay(25); /* 25 us */
6403
6404 /* wait up to one second */
6405 timeout = 1000;
6406 while (timeout > 0) {
6407 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6408 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6409 udelay(25); /* 25 us */
6410 }
6411
6412 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6413
6414 if (status & 0x80)
6415 break;
6416
6417 MDELAY(1);
6418 timeout--;
6419 }
6420
6421 if (timeout == 0) {
6422 /* timeout error */
6423 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6424 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6425 udelay(25); /* 25 us */
6426
6427 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6428 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6429 udelay(25); /* 25 us */
6430
6431 return (1);
6432 }
6433
6434 /* check the status */
6435 if (status & 0x18) {
6436 /* programming error */
6437 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6438 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6439 udelay(25); /* 25 us */
6440
6441 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6442 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6443 udelay(25); /* 25 us */
6444
6445 return (1);
6446 }
6447 } /* end for */
6448
6449 /* Enable reading */
6450 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6451 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6452 udelay(25); /* 25 us */
6453
6454 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6455 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6456 udelay(25); /* 25 us */
6457
6458 return (0);
6459 }
6460
6461 /****************************************************************************/
6462 /* */
6463 /* Routine Name: ips_verify_bios */
6464 /* */
6465 /* Routine Description: */
6466 /* Verify the BIOS on the adapter */
6467 /* */
6468 /****************************************************************************/
6469 static int
6470 ips_verify_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6471 uint32_t offset)
6472 {
6473 uint8_t checksum;
6474 int i;
6475
6476 METHOD_TRACE("ips_verify_bios", 1);
6477
6478 /* test 1st byte */
6479 outl(0, ha->io_addr + IPS_REG_FLAP);
6480 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6481 udelay(25); /* 25 us */
6482
6483 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55)
6484 return (1);
6485
6486 outl(1, ha->io_addr + IPS_REG_FLAP);
6487 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6488 udelay(25); /* 25 us */
6489 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA)
6490 return (1);
6491
6492 checksum = 0xff;
6493 for (i = 2; i < buffersize; i++) {
6494
6495 outl(i + offset, ha->io_addr + IPS_REG_FLAP);
6496 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6497 udelay(25); /* 25 us */
6498
6499 checksum = (uint8_t) checksum + inb(ha->io_addr + IPS_REG_FLDP);
6500 }
6501
6502 if (checksum != 0)
6503 /* failure */
6504 return (1);
6505 else
6506 /* success */
6507 return (0);
6508 }
6509
6510 /****************************************************************************/
6511 /* */
6512 /* Routine Name: ips_verify_bios_memio */
6513 /* */
6514 /* Routine Description: */
6515 /* Verify the BIOS on the adapter */
6516 /* */
6517 /****************************************************************************/
6518 static int
6519 ips_verify_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6520 uint32_t offset)
6521 {
6522 uint8_t checksum;
6523 int i;
6524
6525 METHOD_TRACE("ips_verify_bios_memio", 1);
6526
6527 /* test 1st byte */
6528 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6529 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6530 udelay(25); /* 25 us */
6531
6532 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55)
6533 return (1);
6534
6535 writel(1, ha->mem_ptr + IPS_REG_FLAP);
6536 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6537 udelay(25); /* 25 us */
6538 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA)
6539 return (1);
6540
6541 checksum = 0xff;
6542 for (i = 2; i < buffersize; i++) {
6543
6544 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);
6545 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6546 udelay(25); /* 25 us */
6547
6548 checksum =
6549 (uint8_t) checksum + readb(ha->mem_ptr + IPS_REG_FLDP);
6550 }
6551
6552 if (checksum != 0)
6553 /* failure */
6554 return (1);
6555 else
6556 /* success */
6557 return (0);
6558 }
6559
6560 /****************************************************************************/
6561 /* */
6562 /* Routine Name: ips_abort_init */
6563 /* */
6564 /* Routine Description: */
6565 /* cleanup routine for a failed adapter initialization */
6566 /****************************************************************************/
6567 static int
6568 ips_abort_init(ips_ha_t * ha, int index)
6569 {
6570 ha->active = 0;
6571 ips_free(ha);
6572 ips_ha[index] = NULL;
6573 ips_sh[index] = NULL;
6574 return -1;
6575 }
6576
6577 /****************************************************************************/
6578 /* */
6579 /* Routine Name: ips_shift_controllers */
6580 /* */
6581 /* Routine Description: */
6582 /* helper function for ordering adapters */
6583 /****************************************************************************/
6584 static void
6585 ips_shift_controllers(int lowindex, int highindex)
6586 {
6587 ips_ha_t *ha_sav = ips_ha[highindex];
6588 struct Scsi_Host *sh_sav = ips_sh[highindex];
6589 int i;
6590
6591 for (i = highindex; i > lowindex; i--) {
6592 ips_ha[i] = ips_ha[i - 1];
6593 ips_sh[i] = ips_sh[i - 1];
6594 ips_ha[i]->host_num = i;
6595 }
6596 ha_sav->host_num = lowindex;
6597 ips_ha[lowindex] = ha_sav;
6598 ips_sh[lowindex] = sh_sav;
6599 }
6600
6601 /****************************************************************************/
6602 /* */
6603 /* Routine Name: ips_order_controllers */
6604 /* */
6605 /* Routine Description: */
6606 /* place controllers is the "proper" boot order */
6607 /****************************************************************************/
6608 static void
6609 ips_order_controllers(void)
6610 {
6611 int i, j, tmp, position = 0;
6612 IPS_NVRAM_P5 *nvram;
6613 if (!ips_ha[0])
6614 return;
6615 nvram = ips_ha[0]->nvram;
6616
6617 if (nvram->adapter_order[0]) {
6618 for (i = 1; i <= nvram->adapter_order[0]; i++) {
6619 for (j = position; j < ips_num_controllers; j++) {
6620 switch (ips_ha[j]->ad_type) {
6621 case IPS_ADTYPE_SERVERAID6M:
6622 case IPS_ADTYPE_SERVERAID7M:
6623 if (nvram->adapter_order[i] == 'M') {
6624 ips_shift_controllers(position,
6625 j);
6626 position++;
6627 }
6628 break;
6629 case IPS_ADTYPE_SERVERAID4L:
6630 case IPS_ADTYPE_SERVERAID4M:
6631 case IPS_ADTYPE_SERVERAID4MX:
6632 case IPS_ADTYPE_SERVERAID4LX:
6633 if (nvram->adapter_order[i] == 'N') {
6634 ips_shift_controllers(position,
6635 j);
6636 position++;
6637 }
6638 break;
6639 case IPS_ADTYPE_SERVERAID6I:
6640 case IPS_ADTYPE_SERVERAID5I2:
6641 case IPS_ADTYPE_SERVERAID5I1:
6642 case IPS_ADTYPE_SERVERAID7k:
6643 if (nvram->adapter_order[i] == 'S') {
6644 ips_shift_controllers(position,
6645 j);
6646 position++;
6647 }
6648 break;
6649 case IPS_ADTYPE_SERVERAID:
6650 case IPS_ADTYPE_SERVERAID2:
6651 case IPS_ADTYPE_NAVAJO:
6652 case IPS_ADTYPE_KIOWA:
6653 case IPS_ADTYPE_SERVERAID3L:
6654 case IPS_ADTYPE_SERVERAID3:
6655 case IPS_ADTYPE_SERVERAID4H:
6656 if (nvram->adapter_order[i] == 'A') {
6657 ips_shift_controllers(position,
6658 j);
6659 position++;
6660 }
6661 break;
6662 default:
6663 break;
6664 }
6665 }
6666 }
6667 /* if adapter_order[0], then ordering is complete */
6668 return;
6669 }
6670 /* old bios, use older ordering */
6671 tmp = 0;
6672 for (i = position; i < ips_num_controllers; i++) {
6673 if (ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID5I2 ||
6674 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID5I1) {
6675 ips_shift_controllers(position, i);
6676 position++;
6677 tmp = 1;
6678 }
6679 }
6680 /* if there were no 5I cards, then don't do any extra ordering */
6681 if (!tmp)
6682 return;
6683 for (i = position; i < ips_num_controllers; i++) {
6684 if (ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4L ||
6685 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4M ||
6686 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4LX ||
6687 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4MX) {
6688 ips_shift_controllers(position, i);
6689 position++;
6690 }
6691 }
6692
6693 return;
6694 }
6695
6696 /****************************************************************************/
6697 /* */
6698 /* Routine Name: ips_register_scsi */
6699 /* */
6700 /* Routine Description: */
6701 /* perform any registration and setup with the scsi layer */
6702 /****************************************************************************/
6703 static int
6704 ips_register_scsi(int index)
6705 {
6706 struct Scsi_Host *sh;
6707 ips_ha_t *ha, *oldha = ips_ha[index];
6708 sh = scsi_host_alloc(&ips_driver_template, sizeof (ips_ha_t));
6709 if (!sh) {
6710 IPS_PRINTK(KERN_WARNING, oldha->pcidev,
6711 "Unable to register controller with SCSI subsystem\n");
6712 return -1;
6713 }
6714 ha = IPS_HA(sh);
6715 memcpy(ha, oldha, sizeof (ips_ha_t));
6716 free_irq(oldha->pcidev->irq, oldha);
6717 /* Install the interrupt handler with the new ha */
6718 if (request_irq(ha->pcidev->irq, do_ipsintr, IRQF_SHARED, ips_name, ha)) {
6719 IPS_PRINTK(KERN_WARNING, ha->pcidev,
6720 "Unable to install interrupt handler\n");
6721 goto err_out_sh;
6722 }
6723
6724 kfree(oldha);
6725
6726 /* Store away needed values for later use */
6727 sh->unique_id = (ha->io_addr) ? ha->io_addr : ha->mem_addr;
6728 sh->sg_tablesize = sh->hostt->sg_tablesize;
6729 sh->can_queue = sh->hostt->can_queue;
6730 sh->cmd_per_lun = sh->hostt->cmd_per_lun;
6731 sh->use_clustering = sh->hostt->use_clustering;
6732 sh->max_sectors = 128;
6733
6734 sh->max_id = ha->ntargets;
6735 sh->max_lun = ha->nlun;
6736 sh->max_channel = ha->nbus - 1;
6737 sh->can_queue = ha->max_cmds - 1;
6738
6739 if (scsi_add_host(sh, &ha->pcidev->dev))
6740 goto err_out;
6741
6742 ips_sh[index] = sh;
6743 ips_ha[index] = ha;
6744
6745 scsi_scan_host(sh);
6746
6747 return 0;
6748
6749 err_out:
6750 free_irq(ha->pcidev->irq, ha);
6751 err_out_sh:
6752 scsi_host_put(sh);
6753 return -1;
6754 }
6755
6756 /*---------------------------------------------------------------------------*/
6757 /* Routine Name: ips_remove_device */
6758 /* */
6759 /* Routine Description: */
6760 /* Remove one Adapter ( Hot Plugging ) */
6761 /*---------------------------------------------------------------------------*/
6762 static void
6763 ips_remove_device(struct pci_dev *pci_dev)
6764 {
6765 struct Scsi_Host *sh = pci_get_drvdata(pci_dev);
6766
6767 pci_set_drvdata(pci_dev, NULL);
6768
6769 ips_release(sh);
6770
6771 pci_release_regions(pci_dev);
6772 pci_disable_device(pci_dev);
6773 }
6774
6775 /****************************************************************************/
6776 /* */
6777 /* Routine Name: ips_module_init */
6778 /* */
6779 /* Routine Description: */
6780 /* function called on module load */
6781 /****************************************************************************/
6782 static int __init
6783 ips_module_init(void)
6784 {
6785 #if !defined(__i386__) && !defined(__ia64__) && !defined(__x86_64__)
6786 printk(KERN_ERR "ips: This driver has only been tested on the x86/ia64/x86_64 platforms\n");
6787 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
6788 #endif
6789
6790 if (pci_register_driver(&ips_pci_driver) < 0)
6791 return -ENODEV;
6792 ips_driver_template.module = THIS_MODULE;
6793 ips_order_controllers();
6794 if (!ips_detect(&ips_driver_template)) {
6795 pci_unregister_driver(&ips_pci_driver);
6796 return -ENODEV;
6797 }
6798 register_reboot_notifier(&ips_notifier);
6799 return 0;
6800 }
6801
6802 /****************************************************************************/
6803 /* */
6804 /* Routine Name: ips_module_exit */
6805 /* */
6806 /* Routine Description: */
6807 /* function called on module unload */
6808 /****************************************************************************/
6809 static void __exit
6810 ips_module_exit(void)
6811 {
6812 pci_unregister_driver(&ips_pci_driver);
6813 unregister_reboot_notifier(&ips_notifier);
6814 }
6815
6816 module_init(ips_module_init);
6817 module_exit(ips_module_exit);
6818
6819 /*---------------------------------------------------------------------------*/
6820 /* Routine Name: ips_insert_device */
6821 /* */
6822 /* Routine Description: */
6823 /* Add One Adapter ( Hot Plug ) */
6824 /* */
6825 /* Return Value: */
6826 /* 0 if Successful, else non-zero */
6827 /*---------------------------------------------------------------------------*/
6828 static int
6829 ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent)
6830 {
6831 int index = -1;
6832 int rc;
6833
6834 METHOD_TRACE("ips_insert_device", 1);
6835 rc = pci_enable_device(pci_dev);
6836 if (rc)
6837 return rc;
6838
6839 rc = pci_request_regions(pci_dev, "ips");
6840 if (rc)
6841 goto err_out;
6842
6843 rc = ips_init_phase1(pci_dev, &index);
6844 if (rc == SUCCESS)
6845 rc = ips_init_phase2(index);
6846
6847 if (ips_hotplug)
6848 if (ips_register_scsi(index)) {
6849 ips_free(ips_ha[index]);
6850 rc = -1;
6851 }
6852
6853 if (rc == SUCCESS)
6854 ips_num_controllers++;
6855
6856 ips_next_controller = ips_num_controllers;
6857
6858 if (rc < 0) {
6859 rc = -ENODEV;
6860 goto err_out_regions;
6861 }
6862
6863 pci_set_drvdata(pci_dev, ips_sh[index]);
6864 return 0;
6865
6866 err_out_regions:
6867 pci_release_regions(pci_dev);
6868 err_out:
6869 pci_disable_device(pci_dev);
6870 return rc;
6871 }
6872
6873 /*---------------------------------------------------------------------------*/
6874 /* Routine Name: ips_init_phase1 */
6875 /* */
6876 /* Routine Description: */
6877 /* Adapter Initialization */
6878 /* */
6879 /* Return Value: */
6880 /* 0 if Successful, else non-zero */
6881 /*---------------------------------------------------------------------------*/
6882 static int
6883 ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr)
6884 {
6885 ips_ha_t *ha;
6886 uint32_t io_addr;
6887 uint32_t mem_addr;
6888 uint32_t io_len;
6889 uint32_t mem_len;
6890 uint8_t bus;
6891 uint8_t func;
6892 int j;
6893 int index;
6894 dma_addr_t dma_address;
6895 char __iomem *ioremap_ptr;
6896 char __iomem *mem_ptr;
6897 uint32_t IsDead;
6898
6899 METHOD_TRACE("ips_init_phase1", 1);
6900 index = IPS_MAX_ADAPTERS;
6901 for (j = 0; j < IPS_MAX_ADAPTERS; j++) {
6902 if (ips_ha[j] == NULL) {
6903 index = j;
6904 break;
6905 }
6906 }
6907
6908 if (index >= IPS_MAX_ADAPTERS)
6909 return -1;
6910
6911 /* stuff that we get in dev */
6912 bus = pci_dev->bus->number;
6913 func = pci_dev->devfn;
6914
6915 /* Init MEM/IO addresses to 0 */
6916 mem_addr = 0;
6917 io_addr = 0;
6918 mem_len = 0;
6919 io_len = 0;
6920
6921 for (j = 0; j < 2; j++) {
6922 if (!pci_resource_start(pci_dev, j))
6923 break;
6924
6925 if (pci_resource_flags(pci_dev, j) & IORESOURCE_IO) {
6926 io_addr = pci_resource_start(pci_dev, j);
6927 io_len = pci_resource_len(pci_dev, j);
6928 } else {
6929 mem_addr = pci_resource_start(pci_dev, j);
6930 mem_len = pci_resource_len(pci_dev, j);
6931 }
6932 }
6933
6934 /* setup memory mapped area (if applicable) */
6935 if (mem_addr) {
6936 uint32_t base;
6937 uint32_t offs;
6938
6939 base = mem_addr & PAGE_MASK;
6940 offs = mem_addr - base;
6941 ioremap_ptr = ioremap(base, PAGE_SIZE);
6942 if (!ioremap_ptr)
6943 return -1;
6944 mem_ptr = ioremap_ptr + offs;
6945 } else {
6946 ioremap_ptr = NULL;
6947 mem_ptr = NULL;
6948 }
6949
6950 /* found a controller */
6951 ha = kzalloc(sizeof (ips_ha_t), GFP_KERNEL);
6952 if (ha == NULL) {
6953 IPS_PRINTK(KERN_WARNING, pci_dev,
6954 "Unable to allocate temporary ha struct\n");
6955 return -1;
6956 }
6957
6958 ips_sh[index] = NULL;
6959 ips_ha[index] = ha;
6960 ha->active = 1;
6961
6962 /* Store info in HA structure */
6963 ha->io_addr = io_addr;
6964 ha->io_len = io_len;
6965 ha->mem_addr = mem_addr;
6966 ha->mem_len = mem_len;
6967 ha->mem_ptr = mem_ptr;
6968 ha->ioremap_ptr = ioremap_ptr;
6969 ha->host_num = (uint32_t) index;
6970 ha->slot_num = PCI_SLOT(pci_dev->devfn);
6971 ha->pcidev = pci_dev;
6972
6973 /*
6974 * Set the pci_dev's dma_mask. Not all adapters support 64bit
6975 * addressing so don't enable it if the adapter can't support
6976 * it! Also, don't use 64bit addressing if dma addresses
6977 * are guaranteed to be < 4G.
6978 */
6979 if (IPS_ENABLE_DMA64 && IPS_HAS_ENH_SGLIST(ha) &&
6980 !pci_set_dma_mask(ha->pcidev, DMA_BIT_MASK(64))) {
6981 (ha)->flags |= IPS_HA_ENH_SG;
6982 } else {
6983 if (pci_set_dma_mask(ha->pcidev, DMA_BIT_MASK(32)) != 0) {
6984 printk(KERN_WARNING "Unable to set DMA Mask\n");
6985 return ips_abort_init(ha, index);
6986 }
6987 }
6988 if(ips_cd_boot && !ips_FlashData){
6989 ips_FlashData = pci_alloc_consistent(pci_dev, PAGE_SIZE << 7,
6990 &ips_flashbusaddr);
6991 }
6992
6993 ha->enq = pci_alloc_consistent(pci_dev, sizeof (IPS_ENQ),
6994 &ha->enq_busaddr);
6995 if (!ha->enq) {
6996 IPS_PRINTK(KERN_WARNING, pci_dev,
6997 "Unable to allocate host inquiry structure\n");
6998 return ips_abort_init(ha, index);
6999 }
7000
7001 ha->adapt = pci_alloc_consistent(pci_dev, sizeof (IPS_ADAPTER) +
7002 sizeof (IPS_IO_CMD), &dma_address);
7003 if (!ha->adapt) {
7004 IPS_PRINTK(KERN_WARNING, pci_dev,
7005 "Unable to allocate host adapt & dummy structures\n");
7006 return ips_abort_init(ha, index);
7007 }
7008 ha->adapt->hw_status_start = dma_address;
7009 ha->dummy = (void *) (ha->adapt + 1);
7010
7011
7012
7013 ha->logical_drive_info = pci_alloc_consistent(pci_dev, sizeof (IPS_LD_INFO), &dma_address);
7014 if (!ha->logical_drive_info) {
7015 IPS_PRINTK(KERN_WARNING, pci_dev,
7016 "Unable to allocate logical drive info structure\n");
7017 return ips_abort_init(ha, index);
7018 }
7019 ha->logical_drive_info_dma_addr = dma_address;
7020
7021
7022 ha->conf = kmalloc(sizeof (IPS_CONF), GFP_KERNEL);
7023
7024 if (!ha->conf) {
7025 IPS_PRINTK(KERN_WARNING, pci_dev,
7026 "Unable to allocate host conf structure\n");
7027 return ips_abort_init(ha, index);
7028 }
7029
7030 ha->nvram = kmalloc(sizeof (IPS_NVRAM_P5), GFP_KERNEL);
7031
7032 if (!ha->nvram) {
7033 IPS_PRINTK(KERN_WARNING, pci_dev,
7034 "Unable to allocate host NVRAM structure\n");
7035 return ips_abort_init(ha, index);
7036 }
7037
7038 ha->subsys = kmalloc(sizeof (IPS_SUBSYS), GFP_KERNEL);
7039
7040 if (!ha->subsys) {
7041 IPS_PRINTK(KERN_WARNING, pci_dev,
7042 "Unable to allocate host subsystem structure\n");
7043 return ips_abort_init(ha, index);
7044 }
7045
7046 /* the ioctl buffer is now used during adapter initialization, so its
7047 * successful allocation is now required */
7048 if (ips_ioctlsize < PAGE_SIZE)
7049 ips_ioctlsize = PAGE_SIZE;
7050
7051 ha->ioctl_data = pci_alloc_consistent(pci_dev, ips_ioctlsize,
7052 &ha->ioctl_busaddr);
7053 ha->ioctl_len = ips_ioctlsize;
7054 if (!ha->ioctl_data) {
7055 IPS_PRINTK(KERN_WARNING, pci_dev,
7056 "Unable to allocate IOCTL data\n");
7057 return ips_abort_init(ha, index);
7058 }
7059
7060 /*
7061 * Setup Functions
7062 */
7063 ips_setup_funclist(ha);
7064
7065 if ((IPS_IS_MORPHEUS(ha)) || (IPS_IS_MARCO(ha))) {
7066 /* If Morpheus appears dead, reset it */
7067 IsDead = readl(ha->mem_ptr + IPS_REG_I960_MSG1);
7068 if (IsDead == 0xDEADBEEF) {
7069 ips_reset_morpheus(ha);
7070 }
7071 }
7072
7073 /*
7074 * Initialize the card if it isn't already
7075 */
7076
7077 if (!(*ha->func.isinit) (ha)) {
7078 if (!(*ha->func.init) (ha)) {
7079 /*
7080 * Initialization failed
7081 */
7082 IPS_PRINTK(KERN_WARNING, pci_dev,
7083 "Unable to initialize controller\n");
7084 return ips_abort_init(ha, index);
7085 }
7086 }
7087
7088 *indexPtr = index;
7089 return SUCCESS;
7090 }
7091
7092 /*---------------------------------------------------------------------------*/
7093 /* Routine Name: ips_init_phase2 */
7094 /* */
7095 /* Routine Description: */
7096 /* Adapter Initialization Phase 2 */
7097 /* */
7098 /* Return Value: */
7099 /* 0 if Successful, else non-zero */
7100 /*---------------------------------------------------------------------------*/
7101 static int
7102 ips_init_phase2(int index)
7103 {
7104 ips_ha_t *ha;
7105
7106 ha = ips_ha[index];
7107
7108 METHOD_TRACE("ips_init_phase2", 1);
7109 if (!ha->active) {
7110 ips_ha[index] = NULL;
7111 return -1;
7112 }
7113
7114 /* Install the interrupt handler */
7115 if (request_irq(ha->pcidev->irq, do_ipsintr, IRQF_SHARED, ips_name, ha)) {
7116 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7117 "Unable to install interrupt handler\n");
7118 return ips_abort_init(ha, index);
7119 }
7120
7121 /*
7122 * Allocate a temporary SCB for initialization
7123 */
7124 ha->max_cmds = 1;
7125 if (!ips_allocatescbs(ha)) {
7126 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7127 "Unable to allocate a CCB\n");
7128 free_irq(ha->pcidev->irq, ha);
7129 return ips_abort_init(ha, index);
7130 }
7131
7132 if (!ips_hainit(ha)) {
7133 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7134 "Unable to initialize controller\n");
7135 free_irq(ha->pcidev->irq, ha);
7136 return ips_abort_init(ha, index);
7137 }
7138 /* Free the temporary SCB */
7139 ips_deallocatescbs(ha, 1);
7140
7141 /* allocate CCBs */
7142 if (!ips_allocatescbs(ha)) {
7143 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7144 "Unable to allocate CCBs\n");
7145 free_irq(ha->pcidev->irq, ha);
7146 return ips_abort_init(ha, index);
7147 }
7148
7149 return SUCCESS;
7150 }
7151
7152 MODULE_LICENSE("GPL");
7153 MODULE_DESCRIPTION("IBM ServeRAID Adapter Driver " IPS_VER_STRING);
7154 MODULE_VERSION(IPS_VER_STRING);
7155
7156
7157 /*
7158 * Overrides for Emacs so that we almost follow Linus's tabbing style.
7159 * Emacs will notice this stuff at the end of the file and automatically
7160 * adjust the settings for this buffer only. This must remain at the end
7161 * of the file.
7162 * ---------------------------------------------------------------------------
7163 * Local variables:
7164 * c-indent-level: 2
7165 * c-brace-imaginary-offset: 0
7166 * c-brace-offset: -2
7167 * c-argdecl-indent: 2
7168 * c-label-offset: -2
7169 * c-continued-statement-offset: 2
7170 * c-continued-brace-offset: 0
7171 * indent-tabs-mode: nil
7172 * tab-width: 8
7173 * End:
7174 */
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