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0ebc4cda BH |
1 | /* |
2 | * This file contains the 64-bit "server" PowerPC variant | |
3 | * of the low level exception handling including exception | |
4 | * vectors, exception return, part of the slb and stab | |
5 | * handling and other fixed offset specific things. | |
6 | * | |
7 | * This file is meant to be #included from head_64.S due to | |
25985edc | 8 | * position dependent assembly. |
0ebc4cda BH |
9 | * |
10 | * Most of this originates from head_64.S and thus has the same | |
11 | * copyright history. | |
12 | * | |
13 | */ | |
14 | ||
7230c564 | 15 | #include <asm/hw_irq.h> |
8aa34ab8 | 16 | #include <asm/exception-64s.h> |
46f52210 | 17 | #include <asm/ptrace.h> |
8aa34ab8 | 18 | |
0ebc4cda BH |
19 | /* |
20 | * We layout physical memory as follows: | |
21 | * 0x0000 - 0x00ff : Secondary processor spin code | |
c1fb6816 MN |
22 | * 0x0100 - 0x17ff : pSeries Interrupt prologs |
23 | * 0x1800 - 0x4000 : interrupt support common interrupt prologs | |
24 | * 0x4000 - 0x5fff : pSeries interrupts with IR=1,DR=1 | |
25 | * 0x6000 - 0x6fff : more interrupt support including for IR=1,DR=1 | |
0ebc4cda | 26 | * 0x7000 - 0x7fff : FWNMI data area |
c1fb6816 MN |
27 | * 0x8000 - 0x8fff : Initial (CPU0) segment table |
28 | * 0x9000 - : Early init and support code | |
0ebc4cda | 29 | */ |
742415d6 MN |
30 | /* Syscall routine is used twice, in reloc-off and reloc-on paths */ |
31 | #define SYSCALL_PSERIES_1 \ | |
32 | BEGIN_FTR_SECTION \ | |
33 | cmpdi r0,0x1ebe ; \ | |
34 | beq- 1f ; \ | |
35 | END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) \ | |
36 | mr r9,r13 ; \ | |
37 | GET_PACA(r13) ; \ | |
38 | mfspr r11,SPRN_SRR0 ; \ | |
39 | 0: | |
40 | ||
41 | #define SYSCALL_PSERIES_2_RFID \ | |
42 | mfspr r12,SPRN_SRR1 ; \ | |
43 | ld r10,PACAKBASE(r13) ; \ | |
44 | LOAD_HANDLER(r10, system_call_entry) ; \ | |
45 | mtspr SPRN_SRR0,r10 ; \ | |
46 | ld r10,PACAKMSR(r13) ; \ | |
47 | mtspr SPRN_SRR1,r10 ; \ | |
48 | rfid ; \ | |
49 | b . ; /* prevent speculative execution */ | |
50 | ||
51 | #define SYSCALL_PSERIES_3 \ | |
52 | /* Fast LE/BE switch system call */ \ | |
53 | 1: mfspr r12,SPRN_SRR1 ; \ | |
54 | xori r12,r12,MSR_LE ; \ | |
55 | mtspr SPRN_SRR1,r12 ; \ | |
56 | rfid ; /* return to userspace */ \ | |
57 | b . ; \ | |
58 | 2: mfspr r12,SPRN_SRR1 ; \ | |
59 | andi. r12,r12,MSR_PR ; \ | |
60 | bne 0b ; \ | |
61 | mtspr SPRN_SRR0,r3 ; \ | |
62 | mtspr SPRN_SRR1,r4 ; \ | |
63 | mtspr SPRN_SDR1,r5 ; \ | |
64 | rfid ; \ | |
65 | b . ; /* prevent speculative execution */ | |
66 | ||
4700dfaf MN |
67 | #if defined(CONFIG_RELOCATABLE) |
68 | /* | |
69 | * We can't branch directly; in the direct case we use LR | |
70 | * and system_call_entry restores LR. (We thus need to move | |
71 | * LR to r10 in the RFID case too.) | |
72 | */ | |
73 | #define SYSCALL_PSERIES_2_DIRECT \ | |
74 | mflr r10 ; \ | |
75 | ld r12,PACAKBASE(r13) ; \ | |
76 | LOAD_HANDLER(r12, system_call_entry_direct) ; \ | |
6a404806 | 77 | mtctr r12 ; \ |
4700dfaf MN |
78 | mfspr r12,SPRN_SRR1 ; \ |
79 | /* Re-use of r13... No spare regs to do this */ \ | |
80 | li r13,MSR_RI ; \ | |
81 | mtmsrd r13,1 ; \ | |
82 | GET_PACA(r13) ; /* get r13 back */ \ | |
6a404806 | 83 | bctr ; |
4700dfaf MN |
84 | #else |
85 | /* We can branch directly */ | |
86 | #define SYSCALL_PSERIES_2_DIRECT \ | |
87 | mfspr r12,SPRN_SRR1 ; \ | |
88 | li r10,MSR_RI ; \ | |
89 | mtmsrd r10,1 ; /* Set RI (EE=0) */ \ | |
90 | b system_call_entry_direct ; | |
91 | #endif | |
0ebc4cda | 92 | |
0ebc4cda BH |
93 | /* |
94 | * This is the start of the interrupt handlers for pSeries | |
95 | * This code runs with relocation off. | |
96 | * Code from here to __end_interrupts gets copied down to real | |
97 | * address 0x100 when we are running a relocatable kernel. | |
98 | * Therefore any relative branches in this section must only | |
99 | * branch to labels in this section. | |
100 | */ | |
101 | . = 0x100 | |
102 | .globl __start_interrupts | |
103 | __start_interrupts: | |
104 | ||
948cf67c BH |
105 | .globl system_reset_pSeries; |
106 | system_reset_pSeries: | |
44e9309f | 107 | HMT_MEDIUM_PPR_DISCARD |
948cf67c BH |
108 | SET_SCRATCH0(r13) |
109 | #ifdef CONFIG_PPC_P7_NAP | |
110 | BEGIN_FTR_SECTION | |
111 | /* Running native on arch 2.06 or later, check if we are | |
112 | * waking up from nap. We only handle no state loss and | |
113 | * supervisor state loss. We do -not- handle hypervisor | |
114 | * state loss at this time. | |
115 | */ | |
116 | mfspr r13,SPRN_SRR1 | |
371fefd6 PM |
117 | rlwinm. r13,r13,47-31,30,31 |
118 | beq 9f | |
119 | ||
120 | /* waking up from powersave (nap) state */ | |
121 | cmpwi cr1,r13,2 | |
948cf67c BH |
122 | /* Total loss of HV state is fatal, we could try to use the |
123 | * PIR to locate a PACA, then use an emergency stack etc... | |
124 | * but for now, let's just stay stuck here | |
125 | */ | |
371fefd6 PM |
126 | bgt cr1,. |
127 | GET_PACA(r13) | |
128 | ||
129 | #ifdef CONFIG_KVM_BOOK3S_64_HV | |
f0888f70 PM |
130 | li r0,KVM_HWTHREAD_IN_KERNEL |
131 | stb r0,HSTATE_HWTHREAD_STATE(r13) | |
132 | /* Order setting hwthread_state vs. testing hwthread_req */ | |
133 | sync | |
134 | lbz r0,HSTATE_HWTHREAD_REQ(r13) | |
135 | cmpwi r0,0 | |
136 | beq 1f | |
371fefd6 PM |
137 | b kvm_start_guest |
138 | 1: | |
139 | #endif | |
140 | ||
141 | beq cr1,2f | |
142 | b .power7_wakeup_noloss | |
143 | 2: b .power7_wakeup_loss | |
144 | 9: | |
969391c5 | 145 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) |
948cf67c | 146 | #endif /* CONFIG_PPC_P7_NAP */ |
b01c8b54 PM |
147 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD, |
148 | NOTEST, 0x100) | |
0ebc4cda BH |
149 | |
150 | . = 0x200 | |
b01c8b54 PM |
151 | machine_check_pSeries_1: |
152 | /* This is moved out of line as it can be patched by FW, but | |
153 | * some code path might still want to branch into the original | |
154 | * vector | |
155 | */ | |
1707dd16 PM |
156 | HMT_MEDIUM_PPR_DISCARD |
157 | SET_SCRATCH0(r13) /* save r13 */ | |
158 | EXCEPTION_PROLOG_0(PACA_EXMC) | |
159 | b machine_check_pSeries_0 | |
0ebc4cda BH |
160 | |
161 | . = 0x300 | |
162 | .globl data_access_pSeries | |
163 | data_access_pSeries: | |
44e9309f | 164 | HMT_MEDIUM_PPR_DISCARD |
673b189a | 165 | SET_SCRATCH0(r13) |
0ebc4cda | 166 | BEGIN_FTR_SECTION |
b01c8b54 PM |
167 | b data_access_check_stab |
168 | data_access_not_stab: | |
169 | END_MMU_FTR_SECTION_IFCLR(MMU_FTR_SLB) | |
b01c8b54 | 170 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common, EXC_STD, |
697d3899 | 171 | KVMTEST, 0x300) |
0ebc4cda BH |
172 | |
173 | . = 0x380 | |
174 | .globl data_access_slb_pSeries | |
175 | data_access_slb_pSeries: | |
44e9309f | 176 | HMT_MEDIUM_PPR_DISCARD |
673b189a | 177 | SET_SCRATCH0(r13) |
1707dd16 | 178 | EXCEPTION_PROLOG_0(PACA_EXSLB) |
697d3899 | 179 | EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST, 0x380) |
0ebc4cda BH |
180 | std r3,PACA_EXSLB+EX_R3(r13) |
181 | mfspr r3,SPRN_DAR | |
0ebc4cda BH |
182 | #ifdef __DISABLED__ |
183 | /* Keep that around for when we re-implement dynamic VSIDs */ | |
184 | cmpdi r3,0 | |
185 | bge slb_miss_user_pseries | |
186 | #endif /* __DISABLED__ */ | |
b01c8b54 | 187 | mfspr r12,SPRN_SRR1 |
0ebc4cda BH |
188 | #ifndef CONFIG_RELOCATABLE |
189 | b .slb_miss_realmode | |
190 | #else | |
191 | /* | |
192 | * We can't just use a direct branch to .slb_miss_realmode | |
193 | * because the distance from here to there depends on where | |
194 | * the kernel ends up being put. | |
195 | */ | |
196 | mfctr r11 | |
197 | ld r10,PACAKBASE(r13) | |
198 | LOAD_HANDLER(r10, .slb_miss_realmode) | |
199 | mtctr r10 | |
200 | bctr | |
201 | #endif | |
202 | ||
b3e6b5df | 203 | STD_EXCEPTION_PSERIES(0x400, 0x400, instruction_access) |
0ebc4cda BH |
204 | |
205 | . = 0x480 | |
206 | .globl instruction_access_slb_pSeries | |
207 | instruction_access_slb_pSeries: | |
44e9309f | 208 | HMT_MEDIUM_PPR_DISCARD |
673b189a | 209 | SET_SCRATCH0(r13) |
1707dd16 | 210 | EXCEPTION_PROLOG_0(PACA_EXSLB) |
de56a948 | 211 | EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x480) |
0ebc4cda BH |
212 | std r3,PACA_EXSLB+EX_R3(r13) |
213 | mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ | |
0ebc4cda BH |
214 | #ifdef __DISABLED__ |
215 | /* Keep that around for when we re-implement dynamic VSIDs */ | |
216 | cmpdi r3,0 | |
217 | bge slb_miss_user_pseries | |
218 | #endif /* __DISABLED__ */ | |
b01c8b54 | 219 | mfspr r12,SPRN_SRR1 |
0ebc4cda BH |
220 | #ifndef CONFIG_RELOCATABLE |
221 | b .slb_miss_realmode | |
222 | #else | |
223 | mfctr r11 | |
224 | ld r10,PACAKBASE(r13) | |
225 | LOAD_HANDLER(r10, .slb_miss_realmode) | |
226 | mtctr r10 | |
227 | bctr | |
228 | #endif | |
229 | ||
b3e6b5df BH |
230 | /* We open code these as we can't have a ". = x" (even with |
231 | * x = "." within a feature section | |
232 | */ | |
a5d4f3ad | 233 | . = 0x500; |
b3e6b5df BH |
234 | .globl hardware_interrupt_pSeries; |
235 | .globl hardware_interrupt_hv; | |
a5d4f3ad | 236 | hardware_interrupt_pSeries: |
b3e6b5df | 237 | hardware_interrupt_hv: |
a485c709 | 238 | HMT_MEDIUM_PPR_DISCARD |
a5d4f3ad | 239 | BEGIN_FTR_SECTION |
b01c8b54 PM |
240 | _MASKABLE_EXCEPTION_PSERIES(0x502, hardware_interrupt, |
241 | EXC_HV, SOFTEN_TEST_HV) | |
242 | KVM_HANDLER(PACA_EXGEN, EXC_HV, 0x502) | |
de56a948 PM |
243 | FTR_SECTION_ELSE |
244 | _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt, | |
9e368f29 | 245 | EXC_STD, SOFTEN_TEST_HV_201) |
de56a948 | 246 | KVM_HANDLER(PACA_EXGEN, EXC_STD, 0x500) |
969391c5 | 247 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) |
a5d4f3ad | 248 | |
b3e6b5df | 249 | STD_EXCEPTION_PSERIES(0x600, 0x600, alignment) |
de56a948 | 250 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0x600) |
b01c8b54 | 251 | |
b3e6b5df | 252 | STD_EXCEPTION_PSERIES(0x700, 0x700, program_check) |
de56a948 | 253 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0x700) |
b01c8b54 | 254 | |
b3e6b5df | 255 | STD_EXCEPTION_PSERIES(0x800, 0x800, fp_unavailable) |
de56a948 | 256 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0x800) |
a5d4f3ad | 257 | |
a485c709 PM |
258 | . = 0x900 |
259 | .globl decrementer_pSeries | |
260 | decrementer_pSeries: | |
261 | _MASKABLE_EXCEPTION_PSERIES(0x900, decrementer, EXC_STD, SOFTEN_TEST_PR) | |
262 | ||
dabe859e | 263 | STD_EXCEPTION_HV(0x980, 0x982, hdecrementer) |
a5d4f3ad | 264 | |
1dbdafec | 265 | MASKABLE_EXCEPTION_PSERIES(0xa00, 0xa00, doorbell_super) |
de56a948 | 266 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0xa00) |
b01c8b54 | 267 | |
b3e6b5df | 268 | STD_EXCEPTION_PSERIES(0xb00, 0xb00, trap_0b) |
de56a948 | 269 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0xb00) |
0ebc4cda BH |
270 | |
271 | . = 0xc00 | |
272 | .globl system_call_pSeries | |
273 | system_call_pSeries: | |
274 | HMT_MEDIUM | |
b01c8b54 PM |
275 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER |
276 | SET_SCRATCH0(r13) | |
277 | GET_PACA(r13) | |
278 | std r9,PACA_EXGEN+EX_R9(r13) | |
279 | std r10,PACA_EXGEN+EX_R10(r13) | |
280 | mfcr r9 | |
281 | KVMTEST(0xc00) | |
282 | GET_SCRATCH0(r13) | |
283 | #endif | |
742415d6 MN |
284 | SYSCALL_PSERIES_1 |
285 | SYSCALL_PSERIES_2_RFID | |
286 | SYSCALL_PSERIES_3 | |
b01c8b54 PM |
287 | KVM_HANDLER(PACA_EXGEN, EXC_STD, 0xc00) |
288 | ||
b3e6b5df | 289 | STD_EXCEPTION_PSERIES(0xd00, 0xd00, single_step) |
de56a948 | 290 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0xd00) |
b3e6b5df BH |
291 | |
292 | /* At 0xe??? we have a bunch of hypervisor exceptions, we branch | |
293 | * out of line to handle them | |
294 | */ | |
295 | . = 0xe00 | |
e6a74c6e | 296 | hv_exception_trampoline: |
1707dd16 PM |
297 | SET_SCRATCH0(r13) |
298 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
b3e6b5df | 299 | b h_data_storage_hv |
1707dd16 | 300 | |
b3e6b5df | 301 | . = 0xe20 |
1707dd16 PM |
302 | SET_SCRATCH0(r13) |
303 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
b3e6b5df | 304 | b h_instr_storage_hv |
1707dd16 | 305 | |
b3e6b5df | 306 | . = 0xe40 |
1707dd16 PM |
307 | SET_SCRATCH0(r13) |
308 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
b3e6b5df | 309 | b emulation_assist_hv |
1707dd16 | 310 | |
b3e6b5df | 311 | . = 0xe60 |
1707dd16 PM |
312 | SET_SCRATCH0(r13) |
313 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
b3e6b5df | 314 | b hmi_exception_hv |
1707dd16 | 315 | |
655bb3f4 | 316 | . = 0xe80 |
1707dd16 PM |
317 | SET_SCRATCH0(r13) |
318 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
655bb3f4 | 319 | b h_doorbell_hv |
0ebc4cda BH |
320 | |
321 | /* We need to deal with the Altivec unavailable exception | |
322 | * here which is at 0xf20, thus in the middle of the | |
323 | * prolog code of the PerformanceMonitor one. A little | |
324 | * trickery is thus necessary | |
325 | */ | |
c86e2ead | 326 | performance_monitor_pSeries_1: |
0ebc4cda | 327 | . = 0xf00 |
1707dd16 PM |
328 | SET_SCRATCH0(r13) |
329 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
0ebc4cda BH |
330 | b performance_monitor_pSeries |
331 | ||
c86e2ead | 332 | altivec_unavailable_pSeries_1: |
0ebc4cda | 333 | . = 0xf20 |
1707dd16 PM |
334 | SET_SCRATCH0(r13) |
335 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
0ebc4cda BH |
336 | b altivec_unavailable_pSeries |
337 | ||
c86e2ead | 338 | vsx_unavailable_pSeries_1: |
0ebc4cda | 339 | . = 0xf40 |
1707dd16 PM |
340 | SET_SCRATCH0(r13) |
341 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
0ebc4cda BH |
342 | b vsx_unavailable_pSeries |
343 | ||
d0c0c9a1 MN |
344 | . = 0xf60 |
345 | SET_SCRATCH0(r13) | |
346 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
347 | b tm_unavailable_pSeries | |
348 | ||
0ebc4cda | 349 | #ifdef CONFIG_CBE_RAS |
b3e6b5df | 350 | STD_EXCEPTION_HV(0x1200, 0x1202, cbe_system_error) |
5ccf55dd | 351 | KVM_HANDLER_SKIP(PACA_EXGEN, EXC_HV, 0x1202) |
0ebc4cda | 352 | #endif /* CONFIG_CBE_RAS */ |
b01c8b54 | 353 | |
b3e6b5df | 354 | STD_EXCEPTION_PSERIES(0x1300, 0x1300, instruction_breakpoint) |
de56a948 | 355 | KVM_HANDLER_PR_SKIP(PACA_EXGEN, EXC_STD, 0x1300) |
b01c8b54 | 356 | |
b92a66a6 | 357 | . = 0x1500 |
51cf2b30 | 358 | .global denorm_exception_hv |
b92a66a6 | 359 | denorm_exception_hv: |
44e9309f | 360 | HMT_MEDIUM_PPR_DISCARD |
b92a66a6 | 361 | mtspr SPRN_SPRG_HSCRATCH0,r13 |
1707dd16 | 362 | EXCEPTION_PROLOG_0(PACA_EXGEN) |
b92a66a6 MN |
363 | std r11,PACA_EXGEN+EX_R11(r13) |
364 | std r12,PACA_EXGEN+EX_R12(r13) | |
365 | mfspr r9,SPRN_SPRG_HSCRATCH0 | |
366 | std r9,PACA_EXGEN+EX_R13(r13) | |
367 | mfcr r9 | |
368 | ||
369 | #ifdef CONFIG_PPC_DENORMALISATION | |
370 | mfspr r10,SPRN_HSRR1 | |
371 | mfspr r11,SPRN_HSRR0 /* save HSRR0 */ | |
372 | andis. r10,r10,(HSRR1_DENORM)@h /* denorm? */ | |
373 | addi r11,r11,-4 /* HSRR0 is next instruction */ | |
374 | bne+ denorm_assist | |
375 | #endif | |
376 | ||
377 | EXCEPTION_PROLOG_PSERIES_1(denorm_common, EXC_HV) | |
378 | KVM_HANDLER_SKIP(PACA_EXGEN, EXC_STD, 0x1500) | |
379 | ||
0ebc4cda | 380 | #ifdef CONFIG_CBE_RAS |
b3e6b5df | 381 | STD_EXCEPTION_HV(0x1600, 0x1602, cbe_maintenance) |
5ccf55dd | 382 | KVM_HANDLER_SKIP(PACA_EXGEN, EXC_HV, 0x1602) |
0ebc4cda | 383 | #endif /* CONFIG_CBE_RAS */ |
b01c8b54 | 384 | |
b3e6b5df | 385 | STD_EXCEPTION_PSERIES(0x1700, 0x1700, altivec_assist) |
de56a948 | 386 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0x1700) |
b01c8b54 | 387 | |
0ebc4cda | 388 | #ifdef CONFIG_CBE_RAS |
b3e6b5df | 389 | STD_EXCEPTION_HV(0x1800, 0x1802, cbe_thermal) |
5ccf55dd | 390 | KVM_HANDLER_SKIP(PACA_EXGEN, EXC_HV, 0x1802) |
faab4dd2 MN |
391 | #else |
392 | . = 0x1800 | |
0ebc4cda BH |
393 | #endif /* CONFIG_CBE_RAS */ |
394 | ||
0ebc4cda | 395 | |
b3e6b5df BH |
396 | /*** Out of line interrupts support ***/ |
397 | ||
faab4dd2 | 398 | .align 7 |
b01c8b54 PM |
399 | /* moved from 0x200 */ |
400 | machine_check_pSeries: | |
401 | .globl machine_check_fwnmi | |
402 | machine_check_fwnmi: | |
44e9309f | 403 | HMT_MEDIUM_PPR_DISCARD |
b01c8b54 | 404 | SET_SCRATCH0(r13) /* save r13 */ |
1707dd16 PM |
405 | EXCEPTION_PROLOG_0(PACA_EXMC) |
406 | machine_check_pSeries_0: | |
407 | EXCEPTION_PROLOG_1(PACA_EXMC, KVMTEST, 0x200) | |
408 | EXCEPTION_PROLOG_PSERIES_1(machine_check_common, EXC_STD) | |
b01c8b54 PM |
409 | KVM_HANDLER_SKIP(PACA_EXMC, EXC_STD, 0x200) |
410 | ||
b01c8b54 PM |
411 | /* moved from 0x300 */ |
412 | data_access_check_stab: | |
413 | GET_PACA(r13) | |
414 | std r9,PACA_EXSLB+EX_R9(r13) | |
415 | std r10,PACA_EXSLB+EX_R10(r13) | |
416 | mfspr r10,SPRN_DAR | |
417 | mfspr r9,SPRN_DSISR | |
418 | srdi r10,r10,60 | |
419 | rlwimi r10,r9,16,0x20 | |
de56a948 | 420 | #ifdef CONFIG_KVM_BOOK3S_PR |
3c42bf8a | 421 | lbz r9,HSTATE_IN_GUEST(r13) |
b01c8b54 PM |
422 | rlwimi r10,r9,8,0x300 |
423 | #endif | |
424 | mfcr r9 | |
425 | cmpwi r10,0x2c | |
426 | beq do_stab_bolted_pSeries | |
427 | mtcrf 0x80,r9 | |
428 | ld r9,PACA_EXSLB+EX_R9(r13) | |
429 | ld r10,PACA_EXSLB+EX_R10(r13) | |
430 | b data_access_not_stab | |
431 | do_stab_bolted_pSeries: | |
432 | std r11,PACA_EXSLB+EX_R11(r13) | |
433 | std r12,PACA_EXSLB+EX_R12(r13) | |
434 | GET_SCRATCH0(r10) | |
435 | std r10,PACA_EXSLB+EX_R13(r13) | |
436 | EXCEPTION_PROLOG_PSERIES_1(.do_stab_bolted, EXC_STD) | |
b01c8b54 | 437 | |
697d3899 PM |
438 | KVM_HANDLER_SKIP(PACA_EXGEN, EXC_STD, 0x300) |
439 | KVM_HANDLER_SKIP(PACA_EXSLB, EXC_STD, 0x380) | |
de56a948 PM |
440 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0x400) |
441 | KVM_HANDLER_PR(PACA_EXSLB, EXC_STD, 0x480) | |
442 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0x900) | |
b01c8b54 PM |
443 | KVM_HANDLER(PACA_EXGEN, EXC_HV, 0x982) |
444 | ||
b92a66a6 MN |
445 | #ifdef CONFIG_PPC_DENORMALISATION |
446 | denorm_assist: | |
447 | BEGIN_FTR_SECTION | |
448 | /* | |
449 | * To denormalise we need to move a copy of the register to itself. | |
450 | * For POWER6 do that here for all FP regs. | |
451 | */ | |
452 | mfmsr r10 | |
453 | ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1) | |
454 | xori r10,r10,(MSR_FE0|MSR_FE1) | |
455 | mtmsrd r10 | |
456 | sync | |
d7c67fb1 MN |
457 | |
458 | #define FMR2(n) fmr (n), (n) ; fmr n+1, n+1 | |
459 | #define FMR4(n) FMR2(n) ; FMR2(n+2) | |
460 | #define FMR8(n) FMR4(n) ; FMR4(n+4) | |
461 | #define FMR16(n) FMR8(n) ; FMR8(n+8) | |
462 | #define FMR32(n) FMR16(n) ; FMR16(n+16) | |
463 | FMR32(0) | |
464 | ||
b92a66a6 MN |
465 | FTR_SECTION_ELSE |
466 | /* | |
467 | * To denormalise we need to move a copy of the register to itself. | |
468 | * For POWER7 do that here for the first 32 VSX registers only. | |
469 | */ | |
470 | mfmsr r10 | |
471 | oris r10,r10,MSR_VSX@h | |
472 | mtmsrd r10 | |
473 | sync | |
d7c67fb1 MN |
474 | |
475 | #define XVCPSGNDP2(n) XVCPSGNDP(n,n,n) ; XVCPSGNDP(n+1,n+1,n+1) | |
476 | #define XVCPSGNDP4(n) XVCPSGNDP2(n) ; XVCPSGNDP2(n+2) | |
477 | #define XVCPSGNDP8(n) XVCPSGNDP4(n) ; XVCPSGNDP4(n+4) | |
478 | #define XVCPSGNDP16(n) XVCPSGNDP8(n) ; XVCPSGNDP8(n+8) | |
479 | #define XVCPSGNDP32(n) XVCPSGNDP16(n) ; XVCPSGNDP16(n+16) | |
480 | XVCPSGNDP32(0) | |
481 | ||
b92a66a6 MN |
482 | ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206) |
483 | mtspr SPRN_HSRR0,r11 | |
484 | mtcrf 0x80,r9 | |
485 | ld r9,PACA_EXGEN+EX_R9(r13) | |
44e9309f | 486 | RESTORE_PPR_PACA(PACA_EXGEN, r10) |
b92a66a6 MN |
487 | ld r10,PACA_EXGEN+EX_R10(r13) |
488 | ld r11,PACA_EXGEN+EX_R11(r13) | |
489 | ld r12,PACA_EXGEN+EX_R12(r13) | |
490 | ld r13,PACA_EXGEN+EX_R13(r13) | |
491 | HRFID | |
492 | b . | |
493 | #endif | |
494 | ||
b01c8b54 | 495 | .align 7 |
b3e6b5df | 496 | /* moved from 0xe00 */ |
1707dd16 | 497 | STD_EXCEPTION_HV_OOL(0xe02, h_data_storage) |
b01c8b54 | 498 | KVM_HANDLER_SKIP(PACA_EXGEN, EXC_HV, 0xe02) |
1707dd16 | 499 | STD_EXCEPTION_HV_OOL(0xe22, h_instr_storage) |
b01c8b54 | 500 | KVM_HANDLER(PACA_EXGEN, EXC_HV, 0xe22) |
1707dd16 | 501 | STD_EXCEPTION_HV_OOL(0xe42, emulation_assist) |
b01c8b54 | 502 | KVM_HANDLER(PACA_EXGEN, EXC_HV, 0xe42) |
1707dd16 | 503 | STD_EXCEPTION_HV_OOL(0xe62, hmi_exception) /* need to flush cache ? */ |
b01c8b54 | 504 | KVM_HANDLER(PACA_EXGEN, EXC_HV, 0xe62) |
1707dd16 | 505 | MASKABLE_EXCEPTION_HV_OOL(0xe82, h_doorbell) |
655bb3f4 | 506 | KVM_HANDLER(PACA_EXGEN, EXC_HV, 0xe82) |
0ebc4cda BH |
507 | |
508 | /* moved from 0xf00 */ | |
1707dd16 | 509 | STD_EXCEPTION_PSERIES_OOL(0xf00, performance_monitor) |
de56a948 | 510 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0xf00) |
1707dd16 | 511 | STD_EXCEPTION_PSERIES_OOL(0xf20, altivec_unavailable) |
de56a948 | 512 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0xf20) |
1707dd16 | 513 | STD_EXCEPTION_PSERIES_OOL(0xf40, vsx_unavailable) |
de56a948 | 514 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0xf40) |
d0c0c9a1 MN |
515 | STD_EXCEPTION_PSERIES_OOL(0xf60, tm_unavailable) |
516 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0xf60) | |
0ebc4cda BH |
517 | |
518 | /* | |
fe9e1d54 IM |
519 | * An interrupt came in while soft-disabled. We set paca->irq_happened, then: |
520 | * - If it was a decrementer interrupt, we bump the dec to max and and return. | |
521 | * - If it was a doorbell we return immediately since doorbells are edge | |
522 | * triggered and won't automatically refire. | |
523 | * - else we hard disable and return. | |
524 | * This is called with r10 containing the value to OR to the paca field. | |
0ebc4cda | 525 | */ |
7230c564 BH |
526 | #define MASKED_INTERRUPT(_H) \ |
527 | masked_##_H##interrupt: \ | |
528 | std r11,PACA_EXGEN+EX_R11(r13); \ | |
529 | lbz r11,PACAIRQHAPPENED(r13); \ | |
530 | or r11,r11,r10; \ | |
531 | stb r11,PACAIRQHAPPENED(r13); \ | |
fe9e1d54 IM |
532 | cmpwi r10,PACA_IRQ_DEC; \ |
533 | bne 1f; \ | |
7230c564 BH |
534 | lis r10,0x7fff; \ |
535 | ori r10,r10,0xffff; \ | |
536 | mtspr SPRN_DEC,r10; \ | |
537 | b 2f; \ | |
fe9e1d54 IM |
538 | 1: cmpwi r10,PACA_IRQ_DBELL; \ |
539 | beq 2f; \ | |
540 | mfspr r10,SPRN_##_H##SRR1; \ | |
7230c564 BH |
541 | rldicl r10,r10,48,1; /* clear MSR_EE */ \ |
542 | rotldi r10,r10,16; \ | |
543 | mtspr SPRN_##_H##SRR1,r10; \ | |
544 | 2: mtcrf 0x80,r9; \ | |
545 | ld r9,PACA_EXGEN+EX_R9(r13); \ | |
546 | ld r10,PACA_EXGEN+EX_R10(r13); \ | |
547 | ld r11,PACA_EXGEN+EX_R11(r13); \ | |
548 | GET_SCRATCH0(r13); \ | |
549 | ##_H##rfid; \ | |
0ebc4cda | 550 | b . |
7230c564 BH |
551 | |
552 | MASKED_INTERRUPT() | |
553 | MASKED_INTERRUPT(H) | |
0ebc4cda | 554 | |
7230c564 BH |
555 | /* |
556 | * Called from arch_local_irq_enable when an interrupt needs | |
fe9e1d54 IM |
557 | * to be resent. r3 contains 0x500, 0x900, 0xa00 or 0xe80 to indicate |
558 | * which kind of interrupt. MSR:EE is already off. We generate a | |
7230c564 BH |
559 | * stackframe like if a real interrupt had happened. |
560 | * | |
561 | * Note: While MSR:EE is off, we need to make sure that _MSR | |
562 | * in the generated frame has EE set to 1 or the exception | |
563 | * handler will not properly re-enable them. | |
564 | */ | |
565 | _GLOBAL(__replay_interrupt) | |
566 | /* We are going to jump to the exception common code which | |
567 | * will retrieve various register values from the PACA which | |
568 | * we don't give a damn about, so we don't bother storing them. | |
569 | */ | |
570 | mfmsr r12 | |
571 | mflr r11 | |
572 | mfcr r9 | |
573 | ori r12,r12,MSR_EE | |
fe9e1d54 IM |
574 | cmpwi r3,0x900 |
575 | beq decrementer_common | |
576 | cmpwi r3,0x500 | |
577 | beq hardware_interrupt_common | |
578 | BEGIN_FTR_SECTION | |
579 | cmpwi r3,0xe80 | |
580 | beq h_doorbell_common | |
581 | FTR_SECTION_ELSE | |
582 | cmpwi r3,0xa00 | |
583 | beq doorbell_super_common | |
584 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) | |
585 | blr | |
a5d4f3ad | 586 | |
0ebc4cda BH |
587 | #ifdef CONFIG_PPC_PSERIES |
588 | /* | |
589 | * Vectors for the FWNMI option. Share common code. | |
590 | */ | |
591 | .globl system_reset_fwnmi | |
592 | .align 7 | |
593 | system_reset_fwnmi: | |
44e9309f | 594 | HMT_MEDIUM_PPR_DISCARD |
673b189a | 595 | SET_SCRATCH0(r13) /* save r13 */ |
b01c8b54 PM |
596 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD, |
597 | NOTEST, 0x100) | |
0ebc4cda BH |
598 | |
599 | #endif /* CONFIG_PPC_PSERIES */ | |
600 | ||
601 | #ifdef __DISABLED__ | |
602 | /* | |
603 | * This is used for when the SLB miss handler has to go virtual, | |
604 | * which doesn't happen for now anymore but will once we re-implement | |
605 | * dynamic VSIDs for shared page tables | |
606 | */ | |
607 | slb_miss_user_pseries: | |
608 | std r10,PACA_EXGEN+EX_R10(r13) | |
609 | std r11,PACA_EXGEN+EX_R11(r13) | |
610 | std r12,PACA_EXGEN+EX_R12(r13) | |
673b189a | 611 | GET_SCRATCH0(r10) |
0ebc4cda BH |
612 | ld r11,PACA_EXSLB+EX_R9(r13) |
613 | ld r12,PACA_EXSLB+EX_R3(r13) | |
614 | std r10,PACA_EXGEN+EX_R13(r13) | |
615 | std r11,PACA_EXGEN+EX_R9(r13) | |
616 | std r12,PACA_EXGEN+EX_R3(r13) | |
617 | clrrdi r12,r13,32 | |
618 | mfmsr r10 | |
619 | mfspr r11,SRR0 /* save SRR0 */ | |
620 | ori r12,r12,slb_miss_user_common@l /* virt addr of handler */ | |
621 | ori r10,r10,MSR_IR|MSR_DR|MSR_RI | |
622 | mtspr SRR0,r12 | |
623 | mfspr r12,SRR1 /* and SRR1 */ | |
624 | mtspr SRR1,r10 | |
625 | rfid | |
626 | b . /* prevent spec. execution */ | |
627 | #endif /* __DISABLED__ */ | |
628 | ||
0ebc4cda BH |
629 | /* |
630 | * Code from here down to __end_handlers is invoked from the | |
631 | * exception prologs above. Because the prologs assemble the | |
632 | * addresses of these handlers using the LOAD_HANDLER macro, | |
61e2390e MN |
633 | * which uses an ori instruction, these handlers must be in |
634 | * the first 64k of the kernel image. | |
0ebc4cda BH |
635 | */ |
636 | ||
637 | /*** Common interrupt handlers ***/ | |
638 | ||
639 | STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception) | |
640 | ||
641 | /* | |
642 | * Machine check is different because we use a different | |
643 | * save area: PACA_EXMC instead of PACA_EXGEN. | |
644 | */ | |
645 | .align 7 | |
646 | .globl machine_check_common | |
647 | machine_check_common: | |
ce54152f AK |
648 | |
649 | mfspr r10,SPRN_DAR | |
650 | std r10,PACA_EXGEN+EX_DAR(r13) | |
651 | mfspr r10,SPRN_DSISR | |
652 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
0ebc4cda BH |
653 | EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC) |
654 | FINISH_NAP | |
655 | DISABLE_INTS | |
ce54152f AK |
656 | ld r3,PACA_EXGEN+EX_DAR(r13) |
657 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | |
658 | std r3,_DAR(r1) | |
659 | std r4,_DSISR(r1) | |
0ebc4cda BH |
660 | bl .save_nvgprs |
661 | addi r3,r1,STACK_FRAME_OVERHEAD | |
662 | bl .machine_check_exception | |
663 | b .ret_from_except | |
664 | ||
7450f6f0 BH |
665 | STD_EXCEPTION_COMMON_ASYNC(0x500, hardware_interrupt, do_IRQ) |
666 | STD_EXCEPTION_COMMON_ASYNC(0x900, decrementer, .timer_interrupt) | |
dabe859e | 667 | STD_EXCEPTION_COMMON(0x980, hdecrementer, .hdec_interrupt) |
1dbdafec IM |
668 | #ifdef CONFIG_PPC_DOORBELL |
669 | STD_EXCEPTION_COMMON_ASYNC(0xa00, doorbell_super, .doorbell_exception) | |
670 | #else | |
671 | STD_EXCEPTION_COMMON_ASYNC(0xa00, doorbell_super, .unknown_exception) | |
672 | #endif | |
0ebc4cda BH |
673 | STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception) |
674 | STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception) | |
675 | STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception) | |
278a6cdc MN |
676 | STD_EXCEPTION_COMMON(0xe40, emulation_assist, .program_check_exception) |
677 | STD_EXCEPTION_COMMON(0xe60, hmi_exception, .unknown_exception) | |
655bb3f4 IM |
678 | #ifdef CONFIG_PPC_DOORBELL |
679 | STD_EXCEPTION_COMMON_ASYNC(0xe80, h_doorbell, .doorbell_exception) | |
680 | #else | |
681 | STD_EXCEPTION_COMMON_ASYNC(0xe80, h_doorbell, .unknown_exception) | |
682 | #endif | |
7450f6f0 | 683 | STD_EXCEPTION_COMMON_ASYNC(0xf00, performance_monitor, .performance_monitor_exception) |
0ebc4cda | 684 | STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception) |
b92a66a6 | 685 | STD_EXCEPTION_COMMON(0x1502, denorm, .unknown_exception) |
0ebc4cda BH |
686 | #ifdef CONFIG_ALTIVEC |
687 | STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception) | |
688 | #else | |
689 | STD_EXCEPTION_COMMON(0x1700, altivec_assist, .unknown_exception) | |
690 | #endif | |
691 | #ifdef CONFIG_CBE_RAS | |
692 | STD_EXCEPTION_COMMON(0x1200, cbe_system_error, .cbe_system_error_exception) | |
693 | STD_EXCEPTION_COMMON(0x1600, cbe_maintenance, .cbe_maintenance_exception) | |
694 | STD_EXCEPTION_COMMON(0x1800, cbe_thermal, .cbe_thermal_exception) | |
695 | #endif /* CONFIG_CBE_RAS */ | |
696 | ||
c1fb6816 MN |
697 | /* |
698 | * Relocation-on interrupts: A subset of the interrupts can be delivered | |
699 | * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering | |
700 | * it. Addresses are the same as the original interrupt addresses, but | |
701 | * offset by 0xc000000000004000. | |
702 | * It's impossible to receive interrupts below 0x300 via this mechanism. | |
703 | * KVM: None of these traps are from the guest ; anything that escalated | |
704 | * to HV=1 from HV=0 is delivered via real mode handlers. | |
705 | */ | |
706 | ||
707 | /* | |
708 | * This uses the standard macro, since the original 0x300 vector | |
709 | * only has extra guff for STAB-based processors -- which never | |
710 | * come here. | |
711 | */ | |
712 | STD_RELON_EXCEPTION_PSERIES(0x4300, 0x300, data_access) | |
713 | . = 0x4380 | |
714 | .globl data_access_slb_relon_pSeries | |
715 | data_access_slb_relon_pSeries: | |
c1fb6816 | 716 | SET_SCRATCH0(r13) |
1707dd16 | 717 | EXCEPTION_PROLOG_0(PACA_EXSLB) |
c1fb6816 MN |
718 | EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x380) |
719 | std r3,PACA_EXSLB+EX_R3(r13) | |
720 | mfspr r3,SPRN_DAR | |
721 | mfspr r12,SPRN_SRR1 | |
722 | #ifndef CONFIG_RELOCATABLE | |
723 | b .slb_miss_realmode | |
724 | #else | |
725 | /* | |
726 | * We can't just use a direct branch to .slb_miss_realmode | |
727 | * because the distance from here to there depends on where | |
728 | * the kernel ends up being put. | |
729 | */ | |
730 | mfctr r11 | |
731 | ld r10,PACAKBASE(r13) | |
732 | LOAD_HANDLER(r10, .slb_miss_realmode) | |
733 | mtctr r10 | |
734 | bctr | |
735 | #endif | |
736 | ||
737 | STD_RELON_EXCEPTION_PSERIES(0x4400, 0x400, instruction_access) | |
738 | . = 0x4480 | |
739 | .globl instruction_access_slb_relon_pSeries | |
740 | instruction_access_slb_relon_pSeries: | |
c1fb6816 | 741 | SET_SCRATCH0(r13) |
1707dd16 | 742 | EXCEPTION_PROLOG_0(PACA_EXSLB) |
c1fb6816 MN |
743 | EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x480) |
744 | std r3,PACA_EXSLB+EX_R3(r13) | |
745 | mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ | |
746 | mfspr r12,SPRN_SRR1 | |
747 | #ifndef CONFIG_RELOCATABLE | |
748 | b .slb_miss_realmode | |
749 | #else | |
750 | mfctr r11 | |
751 | ld r10,PACAKBASE(r13) | |
752 | LOAD_HANDLER(r10, .slb_miss_realmode) | |
753 | mtctr r10 | |
754 | bctr | |
755 | #endif | |
756 | ||
757 | . = 0x4500 | |
758 | .globl hardware_interrupt_relon_pSeries; | |
759 | .globl hardware_interrupt_relon_hv; | |
760 | hardware_interrupt_relon_pSeries: | |
761 | hardware_interrupt_relon_hv: | |
762 | BEGIN_FTR_SECTION | |
763 | _MASKABLE_RELON_EXCEPTION_PSERIES(0x502, hardware_interrupt, EXC_HV, SOFTEN_TEST_HV) | |
764 | FTR_SECTION_ELSE | |
765 | _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt, EXC_STD, SOFTEN_TEST_PR) | |
3e96ca7f | 766 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) |
c1fb6816 MN |
767 | STD_RELON_EXCEPTION_PSERIES(0x4600, 0x600, alignment) |
768 | STD_RELON_EXCEPTION_PSERIES(0x4700, 0x700, program_check) | |
769 | STD_RELON_EXCEPTION_PSERIES(0x4800, 0x800, fp_unavailable) | |
770 | MASKABLE_RELON_EXCEPTION_PSERIES(0x4900, 0x900, decrementer) | |
771 | STD_RELON_EXCEPTION_HV(0x4980, 0x982, hdecrementer) | |
1dbdafec | 772 | MASKABLE_RELON_EXCEPTION_PSERIES(0x4a00, 0xa00, doorbell_super) |
c1fb6816 MN |
773 | STD_RELON_EXCEPTION_PSERIES(0x4b00, 0xb00, trap_0b) |
774 | ||
775 | . = 0x4c00 | |
776 | .globl system_call_relon_pSeries | |
777 | system_call_relon_pSeries: | |
778 | HMT_MEDIUM | |
779 | SYSCALL_PSERIES_1 | |
780 | SYSCALL_PSERIES_2_DIRECT | |
781 | SYSCALL_PSERIES_3 | |
782 | ||
783 | STD_RELON_EXCEPTION_PSERIES(0x4d00, 0xd00, single_step) | |
784 | ||
785 | . = 0x4e00 | |
1707dd16 PM |
786 | SET_SCRATCH0(r13) |
787 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
c1fb6816 MN |
788 | b h_data_storage_relon_hv |
789 | ||
790 | . = 0x4e20 | |
1707dd16 PM |
791 | SET_SCRATCH0(r13) |
792 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
c1fb6816 MN |
793 | b h_instr_storage_relon_hv |
794 | ||
795 | . = 0x4e40 | |
1707dd16 PM |
796 | SET_SCRATCH0(r13) |
797 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
c1fb6816 MN |
798 | b emulation_assist_relon_hv |
799 | ||
c1fb6816 | 800 | . = 0x4e60 |
1707dd16 PM |
801 | SET_SCRATCH0(r13) |
802 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
c1fb6816 MN |
803 | b hmi_exception_relon_hv |
804 | ||
655bb3f4 | 805 | . = 0x4e80 |
1707dd16 PM |
806 | SET_SCRATCH0(r13) |
807 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
655bb3f4 | 808 | b h_doorbell_relon_hv |
c1fb6816 MN |
809 | |
810 | performance_monitor_relon_pSeries_1: | |
811 | . = 0x4f00 | |
1707dd16 PM |
812 | SET_SCRATCH0(r13) |
813 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
c1fb6816 MN |
814 | b performance_monitor_relon_pSeries |
815 | ||
816 | altivec_unavailable_relon_pSeries_1: | |
817 | . = 0x4f20 | |
1707dd16 PM |
818 | SET_SCRATCH0(r13) |
819 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
c1fb6816 MN |
820 | b altivec_unavailable_relon_pSeries |
821 | ||
822 | vsx_unavailable_relon_pSeries_1: | |
823 | . = 0x4f40 | |
1707dd16 PM |
824 | SET_SCRATCH0(r13) |
825 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
c1fb6816 MN |
826 | b vsx_unavailable_relon_pSeries |
827 | ||
d0c0c9a1 MN |
828 | tm_unavailable_relon_pSeries_1: |
829 | . = 0x4f60 | |
830 | SET_SCRATCH0(r13) | |
831 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
832 | b tm_unavailable_relon_pSeries | |
833 | ||
c1fb6816 MN |
834 | STD_RELON_EXCEPTION_PSERIES(0x5300, 0x1300, instruction_breakpoint) |
835 | #ifdef CONFIG_PPC_DENORMALISATION | |
836 | . = 0x5500 | |
837 | b denorm_exception_hv | |
838 | #endif | |
c1fb6816 | 839 | STD_RELON_EXCEPTION_PSERIES(0x5700, 0x1700, altivec_assist) |
c1fb6816 MN |
840 | |
841 | /* Other future vectors */ | |
842 | .align 7 | |
843 | .globl __end_interrupts | |
844 | __end_interrupts: | |
845 | ||
0ebc4cda | 846 | .align 7 |
c1fb6816 MN |
847 | system_call_entry_direct: |
848 | #if defined(CONFIG_RELOCATABLE) | |
849 | /* The first level prologue may have used LR to get here, saving | |
850 | * orig in r10. To save hacking/ifdeffing common code, restore here. | |
851 | */ | |
852 | mtlr r10 | |
853 | #endif | |
0ebc4cda BH |
854 | system_call_entry: |
855 | b system_call_common | |
856 | ||
fe1952fc BH |
857 | ppc64_runlatch_on_trampoline: |
858 | b .__ppc64_runlatch_on | |
859 | ||
0ebc4cda BH |
860 | /* |
861 | * Here we have detected that the kernel stack pointer is bad. | |
862 | * R9 contains the saved CR, r13 points to the paca, | |
863 | * r10 contains the (bad) kernel stack pointer, | |
864 | * r11 and r12 contain the saved SRR0 and SRR1. | |
865 | * We switch to using an emergency stack, save the registers there, | |
866 | * and call kernel_bad_stack(), which panics. | |
867 | */ | |
868 | bad_stack: | |
869 | ld r1,PACAEMERGSP(r13) | |
870 | subi r1,r1,64+INT_FRAME_SIZE | |
871 | std r9,_CCR(r1) | |
872 | std r10,GPR1(r1) | |
873 | std r11,_NIP(r1) | |
874 | std r12,_MSR(r1) | |
875 | mfspr r11,SPRN_DAR | |
876 | mfspr r12,SPRN_DSISR | |
877 | std r11,_DAR(r1) | |
878 | std r12,_DSISR(r1) | |
879 | mflr r10 | |
880 | mfctr r11 | |
881 | mfxer r12 | |
882 | std r10,_LINK(r1) | |
883 | std r11,_CTR(r1) | |
884 | std r12,_XER(r1) | |
885 | SAVE_GPR(0,r1) | |
886 | SAVE_GPR(2,r1) | |
1977b502 PM |
887 | ld r10,EX_R3(r3) |
888 | std r10,GPR3(r1) | |
889 | SAVE_GPR(4,r1) | |
890 | SAVE_4GPRS(5,r1) | |
891 | ld r9,EX_R9(r3) | |
892 | ld r10,EX_R10(r3) | |
893 | SAVE_2GPRS(9,r1) | |
894 | ld r9,EX_R11(r3) | |
895 | ld r10,EX_R12(r3) | |
896 | ld r11,EX_R13(r3) | |
897 | std r9,GPR11(r1) | |
898 | std r10,GPR12(r1) | |
899 | std r11,GPR13(r1) | |
48404f2e PM |
900 | BEGIN_FTR_SECTION |
901 | ld r10,EX_CFAR(r3) | |
902 | std r10,ORIG_GPR3(r1) | |
903 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) | |
1977b502 | 904 | SAVE_8GPRS(14,r1) |
0ebc4cda BH |
905 | SAVE_10GPRS(22,r1) |
906 | lhz r12,PACA_TRAP_SAVE(r13) | |
907 | std r12,_TRAP(r1) | |
908 | addi r11,r1,INT_FRAME_SIZE | |
909 | std r11,0(r1) | |
910 | li r12,0 | |
911 | std r12,0(r11) | |
912 | ld r2,PACATOC(r13) | |
1977b502 PM |
913 | ld r11,exception_marker@toc(r2) |
914 | std r12,RESULT(r1) | |
915 | std r11,STACK_FRAME_OVERHEAD-16(r1) | |
0ebc4cda BH |
916 | 1: addi r3,r1,STACK_FRAME_OVERHEAD |
917 | bl .kernel_bad_stack | |
918 | b 1b | |
919 | ||
920 | /* | |
921 | * Here r13 points to the paca, r9 contains the saved CR, | |
922 | * SRR0 and SRR1 are saved in r11 and r12, | |
923 | * r9 - r13 are saved in paca->exgen. | |
924 | */ | |
925 | .align 7 | |
926 | .globl data_access_common | |
927 | data_access_common: | |
928 | mfspr r10,SPRN_DAR | |
929 | std r10,PACA_EXGEN+EX_DAR(r13) | |
930 | mfspr r10,SPRN_DSISR | |
931 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
932 | EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN) | |
a546498f BH |
933 | DISABLE_INTS |
934 | ld r12,_MSR(r1) | |
0ebc4cda BH |
935 | ld r3,PACA_EXGEN+EX_DAR(r13) |
936 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | |
937 | li r5,0x300 | |
278a6cdc | 938 | b .do_hash_page /* Try to handle as hpte fault */ |
0ebc4cda | 939 | |
b3e6b5df | 940 | .align 7 |
278a6cdc | 941 | .globl h_data_storage_common |
b3e6b5df | 942 | h_data_storage_common: |
278a6cdc MN |
943 | mfspr r10,SPRN_HDAR |
944 | std r10,PACA_EXGEN+EX_DAR(r13) | |
945 | mfspr r10,SPRN_HDSISR | |
946 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
947 | EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN) | |
948 | bl .save_nvgprs | |
a546498f | 949 | DISABLE_INTS |
278a6cdc MN |
950 | addi r3,r1,STACK_FRAME_OVERHEAD |
951 | bl .unknown_exception | |
952 | b .ret_from_except | |
b3e6b5df | 953 | |
0ebc4cda BH |
954 | .align 7 |
955 | .globl instruction_access_common | |
956 | instruction_access_common: | |
957 | EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN) | |
a546498f BH |
958 | DISABLE_INTS |
959 | ld r12,_MSR(r1) | |
0ebc4cda BH |
960 | ld r3,_NIP(r1) |
961 | andis. r4,r12,0x5820 | |
962 | li r5,0x400 | |
963 | b .do_hash_page /* Try to handle as hpte fault */ | |
964 | ||
278a6cdc | 965 | STD_EXCEPTION_COMMON(0xe20, h_instr_storage, .unknown_exception) |
b3e6b5df | 966 | |
0ebc4cda BH |
967 | /* |
968 | * Here is the common SLB miss user that is used when going to virtual | |
969 | * mode for SLB misses, that is currently not used | |
970 | */ | |
971 | #ifdef __DISABLED__ | |
972 | .align 7 | |
973 | .globl slb_miss_user_common | |
974 | slb_miss_user_common: | |
975 | mflr r10 | |
976 | std r3,PACA_EXGEN+EX_DAR(r13) | |
977 | stw r9,PACA_EXGEN+EX_CCR(r13) | |
978 | std r10,PACA_EXGEN+EX_LR(r13) | |
979 | std r11,PACA_EXGEN+EX_SRR0(r13) | |
980 | bl .slb_allocate_user | |
981 | ||
982 | ld r10,PACA_EXGEN+EX_LR(r13) | |
983 | ld r3,PACA_EXGEN+EX_R3(r13) | |
984 | lwz r9,PACA_EXGEN+EX_CCR(r13) | |
985 | ld r11,PACA_EXGEN+EX_SRR0(r13) | |
986 | mtlr r10 | |
987 | beq- slb_miss_fault | |
988 | ||
989 | andi. r10,r12,MSR_RI /* check for unrecoverable exception */ | |
990 | beq- unrecov_user_slb | |
991 | mfmsr r10 | |
992 | ||
993 | .machine push | |
994 | .machine "power4" | |
995 | mtcrf 0x80,r9 | |
996 | .machine pop | |
997 | ||
998 | clrrdi r10,r10,2 /* clear RI before setting SRR0/1 */ | |
999 | mtmsrd r10,1 | |
1000 | ||
1001 | mtspr SRR0,r11 | |
1002 | mtspr SRR1,r12 | |
1003 | ||
1004 | ld r9,PACA_EXGEN+EX_R9(r13) | |
1005 | ld r10,PACA_EXGEN+EX_R10(r13) | |
1006 | ld r11,PACA_EXGEN+EX_R11(r13) | |
1007 | ld r12,PACA_EXGEN+EX_R12(r13) | |
1008 | ld r13,PACA_EXGEN+EX_R13(r13) | |
1009 | rfid | |
1010 | b . | |
1011 | ||
1012 | slb_miss_fault: | |
1013 | EXCEPTION_PROLOG_COMMON(0x380, PACA_EXGEN) | |
1014 | ld r4,PACA_EXGEN+EX_DAR(r13) | |
1015 | li r5,0 | |
1016 | std r4,_DAR(r1) | |
1017 | std r5,_DSISR(r1) | |
1018 | b handle_page_fault | |
1019 | ||
1020 | unrecov_user_slb: | |
1021 | EXCEPTION_PROLOG_COMMON(0x4200, PACA_EXGEN) | |
1022 | DISABLE_INTS | |
1023 | bl .save_nvgprs | |
1024 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
1025 | bl .unrecoverable_exception | |
1026 | b 1b | |
1027 | ||
1028 | #endif /* __DISABLED__ */ | |
1029 | ||
1030 | ||
0ebc4cda BH |
1031 | .align 7 |
1032 | .globl alignment_common | |
1033 | alignment_common: | |
1034 | mfspr r10,SPRN_DAR | |
1035 | std r10,PACA_EXGEN+EX_DAR(r13) | |
1036 | mfspr r10,SPRN_DSISR | |
1037 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
1038 | EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN) | |
1039 | ld r3,PACA_EXGEN+EX_DAR(r13) | |
1040 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | |
1041 | std r3,_DAR(r1) | |
1042 | std r4,_DSISR(r1) | |
1043 | bl .save_nvgprs | |
a3512b2d | 1044 | DISABLE_INTS |
0ebc4cda | 1045 | addi r3,r1,STACK_FRAME_OVERHEAD |
0ebc4cda BH |
1046 | bl .alignment_exception |
1047 | b .ret_from_except | |
1048 | ||
1049 | .align 7 | |
1050 | .globl program_check_common | |
1051 | program_check_common: | |
1052 | EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN) | |
1053 | bl .save_nvgprs | |
54321242 | 1054 | DISABLE_INTS |
922b9f86 | 1055 | addi r3,r1,STACK_FRAME_OVERHEAD |
0ebc4cda BH |
1056 | bl .program_check_exception |
1057 | b .ret_from_except | |
1058 | ||
1059 | .align 7 | |
1060 | .globl fp_unavailable_common | |
1061 | fp_unavailable_common: | |
1062 | EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN) | |
1063 | bne 1f /* if from user, just load it up */ | |
1064 | bl .save_nvgprs | |
9f2f79e3 | 1065 | DISABLE_INTS |
0ebc4cda | 1066 | addi r3,r1,STACK_FRAME_OVERHEAD |
0ebc4cda BH |
1067 | bl .kernel_fp_unavailable_exception |
1068 | BUG_OPCODE | |
bc2a9408 MN |
1069 | 1: |
1070 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1071 | BEGIN_FTR_SECTION | |
1072 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in | |
1073 | * transaction), go do TM stuff | |
1074 | */ | |
1075 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) | |
1076 | bne- 2f | |
1077 | END_FTR_SECTION_IFSET(CPU_FTR_TM) | |
1078 | #endif | |
1079 | bl .load_up_fpu | |
0ebc4cda | 1080 | b fast_exception_return |
bc2a9408 MN |
1081 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1082 | 2: /* User process was in a transaction */ | |
1083 | bl .save_nvgprs | |
1084 | DISABLE_INTS | |
1085 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1086 | bl .fp_unavailable_tm | |
1087 | b .ret_from_except | |
1088 | #endif | |
0ebc4cda BH |
1089 | .align 7 |
1090 | .globl altivec_unavailable_common | |
1091 | altivec_unavailable_common: | |
1092 | EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN) | |
1093 | #ifdef CONFIG_ALTIVEC | |
1094 | BEGIN_FTR_SECTION | |
1095 | beq 1f | |
bc2a9408 MN |
1096 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1097 | BEGIN_FTR_SECTION_NESTED(69) | |
1098 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in | |
1099 | * transaction), go do TM stuff | |
1100 | */ | |
1101 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) | |
1102 | bne- 2f | |
1103 | END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) | |
1104 | #endif | |
0ebc4cda BH |
1105 | bl .load_up_altivec |
1106 | b fast_exception_return | |
bc2a9408 MN |
1107 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1108 | 2: /* User process was in a transaction */ | |
1109 | bl .save_nvgprs | |
1110 | DISABLE_INTS | |
1111 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1112 | bl .altivec_unavailable_tm | |
1113 | b .ret_from_except | |
1114 | #endif | |
0ebc4cda BH |
1115 | 1: |
1116 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
1117 | #endif | |
1118 | bl .save_nvgprs | |
9f2f79e3 | 1119 | DISABLE_INTS |
0ebc4cda | 1120 | addi r3,r1,STACK_FRAME_OVERHEAD |
0ebc4cda BH |
1121 | bl .altivec_unavailable_exception |
1122 | b .ret_from_except | |
1123 | ||
1124 | .align 7 | |
1125 | .globl vsx_unavailable_common | |
1126 | vsx_unavailable_common: | |
1127 | EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN) | |
1128 | #ifdef CONFIG_VSX | |
1129 | BEGIN_FTR_SECTION | |
7230c564 | 1130 | beq 1f |
bc2a9408 MN |
1131 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1132 | BEGIN_FTR_SECTION_NESTED(69) | |
1133 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in | |
1134 | * transaction), go do TM stuff | |
1135 | */ | |
1136 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) | |
1137 | bne- 2f | |
1138 | END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) | |
1139 | #endif | |
7230c564 | 1140 | b .load_up_vsx |
bc2a9408 MN |
1141 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1142 | 2: /* User process was in a transaction */ | |
1143 | bl .save_nvgprs | |
1144 | DISABLE_INTS | |
1145 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1146 | bl .vsx_unavailable_tm | |
1147 | b .ret_from_except | |
1148 | #endif | |
0ebc4cda BH |
1149 | 1: |
1150 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
1151 | #endif | |
1152 | bl .save_nvgprs | |
9f2f79e3 | 1153 | DISABLE_INTS |
0ebc4cda | 1154 | addi r3,r1,STACK_FRAME_OVERHEAD |
0ebc4cda BH |
1155 | bl .vsx_unavailable_exception |
1156 | b .ret_from_except | |
1157 | ||
d0c0c9a1 MN |
1158 | .align 7 |
1159 | .globl tm_unavailable_common | |
1160 | tm_unavailable_common: | |
1161 | EXCEPTION_PROLOG_COMMON(0xf60, PACA_EXGEN) | |
1162 | bl .save_nvgprs | |
bc2a9408 | 1163 | DISABLE_INTS |
d0c0c9a1 MN |
1164 | addi r3,r1,STACK_FRAME_OVERHEAD |
1165 | bl .tm_unavailable_exception | |
1166 | b .ret_from_except | |
1167 | ||
0ebc4cda BH |
1168 | .align 7 |
1169 | .globl __end_handlers | |
1170 | __end_handlers: | |
1171 | ||
61383407 | 1172 | /* Equivalents to the above handlers for relocation-on interrupt vectors */ |
1707dd16 | 1173 | STD_RELON_EXCEPTION_HV_OOL(0xe00, h_data_storage) |
61383407 | 1174 | KVM_HANDLER(PACA_EXGEN, EXC_HV, 0xe00) |
1707dd16 | 1175 | STD_RELON_EXCEPTION_HV_OOL(0xe20, h_instr_storage) |
61383407 | 1176 | KVM_HANDLER(PACA_EXGEN, EXC_HV, 0xe20) |
1707dd16 | 1177 | STD_RELON_EXCEPTION_HV_OOL(0xe40, emulation_assist) |
61383407 | 1178 | KVM_HANDLER(PACA_EXGEN, EXC_HV, 0xe40) |
1707dd16 | 1179 | STD_RELON_EXCEPTION_HV_OOL(0xe60, hmi_exception) |
61383407 | 1180 | KVM_HANDLER(PACA_EXGEN, EXC_HV, 0xe60) |
1707dd16 | 1181 | MASKABLE_RELON_EXCEPTION_HV_OOL(0xe80, h_doorbell) |
61383407 BH |
1182 | KVM_HANDLER(PACA_EXGEN, EXC_HV, 0xe80) |
1183 | ||
1707dd16 PM |
1184 | STD_RELON_EXCEPTION_PSERIES_OOL(0xf00, performance_monitor) |
1185 | STD_RELON_EXCEPTION_PSERIES_OOL(0xf20, altivec_unavailable) | |
1186 | STD_RELON_EXCEPTION_PSERIES_OOL(0xf40, vsx_unavailable) | |
d0c0c9a1 | 1187 | STD_RELON_EXCEPTION_PSERIES_OOL(0xf60, tm_unavailable) |
61383407 BH |
1188 | |
1189 | #if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV) | |
1190 | /* | |
1191 | * Data area reserved for FWNMI option. | |
1192 | * This address (0x7000) is fixed by the RPA. | |
1193 | */ | |
1194 | .= 0x7000 | |
1195 | .globl fwnmi_data_area | |
1196 | fwnmi_data_area: | |
1197 | ||
1198 | /* pseries and powernv need to keep the whole page from | |
1199 | * 0x7000 to 0x8000 free for use by the firmware | |
1200 | */ | |
1201 | . = 0x8000 | |
1202 | #endif /* defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV) */ | |
1203 | ||
1204 | /* Space for CPU0's segment table */ | |
1205 | .balign 4096 | |
1206 | .globl initial_stab | |
1207 | initial_stab: | |
1208 | .space 4096 | |
1209 | ||
1210 | #ifdef CONFIG_PPC_POWERNV | |
1211 | _GLOBAL(opal_mc_secondary_handler) | |
1212 | HMT_MEDIUM_PPR_DISCARD | |
1213 | SET_SCRATCH0(r13) | |
1214 | GET_PACA(r13) | |
1215 | clrldi r3,r3,2 | |
1216 | tovirt(r3,r3) | |
1217 | std r3,PACA_OPAL_MC_EVT(r13) | |
1218 | ld r13,OPAL_MC_SRR0(r3) | |
1219 | mtspr SPRN_SRR0,r13 | |
1220 | ld r13,OPAL_MC_SRR1(r3) | |
1221 | mtspr SPRN_SRR1,r13 | |
1222 | ld r3,OPAL_MC_GPR3(r3) | |
1223 | GET_SCRATCH0(r13) | |
1224 | b machine_check_pSeries | |
1225 | #endif /* CONFIG_PPC_POWERNV */ | |
1226 | ||
1227 | ||
087aa036 CG |
1228 | /* |
1229 | * r13 points to the PACA, r9 contains the saved CR, | |
1230 | * r12 contain the saved SRR1, SRR0 is still ready for return | |
1231 | * r3 has the faulting address | |
1232 | * r9 - r13 are saved in paca->exslb. | |
1233 | * r3 is saved in paca->slb_r3 | |
1234 | * We assume we aren't going to take any exceptions during this procedure. | |
1235 | */ | |
1236 | _GLOBAL(slb_miss_realmode) | |
1237 | mflr r10 | |
1238 | #ifdef CONFIG_RELOCATABLE | |
1239 | mtctr r11 | |
1240 | #endif | |
1241 | ||
1242 | stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ | |
1243 | std r10,PACA_EXSLB+EX_LR(r13) /* save LR */ | |
1244 | ||
1245 | bl .slb_allocate_realmode | |
1246 | ||
1247 | /* All done -- return from exception. */ | |
1248 | ||
1249 | ld r10,PACA_EXSLB+EX_LR(r13) | |
1250 | ld r3,PACA_EXSLB+EX_R3(r13) | |
1251 | lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ | |
1252 | ||
1253 | mtlr r10 | |
1254 | ||
1255 | andi. r10,r12,MSR_RI /* check for unrecoverable exception */ | |
1256 | beq- 2f | |
1257 | ||
1258 | .machine push | |
1259 | .machine "power4" | |
1260 | mtcrf 0x80,r9 | |
1261 | mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */ | |
1262 | .machine pop | |
1263 | ||
1264 | RESTORE_PPR_PACA(PACA_EXSLB, r9) | |
1265 | ld r9,PACA_EXSLB+EX_R9(r13) | |
1266 | ld r10,PACA_EXSLB+EX_R10(r13) | |
1267 | ld r11,PACA_EXSLB+EX_R11(r13) | |
1268 | ld r12,PACA_EXSLB+EX_R12(r13) | |
1269 | ld r13,PACA_EXSLB+EX_R13(r13) | |
1270 | rfid | |
1271 | b . /* prevent speculative execution */ | |
1272 | ||
1273 | 2: mfspr r11,SPRN_SRR0 | |
1274 | ld r10,PACAKBASE(r13) | |
1275 | LOAD_HANDLER(r10,unrecov_slb) | |
1276 | mtspr SPRN_SRR0,r10 | |
1277 | ld r10,PACAKMSR(r13) | |
1278 | mtspr SPRN_SRR1,r10 | |
1279 | rfid | |
1280 | b . | |
1281 | ||
1282 | unrecov_slb: | |
1283 | EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB) | |
1284 | DISABLE_INTS | |
1285 | bl .save_nvgprs | |
1286 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
1287 | bl .unrecoverable_exception | |
1288 | b 1b | |
1289 | ||
1290 | ||
1291 | #ifdef CONFIG_PPC_970_NAP | |
1292 | power4_fixup_nap: | |
1293 | andc r9,r9,r10 | |
1294 | std r9,TI_LOCAL_FLAGS(r11) | |
1295 | ld r10,_LINK(r1) /* make idle task do the */ | |
1296 | std r10,_NIP(r1) /* equivalent of a blr */ | |
1297 | blr | |
1298 | #endif | |
1299 | ||
0ebc4cda BH |
1300 | /* |
1301 | * Hash table stuff | |
1302 | */ | |
1303 | .align 7 | |
1304 | _STATIC(do_hash_page) | |
1305 | std r3,_DAR(r1) | |
1306 | std r4,_DSISR(r1) | |
1307 | ||
9c7cc234 | 1308 | andis. r0,r4,0xa410 /* weird error? */ |
0ebc4cda | 1309 | bne- handle_page_fault /* if not, try to insert a HPTE */ |
9c7cc234 P |
1310 | andis. r0,r4,DSISR_DABRMATCH@h |
1311 | bne- handle_dabr_fault | |
1312 | ||
0ebc4cda BH |
1313 | BEGIN_FTR_SECTION |
1314 | andis. r0,r4,0x0020 /* Is it a segment table fault? */ | |
1315 | bne- do_ste_alloc /* If so handle it */ | |
44ae3ab3 | 1316 | END_MMU_FTR_SECTION_IFCLR(MMU_FTR_SLB) |
0ebc4cda | 1317 | |
9778b696 | 1318 | CURRENT_THREAD_INFO(r11, r1) |
9c1e1052 PM |
1319 | lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */ |
1320 | andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */ | |
1321 | bne 77f /* then don't call hash_page now */ | |
0ebc4cda BH |
1322 | /* |
1323 | * We need to set the _PAGE_USER bit if MSR_PR is set or if we are | |
1324 | * accessing a userspace segment (even from the kernel). We assume | |
1325 | * kernel addresses always have the high bit set. | |
1326 | */ | |
1327 | rlwinm r4,r4,32-25+9,31-9,31-9 /* DSISR_STORE -> _PAGE_RW */ | |
1328 | rotldi r0,r3,15 /* Move high bit into MSR_PR posn */ | |
1329 | orc r0,r12,r0 /* MSR_PR | ~high_bit */ | |
1330 | rlwimi r4,r0,32-13,30,30 /* becomes _PAGE_USER access bit */ | |
1331 | ori r4,r4,1 /* add _PAGE_PRESENT */ | |
1332 | rlwimi r4,r5,22+2,31-2,31-2 /* Set _PAGE_EXEC if trap is 0x400 */ | |
1333 | ||
1334 | /* | |
1335 | * r3 contains the faulting address | |
1336 | * r4 contains the required access permissions | |
1337 | * r5 contains the trap number | |
1338 | * | |
7230c564 | 1339 | * at return r3 = 0 for success, 1 for page fault, negative for error |
0ebc4cda BH |
1340 | */ |
1341 | bl .hash_page /* build HPTE if possible */ | |
1342 | cmpdi r3,0 /* see if hash_page succeeded */ | |
1343 | ||
7230c564 | 1344 | /* Success */ |
0ebc4cda | 1345 | beq fast_exc_return_irq /* Return from exception on success */ |
0ebc4cda | 1346 | |
7230c564 BH |
1347 | /* Error */ |
1348 | blt- 13f | |
9c7cc234 | 1349 | |
0ebc4cda BH |
1350 | /* Here we have a page fault that hash_page can't handle. */ |
1351 | handle_page_fault: | |
0ebc4cda BH |
1352 | 11: ld r4,_DAR(r1) |
1353 | ld r5,_DSISR(r1) | |
1354 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1355 | bl .do_page_fault | |
1356 | cmpdi r3,0 | |
a546498f | 1357 | beq+ 12f |
0ebc4cda BH |
1358 | bl .save_nvgprs |
1359 | mr r5,r3 | |
1360 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1361 | lwz r4,_DAR(r1) | |
1362 | bl .bad_page_fault | |
1363 | b .ret_from_except | |
1364 | ||
a546498f BH |
1365 | /* We have a data breakpoint exception - handle it */ |
1366 | handle_dabr_fault: | |
1367 | bl .save_nvgprs | |
1368 | ld r4,_DAR(r1) | |
1369 | ld r5,_DSISR(r1) | |
1370 | addi r3,r1,STACK_FRAME_OVERHEAD | |
9422de3e | 1371 | bl .do_break |
a546498f BH |
1372 | 12: b .ret_from_except_lite |
1373 | ||
0ebc4cda BH |
1374 | |
1375 | /* We have a page fault that hash_page could handle but HV refused | |
1376 | * the PTE insertion | |
1377 | */ | |
a546498f | 1378 | 13: bl .save_nvgprs |
0ebc4cda BH |
1379 | mr r5,r3 |
1380 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1381 | ld r4,_DAR(r1) | |
1382 | bl .low_hash_fault | |
1383 | b .ret_from_except | |
1384 | ||
9c1e1052 PM |
1385 | /* |
1386 | * We come here as a result of a DSI at a point where we don't want | |
1387 | * to call hash_page, such as when we are accessing memory (possibly | |
1388 | * user memory) inside a PMU interrupt that occurred while interrupts | |
1389 | * were soft-disabled. We want to invoke the exception handler for | |
1390 | * the access, or panic if there isn't a handler. | |
1391 | */ | |
1392 | 77: bl .save_nvgprs | |
1393 | mr r4,r3 | |
1394 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1395 | li r5,SIGSEGV | |
1396 | bl .bad_page_fault | |
1397 | b .ret_from_except | |
1398 | ||
0ebc4cda BH |
1399 | /* here we have a segment miss */ |
1400 | do_ste_alloc: | |
1401 | bl .ste_allocate /* try to insert stab entry */ | |
1402 | cmpdi r3,0 | |
1403 | bne- handle_page_fault | |
1404 | b fast_exception_return | |
1405 | ||
1406 | /* | |
1407 | * r13 points to the PACA, r9 contains the saved CR, | |
1408 | * r11 and r12 contain the saved SRR0 and SRR1. | |
1409 | * r9 - r13 are saved in paca->exslb. | |
1410 | * We assume we aren't going to take any exceptions during this procedure. | |
1411 | * We assume (DAR >> 60) == 0xc. | |
1412 | */ | |
1413 | .align 7 | |
1414 | _GLOBAL(do_stab_bolted) | |
1415 | stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ | |
1416 | std r11,PACA_EXSLB+EX_SRR0(r13) /* save SRR0 in exc. frame */ | |
c60ac569 | 1417 | mfspr r11,SPRN_DAR /* ea */ |
0ebc4cda | 1418 | |
c60ac569 AK |
1419 | /* |
1420 | * check for bad kernel/user address | |
1421 | * (ea & ~REGION_MASK) >= PGTABLE_RANGE | |
1422 | */ | |
1423 | rldicr. r9,r11,4,(63 - 46 - 4) | |
1424 | li r9,0 /* VSID = 0 for bad address */ | |
1425 | bne- 0f | |
1426 | ||
1427 | /* | |
1428 | * Calculate VSID: | |
1429 | * This is the kernel vsid, we take the top for context from | |
1430 | * the range. context = (MAX_USER_CONTEXT) + ((ea >> 60) - 0xc) + 1 | |
1431 | * Here we know that (ea >> 60) == 0xc | |
1432 | */ | |
1433 | lis r9,(MAX_USER_CONTEXT + 1)@ha | |
1434 | addi r9,r9,(MAX_USER_CONTEXT + 1)@l | |
1435 | ||
1436 | srdi r10,r11,SID_SHIFT | |
af81d787 | 1437 | rldimi r10,r9,ESID_BITS,0 /* proto vsid */ |
c60ac569 AK |
1438 | ASM_VSID_SCRAMBLE(r10, r9, 256M) |
1439 | rldic r9,r10,12,16 /* r9 = vsid << 12 */ | |
1440 | ||
1441 | 0: | |
0ebc4cda BH |
1442 | /* Hash to the primary group */ |
1443 | ld r10,PACASTABVIRT(r13) | |
c60ac569 | 1444 | srdi r11,r11,SID_SHIFT |
0ebc4cda BH |
1445 | rldimi r10,r11,7,52 /* r10 = first ste of the group */ |
1446 | ||
0ebc4cda BH |
1447 | /* Search the primary group for a free entry */ |
1448 | 1: ld r11,0(r10) /* Test valid bit of the current ste */ | |
1449 | andi. r11,r11,0x80 | |
1450 | beq 2f | |
1451 | addi r10,r10,16 | |
1452 | andi. r11,r10,0x70 | |
1453 | bne 1b | |
1454 | ||
1455 | /* Stick for only searching the primary group for now. */ | |
1456 | /* At least for now, we use a very simple random castout scheme */ | |
1457 | /* Use the TB as a random number ; OR in 1 to avoid entry 0 */ | |
1458 | mftb r11 | |
1459 | rldic r11,r11,4,57 /* r11 = (r11 << 4) & 0x70 */ | |
1460 | ori r11,r11,0x10 | |
1461 | ||
1462 | /* r10 currently points to an ste one past the group of interest */ | |
1463 | /* make it point to the randomly selected entry */ | |
1464 | subi r10,r10,128 | |
1465 | or r10,r10,r11 /* r10 is the entry to invalidate */ | |
1466 | ||
1467 | isync /* mark the entry invalid */ | |
1468 | ld r11,0(r10) | |
1469 | rldicl r11,r11,56,1 /* clear the valid bit */ | |
1470 | rotldi r11,r11,8 | |
1471 | std r11,0(r10) | |
1472 | sync | |
1473 | ||
1474 | clrrdi r11,r11,28 /* Get the esid part of the ste */ | |
1475 | slbie r11 | |
1476 | ||
1477 | 2: std r9,8(r10) /* Store the vsid part of the ste */ | |
1478 | eieio | |
1479 | ||
1480 | mfspr r11,SPRN_DAR /* Get the new esid */ | |
1481 | clrrdi r11,r11,28 /* Permits a full 32b of ESID */ | |
1482 | ori r11,r11,0x90 /* Turn on valid and kp */ | |
1483 | std r11,0(r10) /* Put new entry back into the stab */ | |
1484 | ||
1485 | sync | |
1486 | ||
1487 | /* All done -- return from exception. */ | |
1488 | lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ | |
1489 | ld r11,PACA_EXSLB+EX_SRR0(r13) /* get saved SRR0 */ | |
1490 | ||
1491 | andi. r10,r12,MSR_RI | |
1492 | beq- unrecov_slb | |
1493 | ||
1494 | mtcrf 0x80,r9 /* restore CR */ | |
1495 | ||
1496 | mfmsr r10 | |
1497 | clrrdi r10,r10,2 | |
1498 | mtmsrd r10,1 | |
1499 | ||
1500 | mtspr SPRN_SRR0,r11 | |
1501 | mtspr SPRN_SRR1,r12 | |
1502 | ld r9,PACA_EXSLB+EX_R9(r13) | |
1503 | ld r10,PACA_EXSLB+EX_R10(r13) | |
1504 | ld r11,PACA_EXSLB+EX_R11(r13) | |
1505 | ld r12,PACA_EXSLB+EX_R12(r13) | |
1506 | ld r13,PACA_EXSLB+EX_R13(r13) | |
1507 | rfid | |
1508 | b . /* prevent speculative execution */ |