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Commit | Line | Data |
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c21e0bbf MO |
1 | /* |
2 | * CXL Flash Device Driver | |
3 | * | |
4 | * Written by: Manoj N. Kumar <manoj@linux.vnet.ibm.com>, IBM Corporation | |
5 | * Matthew R. Ochs <mrochs@linux.vnet.ibm.com>, IBM Corporation | |
6 | * | |
7 | * Copyright (C) 2015 IBM Corporation | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * as published by the Free Software Foundation; either version | |
12 | * 2 of the License, or (at your option) any later version. | |
13 | */ | |
14 | ||
15 | #ifndef _CXLFLASH_COMMON_H | |
16 | #define _CXLFLASH_COMMON_H | |
17 | ||
3b4f03cd | 18 | #include <linux/async.h> |
f3d79b3e | 19 | #include <linux/cdev.h> |
2588f222 | 20 | #include <linux/irq_poll.h> |
c21e0bbf | 21 | #include <linux/list.h> |
0a27ae51 | 22 | #include <linux/rwsem.h> |
c21e0bbf MO |
23 | #include <linux/types.h> |
24 | #include <scsi/scsi.h> | |
5fbb96c8 | 25 | #include <scsi/scsi_cmnd.h> |
c21e0bbf MO |
26 | #include <scsi/scsi_device.h> |
27 | ||
17ead26f | 28 | extern const struct file_operations cxlflash_cxl_fops; |
c21e0bbf | 29 | |
66d4bce4 | 30 | #define MAX_CONTEXT CXLFLASH_MAX_CONTEXT /* num contexts per afu */ |
a290b480 MO |
31 | #define MAX_FC_PORTS CXLFLASH_MAX_FC_PORTS /* max ports per AFU */ |
32 | #define LEGACY_FC_PORTS 2 /* legacy ports per AFU */ | |
33 | ||
34 | #define CHAN2PORTBANK(_x) ((_x) >> ilog2(CXLFLASH_NUM_FC_PORTS_PER_BANK)) | |
35 | #define CHAN2BANKPORT(_x) ((_x) & (CXLFLASH_NUM_FC_PORTS_PER_BANK - 1)) | |
c21e0bbf | 36 | |
e8e17ea6 MO |
37 | #define CHAN2PORTMASK(_x) (1 << (_x)) /* channel to port mask */ |
38 | #define PORTMASK2CHAN(_x) (ilog2((_x))) /* port mask to channel */ | |
39 | #define PORTNUM2CHAN(_x) ((_x) - 1) /* port number to channel */ | |
40 | ||
39e9d618 | 41 | #define CXLFLASH_BLOCK_SIZE 4096 /* 4K blocks */ |
c21e0bbf MO |
42 | #define CXLFLASH_MAX_XFER_SIZE 16777216 /* 16MB transfer */ |
43 | #define CXLFLASH_MAX_SECTORS (CXLFLASH_MAX_XFER_SIZE/512) /* SCSI wants | |
39e9d618 MO |
44 | * max_sectors |
45 | * in units of | |
46 | * 512 byte | |
47 | * sectors | |
48 | */ | |
c21e0bbf | 49 | |
c21e0bbf MO |
50 | #define MAX_RHT_PER_CONTEXT (PAGE_SIZE / sizeof(struct sisl_rht_entry)) |
51 | ||
52 | /* AFU command retry limit */ | |
39e9d618 | 53 | #define MC_RETRY_CNT 5 /* Sufficient for SCSI and certain AFU errors */ |
c21e0bbf MO |
54 | |
55 | /* Command management definitions */ | |
83430833 | 56 | #define CXLFLASH_MAX_CMDS 256 |
c21e0bbf MO |
57 | #define CXLFLASH_MAX_CMDS_PER_LUN CXLFLASH_MAX_CMDS |
58 | ||
83430833 MK |
59 | /* RRQ for master issued cmds */ |
60 | #define NUM_RRQ_ENTRY CXLFLASH_MAX_CMDS | |
61 | ||
bae0ac69 MO |
62 | /* SQ for master issued cmds */ |
63 | #define NUM_SQ_ENTRY CXLFLASH_MAX_CMDS | |
64 | ||
bb85ef68 MO |
65 | /* Hardware queue definitions */ |
66 | #define CXLFLASH_DEF_HWQS 1 | |
67 | #define CXLFLASH_MAX_HWQS 8 | |
a583d00a UK |
68 | #define PRIMARY_HWQ 0 |
69 | ||
c21e0bbf MO |
70 | |
71 | static inline void check_sizes(void) | |
72 | { | |
a290b480 | 73 | BUILD_BUG_ON_NOT_POWER_OF_2(CXLFLASH_NUM_FC_PORTS_PER_BANK); |
db853d50 | 74 | BUILD_BUG_ON_NOT_POWER_OF_2(CXLFLASH_MAX_CMDS); |
c21e0bbf MO |
75 | } |
76 | ||
77 | /* AFU defines a fixed size of 4K for command buffers (borrow 4K page define) */ | |
78 | #define CMD_BUFSIZE SIZE_4K | |
79 | ||
c21e0bbf MO |
80 | enum cxlflash_lr_state { |
81 | LINK_RESET_INVALID, | |
82 | LINK_RESET_REQUIRED, | |
83 | LINK_RESET_COMPLETE | |
84 | }; | |
85 | ||
86 | enum cxlflash_init_state { | |
87 | INIT_STATE_NONE, | |
88 | INIT_STATE_PCI, | |
89 | INIT_STATE_AFU, | |
f3d79b3e UK |
90 | INIT_STATE_SCSI, |
91 | INIT_STATE_CDEV | |
c21e0bbf MO |
92 | }; |
93 | ||
5cdac81a | 94 | enum cxlflash_state { |
f92ba507 MO |
95 | STATE_PROBING, /* Initial state during probe */ |
96 | STATE_PROBED, /* Temporary state, probe completed but EEH occurred */ | |
5cdac81a | 97 | STATE_NORMAL, /* Normal running state, everything good */ |
439e85c1 | 98 | STATE_RESET, /* Reset state, trying to reset/recover */ |
5cdac81a MO |
99 | STATE_FAILTERM /* Failed/terminating state, error out users/threads */ |
100 | }; | |
101 | ||
8c052e9e MO |
102 | enum cxlflash_hwq_mode { |
103 | HWQ_MODE_RR, /* Roundrobin (default) */ | |
104 | HWQ_MODE_TAG, /* Distribute based on block MQ tag */ | |
105 | HWQ_MODE_CPU, /* CPU affinity */ | |
106 | MAX_HWQ_MODE | |
107 | }; | |
108 | ||
c21e0bbf MO |
109 | /* |
110 | * Each context has its own set of resource handles that is visible | |
111 | * only from that context. | |
112 | */ | |
113 | ||
114 | struct cxlflash_cfg { | |
115 | struct afu *afu; | |
c21e0bbf MO |
116 | |
117 | struct pci_dev *dev; | |
118 | struct pci_device_id *dev_id; | |
119 | struct Scsi_Host *host; | |
66d4bce4 | 120 | int num_fc_ports; |
f3d79b3e UK |
121 | struct cdev cdev; |
122 | struct device *chardev; | |
c21e0bbf MO |
123 | |
124 | ulong cxlflash_regs_pci; | |
125 | ||
c21e0bbf MO |
126 | struct work_struct work_q; |
127 | enum cxlflash_init_state init_state; | |
128 | enum cxlflash_lr_state lr_state; | |
129 | int lr_port; | |
ef51074a | 130 | atomic_t scan_host_needed; |
c21e0bbf MO |
131 | |
132 | struct cxl_afu *cxl_afu; | |
c21e0bbf | 133 | |
65be2c79 MO |
134 | atomic_t recovery_threads; |
135 | struct mutex ctx_recovery_mutex; | |
136 | struct mutex ctx_tbl_list_mutex; | |
0a27ae51 | 137 | struct rw_semaphore ioctl_rwsem; |
65be2c79 MO |
138 | struct ctx_info *ctx_tbl[MAX_CONTEXT]; |
139 | struct list_head ctx_err_recovery; /* contexts w/ recovery pending */ | |
140 | struct file_operations cxl_fops; | |
141 | ||
2cb79266 | 142 | /* Parameters that are LUN table related */ |
66d4bce4 | 143 | int last_lun_index[MAX_FC_PORTS]; |
2cb79266 | 144 | int promote_lun_index; |
65be2c79 MO |
145 | struct list_head lluns; /* list of llun_info structs */ |
146 | ||
c21e0bbf | 147 | wait_queue_head_t tmf_waitq; |
018d1dc9 | 148 | spinlock_t tmf_slock; |
c21e0bbf | 149 | bool tmf_active; |
cb1e7bff | 150 | bool ws_unmap; /* Write-same unmap supported */ |
439e85c1 | 151 | wait_queue_head_t reset_waitq; |
5cdac81a | 152 | enum cxlflash_state state; |
3b4f03cd | 153 | async_cookie_t async_reset_cookie; |
c21e0bbf MO |
154 | }; |
155 | ||
156 | struct afu_cmd { | |
157 | struct sisl_ioarcb rcb; /* IOARCB (cache line aligned) */ | |
158 | struct sisl_ioasa sa; /* IOASA must follow IOARCB */ | |
c21e0bbf | 159 | struct afu *parent; |
fe7f9698 | 160 | struct scsi_cmnd *scp; |
9ba848ac | 161 | struct completion cevent; |
7bb512aa | 162 | struct list_head queue; |
8c052e9e | 163 | u32 hwq_index; |
c21e0bbf | 164 | |
2450a5e3 UK |
165 | u8 cmd_tmf:1, |
166 | cmd_aborted:1; | |
167 | ||
d732d14f | 168 | struct list_head list; /* Pending commands link */ |
c21e0bbf MO |
169 | |
170 | /* As per the SISLITE spec the IOARCB EA has to be 16-byte aligned. | |
171 | * However for performance reasons the IOARCB/IOASA should be | |
172 | * cache line aligned. | |
173 | */ | |
174 | } __aligned(cache_line_size()); | |
175 | ||
5fbb96c8 MO |
176 | static inline struct afu_cmd *sc_to_afuc(struct scsi_cmnd *sc) |
177 | { | |
178 | return PTR_ALIGN(scsi_cmd_priv(sc), __alignof__(struct afu_cmd)); | |
179 | } | |
180 | ||
181 | static inline struct afu_cmd *sc_to_afucz(struct scsi_cmnd *sc) | |
182 | { | |
183 | struct afu_cmd *afuc = sc_to_afuc(sc); | |
184 | ||
185 | memset(afuc, 0, sizeof(*afuc)); | |
2450a5e3 | 186 | INIT_LIST_HEAD(&afuc->queue); |
5fbb96c8 MO |
187 | return afuc; |
188 | } | |
189 | ||
a583d00a | 190 | struct hwq { |
c21e0bbf | 191 | /* Stuff requiring alignment go first. */ |
bae0ac69 MO |
192 | struct sisl_ioarcb sq[NUM_SQ_ENTRY]; /* 16K SQ */ |
193 | u64 rrq_entry[NUM_RRQ_ENTRY]; /* 2K RRQ */ | |
c21e0bbf MO |
194 | |
195 | /* Beware of alignment till here. Preferably introduce new | |
196 | * fields after this point | |
197 | */ | |
a583d00a UK |
198 | struct afu *afu; |
199 | struct cxl_context *ctx; | |
c21e0bbf | 200 | struct cxl_ioctl_start_work work; |
1786f4a0 MO |
201 | struct sisl_host_map __iomem *host_map; /* MC host map */ |
202 | struct sisl_ctrl_map __iomem *ctrl_map; /* MC control map */ | |
c21e0bbf | 203 | ctx_hndl_t ctx_hndl; /* master's context handle */ |
a583d00a | 204 | u32 index; /* Index of this hwq */ |
d732d14f | 205 | struct list_head pending_cmds; /* Commands pending completion */ |
bae0ac69 MO |
206 | |
207 | atomic_t hsq_credits; | |
edc034e8 | 208 | spinlock_t hsq_slock; /* Hardware send queue lock */ |
bae0ac69 MO |
209 | struct sisl_ioarcb *hsq_start; |
210 | struct sisl_ioarcb *hsq_end; | |
211 | struct sisl_ioarcb *hsq_curr; | |
7bb512aa | 212 | spinlock_t hrrq_slock; |
c21e0bbf MO |
213 | u64 *hrrq_start; |
214 | u64 *hrrq_end; | |
215 | u64 *hrrq_curr; | |
216 | bool toggle; | |
a583d00a | 217 | |
11f7b184 | 218 | s64 room; |
a583d00a UK |
219 | |
220 | struct irq_poll irqpoll; | |
221 | } __aligned(cache_line_size()); | |
222 | ||
223 | struct afu { | |
bb85ef68 | 224 | struct hwq hwqs[CXLFLASH_MAX_HWQS]; |
a583d00a | 225 | int (*send_cmd)(struct afu *, struct afu_cmd *); |
ddc869e9 | 226 | int (*context_reset)(struct hwq *); |
a583d00a UK |
227 | |
228 | /* AFU HW */ | |
229 | struct cxlflash_afu_map __iomem *afu_map; /* entire MMIO map */ | |
230 | ||
231 | atomic_t cmds_active; /* Number of currently active AFU commands */ | |
c21e0bbf | 232 | u64 hb; |
c21e0bbf | 233 | u32 internal_lun; /* User-desired LUN mode for this AFU */ |
8c052e9e | 234 | |
bb85ef68 MO |
235 | u32 num_hwqs; /* Number of hardware queues */ |
236 | u32 desired_hwqs; /* Desired h/w queues, effective on AFU reset */ | |
8c052e9e MO |
237 | enum cxlflash_hwq_mode hwq_mode; /* Steering mode for h/w queues */ |
238 | u32 hwq_rr_count; /* Count to distribute traffic for roundrobin */ | |
c21e0bbf | 239 | |
e5ce067b | 240 | char version[16]; |
c21e0bbf MO |
241 | u64 interface_version; |
242 | ||
2588f222 | 243 | u32 irqpoll_weight; |
c21e0bbf | 244 | struct cxlflash_cfg *parent; /* Pointer back to parent cxlflash_cfg */ |
c21e0bbf MO |
245 | }; |
246 | ||
a583d00a UK |
247 | static inline struct hwq *get_hwq(struct afu *afu, u32 index) |
248 | { | |
bb85ef68 | 249 | WARN_ON(index >= CXLFLASH_MAX_HWQS); |
a583d00a UK |
250 | |
251 | return &afu->hwqs[index]; | |
252 | } | |
253 | ||
2588f222 MO |
254 | static inline bool afu_is_irqpoll_enabled(struct afu *afu) |
255 | { | |
256 | return !!afu->irqpoll_weight; | |
257 | } | |
258 | ||
0808aa95 | 259 | static inline bool afu_has_cap(struct afu *afu, u64 cap) |
bae0ac69 MO |
260 | { |
261 | u64 afu_cap = afu->interface_version >> SISL_INTVER_CAP_SHIFT; | |
262 | ||
0808aa95 | 263 | return afu_cap & cap; |
bae0ac69 MO |
264 | } |
265 | ||
d3c606a7 MO |
266 | static inline bool afu_is_afu_debug(struct afu *afu) |
267 | { | |
268 | return afu_has_cap(afu, SISL_INTVER_CAP_AFU_DEBUG); | |
269 | } | |
270 | ||
1f829583 MO |
271 | static inline bool afu_is_lun_provision(struct afu *afu) |
272 | { | |
273 | return afu_has_cap(afu, SISL_INTVER_CAP_LUN_PROVISION); | |
274 | } | |
275 | ||
bae0ac69 MO |
276 | static inline bool afu_is_sq_cmd_mode(struct afu *afu) |
277 | { | |
0808aa95 | 278 | return afu_has_cap(afu, SISL_INTVER_CAP_SQ_CMD_MODE); |
bae0ac69 MO |
279 | } |
280 | ||
281 | static inline bool afu_is_ioarrin_cmd_mode(struct afu *afu) | |
282 | { | |
0808aa95 | 283 | return afu_has_cap(afu, SISL_INTVER_CAP_IOARRIN_CMD_MODE); |
bae0ac69 MO |
284 | } |
285 | ||
c21e0bbf MO |
286 | static inline u64 lun_to_lunid(u64 lun) |
287 | { | |
1786f4a0 | 288 | __be64 lun_id; |
c21e0bbf MO |
289 | |
290 | int_to_scsilun(lun, (struct scsi_lun *)&lun_id); | |
1786f4a0 | 291 | return be64_to_cpu(lun_id); |
c21e0bbf MO |
292 | } |
293 | ||
a290b480 MO |
294 | static inline struct fc_port_bank __iomem *get_fc_port_bank( |
295 | struct cxlflash_cfg *cfg, int i) | |
c885d3fe MO |
296 | { |
297 | struct afu *afu = cfg->afu; | |
298 | ||
a290b480 MO |
299 | return &afu->afu_map->global.bank[CHAN2PORTBANK(i)]; |
300 | } | |
301 | ||
302 | static inline __be64 __iomem *get_fc_port_regs(struct cxlflash_cfg *cfg, int i) | |
303 | { | |
304 | struct fc_port_bank __iomem *fcpb = get_fc_port_bank(cfg, i); | |
305 | ||
306 | return &fcpb->fc_port_regs[CHAN2BANKPORT(i)][0]; | |
c885d3fe MO |
307 | } |
308 | ||
309 | static inline __be64 __iomem *get_fc_port_luns(struct cxlflash_cfg *cfg, int i) | |
310 | { | |
a290b480 | 311 | struct fc_port_bank __iomem *fcpb = get_fc_port_bank(cfg, i); |
c885d3fe | 312 | |
a290b480 | 313 | return &fcpb->fc_port_luns[CHAN2BANKPORT(i)][0]; |
c885d3fe MO |
314 | } |
315 | ||
39e9d618 | 316 | int cxlflash_afu_sync(struct afu *afu, ctx_hndl_t c, res_hndl_t r, u8 mode); |
65be2c79 MO |
317 | void cxlflash_list_init(void); |
318 | void cxlflash_term_global_luns(void); | |
319 | void cxlflash_free_errpage(void); | |
39e9d618 MO |
320 | int cxlflash_ioctl(struct scsi_device *sdev, int cmd, void __user *arg); |
321 | void cxlflash_stop_term_user_contexts(struct cxlflash_cfg *cfg); | |
322 | int cxlflash_mark_contexts_error(struct cxlflash_cfg *cfg); | |
323 | void cxlflash_term_local_luns(struct cxlflash_cfg *cfg); | |
324 | void cxlflash_restore_luntable(struct cxlflash_cfg *cfg); | |
65be2c79 | 325 | |
c21e0bbf | 326 | #endif /* ifndef _CXLFLASH_COMMON_H */ |