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Commit | Line | Data |
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c21e0bbf MO |
1 | /* |
2 | * CXL Flash Device Driver | |
3 | * | |
4 | * Written by: Manoj N. Kumar <manoj@linux.vnet.ibm.com>, IBM Corporation | |
5 | * Matthew R. Ochs <mrochs@linux.vnet.ibm.com>, IBM Corporation | |
6 | * | |
7 | * Copyright (C) 2015 IBM Corporation | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * as published by the Free Software Foundation; either version | |
12 | * 2 of the License, or (at your option) any later version. | |
13 | */ | |
14 | ||
15 | #include <linux/delay.h> | |
16 | #include <linux/list.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/pci.h> | |
19 | ||
20 | #include <asm/unaligned.h> | |
21 | ||
22 | #include <misc/cxl.h> | |
23 | ||
24 | #include <scsi/scsi_cmnd.h> | |
25 | #include <scsi/scsi_host.h> | |
65be2c79 | 26 | #include <uapi/scsi/cxlflash_ioctl.h> |
c21e0bbf MO |
27 | |
28 | #include "main.h" | |
29 | #include "sislite.h" | |
30 | #include "common.h" | |
31 | ||
32 | MODULE_DESCRIPTION(CXLFLASH_ADAPTER_NAME); | |
33 | MODULE_AUTHOR("Manoj N. Kumar <manoj@linux.vnet.ibm.com>"); | |
34 | MODULE_AUTHOR("Matthew R. Ochs <mrochs@linux.vnet.ibm.com>"); | |
35 | MODULE_LICENSE("GPL"); | |
36 | ||
f3d79b3e UK |
37 | static struct class *cxlflash_class; |
38 | static u32 cxlflash_major; | |
39 | static DECLARE_BITMAP(cxlflash_minor, CXLFLASH_MAX_ADAPTERS); | |
40 | ||
c21e0bbf MO |
41 | /** |
42 | * process_cmd_err() - command error handler | |
43 | * @cmd: AFU command that experienced the error. | |
44 | * @scp: SCSI command associated with the AFU command in error. | |
45 | * | |
46 | * Translates error bits from AFU command to SCSI command results. | |
47 | */ | |
48 | static void process_cmd_err(struct afu_cmd *cmd, struct scsi_cmnd *scp) | |
49 | { | |
88d33628 MO |
50 | struct afu *afu = cmd->parent; |
51 | struct cxlflash_cfg *cfg = afu->parent; | |
52 | struct device *dev = &cfg->dev->dev; | |
c21e0bbf MO |
53 | struct sisl_ioarcb *ioarcb; |
54 | struct sisl_ioasa *ioasa; | |
8396012f | 55 | u32 resid; |
c21e0bbf MO |
56 | |
57 | if (unlikely(!cmd)) | |
58 | return; | |
59 | ||
60 | ioarcb = &(cmd->rcb); | |
61 | ioasa = &(cmd->sa); | |
62 | ||
63 | if (ioasa->rc.flags & SISL_RC_FLAGS_UNDERRUN) { | |
8396012f MO |
64 | resid = ioasa->resid; |
65 | scsi_set_resid(scp, resid); | |
88d33628 MO |
66 | dev_dbg(dev, "%s: cmd underrun cmd = %p scp = %p, resid = %d\n", |
67 | __func__, cmd, scp, resid); | |
c21e0bbf MO |
68 | } |
69 | ||
70 | if (ioasa->rc.flags & SISL_RC_FLAGS_OVERRUN) { | |
88d33628 MO |
71 | dev_dbg(dev, "%s: cmd underrun cmd = %p scp = %p\n", |
72 | __func__, cmd, scp); | |
c21e0bbf MO |
73 | scp->result = (DID_ERROR << 16); |
74 | } | |
75 | ||
88d33628 MO |
76 | dev_dbg(dev, "%s: cmd failed afu_rc=%02x scsi_rc=%02x fc_rc=%02x " |
77 | "afu_extra=%02x scsi_extra=%02x fc_extra=%02x\n", __func__, | |
78 | ioasa->rc.afu_rc, ioasa->rc.scsi_rc, ioasa->rc.fc_rc, | |
79 | ioasa->afu_extra, ioasa->scsi_extra, ioasa->fc_extra); | |
c21e0bbf MO |
80 | |
81 | if (ioasa->rc.scsi_rc) { | |
82 | /* We have a SCSI status */ | |
83 | if (ioasa->rc.flags & SISL_RC_FLAGS_SENSE_VALID) { | |
84 | memcpy(scp->sense_buffer, ioasa->sense_data, | |
85 | SISL_SENSE_DATA_LEN); | |
86 | scp->result = ioasa->rc.scsi_rc; | |
87 | } else | |
88 | scp->result = ioasa->rc.scsi_rc | (DID_ERROR << 16); | |
89 | } | |
90 | ||
91 | /* | |
92 | * We encountered an error. Set scp->result based on nature | |
93 | * of error. | |
94 | */ | |
95 | if (ioasa->rc.fc_rc) { | |
96 | /* We have an FC status */ | |
97 | switch (ioasa->rc.fc_rc) { | |
98 | case SISL_FC_RC_LINKDOWN: | |
99 | scp->result = (DID_REQUEUE << 16); | |
100 | break; | |
101 | case SISL_FC_RC_RESID: | |
102 | /* This indicates an FCP resid underrun */ | |
103 | if (!(ioasa->rc.flags & SISL_RC_FLAGS_OVERRUN)) { | |
104 | /* If the SISL_RC_FLAGS_OVERRUN flag was set, | |
105 | * then we will handle this error else where. | |
106 | * If not then we must handle it here. | |
8396012f | 107 | * This is probably an AFU bug. |
c21e0bbf MO |
108 | */ |
109 | scp->result = (DID_ERROR << 16); | |
110 | } | |
111 | break; | |
112 | case SISL_FC_RC_RESIDERR: | |
113 | /* Resid mismatch between adapter and device */ | |
114 | case SISL_FC_RC_TGTABORT: | |
115 | case SISL_FC_RC_ABORTOK: | |
116 | case SISL_FC_RC_ABORTFAIL: | |
117 | case SISL_FC_RC_NOLOGI: | |
118 | case SISL_FC_RC_ABORTPEND: | |
119 | case SISL_FC_RC_WRABORTPEND: | |
120 | case SISL_FC_RC_NOEXP: | |
121 | case SISL_FC_RC_INUSE: | |
122 | scp->result = (DID_ERROR << 16); | |
123 | break; | |
124 | } | |
125 | } | |
126 | ||
127 | if (ioasa->rc.afu_rc) { | |
128 | /* We have an AFU error */ | |
129 | switch (ioasa->rc.afu_rc) { | |
130 | case SISL_AFU_RC_NO_CHANNELS: | |
8396012f | 131 | scp->result = (DID_NO_CONNECT << 16); |
c21e0bbf MO |
132 | break; |
133 | case SISL_AFU_RC_DATA_DMA_ERR: | |
134 | switch (ioasa->afu_extra) { | |
135 | case SISL_AFU_DMA_ERR_PAGE_IN: | |
136 | /* Retry */ | |
137 | scp->result = (DID_IMM_RETRY << 16); | |
138 | break; | |
139 | case SISL_AFU_DMA_ERR_INVALID_EA: | |
140 | default: | |
141 | scp->result = (DID_ERROR << 16); | |
142 | } | |
143 | break; | |
144 | case SISL_AFU_RC_OUT_OF_DATA_BUFS: | |
145 | /* Retry */ | |
146 | scp->result = (DID_ALLOC_FAILURE << 16); | |
147 | break; | |
148 | default: | |
149 | scp->result = (DID_ERROR << 16); | |
150 | } | |
151 | } | |
152 | } | |
153 | ||
154 | /** | |
155 | * cmd_complete() - command completion handler | |
156 | * @cmd: AFU command that has completed. | |
157 | * | |
158 | * Prepares and submits command that has either completed or timed out to | |
159 | * the SCSI stack. Checks AFU command back into command pool for non-internal | |
fe7f9698 | 160 | * (cmd->scp populated) commands. |
c21e0bbf MO |
161 | */ |
162 | static void cmd_complete(struct afu_cmd *cmd) | |
163 | { | |
164 | struct scsi_cmnd *scp; | |
c21e0bbf MO |
165 | ulong lock_flags; |
166 | struct afu *afu = cmd->parent; | |
167 | struct cxlflash_cfg *cfg = afu->parent; | |
88d33628 | 168 | struct device *dev = &cfg->dev->dev; |
d732d14f | 169 | struct hwq *hwq = get_hwq(afu, cmd->hwq_index); |
c21e0bbf MO |
170 | bool cmd_is_tmf; |
171 | ||
d732d14f UK |
172 | spin_lock_irqsave(&hwq->hsq_slock, lock_flags); |
173 | list_del(&cmd->list); | |
174 | spin_unlock_irqrestore(&hwq->hsq_slock, lock_flags); | |
175 | ||
fe7f9698 MO |
176 | if (cmd->scp) { |
177 | scp = cmd->scp; | |
8396012f | 178 | if (unlikely(cmd->sa.ioasc)) |
c21e0bbf MO |
179 | process_cmd_err(cmd, scp); |
180 | else | |
181 | scp->result = (DID_OK << 16); | |
182 | ||
c21e0bbf | 183 | cmd_is_tmf = cmd->cmd_tmf; |
c21e0bbf | 184 | |
88d33628 MO |
185 | dev_dbg_ratelimited(dev, "%s:scp=%p result=%08x ioasc=%08x\n", |
186 | __func__, scp, scp->result, cmd->sa.ioasc); | |
c21e0bbf | 187 | |
c21e0bbf MO |
188 | scp->scsi_done(scp); |
189 | ||
190 | if (cmd_is_tmf) { | |
018d1dc9 | 191 | spin_lock_irqsave(&cfg->tmf_slock, lock_flags); |
c21e0bbf MO |
192 | cfg->tmf_active = false; |
193 | wake_up_all_locked(&cfg->tmf_waitq); | |
018d1dc9 | 194 | spin_unlock_irqrestore(&cfg->tmf_slock, lock_flags); |
c21e0bbf MO |
195 | } |
196 | } else | |
197 | complete(&cmd->cevent); | |
198 | } | |
199 | ||
2450a5e3 UK |
200 | /** |
201 | * flush_pending_cmds() - flush all pending commands on this hardware queue | |
202 | * @hwq: Hardware queue to flush. | |
203 | * | |
204 | * The hardware send queue lock associated with this hardware queue must be | |
205 | * held when calling this routine. | |
206 | */ | |
207 | static void flush_pending_cmds(struct hwq *hwq) | |
208 | { | |
209 | struct afu_cmd *cmd, *tmp; | |
210 | struct scsi_cmnd *scp; | |
211 | ||
212 | list_for_each_entry_safe(cmd, tmp, &hwq->pending_cmds, list) { | |
213 | /* Bypass command when on a doneq, cmd_complete() will handle */ | |
214 | if (!list_empty(&cmd->queue)) | |
215 | continue; | |
216 | ||
217 | list_del(&cmd->list); | |
218 | ||
219 | if (cmd->scp) { | |
220 | scp = cmd->scp; | |
221 | scp->result = (DID_IMM_RETRY << 16); | |
222 | scp->scsi_done(scp); | |
223 | } else { | |
224 | cmd->cmd_aborted = true; | |
225 | complete(&cmd->cevent); | |
226 | } | |
227 | } | |
228 | } | |
229 | ||
15305514 | 230 | /** |
ddc869e9 UK |
231 | * context_reset() - reset context via specified register |
232 | * @hwq: Hardware queue owning the context to be reset. | |
74579cfb | 233 | * @reset_reg: MMIO register to perform reset. |
ddc869e9 | 234 | * |
4ab47257 UK |
235 | * When the reset is successful, the SISLite specification guarantees that |
236 | * the AFU has aborted all currently pending I/O. Accordingly, these commands | |
237 | * must be flushed. | |
238 | * | |
ddc869e9 | 239 | * Return: 0 on success, -errno on failure |
15305514 | 240 | */ |
ddc869e9 | 241 | static int context_reset(struct hwq *hwq, __be64 __iomem *reset_reg) |
15305514 | 242 | { |
ddc869e9 | 243 | struct cxlflash_cfg *cfg = hwq->afu->parent; |
3d2f617d | 244 | struct device *dev = &cfg->dev->dev; |
ddc869e9 UK |
245 | int rc = -ETIMEDOUT; |
246 | int nretry = 0; | |
247 | u64 val = 0x1; | |
4ab47257 | 248 | ulong lock_flags; |
15305514 | 249 | |
ddc869e9 | 250 | dev_dbg(dev, "%s: hwq=%p\n", __func__, hwq); |
15305514 | 251 | |
4ab47257 UK |
252 | spin_lock_irqsave(&hwq->hsq_slock, lock_flags); |
253 | ||
ddc869e9 | 254 | writeq_be(val, reset_reg); |
15305514 | 255 | do { |
ddc869e9 UK |
256 | val = readq_be(reset_reg); |
257 | if ((val & 0x1) == 0x0) { | |
258 | rc = 0; | |
15305514 | 259 | break; |
ddc869e9 UK |
260 | } |
261 | ||
15305514 | 262 | /* Double delay each time */ |
ea765431 | 263 | udelay(1 << nretry); |
15305514 | 264 | } while (nretry++ < MC_ROOM_RETRY_CNT); |
3d2f617d | 265 | |
4ab47257 UK |
266 | if (!rc) |
267 | flush_pending_cmds(hwq); | |
268 | ||
269 | spin_unlock_irqrestore(&hwq->hsq_slock, lock_flags); | |
270 | ||
ddc869e9 UK |
271 | dev_dbg(dev, "%s: returning rc=%d, val=%016llx nretry=%d\n", |
272 | __func__, rc, val, nretry); | |
273 | return rc; | |
15305514 MO |
274 | } |
275 | ||
74579cfb | 276 | /** |
ddc869e9 UK |
277 | * context_reset_ioarrin() - reset context via IOARRIN register |
278 | * @hwq: Hardware queue owning the context to be reset. | |
279 | * | |
280 | * Return: 0 on success, -errno on failure | |
74579cfb | 281 | */ |
ddc869e9 | 282 | static int context_reset_ioarrin(struct hwq *hwq) |
74579cfb | 283 | { |
ddc869e9 | 284 | return context_reset(hwq, &hwq->host_map->ioarrin); |
74579cfb MO |
285 | } |
286 | ||
bae0ac69 | 287 | /** |
ddc869e9 UK |
288 | * context_reset_sq() - reset context via SQ_CONTEXT_RESET register |
289 | * @hwq: Hardware queue owning the context to be reset. | |
290 | * | |
291 | * Return: 0 on success, -errno on failure | |
bae0ac69 | 292 | */ |
ddc869e9 | 293 | static int context_reset_sq(struct hwq *hwq) |
bae0ac69 | 294 | { |
ddc869e9 | 295 | return context_reset(hwq, &hwq->host_map->sq_ctx_reset); |
bae0ac69 MO |
296 | } |
297 | ||
15305514 | 298 | /** |
48b4be36 | 299 | * send_cmd_ioarrin() - sends an AFU command via IOARRIN register |
15305514 MO |
300 | * @afu: AFU associated with the host. |
301 | * @cmd: AFU command to send. | |
302 | * | |
303 | * Return: | |
1284fb0c | 304 | * 0 on success, SCSI_MLQUEUE_HOST_BUSY on failure |
15305514 | 305 | */ |
48b4be36 | 306 | static int send_cmd_ioarrin(struct afu *afu, struct afu_cmd *cmd) |
15305514 MO |
307 | { |
308 | struct cxlflash_cfg *cfg = afu->parent; | |
309 | struct device *dev = &cfg->dev->dev; | |
a583d00a | 310 | struct hwq *hwq = get_hwq(afu, cmd->hwq_index); |
15305514 | 311 | int rc = 0; |
11f7b184 UK |
312 | s64 room; |
313 | ulong lock_flags; | |
15305514 MO |
314 | |
315 | /* | |
11f7b184 UK |
316 | * To avoid the performance penalty of MMIO, spread the update of |
317 | * 'room' over multiple commands. | |
15305514 | 318 | */ |
edc034e8 | 319 | spin_lock_irqsave(&hwq->hsq_slock, lock_flags); |
a583d00a UK |
320 | if (--hwq->room < 0) { |
321 | room = readq_be(&hwq->host_map->cmd_room); | |
11f7b184 UK |
322 | if (room <= 0) { |
323 | dev_dbg_ratelimited(dev, "%s: no cmd_room to send " | |
324 | "0x%02X, room=0x%016llX\n", | |
325 | __func__, cmd->rcb.cdb[0], room); | |
a583d00a | 326 | hwq->room = 0; |
11f7b184 UK |
327 | rc = SCSI_MLQUEUE_HOST_BUSY; |
328 | goto out; | |
15305514 | 329 | } |
a583d00a | 330 | hwq->room = room - 1; |
15305514 MO |
331 | } |
332 | ||
d732d14f | 333 | list_add(&cmd->list, &hwq->pending_cmds); |
a583d00a | 334 | writeq_be((u64)&cmd->rcb, &hwq->host_map->ioarrin); |
15305514 | 335 | out: |
edc034e8 | 336 | spin_unlock_irqrestore(&hwq->hsq_slock, lock_flags); |
88d33628 MO |
337 | dev_dbg(dev, "%s: cmd=%p len=%u ea=%016llx rc=%d\n", __func__, |
338 | cmd, cmd->rcb.data_len, cmd->rcb.data_ea, rc); | |
15305514 | 339 | return rc; |
15305514 MO |
340 | } |
341 | ||
bae0ac69 MO |
342 | /** |
343 | * send_cmd_sq() - sends an AFU command via SQ ring | |
344 | * @afu: AFU associated with the host. | |
345 | * @cmd: AFU command to send. | |
346 | * | |
347 | * Return: | |
348 | * 0 on success, SCSI_MLQUEUE_HOST_BUSY on failure | |
349 | */ | |
350 | static int send_cmd_sq(struct afu *afu, struct afu_cmd *cmd) | |
351 | { | |
352 | struct cxlflash_cfg *cfg = afu->parent; | |
353 | struct device *dev = &cfg->dev->dev; | |
a583d00a | 354 | struct hwq *hwq = get_hwq(afu, cmd->hwq_index); |
bae0ac69 MO |
355 | int rc = 0; |
356 | int newval; | |
357 | ulong lock_flags; | |
358 | ||
a583d00a | 359 | newval = atomic_dec_if_positive(&hwq->hsq_credits); |
bae0ac69 MO |
360 | if (newval <= 0) { |
361 | rc = SCSI_MLQUEUE_HOST_BUSY; | |
362 | goto out; | |
363 | } | |
364 | ||
365 | cmd->rcb.ioasa = &cmd->sa; | |
366 | ||
a583d00a | 367 | spin_lock_irqsave(&hwq->hsq_slock, lock_flags); |
bae0ac69 | 368 | |
a583d00a UK |
369 | *hwq->hsq_curr = cmd->rcb; |
370 | if (hwq->hsq_curr < hwq->hsq_end) | |
371 | hwq->hsq_curr++; | |
bae0ac69 | 372 | else |
a583d00a | 373 | hwq->hsq_curr = hwq->hsq_start; |
d732d14f UK |
374 | |
375 | list_add(&cmd->list, &hwq->pending_cmds); | |
a583d00a | 376 | writeq_be((u64)hwq->hsq_curr, &hwq->host_map->sq_tail); |
bae0ac69 | 377 | |
a583d00a | 378 | spin_unlock_irqrestore(&hwq->hsq_slock, lock_flags); |
bae0ac69 | 379 | out: |
88d33628 MO |
380 | dev_dbg(dev, "%s: cmd=%p len=%u ea=%016llx ioasa=%p rc=%d curr=%p " |
381 | "head=%016llx tail=%016llx\n", __func__, cmd, cmd->rcb.data_len, | |
a583d00a UK |
382 | cmd->rcb.data_ea, cmd->rcb.ioasa, rc, hwq->hsq_curr, |
383 | readq_be(&hwq->host_map->sq_head), | |
384 | readq_be(&hwq->host_map->sq_tail)); | |
bae0ac69 MO |
385 | return rc; |
386 | } | |
387 | ||
15305514 MO |
388 | /** |
389 | * wait_resp() - polls for a response or timeout to a sent AFU command | |
390 | * @afu: AFU associated with the host. | |
391 | * @cmd: AFU command that was sent. | |
9ba848ac | 392 | * |
ddc869e9 | 393 | * Return: 0 on success, -errno on failure |
15305514 | 394 | */ |
9ba848ac | 395 | static int wait_resp(struct afu *afu, struct afu_cmd *cmd) |
15305514 | 396 | { |
88d33628 MO |
397 | struct cxlflash_cfg *cfg = afu->parent; |
398 | struct device *dev = &cfg->dev->dev; | |
9ba848ac | 399 | int rc = 0; |
15305514 MO |
400 | ulong timeout = msecs_to_jiffies(cmd->rcb.timeout * 2 * 1000); |
401 | ||
402 | timeout = wait_for_completion_timeout(&cmd->cevent, timeout); | |
ddc869e9 UK |
403 | if (!timeout) |
404 | rc = -ETIMEDOUT; | |
15305514 | 405 | |
2450a5e3 UK |
406 | if (cmd->cmd_aborted) |
407 | rc = -EAGAIN; | |
408 | ||
9ba848ac | 409 | if (unlikely(cmd->sa.ioasc != 0)) { |
88d33628 MO |
410 | dev_err(dev, "%s: cmd %02x failed, ioasc=%08x\n", |
411 | __func__, cmd->rcb.cdb[0], cmd->sa.ioasc); | |
ddc869e9 | 412 | rc = -EIO; |
9ba848ac MO |
413 | } |
414 | ||
415 | return rc; | |
15305514 MO |
416 | } |
417 | ||
8c052e9e MO |
418 | /** |
419 | * cmd_to_target_hwq() - selects a target hardware queue for a SCSI command | |
420 | * @host: SCSI host associated with device. | |
421 | * @scp: SCSI command to send. | |
422 | * @afu: SCSI command to send. | |
423 | * | |
424 | * Hashes a command based upon the hardware queue mode. | |
425 | * | |
426 | * Return: Trusted index of target hardware queue | |
427 | */ | |
428 | static u32 cmd_to_target_hwq(struct Scsi_Host *host, struct scsi_cmnd *scp, | |
429 | struct afu *afu) | |
430 | { | |
431 | u32 tag; | |
432 | u32 hwq = 0; | |
433 | ||
434 | if (afu->num_hwqs == 1) | |
435 | return 0; | |
436 | ||
437 | switch (afu->hwq_mode) { | |
438 | case HWQ_MODE_RR: | |
439 | hwq = afu->hwq_rr_count++ % afu->num_hwqs; | |
440 | break; | |
441 | case HWQ_MODE_TAG: | |
442 | tag = blk_mq_unique_tag(scp->request); | |
443 | hwq = blk_mq_unique_tag_to_hwq(tag); | |
444 | break; | |
445 | case HWQ_MODE_CPU: | |
446 | hwq = smp_processor_id() % afu->num_hwqs; | |
447 | break; | |
448 | default: | |
449 | WARN_ON_ONCE(1); | |
450 | } | |
451 | ||
452 | return hwq; | |
453 | } | |
454 | ||
c21e0bbf MO |
455 | /** |
456 | * send_tmf() - sends a Task Management Function (TMF) | |
457 | * @afu: AFU to checkout from. | |
458 | * @scp: SCSI command from stack. | |
459 | * @tmfcmd: TMF command to send. | |
460 | * | |
461 | * Return: | |
1284fb0c | 462 | * 0 on success, SCSI_MLQUEUE_HOST_BUSY on failure |
c21e0bbf MO |
463 | */ |
464 | static int send_tmf(struct afu *afu, struct scsi_cmnd *scp, u64 tmfcmd) | |
465 | { | |
8c052e9e MO |
466 | struct Scsi_Host *host = scp->device->host; |
467 | struct cxlflash_cfg *cfg = shost_priv(host); | |
d4ace351 | 468 | struct afu_cmd *cmd = sc_to_afucz(scp); |
4392ba49 | 469 | struct device *dev = &cfg->dev->dev; |
8c052e9e MO |
470 | int hwq_index = cmd_to_target_hwq(host, scp, afu); |
471 | struct hwq *hwq = get_hwq(afu, hwq_index); | |
c21e0bbf MO |
472 | ulong lock_flags; |
473 | int rc = 0; | |
018d1dc9 | 474 | ulong to; |
c21e0bbf | 475 | |
018d1dc9 MO |
476 | /* When Task Management Function is active do not send another */ |
477 | spin_lock_irqsave(&cfg->tmf_slock, lock_flags); | |
c21e0bbf | 478 | if (cfg->tmf_active) |
018d1dc9 MO |
479 | wait_event_interruptible_lock_irq(cfg->tmf_waitq, |
480 | !cfg->tmf_active, | |
481 | cfg->tmf_slock); | |
c21e0bbf | 482 | cfg->tmf_active = true; |
018d1dc9 | 483 | spin_unlock_irqrestore(&cfg->tmf_slock, lock_flags); |
c21e0bbf | 484 | |
fe7f9698 | 485 | cmd->scp = scp; |
d4ace351 MO |
486 | cmd->parent = afu; |
487 | cmd->cmd_tmf = true; | |
8c052e9e | 488 | cmd->hwq_index = hwq_index; |
d4ace351 | 489 | |
a583d00a | 490 | cmd->rcb.ctx_id = hwq->ctx_hndl; |
5fbb96c8 | 491 | cmd->rcb.msi = SISL_MSI_RRQ_UPDATED; |
e8e17ea6 | 492 | cmd->rcb.port_sel = CHAN2PORTMASK(scp->device->channel); |
c21e0bbf | 493 | cmd->rcb.lun_id = lun_to_lunid(scp->device->lun); |
c21e0bbf | 494 | cmd->rcb.req_flags = (SISL_REQ_FLAGS_PORT_LUN_ID | |
d4ace351 MO |
495 | SISL_REQ_FLAGS_SUP_UNDERRUN | |
496 | SISL_REQ_FLAGS_TMF_CMD); | |
c21e0bbf MO |
497 | memcpy(cmd->rcb.cdb, &tmfcmd, sizeof(tmfcmd)); |
498 | ||
48b4be36 | 499 | rc = afu->send_cmd(afu, cmd); |
c21e0bbf | 500 | if (unlikely(rc)) { |
018d1dc9 | 501 | spin_lock_irqsave(&cfg->tmf_slock, lock_flags); |
c21e0bbf | 502 | cfg->tmf_active = false; |
018d1dc9 | 503 | spin_unlock_irqrestore(&cfg->tmf_slock, lock_flags); |
c21e0bbf MO |
504 | goto out; |
505 | } | |
506 | ||
018d1dc9 MO |
507 | spin_lock_irqsave(&cfg->tmf_slock, lock_flags); |
508 | to = msecs_to_jiffies(5000); | |
509 | to = wait_event_interruptible_lock_irq_timeout(cfg->tmf_waitq, | |
510 | !cfg->tmf_active, | |
511 | cfg->tmf_slock, | |
512 | to); | |
513 | if (!to) { | |
514 | cfg->tmf_active = false; | |
88d33628 | 515 | dev_err(dev, "%s: TMF timed out\n", __func__); |
018d1dc9 MO |
516 | rc = -1; |
517 | } | |
518 | spin_unlock_irqrestore(&cfg->tmf_slock, lock_flags); | |
c21e0bbf MO |
519 | out: |
520 | return rc; | |
521 | } | |
522 | ||
523 | /** | |
524 | * cxlflash_driver_info() - information handler for this host driver | |
525 | * @host: SCSI host associated with device. | |
526 | * | |
527 | * Return: A string describing the device. | |
528 | */ | |
529 | static const char *cxlflash_driver_info(struct Scsi_Host *host) | |
530 | { | |
531 | return CXLFLASH_ADAPTER_NAME; | |
532 | } | |
533 | ||
534 | /** | |
535 | * cxlflash_queuecommand() - sends a mid-layer request | |
536 | * @host: SCSI host associated with device. | |
537 | * @scp: SCSI command to send. | |
538 | * | |
1284fb0c | 539 | * Return: 0 on success, SCSI_MLQUEUE_HOST_BUSY on failure |
c21e0bbf MO |
540 | */ |
541 | static int cxlflash_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *scp) | |
542 | { | |
88d33628 | 543 | struct cxlflash_cfg *cfg = shost_priv(host); |
c21e0bbf | 544 | struct afu *afu = cfg->afu; |
4392ba49 | 545 | struct device *dev = &cfg->dev->dev; |
5fbb96c8 | 546 | struct afu_cmd *cmd = sc_to_afucz(scp); |
9d89326c | 547 | struct scatterlist *sg = scsi_sglist(scp); |
8c052e9e MO |
548 | int hwq_index = cmd_to_target_hwq(host, scp, afu); |
549 | struct hwq *hwq = get_hwq(afu, hwq_index); | |
9d89326c | 550 | u16 req_flags = SISL_REQ_FLAGS_SUP_UNDERRUN; |
c21e0bbf | 551 | ulong lock_flags; |
c21e0bbf MO |
552 | int rc = 0; |
553 | ||
4392ba49 | 554 | dev_dbg_ratelimited(dev, "%s: (scp=%p) %d/%d/%d/%llu " |
88d33628 | 555 | "cdb=(%08x-%08x-%08x-%08x)\n", |
4392ba49 MO |
556 | __func__, scp, host->host_no, scp->device->channel, |
557 | scp->device->id, scp->device->lun, | |
558 | get_unaligned_be32(&((u32 *)scp->cmnd)[0]), | |
559 | get_unaligned_be32(&((u32 *)scp->cmnd)[1]), | |
560 | get_unaligned_be32(&((u32 *)scp->cmnd)[2]), | |
561 | get_unaligned_be32(&((u32 *)scp->cmnd)[3])); | |
c21e0bbf | 562 | |
018d1dc9 MO |
563 | /* |
564 | * If a Task Management Function is active, wait for it to complete | |
c21e0bbf MO |
565 | * before continuing with regular commands. |
566 | */ | |
018d1dc9 | 567 | spin_lock_irqsave(&cfg->tmf_slock, lock_flags); |
c21e0bbf | 568 | if (cfg->tmf_active) { |
018d1dc9 | 569 | spin_unlock_irqrestore(&cfg->tmf_slock, lock_flags); |
c21e0bbf MO |
570 | rc = SCSI_MLQUEUE_HOST_BUSY; |
571 | goto out; | |
572 | } | |
018d1dc9 | 573 | spin_unlock_irqrestore(&cfg->tmf_slock, lock_flags); |
c21e0bbf | 574 | |
5cdac81a | 575 | switch (cfg->state) { |
f92ba507 MO |
576 | case STATE_PROBING: |
577 | case STATE_PROBED: | |
439e85c1 | 578 | case STATE_RESET: |
88d33628 | 579 | dev_dbg_ratelimited(dev, "%s: device is in reset\n", __func__); |
5cdac81a MO |
580 | rc = SCSI_MLQUEUE_HOST_BUSY; |
581 | goto out; | |
582 | case STATE_FAILTERM: | |
88d33628 | 583 | dev_dbg_ratelimited(dev, "%s: device has failed\n", __func__); |
5cdac81a MO |
584 | scp->result = (DID_NO_CONNECT << 16); |
585 | scp->scsi_done(scp); | |
586 | rc = 0; | |
587 | goto out; | |
588 | default: | |
589 | break; | |
590 | } | |
591 | ||
9d89326c | 592 | if (likely(sg)) { |
fdc3f382 MO |
593 | cmd->rcb.data_len = sg->length; |
594 | cmd->rcb.data_ea = (uintptr_t)sg_virt(sg); | |
9d89326c | 595 | } |
c21e0bbf | 596 | |
fe7f9698 | 597 | cmd->scp = scp; |
5fbb96c8 | 598 | cmd->parent = afu; |
8c052e9e | 599 | cmd->hwq_index = hwq_index; |
c21e0bbf | 600 | |
a583d00a | 601 | cmd->rcb.ctx_id = hwq->ctx_hndl; |
9d89326c | 602 | cmd->rcb.msi = SISL_MSI_RRQ_UPDATED; |
e8e17ea6 | 603 | cmd->rcb.port_sel = CHAN2PORTMASK(scp->device->channel); |
9d89326c | 604 | cmd->rcb.lun_id = lun_to_lunid(scp->device->lun); |
c21e0bbf | 605 | |
9d89326c MO |
606 | if (scp->sc_data_direction == DMA_TO_DEVICE) |
607 | req_flags |= SISL_REQ_FLAGS_HOST_WRITE; | |
c21e0bbf | 608 | |
9d89326c | 609 | cmd->rcb.req_flags = req_flags; |
c21e0bbf MO |
610 | memcpy(cmd->rcb.cdb, scp->cmnd, sizeof(cmd->rcb.cdb)); |
611 | ||
48b4be36 | 612 | rc = afu->send_cmd(afu, cmd); |
c21e0bbf MO |
613 | out: |
614 | return rc; | |
615 | } | |
616 | ||
617 | /** | |
15305514 | 618 | * cxlflash_wait_for_pci_err_recovery() - wait for error recovery during probe |
1284fb0c | 619 | * @cfg: Internal structure associated with the host. |
c21e0bbf | 620 | */ |
15305514 | 621 | static void cxlflash_wait_for_pci_err_recovery(struct cxlflash_cfg *cfg) |
c21e0bbf | 622 | { |
15305514 | 623 | struct pci_dev *pdev = cfg->dev; |
c21e0bbf | 624 | |
15305514 MO |
625 | if (pci_channel_offline(pdev)) |
626 | wait_event_timeout(cfg->reset_waitq, | |
627 | !pci_channel_offline(pdev), | |
628 | CXLFLASH_PCI_ERROR_RECOVERY_TIMEOUT); | |
c21e0bbf MO |
629 | } |
630 | ||
631 | /** | |
15305514 | 632 | * free_mem() - free memory associated with the AFU |
1284fb0c | 633 | * @cfg: Internal structure associated with the host. |
c21e0bbf | 634 | */ |
15305514 | 635 | static void free_mem(struct cxlflash_cfg *cfg) |
c21e0bbf | 636 | { |
15305514 | 637 | struct afu *afu = cfg->afu; |
c21e0bbf | 638 | |
15305514 | 639 | if (cfg->afu) { |
15305514 MO |
640 | free_pages((ulong)afu, get_order(sizeof(struct afu))); |
641 | cfg->afu = NULL; | |
5cdac81a | 642 | } |
c21e0bbf MO |
643 | } |
644 | ||
3b4f03cd UK |
645 | /** |
646 | * cxlflash_reset_sync() - synchronizing point for asynchronous resets | |
647 | * @cfg: Internal structure associated with the host. | |
648 | */ | |
649 | static void cxlflash_reset_sync(struct cxlflash_cfg *cfg) | |
650 | { | |
651 | if (cfg->async_reset_cookie == 0) | |
652 | return; | |
653 | ||
654 | /* Wait until all async calls prior to this cookie have completed */ | |
655 | async_synchronize_cookie(cfg->async_reset_cookie + 1); | |
656 | cfg->async_reset_cookie = 0; | |
657 | } | |
658 | ||
c21e0bbf | 659 | /** |
15305514 | 660 | * stop_afu() - stops the AFU command timers and unmaps the MMIO space |
1284fb0c | 661 | * @cfg: Internal structure associated with the host. |
c21e0bbf | 662 | * |
15305514 | 663 | * Safe to call with AFU in a partially allocated/initialized state. |
ee91e332 | 664 | * |
d940f9ae | 665 | * Cancels scheduled worker threads, waits for any active internal AFU |
2588f222 | 666 | * commands to timeout, disables IRQ polling and then unmaps the MMIO space. |
c21e0bbf | 667 | */ |
15305514 | 668 | static void stop_afu(struct cxlflash_cfg *cfg) |
c21e0bbf | 669 | { |
15305514 | 670 | struct afu *afu = cfg->afu; |
a583d00a UK |
671 | struct hwq *hwq; |
672 | int i; | |
c21e0bbf | 673 | |
d940f9ae | 674 | cancel_work_sync(&cfg->work_q); |
3b4f03cd UK |
675 | if (!current_is_async()) |
676 | cxlflash_reset_sync(cfg); | |
d940f9ae | 677 | |
15305514 | 678 | if (likely(afu)) { |
de01283b MO |
679 | while (atomic_read(&afu->cmds_active)) |
680 | ssleep(1); | |
a583d00a UK |
681 | |
682 | if (afu_is_irqpoll_enabled(afu)) { | |
bb85ef68 | 683 | for (i = 0; i < afu->num_hwqs; i++) { |
a583d00a UK |
684 | hwq = get_hwq(afu, i); |
685 | ||
686 | irq_poll_disable(&hwq->irqpoll); | |
687 | } | |
688 | } | |
689 | ||
c21e0bbf | 690 | if (likely(afu->afu_map)) { |
1786f4a0 | 691 | cxl_psa_unmap((void __iomem *)afu->afu_map); |
c21e0bbf MO |
692 | afu->afu_map = NULL; |
693 | } | |
694 | } | |
695 | } | |
696 | ||
697 | /** | |
9526f360 | 698 | * term_intr() - disables all AFU interrupts |
1284fb0c | 699 | * @cfg: Internal structure associated with the host. |
c21e0bbf | 700 | * @level: Depth of allocation, where to begin waterfall tear down. |
a583d00a | 701 | * @index: Index of the hardware queue. |
c21e0bbf MO |
702 | * |
703 | * Safe to call with AFU/MC in partially allocated/initialized state. | |
704 | */ | |
a583d00a UK |
705 | static void term_intr(struct cxlflash_cfg *cfg, enum undo_level level, |
706 | u32 index) | |
c21e0bbf | 707 | { |
c21e0bbf | 708 | struct afu *afu = cfg->afu; |
4392ba49 | 709 | struct device *dev = &cfg->dev->dev; |
a583d00a | 710 | struct hwq *hwq; |
c21e0bbf | 711 | |
a583d00a UK |
712 | if (!afu) { |
713 | dev_err(dev, "%s: returning with NULL afu\n", __func__); | |
714 | return; | |
715 | } | |
716 | ||
717 | hwq = get_hwq(afu, index); | |
718 | ||
719 | if (!hwq->ctx) { | |
720 | dev_err(dev, "%s: returning with NULL MC\n", __func__); | |
c21e0bbf MO |
721 | return; |
722 | } | |
723 | ||
724 | switch (level) { | |
c21e0bbf | 725 | case UNMAP_THREE: |
a583d00a UK |
726 | /* SISL_MSI_ASYNC_ERROR is setup only for the primary HWQ */ |
727 | if (index == PRIMARY_HWQ) | |
728 | cxl_unmap_afu_irq(hwq->ctx, 3, hwq); | |
c21e0bbf | 729 | case UNMAP_TWO: |
a583d00a | 730 | cxl_unmap_afu_irq(hwq->ctx, 2, hwq); |
c21e0bbf | 731 | case UNMAP_ONE: |
a583d00a | 732 | cxl_unmap_afu_irq(hwq->ctx, 1, hwq); |
c21e0bbf | 733 | case FREE_IRQ: |
a583d00a | 734 | cxl_free_afu_irqs(hwq->ctx); |
9526f360 MK |
735 | /* fall through */ |
736 | case UNDO_NOOP: | |
737 | /* No action required */ | |
738 | break; | |
739 | } | |
740 | } | |
741 | ||
742 | /** | |
743 | * term_mc() - terminates the master context | |
744 | * @cfg: Internal structure associated with the host. | |
a583d00a | 745 | * @index: Index of the hardware queue. |
9526f360 MK |
746 | * |
747 | * Safe to call with AFU/MC in partially allocated/initialized state. | |
748 | */ | |
a583d00a | 749 | static void term_mc(struct cxlflash_cfg *cfg, u32 index) |
9526f360 | 750 | { |
9526f360 MK |
751 | struct afu *afu = cfg->afu; |
752 | struct device *dev = &cfg->dev->dev; | |
a583d00a | 753 | struct hwq *hwq; |
2450a5e3 | 754 | ulong lock_flags; |
9526f360 | 755 | |
a583d00a UK |
756 | if (!afu) { |
757 | dev_err(dev, "%s: returning with NULL afu\n", __func__); | |
9526f360 | 758 | return; |
c21e0bbf | 759 | } |
9526f360 | 760 | |
a583d00a UK |
761 | hwq = get_hwq(afu, index); |
762 | ||
763 | if (!hwq->ctx) { | |
764 | dev_err(dev, "%s: returning with NULL MC\n", __func__); | |
765 | return; | |
766 | } | |
767 | ||
768 | WARN_ON(cxl_stop_context(hwq->ctx)); | |
769 | if (index != PRIMARY_HWQ) | |
770 | WARN_ON(cxl_release_context(hwq->ctx)); | |
771 | hwq->ctx = NULL; | |
2450a5e3 UK |
772 | |
773 | spin_lock_irqsave(&hwq->hsq_slock, lock_flags); | |
774 | flush_pending_cmds(hwq); | |
775 | spin_unlock_irqrestore(&hwq->hsq_slock, lock_flags); | |
c21e0bbf MO |
776 | } |
777 | ||
778 | /** | |
779 | * term_afu() - terminates the AFU | |
1284fb0c | 780 | * @cfg: Internal structure associated with the host. |
c21e0bbf MO |
781 | * |
782 | * Safe to call with AFU/MC in partially allocated/initialized state. | |
783 | */ | |
784 | static void term_afu(struct cxlflash_cfg *cfg) | |
785 | { | |
88d33628 | 786 | struct device *dev = &cfg->dev->dev; |
a583d00a | 787 | int k; |
88d33628 | 788 | |
9526f360 MK |
789 | /* |
790 | * Tear down is carefully orchestrated to ensure | |
791 | * no interrupts can come in when the problem state | |
792 | * area is unmapped. | |
793 | * | |
a583d00a | 794 | * 1) Disable all AFU interrupts for each master |
9526f360 | 795 | * 2) Unmap the problem state area |
a583d00a | 796 | * 3) Stop each master context |
9526f360 | 797 | */ |
bb85ef68 | 798 | for (k = cfg->afu->num_hwqs - 1; k >= 0; k--) |
a583d00a UK |
799 | term_intr(cfg, UNMAP_THREE, k); |
800 | ||
c21e0bbf MO |
801 | if (cfg->afu) |
802 | stop_afu(cfg); | |
803 | ||
bb85ef68 | 804 | for (k = cfg->afu->num_hwqs - 1; k >= 0; k--) |
a583d00a | 805 | term_mc(cfg, k); |
6ded8b3c | 806 | |
88d33628 | 807 | dev_dbg(dev, "%s: returning\n", __func__); |
c21e0bbf MO |
808 | } |
809 | ||
704c4b0d UK |
810 | /** |
811 | * notify_shutdown() - notifies device of pending shutdown | |
812 | * @cfg: Internal structure associated with the host. | |
813 | * @wait: Whether to wait for shutdown processing to complete. | |
814 | * | |
815 | * This function will notify the AFU that the adapter is being shutdown | |
816 | * and will wait for shutdown processing to complete if wait is true. | |
817 | * This notification should flush pending I/Os to the device and halt | |
818 | * further I/Os until the next AFU reset is issued and device restarted. | |
819 | */ | |
820 | static void notify_shutdown(struct cxlflash_cfg *cfg, bool wait) | |
821 | { | |
822 | struct afu *afu = cfg->afu; | |
823 | struct device *dev = &cfg->dev->dev; | |
704c4b0d | 824 | struct dev_dependent_vals *ddv; |
c885d3fe | 825 | __be64 __iomem *fc_port_regs; |
704c4b0d UK |
826 | u64 reg, status; |
827 | int i, retry_cnt = 0; | |
828 | ||
829 | ddv = (struct dev_dependent_vals *)cfg->dev_id->driver_data; | |
830 | if (!(ddv->flags & CXLFLASH_NOTIFY_SHUTDOWN)) | |
831 | return; | |
832 | ||
1bd2b282 | 833 | if (!afu || !afu->afu_map) { |
88d33628 | 834 | dev_dbg(dev, "%s: Problem state area not mapped\n", __func__); |
1bd2b282 UK |
835 | return; |
836 | } | |
837 | ||
704c4b0d | 838 | /* Notify AFU */ |
66d4bce4 | 839 | for (i = 0; i < cfg->num_fc_ports; i++) { |
c885d3fe MO |
840 | fc_port_regs = get_fc_port_regs(cfg, i); |
841 | ||
842 | reg = readq_be(&fc_port_regs[FC_CONFIG2 / 8]); | |
704c4b0d | 843 | reg |= SISL_FC_SHUTDOWN_NORMAL; |
c885d3fe | 844 | writeq_be(reg, &fc_port_regs[FC_CONFIG2 / 8]); |
704c4b0d UK |
845 | } |
846 | ||
847 | if (!wait) | |
848 | return; | |
849 | ||
850 | /* Wait up to 1.5 seconds for shutdown processing to complete */ | |
66d4bce4 | 851 | for (i = 0; i < cfg->num_fc_ports; i++) { |
c885d3fe | 852 | fc_port_regs = get_fc_port_regs(cfg, i); |
704c4b0d | 853 | retry_cnt = 0; |
c885d3fe | 854 | |
704c4b0d | 855 | while (true) { |
c885d3fe | 856 | status = readq_be(&fc_port_regs[FC_STATUS / 8]); |
704c4b0d UK |
857 | if (status & SISL_STATUS_SHUTDOWN_COMPLETE) |
858 | break; | |
859 | if (++retry_cnt >= MC_RETRY_CNT) { | |
860 | dev_dbg(dev, "%s: port %d shutdown processing " | |
861 | "not yet completed\n", __func__, i); | |
862 | break; | |
863 | } | |
864 | msleep(100 * retry_cnt); | |
865 | } | |
866 | } | |
867 | } | |
868 | ||
f3d79b3e UK |
869 | /** |
870 | * cxlflash_get_minor() - gets the first available minor number | |
871 | * | |
872 | * Return: Unique minor number that can be used to create the character device. | |
873 | */ | |
874 | static int cxlflash_get_minor(void) | |
875 | { | |
876 | int minor; | |
877 | long bit; | |
878 | ||
879 | bit = find_first_zero_bit(cxlflash_minor, CXLFLASH_MAX_ADAPTERS); | |
880 | if (bit >= CXLFLASH_MAX_ADAPTERS) | |
881 | return -1; | |
882 | ||
883 | minor = bit & MINORMASK; | |
884 | set_bit(minor, cxlflash_minor); | |
885 | return minor; | |
886 | } | |
887 | ||
888 | /** | |
889 | * cxlflash_put_minor() - releases the minor number | |
890 | * @minor: Minor number that is no longer needed. | |
891 | */ | |
892 | static void cxlflash_put_minor(int minor) | |
893 | { | |
894 | clear_bit(minor, cxlflash_minor); | |
895 | } | |
896 | ||
897 | /** | |
898 | * cxlflash_release_chrdev() - release the character device for the host | |
899 | * @cfg: Internal structure associated with the host. | |
900 | */ | |
901 | static void cxlflash_release_chrdev(struct cxlflash_cfg *cfg) | |
902 | { | |
903 | put_device(cfg->chardev); | |
904 | device_unregister(cfg->chardev); | |
905 | cfg->chardev = NULL; | |
906 | cdev_del(&cfg->cdev); | |
907 | cxlflash_put_minor(MINOR(cfg->cdev.dev)); | |
908 | } | |
909 | ||
c21e0bbf MO |
910 | /** |
911 | * cxlflash_remove() - PCI entry point to tear down host | |
912 | * @pdev: PCI device associated with the host. | |
913 | * | |
f92ba507 MO |
914 | * Safe to use as a cleanup in partially allocated/initialized state. Note that |
915 | * the reset_waitq is flushed as part of the stop/termination of user contexts. | |
c21e0bbf MO |
916 | */ |
917 | static void cxlflash_remove(struct pci_dev *pdev) | |
918 | { | |
919 | struct cxlflash_cfg *cfg = pci_get_drvdata(pdev); | |
88d33628 | 920 | struct device *dev = &pdev->dev; |
c21e0bbf MO |
921 | ulong lock_flags; |
922 | ||
babf985d | 923 | if (!pci_is_enabled(pdev)) { |
88d33628 | 924 | dev_dbg(dev, "%s: Device is disabled\n", __func__); |
babf985d UK |
925 | return; |
926 | } | |
927 | ||
c21e0bbf MO |
928 | /* If a Task Management Function is active, wait for it to complete |
929 | * before continuing with remove. | |
930 | */ | |
018d1dc9 | 931 | spin_lock_irqsave(&cfg->tmf_slock, lock_flags); |
c21e0bbf | 932 | if (cfg->tmf_active) |
018d1dc9 MO |
933 | wait_event_interruptible_lock_irq(cfg->tmf_waitq, |
934 | !cfg->tmf_active, | |
935 | cfg->tmf_slock); | |
936 | spin_unlock_irqrestore(&cfg->tmf_slock, lock_flags); | |
c21e0bbf | 937 | |
704c4b0d UK |
938 | /* Notify AFU and wait for shutdown processing to complete */ |
939 | notify_shutdown(cfg, true); | |
940 | ||
5cdac81a | 941 | cfg->state = STATE_FAILTERM; |
65be2c79 | 942 | cxlflash_stop_term_user_contexts(cfg); |
5cdac81a | 943 | |
c21e0bbf | 944 | switch (cfg->init_state) { |
f3d79b3e UK |
945 | case INIT_STATE_CDEV: |
946 | cxlflash_release_chrdev(cfg); | |
c21e0bbf | 947 | case INIT_STATE_SCSI: |
65be2c79 | 948 | cxlflash_term_local_luns(cfg); |
c21e0bbf | 949 | scsi_remove_host(cfg->host); |
c21e0bbf | 950 | case INIT_STATE_AFU: |
b45cdbaf | 951 | term_afu(cfg); |
c21e0bbf | 952 | case INIT_STATE_PCI: |
c21e0bbf MO |
953 | pci_disable_device(pdev); |
954 | case INIT_STATE_NONE: | |
c21e0bbf | 955 | free_mem(cfg); |
8b5b1e87 | 956 | scsi_host_put(cfg->host); |
c21e0bbf MO |
957 | break; |
958 | } | |
959 | ||
88d33628 | 960 | dev_dbg(dev, "%s: returning\n", __func__); |
c21e0bbf MO |
961 | } |
962 | ||
963 | /** | |
964 | * alloc_mem() - allocates the AFU and its command pool | |
1284fb0c | 965 | * @cfg: Internal structure associated with the host. |
c21e0bbf MO |
966 | * |
967 | * A partially allocated state remains on failure. | |
968 | * | |
969 | * Return: | |
970 | * 0 on success | |
971 | * -ENOMEM on failure to allocate memory | |
972 | */ | |
973 | static int alloc_mem(struct cxlflash_cfg *cfg) | |
974 | { | |
975 | int rc = 0; | |
4392ba49 | 976 | struct device *dev = &cfg->dev->dev; |
c21e0bbf | 977 | |
bae0ac69 | 978 | /* AFU is ~28k, i.e. only one 64k page or up to seven 4k pages */ |
c21e0bbf MO |
979 | cfg->afu = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
980 | get_order(sizeof(struct afu))); | |
981 | if (unlikely(!cfg->afu)) { | |
4392ba49 MO |
982 | dev_err(dev, "%s: cannot get %d free pages\n", |
983 | __func__, get_order(sizeof(struct afu))); | |
c21e0bbf MO |
984 | rc = -ENOMEM; |
985 | goto out; | |
986 | } | |
987 | cfg->afu->parent = cfg; | |
bb85ef68 | 988 | cfg->afu->desired_hwqs = CXLFLASH_DEF_HWQS; |
c21e0bbf | 989 | cfg->afu->afu_map = NULL; |
c21e0bbf MO |
990 | out: |
991 | return rc; | |
992 | } | |
993 | ||
994 | /** | |
995 | * init_pci() - initializes the host as a PCI device | |
1284fb0c | 996 | * @cfg: Internal structure associated with the host. |
c21e0bbf | 997 | * |
1284fb0c | 998 | * Return: 0 on success, -errno on failure |
c21e0bbf MO |
999 | */ |
1000 | static int init_pci(struct cxlflash_cfg *cfg) | |
1001 | { | |
1002 | struct pci_dev *pdev = cfg->dev; | |
88d33628 | 1003 | struct device *dev = &cfg->dev->dev; |
c21e0bbf MO |
1004 | int rc = 0; |
1005 | ||
c21e0bbf MO |
1006 | rc = pci_enable_device(pdev); |
1007 | if (rc || pci_channel_offline(pdev)) { | |
1008 | if (pci_channel_offline(pdev)) { | |
1009 | cxlflash_wait_for_pci_err_recovery(cfg); | |
1010 | rc = pci_enable_device(pdev); | |
1011 | } | |
1012 | ||
1013 | if (rc) { | |
88d33628 | 1014 | dev_err(dev, "%s: Cannot enable adapter\n", __func__); |
c21e0bbf | 1015 | cxlflash_wait_for_pci_err_recovery(cfg); |
961487e4 | 1016 | goto out; |
c21e0bbf MO |
1017 | } |
1018 | } | |
1019 | ||
c21e0bbf | 1020 | out: |
88d33628 | 1021 | dev_dbg(dev, "%s: returning rc=%d\n", __func__, rc); |
c21e0bbf | 1022 | return rc; |
c21e0bbf MO |
1023 | } |
1024 | ||
1025 | /** | |
1026 | * init_scsi() - adds the host to the SCSI stack and kicks off host scan | |
1284fb0c | 1027 | * @cfg: Internal structure associated with the host. |
c21e0bbf | 1028 | * |
1284fb0c | 1029 | * Return: 0 on success, -errno on failure |
c21e0bbf MO |
1030 | */ |
1031 | static int init_scsi(struct cxlflash_cfg *cfg) | |
1032 | { | |
1033 | struct pci_dev *pdev = cfg->dev; | |
88d33628 | 1034 | struct device *dev = &cfg->dev->dev; |
c21e0bbf MO |
1035 | int rc = 0; |
1036 | ||
1037 | rc = scsi_add_host(cfg->host, &pdev->dev); | |
1038 | if (rc) { | |
88d33628 | 1039 | dev_err(dev, "%s: scsi_add_host failed rc=%d\n", __func__, rc); |
c21e0bbf MO |
1040 | goto out; |
1041 | } | |
1042 | ||
1043 | scsi_scan_host(cfg->host); | |
1044 | ||
1045 | out: | |
88d33628 | 1046 | dev_dbg(dev, "%s: returning rc=%d\n", __func__, rc); |
c21e0bbf MO |
1047 | return rc; |
1048 | } | |
1049 | ||
1050 | /** | |
1051 | * set_port_online() - transitions the specified host FC port to online state | |
1052 | * @fc_regs: Top of MMIO region defined for specified port. | |
1053 | * | |
1054 | * The provided MMIO region must be mapped prior to call. Online state means | |
1055 | * that the FC link layer has synced, completed the handshaking process, and | |
1056 | * is ready for login to start. | |
1057 | */ | |
1786f4a0 | 1058 | static void set_port_online(__be64 __iomem *fc_regs) |
c21e0bbf MO |
1059 | { |
1060 | u64 cmdcfg; | |
1061 | ||
1062 | cmdcfg = readq_be(&fc_regs[FC_MTIP_CMDCONFIG / 8]); | |
1063 | cmdcfg &= (~FC_MTIP_CMDCONFIG_OFFLINE); /* clear OFF_LINE */ | |
1064 | cmdcfg |= (FC_MTIP_CMDCONFIG_ONLINE); /* set ON_LINE */ | |
1065 | writeq_be(cmdcfg, &fc_regs[FC_MTIP_CMDCONFIG / 8]); | |
1066 | } | |
1067 | ||
1068 | /** | |
1069 | * set_port_offline() - transitions the specified host FC port to offline state | |
1070 | * @fc_regs: Top of MMIO region defined for specified port. | |
1071 | * | |
1072 | * The provided MMIO region must be mapped prior to call. | |
1073 | */ | |
1786f4a0 | 1074 | static void set_port_offline(__be64 __iomem *fc_regs) |
c21e0bbf MO |
1075 | { |
1076 | u64 cmdcfg; | |
1077 | ||
1078 | cmdcfg = readq_be(&fc_regs[FC_MTIP_CMDCONFIG / 8]); | |
1079 | cmdcfg &= (~FC_MTIP_CMDCONFIG_ONLINE); /* clear ON_LINE */ | |
1080 | cmdcfg |= (FC_MTIP_CMDCONFIG_OFFLINE); /* set OFF_LINE */ | |
1081 | writeq_be(cmdcfg, &fc_regs[FC_MTIP_CMDCONFIG / 8]); | |
1082 | } | |
1083 | ||
1084 | /** | |
1085 | * wait_port_online() - waits for the specified host FC port come online | |
1086 | * @fc_regs: Top of MMIO region defined for specified port. | |
1087 | * @delay_us: Number of microseconds to delay between reading port status. | |
1088 | * @nretry: Number of cycles to retry reading port status. | |
1089 | * | |
1090 | * The provided MMIO region must be mapped prior to call. This will timeout | |
1091 | * when the cable is not plugged in. | |
1092 | * | |
1093 | * Return: | |
1094 | * TRUE (1) when the specified port is online | |
1095 | * FALSE (0) when the specified port fails to come online after timeout | |
c21e0bbf | 1096 | */ |
88d33628 | 1097 | static bool wait_port_online(__be64 __iomem *fc_regs, u32 delay_us, u32 nretry) |
c21e0bbf MO |
1098 | { |
1099 | u64 status; | |
1100 | ||
88d33628 | 1101 | WARN_ON(delay_us < 1000); |
c21e0bbf MO |
1102 | |
1103 | do { | |
1104 | msleep(delay_us / 1000); | |
1105 | status = readq_be(&fc_regs[FC_MTIP_STATUS / 8]); | |
05dab432 MO |
1106 | if (status == U64_MAX) |
1107 | nretry /= 2; | |
c21e0bbf MO |
1108 | } while ((status & FC_MTIP_STATUS_MASK) != FC_MTIP_STATUS_ONLINE && |
1109 | nretry--); | |
1110 | ||
1111 | return ((status & FC_MTIP_STATUS_MASK) == FC_MTIP_STATUS_ONLINE); | |
1112 | } | |
1113 | ||
1114 | /** | |
1115 | * wait_port_offline() - waits for the specified host FC port go offline | |
1116 | * @fc_regs: Top of MMIO region defined for specified port. | |
1117 | * @delay_us: Number of microseconds to delay between reading port status. | |
1118 | * @nretry: Number of cycles to retry reading port status. | |
1119 | * | |
1120 | * The provided MMIO region must be mapped prior to call. | |
1121 | * | |
1122 | * Return: | |
1123 | * TRUE (1) when the specified port is offline | |
1124 | * FALSE (0) when the specified port fails to go offline after timeout | |
c21e0bbf | 1125 | */ |
88d33628 | 1126 | static bool wait_port_offline(__be64 __iomem *fc_regs, u32 delay_us, u32 nretry) |
c21e0bbf MO |
1127 | { |
1128 | u64 status; | |
1129 | ||
88d33628 | 1130 | WARN_ON(delay_us < 1000); |
c21e0bbf MO |
1131 | |
1132 | do { | |
1133 | msleep(delay_us / 1000); | |
1134 | status = readq_be(&fc_regs[FC_MTIP_STATUS / 8]); | |
05dab432 MO |
1135 | if (status == U64_MAX) |
1136 | nretry /= 2; | |
c21e0bbf MO |
1137 | } while ((status & FC_MTIP_STATUS_MASK) != FC_MTIP_STATUS_OFFLINE && |
1138 | nretry--); | |
1139 | ||
1140 | return ((status & FC_MTIP_STATUS_MASK) == FC_MTIP_STATUS_OFFLINE); | |
1141 | } | |
1142 | ||
1143 | /** | |
1144 | * afu_set_wwpn() - configures the WWPN for the specified host FC port | |
1145 | * @afu: AFU associated with the host that owns the specified FC port. | |
1146 | * @port: Port number being configured. | |
1147 | * @fc_regs: Top of MMIO region defined for specified port. | |
1148 | * @wwpn: The world-wide-port-number previously discovered for port. | |
1149 | * | |
1150 | * The provided MMIO region must be mapped prior to call. As part of the | |
1151 | * sequence to configure the WWPN, the port is toggled offline and then back | |
1152 | * online. This toggling action can cause this routine to delay up to a few | |
1153 | * seconds. When configured to use the internal LUN feature of the AFU, a | |
1154 | * failure to come online is overridden. | |
c21e0bbf | 1155 | */ |
f8013261 MO |
1156 | static void afu_set_wwpn(struct afu *afu, int port, __be64 __iomem *fc_regs, |
1157 | u64 wwpn) | |
c21e0bbf | 1158 | { |
88d33628 MO |
1159 | struct cxlflash_cfg *cfg = afu->parent; |
1160 | struct device *dev = &cfg->dev->dev; | |
1161 | ||
c21e0bbf | 1162 | set_port_offline(fc_regs); |
c21e0bbf MO |
1163 | if (!wait_port_offline(fc_regs, FC_PORT_STATUS_RETRY_INTERVAL_US, |
1164 | FC_PORT_STATUS_RETRY_CNT)) { | |
88d33628 MO |
1165 | dev_dbg(dev, "%s: wait on port %d to go offline timed out\n", |
1166 | __func__, port); | |
c21e0bbf MO |
1167 | } |
1168 | ||
f8013261 | 1169 | writeq_be(wwpn, &fc_regs[FC_PNAME / 8]); |
964497b3 | 1170 | |
c21e0bbf | 1171 | set_port_online(fc_regs); |
c21e0bbf MO |
1172 | if (!wait_port_online(fc_regs, FC_PORT_STATUS_RETRY_INTERVAL_US, |
1173 | FC_PORT_STATUS_RETRY_CNT)) { | |
88d33628 MO |
1174 | dev_dbg(dev, "%s: wait on port %d to go online timed out\n", |
1175 | __func__, port); | |
c21e0bbf | 1176 | } |
c21e0bbf MO |
1177 | } |
1178 | ||
1179 | /** | |
1180 | * afu_link_reset() - resets the specified host FC port | |
1181 | * @afu: AFU associated with the host that owns the specified FC port. | |
1182 | * @port: Port number being configured. | |
1183 | * @fc_regs: Top of MMIO region defined for specified port. | |
1184 | * | |
1185 | * The provided MMIO region must be mapped prior to call. The sequence to | |
1186 | * reset the port involves toggling it offline and then back online. This | |
1187 | * action can cause this routine to delay up to a few seconds. An effort | |
1188 | * is made to maintain link with the device by switching to host to use | |
1189 | * the alternate port exclusively while the reset takes place. | |
1190 | * failure to come online is overridden. | |
1191 | */ | |
1786f4a0 | 1192 | static void afu_link_reset(struct afu *afu, int port, __be64 __iomem *fc_regs) |
c21e0bbf | 1193 | { |
88d33628 MO |
1194 | struct cxlflash_cfg *cfg = afu->parent; |
1195 | struct device *dev = &cfg->dev->dev; | |
c21e0bbf MO |
1196 | u64 port_sel; |
1197 | ||
1198 | /* first switch the AFU to the other links, if any */ | |
1199 | port_sel = readq_be(&afu->afu_map->global.regs.afu_port_sel); | |
4da74db0 | 1200 | port_sel &= ~(1ULL << port); |
c21e0bbf MO |
1201 | writeq_be(port_sel, &afu->afu_map->global.regs.afu_port_sel); |
1202 | cxlflash_afu_sync(afu, 0, 0, AFU_GSYNC); | |
1203 | ||
1204 | set_port_offline(fc_regs); | |
1205 | if (!wait_port_offline(fc_regs, FC_PORT_STATUS_RETRY_INTERVAL_US, | |
1206 | FC_PORT_STATUS_RETRY_CNT)) | |
88d33628 MO |
1207 | dev_err(dev, "%s: wait on port %d to go offline timed out\n", |
1208 | __func__, port); | |
c21e0bbf MO |
1209 | |
1210 | set_port_online(fc_regs); | |
1211 | if (!wait_port_online(fc_regs, FC_PORT_STATUS_RETRY_INTERVAL_US, | |
1212 | FC_PORT_STATUS_RETRY_CNT)) | |
88d33628 MO |
1213 | dev_err(dev, "%s: wait on port %d to go online timed out\n", |
1214 | __func__, port); | |
c21e0bbf MO |
1215 | |
1216 | /* switch back to include this port */ | |
4da74db0 | 1217 | port_sel |= (1ULL << port); |
c21e0bbf MO |
1218 | writeq_be(port_sel, &afu->afu_map->global.regs.afu_port_sel); |
1219 | cxlflash_afu_sync(afu, 0, 0, AFU_GSYNC); | |
1220 | ||
88d33628 | 1221 | dev_dbg(dev, "%s: returning port_sel=%016llx\n", __func__, port_sel); |
c21e0bbf MO |
1222 | } |
1223 | ||
c21e0bbf MO |
1224 | /** |
1225 | * afu_err_intr_init() - clears and initializes the AFU for error interrupts | |
1226 | * @afu: AFU associated with the host. | |
1227 | */ | |
1228 | static void afu_err_intr_init(struct afu *afu) | |
1229 | { | |
66d4bce4 | 1230 | struct cxlflash_cfg *cfg = afu->parent; |
c885d3fe | 1231 | __be64 __iomem *fc_port_regs; |
c21e0bbf | 1232 | int i; |
a583d00a | 1233 | struct hwq *hwq = get_hwq(afu, PRIMARY_HWQ); |
c21e0bbf MO |
1234 | u64 reg; |
1235 | ||
1236 | /* global async interrupts: AFU clears afu_ctrl on context exit | |
1237 | * if async interrupts were sent to that context. This prevents | |
1238 | * the AFU form sending further async interrupts when | |
1239 | * there is | |
1240 | * nobody to receive them. | |
1241 | */ | |
1242 | ||
1243 | /* mask all */ | |
1244 | writeq_be(-1ULL, &afu->afu_map->global.regs.aintr_mask); | |
a583d00a UK |
1245 | /* set LISN# to send and point to primary master context */ |
1246 | reg = ((u64) (((hwq->ctx_hndl << 8) | SISL_MSI_ASYNC_ERROR)) << 40); | |
c21e0bbf MO |
1247 | |
1248 | if (afu->internal_lun) | |
1249 | reg |= 1; /* Bit 63 indicates local lun */ | |
1250 | writeq_be(reg, &afu->afu_map->global.regs.afu_ctrl); | |
1251 | /* clear all */ | |
1252 | writeq_be(-1ULL, &afu->afu_map->global.regs.aintr_clear); | |
1253 | /* unmask bits that are of interest */ | |
1254 | /* note: afu can send an interrupt after this step */ | |
1255 | writeq_be(SISL_ASTATUS_MASK, &afu->afu_map->global.regs.aintr_mask); | |
1256 | /* clear again in case a bit came on after previous clear but before */ | |
1257 | /* unmask */ | |
1258 | writeq_be(-1ULL, &afu->afu_map->global.regs.aintr_clear); | |
1259 | ||
1260 | /* Clear/Set internal lun bits */ | |
c885d3fe MO |
1261 | fc_port_regs = get_fc_port_regs(cfg, 0); |
1262 | reg = readq_be(&fc_port_regs[FC_CONFIG2 / 8]); | |
c21e0bbf MO |
1263 | reg &= SISL_FC_INTERNAL_MASK; |
1264 | if (afu->internal_lun) | |
1265 | reg |= ((u64)(afu->internal_lun - 1) << SISL_FC_INTERNAL_SHIFT); | |
c885d3fe | 1266 | writeq_be(reg, &fc_port_regs[FC_CONFIG2 / 8]); |
c21e0bbf MO |
1267 | |
1268 | /* now clear FC errors */ | |
66d4bce4 | 1269 | for (i = 0; i < cfg->num_fc_ports; i++) { |
c885d3fe MO |
1270 | fc_port_regs = get_fc_port_regs(cfg, i); |
1271 | ||
1272 | writeq_be(0xFFFFFFFFU, &fc_port_regs[FC_ERROR / 8]); | |
1273 | writeq_be(0, &fc_port_regs[FC_ERRCAP / 8]); | |
c21e0bbf MO |
1274 | } |
1275 | ||
1276 | /* sync interrupts for master's IOARRIN write */ | |
1277 | /* note that unlike asyncs, there can be no pending sync interrupts */ | |
1278 | /* at this time (this is a fresh context and master has not written */ | |
1279 | /* IOARRIN yet), so there is nothing to clear. */ | |
1280 | ||
1281 | /* set LISN#, it is always sent to the context that wrote IOARRIN */ | |
bb85ef68 | 1282 | for (i = 0; i < afu->num_hwqs; i++) { |
a583d00a UK |
1283 | hwq = get_hwq(afu, i); |
1284 | ||
1285 | writeq_be(SISL_MSI_SYNC_ERROR, &hwq->host_map->ctx_ctrl); | |
1286 | writeq_be(SISL_ISTATUS_MASK, &hwq->host_map->intr_mask); | |
1287 | } | |
c21e0bbf MO |
1288 | } |
1289 | ||
1290 | /** | |
1291 | * cxlflash_sync_err_irq() - interrupt handler for synchronous errors | |
1292 | * @irq: Interrupt number. | |
1293 | * @data: Private data provided at interrupt registration, the AFU. | |
1294 | * | |
1295 | * Return: Always return IRQ_HANDLED. | |
1296 | */ | |
1297 | static irqreturn_t cxlflash_sync_err_irq(int irq, void *data) | |
1298 | { | |
a583d00a UK |
1299 | struct hwq *hwq = (struct hwq *)data; |
1300 | struct cxlflash_cfg *cfg = hwq->afu->parent; | |
88d33628 | 1301 | struct device *dev = &cfg->dev->dev; |
c21e0bbf MO |
1302 | u64 reg; |
1303 | u64 reg_unmasked; | |
1304 | ||
a583d00a | 1305 | reg = readq_be(&hwq->host_map->intr_status); |
c21e0bbf MO |
1306 | reg_unmasked = (reg & SISL_ISTATUS_UNMASK); |
1307 | ||
1308 | if (reg_unmasked == 0UL) { | |
88d33628 MO |
1309 | dev_err(dev, "%s: spurious interrupt, intr_status=%016llx\n", |
1310 | __func__, reg); | |
c21e0bbf MO |
1311 | goto cxlflash_sync_err_irq_exit; |
1312 | } | |
1313 | ||
88d33628 MO |
1314 | dev_err(dev, "%s: unexpected interrupt, intr_status=%016llx\n", |
1315 | __func__, reg); | |
c21e0bbf | 1316 | |
a583d00a | 1317 | writeq_be(reg_unmasked, &hwq->host_map->intr_clear); |
c21e0bbf MO |
1318 | |
1319 | cxlflash_sync_err_irq_exit: | |
c21e0bbf MO |
1320 | return IRQ_HANDLED; |
1321 | } | |
1322 | ||
1323 | /** | |
9ba1a1fb MO |
1324 | * process_hrrq() - process the read-response queue |
1325 | * @afu: AFU associated with the host. | |
7bb512aa | 1326 | * @doneq: Queue of commands harvested from the RRQ. |
2588f222 | 1327 | * @budget: Threshold of RRQ entries to process. |
7bb512aa MO |
1328 | * |
1329 | * This routine must be called holding the disabled RRQ spin lock. | |
c21e0bbf | 1330 | * |
9ba1a1fb | 1331 | * Return: The number of entries processed. |
c21e0bbf | 1332 | */ |
a583d00a | 1333 | static int process_hrrq(struct hwq *hwq, struct list_head *doneq, int budget) |
c21e0bbf | 1334 | { |
a583d00a | 1335 | struct afu *afu = hwq->afu; |
c21e0bbf | 1336 | struct afu_cmd *cmd; |
bae0ac69 MO |
1337 | struct sisl_ioasa *ioasa; |
1338 | struct sisl_ioarcb *ioarcb; | |
a583d00a | 1339 | bool toggle = hwq->toggle; |
9ba1a1fb | 1340 | int num_hrrq = 0; |
c21e0bbf | 1341 | u64 entry, |
a583d00a UK |
1342 | *hrrq_start = hwq->hrrq_start, |
1343 | *hrrq_end = hwq->hrrq_end, | |
1344 | *hrrq_curr = hwq->hrrq_curr; | |
c21e0bbf | 1345 | |
2588f222 | 1346 | /* Process ready RRQ entries up to the specified budget (if any) */ |
c21e0bbf MO |
1347 | while (true) { |
1348 | entry = *hrrq_curr; | |
1349 | ||
1350 | if ((entry & SISL_RESP_HANDLE_T_BIT) != toggle) | |
1351 | break; | |
1352 | ||
bae0ac69 MO |
1353 | entry &= ~SISL_RESP_HANDLE_T_BIT; |
1354 | ||
1355 | if (afu_is_sq_cmd_mode(afu)) { | |
1356 | ioasa = (struct sisl_ioasa *)entry; | |
1357 | cmd = container_of(ioasa, struct afu_cmd, sa); | |
1358 | } else { | |
1359 | ioarcb = (struct sisl_ioarcb *)entry; | |
1360 | cmd = container_of(ioarcb, struct afu_cmd, rcb); | |
1361 | } | |
1362 | ||
7bb512aa | 1363 | list_add_tail(&cmd->queue, doneq); |
c21e0bbf MO |
1364 | |
1365 | /* Advance to next entry or wrap and flip the toggle bit */ | |
1366 | if (hrrq_curr < hrrq_end) | |
1367 | hrrq_curr++; | |
1368 | else { | |
1369 | hrrq_curr = hrrq_start; | |
1370 | toggle ^= SISL_RESP_HANDLE_T_BIT; | |
1371 | } | |
bae0ac69 | 1372 | |
a583d00a | 1373 | atomic_inc(&hwq->hsq_credits); |
9ba1a1fb | 1374 | num_hrrq++; |
2588f222 MO |
1375 | |
1376 | if (budget > 0 && num_hrrq >= budget) | |
1377 | break; | |
c21e0bbf MO |
1378 | } |
1379 | ||
a583d00a UK |
1380 | hwq->hrrq_curr = hrrq_curr; |
1381 | hwq->toggle = toggle; | |
c21e0bbf | 1382 | |
9ba1a1fb MO |
1383 | return num_hrrq; |
1384 | } | |
1385 | ||
7bb512aa MO |
1386 | /** |
1387 | * process_cmd_doneq() - process a queue of harvested RRQ commands | |
1388 | * @doneq: Queue of completed commands. | |
1389 | * | |
1390 | * Note that upon return the queue can no longer be trusted. | |
1391 | */ | |
1392 | static void process_cmd_doneq(struct list_head *doneq) | |
1393 | { | |
1394 | struct afu_cmd *cmd, *tmp; | |
1395 | ||
1396 | WARN_ON(list_empty(doneq)); | |
1397 | ||
1398 | list_for_each_entry_safe(cmd, tmp, doneq, queue) | |
1399 | cmd_complete(cmd); | |
1400 | } | |
1401 | ||
2588f222 MO |
1402 | /** |
1403 | * cxlflash_irqpoll() - process a queue of harvested RRQ commands | |
1404 | * @irqpoll: IRQ poll structure associated with queue to poll. | |
1405 | * @budget: Threshold of RRQ entries to process per poll. | |
1406 | * | |
1407 | * Return: The number of entries processed. | |
1408 | */ | |
1409 | static int cxlflash_irqpoll(struct irq_poll *irqpoll, int budget) | |
1410 | { | |
a583d00a | 1411 | struct hwq *hwq = container_of(irqpoll, struct hwq, irqpoll); |
2588f222 MO |
1412 | unsigned long hrrq_flags; |
1413 | LIST_HEAD(doneq); | |
1414 | int num_entries = 0; | |
1415 | ||
a583d00a | 1416 | spin_lock_irqsave(&hwq->hrrq_slock, hrrq_flags); |
2588f222 | 1417 | |
a583d00a | 1418 | num_entries = process_hrrq(hwq, &doneq, budget); |
2588f222 MO |
1419 | if (num_entries < budget) |
1420 | irq_poll_complete(irqpoll); | |
1421 | ||
a583d00a | 1422 | spin_unlock_irqrestore(&hwq->hrrq_slock, hrrq_flags); |
2588f222 MO |
1423 | |
1424 | process_cmd_doneq(&doneq); | |
1425 | return num_entries; | |
1426 | } | |
1427 | ||
9ba1a1fb MO |
1428 | /** |
1429 | * cxlflash_rrq_irq() - interrupt handler for read-response queue (normal path) | |
1430 | * @irq: Interrupt number. | |
1431 | * @data: Private data provided at interrupt registration, the AFU. | |
1432 | * | |
7bb512aa | 1433 | * Return: IRQ_HANDLED or IRQ_NONE when no ready entries found. |
9ba1a1fb MO |
1434 | */ |
1435 | static irqreturn_t cxlflash_rrq_irq(int irq, void *data) | |
1436 | { | |
a583d00a UK |
1437 | struct hwq *hwq = (struct hwq *)data; |
1438 | struct afu *afu = hwq->afu; | |
7bb512aa MO |
1439 | unsigned long hrrq_flags; |
1440 | LIST_HEAD(doneq); | |
1441 | int num_entries = 0; | |
9ba1a1fb | 1442 | |
a583d00a | 1443 | spin_lock_irqsave(&hwq->hrrq_slock, hrrq_flags); |
2588f222 MO |
1444 | |
1445 | if (afu_is_irqpoll_enabled(afu)) { | |
a583d00a UK |
1446 | irq_poll_sched(&hwq->irqpoll); |
1447 | spin_unlock_irqrestore(&hwq->hrrq_slock, hrrq_flags); | |
2588f222 MO |
1448 | return IRQ_HANDLED; |
1449 | } | |
1450 | ||
a583d00a UK |
1451 | num_entries = process_hrrq(hwq, &doneq, -1); |
1452 | spin_unlock_irqrestore(&hwq->hrrq_slock, hrrq_flags); | |
7bb512aa MO |
1453 | |
1454 | if (num_entries == 0) | |
1455 | return IRQ_NONE; | |
1456 | ||
1457 | process_cmd_doneq(&doneq); | |
c21e0bbf MO |
1458 | return IRQ_HANDLED; |
1459 | } | |
1460 | ||
8056044c MO |
1461 | /* |
1462 | * Asynchronous interrupt information table | |
1463 | * | |
1464 | * NOTE: | |
1465 | * - Order matters here as this array is indexed by bit position. | |
1466 | * | |
1467 | * - The checkpatch script considers the BUILD_SISL_ASTATUS_FC_PORT macro | |
1468 | * as complex and complains due to a lack of parentheses/braces. | |
1469 | */ | |
1470 | #define ASTATUS_FC(_a, _b, _c, _d) \ | |
1471 | { SISL_ASTATUS_FC##_a##_##_b, _c, _a, (_d) } | |
1472 | ||
1473 | #define BUILD_SISL_ASTATUS_FC_PORT(_a) \ | |
1474 | ASTATUS_FC(_a, LINK_UP, "link up", 0), \ | |
1475 | ASTATUS_FC(_a, LINK_DN, "link down", 0), \ | |
1476 | ASTATUS_FC(_a, LOGI_S, "login succeeded", SCAN_HOST), \ | |
1477 | ASTATUS_FC(_a, LOGI_F, "login failed", CLR_FC_ERROR), \ | |
1478 | ASTATUS_FC(_a, LOGI_R, "login timed out, retrying", LINK_RESET), \ | |
1479 | ASTATUS_FC(_a, CRC_T, "CRC threshold exceeded", LINK_RESET), \ | |
1480 | ASTATUS_FC(_a, LOGO, "target initiated LOGO", 0), \ | |
1481 | ASTATUS_FC(_a, OTHER, "other error", CLR_FC_ERROR | LINK_RESET) | |
1482 | ||
1483 | static const struct asyc_intr_info ainfo[] = { | |
1484 | BUILD_SISL_ASTATUS_FC_PORT(1), | |
1485 | BUILD_SISL_ASTATUS_FC_PORT(0), | |
1486 | BUILD_SISL_ASTATUS_FC_PORT(3), | |
1487 | BUILD_SISL_ASTATUS_FC_PORT(2) | |
1488 | }; | |
1489 | ||
c21e0bbf MO |
1490 | /** |
1491 | * cxlflash_async_err_irq() - interrupt handler for asynchronous errors | |
1492 | * @irq: Interrupt number. | |
1493 | * @data: Private data provided at interrupt registration, the AFU. | |
1494 | * | |
1495 | * Return: Always return IRQ_HANDLED. | |
1496 | */ | |
1497 | static irqreturn_t cxlflash_async_err_irq(int irq, void *data) | |
1498 | { | |
a583d00a UK |
1499 | struct hwq *hwq = (struct hwq *)data; |
1500 | struct afu *afu = hwq->afu; | |
4392ba49 MO |
1501 | struct cxlflash_cfg *cfg = afu->parent; |
1502 | struct device *dev = &cfg->dev->dev; | |
c21e0bbf | 1503 | const struct asyc_intr_info *info; |
1786f4a0 | 1504 | struct sisl_global_map __iomem *global = &afu->afu_map->global; |
c885d3fe | 1505 | __be64 __iomem *fc_port_regs; |
8056044c | 1506 | u64 reg_unmasked; |
c21e0bbf | 1507 | u64 reg; |
8056044c | 1508 | u64 bit; |
c21e0bbf | 1509 | u8 port; |
c21e0bbf | 1510 | |
c21e0bbf MO |
1511 | reg = readq_be(&global->regs.aintr_status); |
1512 | reg_unmasked = (reg & SISL_ASTATUS_UNMASK); | |
1513 | ||
8056044c | 1514 | if (unlikely(reg_unmasked == 0)) { |
88d33628 | 1515 | dev_err(dev, "%s: spurious interrupt, aintr_status=%016llx\n", |
4392ba49 | 1516 | __func__, reg); |
c21e0bbf MO |
1517 | goto out; |
1518 | } | |
1519 | ||
f15fbf8d | 1520 | /* FYI, it is 'okay' to clear AFU status before FC_ERROR */ |
c21e0bbf MO |
1521 | writeq_be(reg_unmasked, &global->regs.aintr_clear); |
1522 | ||
f15fbf8d | 1523 | /* Check each bit that is on */ |
8056044c MO |
1524 | for_each_set_bit(bit, (ulong *)®_unmasked, BITS_PER_LONG) { |
1525 | if (unlikely(bit >= ARRAY_SIZE(ainfo))) { | |
1526 | WARN_ON_ONCE(1); | |
c21e0bbf | 1527 | continue; |
8056044c MO |
1528 | } |
1529 | ||
1530 | info = &ainfo[bit]; | |
1531 | if (unlikely(info->status != 1ULL << bit)) { | |
1532 | WARN_ON_ONCE(1); | |
1533 | continue; | |
1534 | } | |
c21e0bbf MO |
1535 | |
1536 | port = info->port; | |
c885d3fe | 1537 | fc_port_regs = get_fc_port_regs(cfg, port); |
c21e0bbf | 1538 | |
88d33628 | 1539 | dev_err(dev, "%s: FC Port %d -> %s, fc_status=%016llx\n", |
4392ba49 | 1540 | __func__, port, info->desc, |
c885d3fe | 1541 | readq_be(&fc_port_regs[FC_STATUS / 8])); |
c21e0bbf MO |
1542 | |
1543 | /* | |
f15fbf8d | 1544 | * Do link reset first, some OTHER errors will set FC_ERROR |
c21e0bbf MO |
1545 | * again if cleared before or w/o a reset |
1546 | */ | |
1547 | if (info->action & LINK_RESET) { | |
4392ba49 MO |
1548 | dev_err(dev, "%s: FC Port %d: resetting link\n", |
1549 | __func__, port); | |
c21e0bbf MO |
1550 | cfg->lr_state = LINK_RESET_REQUIRED; |
1551 | cfg->lr_port = port; | |
1552 | schedule_work(&cfg->work_q); | |
1553 | } | |
1554 | ||
1555 | if (info->action & CLR_FC_ERROR) { | |
c885d3fe | 1556 | reg = readq_be(&fc_port_regs[FC_ERROR / 8]); |
c21e0bbf MO |
1557 | |
1558 | /* | |
f15fbf8d | 1559 | * Since all errors are unmasked, FC_ERROR and FC_ERRCAP |
c21e0bbf MO |
1560 | * should be the same and tracing one is sufficient. |
1561 | */ | |
1562 | ||
88d33628 | 1563 | dev_err(dev, "%s: fc %d: clearing fc_error=%016llx\n", |
4392ba49 | 1564 | __func__, port, reg); |
c21e0bbf | 1565 | |
c885d3fe MO |
1566 | writeq_be(reg, &fc_port_regs[FC_ERROR / 8]); |
1567 | writeq_be(0, &fc_port_regs[FC_ERRCAP / 8]); | |
c21e0bbf | 1568 | } |
ef51074a MO |
1569 | |
1570 | if (info->action & SCAN_HOST) { | |
1571 | atomic_inc(&cfg->scan_host_needed); | |
1572 | schedule_work(&cfg->work_q); | |
1573 | } | |
c21e0bbf MO |
1574 | } |
1575 | ||
1576 | out: | |
c21e0bbf MO |
1577 | return IRQ_HANDLED; |
1578 | } | |
1579 | ||
1580 | /** | |
1581 | * start_context() - starts the master context | |
1284fb0c | 1582 | * @cfg: Internal structure associated with the host. |
a583d00a | 1583 | * @index: Index of the hardware queue. |
c21e0bbf MO |
1584 | * |
1585 | * Return: A success or failure value from CXL services. | |
1586 | */ | |
a583d00a | 1587 | static int start_context(struct cxlflash_cfg *cfg, u32 index) |
c21e0bbf | 1588 | { |
88d33628 | 1589 | struct device *dev = &cfg->dev->dev; |
a583d00a | 1590 | struct hwq *hwq = get_hwq(cfg->afu, index); |
c21e0bbf MO |
1591 | int rc = 0; |
1592 | ||
a583d00a UK |
1593 | rc = cxl_start_context(hwq->ctx, |
1594 | hwq->work.work_element_descriptor, | |
c21e0bbf MO |
1595 | NULL); |
1596 | ||
88d33628 | 1597 | dev_dbg(dev, "%s: returning rc=%d\n", __func__, rc); |
c21e0bbf MO |
1598 | return rc; |
1599 | } | |
1600 | ||
1601 | /** | |
1602 | * read_vpd() - obtains the WWPNs from VPD | |
1284fb0c | 1603 | * @cfg: Internal structure associated with the host. |
66d4bce4 | 1604 | * @wwpn: Array of size MAX_FC_PORTS to pass back WWPNs |
c21e0bbf | 1605 | * |
1284fb0c | 1606 | * Return: 0 on success, -errno on failure |
c21e0bbf MO |
1607 | */ |
1608 | static int read_vpd(struct cxlflash_cfg *cfg, u64 wwpn[]) | |
1609 | { | |
88d33628 MO |
1610 | struct device *dev = &cfg->dev->dev; |
1611 | struct pci_dev *pdev = cfg->dev; | |
c21e0bbf MO |
1612 | int rc = 0; |
1613 | int ro_start, ro_size, i, j, k; | |
1614 | ssize_t vpd_size; | |
1615 | char vpd_data[CXLFLASH_VPD_LEN]; | |
1616 | char tmp_buf[WWPN_BUF_LEN] = { 0 }; | |
bdcff1c5 | 1617 | char *wwpn_vpd_tags[MAX_FC_PORTS] = { "V5", "V6", "V7", "V8" }; |
c21e0bbf MO |
1618 | |
1619 | /* Get the VPD data from the device */ | |
88d33628 | 1620 | vpd_size = cxl_read_adapter_vpd(pdev, vpd_data, sizeof(vpd_data)); |
c21e0bbf | 1621 | if (unlikely(vpd_size <= 0)) { |
88d33628 MO |
1622 | dev_err(dev, "%s: Unable to read VPD (size = %ld)\n", |
1623 | __func__, vpd_size); | |
c21e0bbf MO |
1624 | rc = -ENODEV; |
1625 | goto out; | |
1626 | } | |
1627 | ||
1628 | /* Get the read only section offset */ | |
1629 | ro_start = pci_vpd_find_tag(vpd_data, 0, vpd_size, | |
1630 | PCI_VPD_LRDT_RO_DATA); | |
1631 | if (unlikely(ro_start < 0)) { | |
88d33628 | 1632 | dev_err(dev, "%s: VPD Read-only data not found\n", __func__); |
c21e0bbf MO |
1633 | rc = -ENODEV; |
1634 | goto out; | |
1635 | } | |
1636 | ||
1637 | /* Get the read only section size, cap when extends beyond read VPD */ | |
1638 | ro_size = pci_vpd_lrdt_size(&vpd_data[ro_start]); | |
1639 | j = ro_size; | |
1640 | i = ro_start + PCI_VPD_LRDT_TAG_SIZE; | |
1641 | if (unlikely((i + j) > vpd_size)) { | |
88d33628 MO |
1642 | dev_dbg(dev, "%s: Might need to read more VPD (%d > %ld)\n", |
1643 | __func__, (i + j), vpd_size); | |
c21e0bbf MO |
1644 | ro_size = vpd_size - i; |
1645 | } | |
1646 | ||
1647 | /* | |
1648 | * Find the offset of the WWPN tag within the read only | |
1649 | * VPD data and validate the found field (partials are | |
1650 | * no good to us). Convert the ASCII data to an integer | |
1651 | * value. Note that we must copy to a temporary buffer | |
1652 | * because the conversion service requires that the ASCII | |
1653 | * string be terminated. | |
1654 | */ | |
66d4bce4 | 1655 | for (k = 0; k < cfg->num_fc_ports; k++) { |
c21e0bbf MO |
1656 | j = ro_size; |
1657 | i = ro_start + PCI_VPD_LRDT_TAG_SIZE; | |
1658 | ||
1659 | i = pci_vpd_find_info_keyword(vpd_data, i, j, wwpn_vpd_tags[k]); | |
1660 | if (unlikely(i < 0)) { | |
88d33628 MO |
1661 | dev_err(dev, "%s: Port %d WWPN not found in VPD\n", |
1662 | __func__, k); | |
c21e0bbf MO |
1663 | rc = -ENODEV; |
1664 | goto out; | |
1665 | } | |
1666 | ||
1667 | j = pci_vpd_info_field_size(&vpd_data[i]); | |
1668 | i += PCI_VPD_INFO_FLD_HDR_SIZE; | |
1669 | if (unlikely((i + j > vpd_size) || (j != WWPN_LEN))) { | |
88d33628 MO |
1670 | dev_err(dev, "%s: Port %d WWPN incomplete or bad VPD\n", |
1671 | __func__, k); | |
c21e0bbf MO |
1672 | rc = -ENODEV; |
1673 | goto out; | |
1674 | } | |
1675 | ||
1676 | memcpy(tmp_buf, &vpd_data[i], WWPN_LEN); | |
1677 | rc = kstrtoul(tmp_buf, WWPN_LEN, (ulong *)&wwpn[k]); | |
1678 | if (unlikely(rc)) { | |
88d33628 MO |
1679 | dev_err(dev, "%s: WWPN conversion failed for port %d\n", |
1680 | __func__, k); | |
c21e0bbf MO |
1681 | rc = -ENODEV; |
1682 | goto out; | |
1683 | } | |
66d4bce4 MO |
1684 | |
1685 | dev_dbg(dev, "%s: wwpn%d=%016llx\n", __func__, k, wwpn[k]); | |
c21e0bbf MO |
1686 | } |
1687 | ||
1688 | out: | |
88d33628 | 1689 | dev_dbg(dev, "%s: returning rc=%d\n", __func__, rc); |
c21e0bbf MO |
1690 | return rc; |
1691 | } | |
1692 | ||
1693 | /** | |
15305514 | 1694 | * init_pcr() - initialize the provisioning and control registers |
1284fb0c | 1695 | * @cfg: Internal structure associated with the host. |
c21e0bbf | 1696 | * |
15305514 MO |
1697 | * Also sets up fast access to the mapped registers and initializes AFU |
1698 | * command fields that never change. | |
c21e0bbf | 1699 | */ |
15305514 | 1700 | static void init_pcr(struct cxlflash_cfg *cfg) |
c21e0bbf MO |
1701 | { |
1702 | struct afu *afu = cfg->afu; | |
1786f4a0 | 1703 | struct sisl_ctrl_map __iomem *ctrl_map; |
a583d00a | 1704 | struct hwq *hwq; |
c21e0bbf MO |
1705 | int i; |
1706 | ||
1707 | for (i = 0; i < MAX_CONTEXT; i++) { | |
1708 | ctrl_map = &afu->afu_map->ctrls[i].ctrl; | |
f15fbf8d MO |
1709 | /* Disrupt any clients that could be running */ |
1710 | /* e.g. clients that survived a master restart */ | |
c21e0bbf MO |
1711 | writeq_be(0, &ctrl_map->rht_start); |
1712 | writeq_be(0, &ctrl_map->rht_cnt_id); | |
1713 | writeq_be(0, &ctrl_map->ctx_cap); | |
1714 | } | |
1715 | ||
a583d00a | 1716 | /* Copy frequently used fields into hwq */ |
bb85ef68 | 1717 | for (i = 0; i < afu->num_hwqs; i++) { |
a583d00a UK |
1718 | hwq = get_hwq(afu, i); |
1719 | ||
1720 | hwq->ctx_hndl = (u16) cxl_process_element(hwq->ctx); | |
1721 | hwq->host_map = &afu->afu_map->hosts[hwq->ctx_hndl].host; | |
1722 | hwq->ctrl_map = &afu->afu_map->ctrls[hwq->ctx_hndl].ctrl; | |
c21e0bbf | 1723 | |
a583d00a UK |
1724 | /* Program the Endian Control for the master context */ |
1725 | writeq_be(SISL_ENDIAN_CTRL, &hwq->host_map->endian_ctrl); | |
1726 | } | |
c21e0bbf MO |
1727 | } |
1728 | ||
1729 | /** | |
1730 | * init_global() - initialize AFU global registers | |
1284fb0c | 1731 | * @cfg: Internal structure associated with the host. |
c21e0bbf | 1732 | */ |
15305514 | 1733 | static int init_global(struct cxlflash_cfg *cfg) |
c21e0bbf MO |
1734 | { |
1735 | struct afu *afu = cfg->afu; | |
4392ba49 | 1736 | struct device *dev = &cfg->dev->dev; |
a583d00a UK |
1737 | struct hwq *hwq; |
1738 | struct sisl_host_map __iomem *hmap; | |
c885d3fe | 1739 | __be64 __iomem *fc_port_regs; |
66d4bce4 | 1740 | u64 wwpn[MAX_FC_PORTS]; /* wwpn of AFU ports */ |
c21e0bbf MO |
1741 | int i = 0, num_ports = 0; |
1742 | int rc = 0; | |
1743 | u64 reg; | |
1744 | ||
1745 | rc = read_vpd(cfg, &wwpn[0]); | |
1746 | if (rc) { | |
4392ba49 | 1747 | dev_err(dev, "%s: could not read vpd rc=%d\n", __func__, rc); |
c21e0bbf MO |
1748 | goto out; |
1749 | } | |
1750 | ||
a583d00a | 1751 | /* Set up RRQ and SQ in HWQ for master issued cmds */ |
bb85ef68 | 1752 | for (i = 0; i < afu->num_hwqs; i++) { |
a583d00a UK |
1753 | hwq = get_hwq(afu, i); |
1754 | hmap = hwq->host_map; | |
c21e0bbf | 1755 | |
a583d00a UK |
1756 | writeq_be((u64) hwq->hrrq_start, &hmap->rrq_start); |
1757 | writeq_be((u64) hwq->hrrq_end, &hmap->rrq_end); | |
1758 | ||
1759 | if (afu_is_sq_cmd_mode(afu)) { | |
1760 | writeq_be((u64)hwq->hsq_start, &hmap->sq_start); | |
1761 | writeq_be((u64)hwq->hsq_end, &hmap->sq_end); | |
1762 | } | |
bae0ac69 MO |
1763 | } |
1764 | ||
c21e0bbf MO |
1765 | /* AFU configuration */ |
1766 | reg = readq_be(&afu->afu_map->global.regs.afu_config); | |
1767 | reg |= SISL_AFUCONF_AR_ALL|SISL_AFUCONF_ENDIAN; | |
1768 | /* enable all auto retry options and control endianness */ | |
1769 | /* leave others at default: */ | |
1770 | /* CTX_CAP write protected, mbox_r does not clear on read and */ | |
1771 | /* checker on if dual afu */ | |
1772 | writeq_be(reg, &afu->afu_map->global.regs.afu_config); | |
1773 | ||
f15fbf8d | 1774 | /* Global port select: select either port */ |
c21e0bbf | 1775 | if (afu->internal_lun) { |
f15fbf8d | 1776 | /* Only use port 0 */ |
c21e0bbf | 1777 | writeq_be(PORT0, &afu->afu_map->global.regs.afu_port_sel); |
66d4bce4 | 1778 | num_ports = 0; |
c21e0bbf | 1779 | } else { |
e8e17ea6 MO |
1780 | writeq_be(PORT_MASK(cfg->num_fc_ports), |
1781 | &afu->afu_map->global.regs.afu_port_sel); | |
66d4bce4 | 1782 | num_ports = cfg->num_fc_ports; |
c21e0bbf MO |
1783 | } |
1784 | ||
1785 | for (i = 0; i < num_ports; i++) { | |
c885d3fe MO |
1786 | fc_port_regs = get_fc_port_regs(cfg, i); |
1787 | ||
f15fbf8d | 1788 | /* Unmask all errors (but they are still masked at AFU) */ |
c885d3fe | 1789 | writeq_be(0, &fc_port_regs[FC_ERRMSK / 8]); |
f15fbf8d | 1790 | /* Clear CRC error cnt & set a threshold */ |
c885d3fe MO |
1791 | (void)readq_be(&fc_port_regs[FC_CNT_CRCERR / 8]); |
1792 | writeq_be(MC_CRC_THRESH, &fc_port_regs[FC_CRC_THRESH / 8]); | |
c21e0bbf | 1793 | |
f15fbf8d | 1794 | /* Set WWPNs. If already programmed, wwpn[i] is 0 */ |
f8013261 | 1795 | if (wwpn[i] != 0) |
c885d3fe | 1796 | afu_set_wwpn(afu, i, &fc_port_regs[0], wwpn[i]); |
c21e0bbf MO |
1797 | /* Programming WWPN back to back causes additional |
1798 | * offline/online transitions and a PLOGI | |
1799 | */ | |
1800 | msleep(100); | |
c21e0bbf MO |
1801 | } |
1802 | ||
f15fbf8d MO |
1803 | /* Set up master's own CTX_CAP to allow real mode, host translation */ |
1804 | /* tables, afu cmds and read/write GSCSI cmds. */ | |
c21e0bbf | 1805 | /* First, unlock ctx_cap write by reading mbox */ |
bb85ef68 | 1806 | for (i = 0; i < afu->num_hwqs; i++) { |
a583d00a UK |
1807 | hwq = get_hwq(afu, i); |
1808 | ||
1809 | (void)readq_be(&hwq->ctrl_map->mbox_r); /* unlock ctx_cap */ | |
1810 | writeq_be((SISL_CTX_CAP_REAL_MODE | SISL_CTX_CAP_HOST_XLATE | | |
1811 | SISL_CTX_CAP_READ_CMD | SISL_CTX_CAP_WRITE_CMD | | |
1812 | SISL_CTX_CAP_AFU_CMD | SISL_CTX_CAP_GSCSI_CMD), | |
1813 | &hwq->ctrl_map->ctx_cap); | |
1814 | } | |
f15fbf8d | 1815 | /* Initialize heartbeat */ |
c21e0bbf | 1816 | afu->hb = readq_be(&afu->afu_map->global.regs.afu_hb); |
c21e0bbf MO |
1817 | out: |
1818 | return rc; | |
1819 | } | |
1820 | ||
1821 | /** | |
1822 | * start_afu() - initializes and starts the AFU | |
1284fb0c | 1823 | * @cfg: Internal structure associated with the host. |
c21e0bbf MO |
1824 | */ |
1825 | static int start_afu(struct cxlflash_cfg *cfg) | |
1826 | { | |
1827 | struct afu *afu = cfg->afu; | |
88d33628 | 1828 | struct device *dev = &cfg->dev->dev; |
a583d00a | 1829 | struct hwq *hwq; |
c21e0bbf | 1830 | int rc = 0; |
a583d00a | 1831 | int i; |
c21e0bbf | 1832 | |
c21e0bbf MO |
1833 | init_pcr(cfg); |
1834 | ||
a583d00a | 1835 | /* Initialize each HWQ */ |
bb85ef68 | 1836 | for (i = 0; i < afu->num_hwqs; i++) { |
a583d00a | 1837 | hwq = get_hwq(afu, i); |
c21e0bbf | 1838 | |
a583d00a UK |
1839 | /* After an AFU reset, RRQ entries are stale, clear them */ |
1840 | memset(&hwq->rrq_entry, 0, sizeof(hwq->rrq_entry)); | |
bae0ac69 | 1841 | |
a583d00a UK |
1842 | /* Initialize RRQ pointers */ |
1843 | hwq->hrrq_start = &hwq->rrq_entry[0]; | |
1844 | hwq->hrrq_end = &hwq->rrq_entry[NUM_RRQ_ENTRY - 1]; | |
1845 | hwq->hrrq_curr = hwq->hrrq_start; | |
1846 | hwq->toggle = 1; | |
edc034e8 UK |
1847 | |
1848 | /* Initialize spin locks */ | |
a583d00a | 1849 | spin_lock_init(&hwq->hrrq_slock); |
edc034e8 | 1850 | spin_lock_init(&hwq->hsq_slock); |
bae0ac69 | 1851 | |
a583d00a UK |
1852 | /* Initialize SQ */ |
1853 | if (afu_is_sq_cmd_mode(afu)) { | |
1854 | memset(&hwq->sq, 0, sizeof(hwq->sq)); | |
1855 | hwq->hsq_start = &hwq->sq[0]; | |
1856 | hwq->hsq_end = &hwq->sq[NUM_SQ_ENTRY - 1]; | |
1857 | hwq->hsq_curr = hwq->hsq_start; | |
1858 | ||
a583d00a UK |
1859 | atomic_set(&hwq->hsq_credits, NUM_SQ_ENTRY - 1); |
1860 | } | |
1861 | ||
1862 | /* Initialize IRQ poll */ | |
1863 | if (afu_is_irqpoll_enabled(afu)) | |
1864 | irq_poll_init(&hwq->irqpoll, afu->irqpoll_weight, | |
1865 | cxlflash_irqpoll); | |
1866 | ||
1867 | } | |
2588f222 | 1868 | |
c21e0bbf MO |
1869 | rc = init_global(cfg); |
1870 | ||
88d33628 | 1871 | dev_dbg(dev, "%s: returning rc=%d\n", __func__, rc); |
c21e0bbf MO |
1872 | return rc; |
1873 | } | |
1874 | ||
1875 | /** | |
9526f360 | 1876 | * init_intr() - setup interrupt handlers for the master context |
1284fb0c | 1877 | * @cfg: Internal structure associated with the host. |
a583d00a | 1878 | * @hwq: Hardware queue to initialize. |
c21e0bbf | 1879 | * |
1284fb0c | 1880 | * Return: 0 on success, -errno on failure |
c21e0bbf | 1881 | */ |
9526f360 | 1882 | static enum undo_level init_intr(struct cxlflash_cfg *cfg, |
a583d00a | 1883 | struct hwq *hwq) |
c21e0bbf | 1884 | { |
9526f360 | 1885 | struct device *dev = &cfg->dev->dev; |
a583d00a | 1886 | struct cxl_context *ctx = hwq->ctx; |
c21e0bbf | 1887 | int rc = 0; |
9526f360 | 1888 | enum undo_level level = UNDO_NOOP; |
a583d00a UK |
1889 | bool is_primary_hwq = (hwq->index == PRIMARY_HWQ); |
1890 | int num_irqs = is_primary_hwq ? 3 : 2; | |
c21e0bbf | 1891 | |
a583d00a | 1892 | rc = cxl_allocate_afu_irqs(ctx, num_irqs); |
c21e0bbf | 1893 | if (unlikely(rc)) { |
88d33628 | 1894 | dev_err(dev, "%s: allocate_afu_irqs failed rc=%d\n", |
c21e0bbf | 1895 | __func__, rc); |
9526f360 | 1896 | level = UNDO_NOOP; |
c21e0bbf MO |
1897 | goto out; |
1898 | } | |
1899 | ||
a583d00a | 1900 | rc = cxl_map_afu_irq(ctx, 1, cxlflash_sync_err_irq, hwq, |
c21e0bbf MO |
1901 | "SISL_MSI_SYNC_ERROR"); |
1902 | if (unlikely(rc <= 0)) { | |
88d33628 | 1903 | dev_err(dev, "%s: SISL_MSI_SYNC_ERROR map failed\n", __func__); |
c21e0bbf MO |
1904 | level = FREE_IRQ; |
1905 | goto out; | |
1906 | } | |
1907 | ||
a583d00a | 1908 | rc = cxl_map_afu_irq(ctx, 2, cxlflash_rrq_irq, hwq, |
c21e0bbf MO |
1909 | "SISL_MSI_RRQ_UPDATED"); |
1910 | if (unlikely(rc <= 0)) { | |
88d33628 | 1911 | dev_err(dev, "%s: SISL_MSI_RRQ_UPDATED map failed\n", __func__); |
c21e0bbf MO |
1912 | level = UNMAP_ONE; |
1913 | goto out; | |
1914 | } | |
1915 | ||
a583d00a UK |
1916 | /* SISL_MSI_ASYNC_ERROR is setup only for the primary HWQ */ |
1917 | if (!is_primary_hwq) | |
1918 | goto out; | |
1919 | ||
1920 | rc = cxl_map_afu_irq(ctx, 3, cxlflash_async_err_irq, hwq, | |
c21e0bbf MO |
1921 | "SISL_MSI_ASYNC_ERROR"); |
1922 | if (unlikely(rc <= 0)) { | |
88d33628 | 1923 | dev_err(dev, "%s: SISL_MSI_ASYNC_ERROR map failed\n", __func__); |
c21e0bbf MO |
1924 | level = UNMAP_TWO; |
1925 | goto out; | |
1926 | } | |
9526f360 MK |
1927 | out: |
1928 | return level; | |
1929 | } | |
c21e0bbf | 1930 | |
9526f360 MK |
1931 | /** |
1932 | * init_mc() - create and register as the master context | |
1933 | * @cfg: Internal structure associated with the host. | |
a583d00a | 1934 | * index: HWQ Index of the master context. |
9526f360 MK |
1935 | * |
1936 | * Return: 0 on success, -errno on failure | |
1937 | */ | |
a583d00a | 1938 | static int init_mc(struct cxlflash_cfg *cfg, u32 index) |
9526f360 MK |
1939 | { |
1940 | struct cxl_context *ctx; | |
1941 | struct device *dev = &cfg->dev->dev; | |
a583d00a | 1942 | struct hwq *hwq = get_hwq(cfg->afu, index); |
9526f360 MK |
1943 | int rc = 0; |
1944 | enum undo_level level; | |
1945 | ||
a583d00a UK |
1946 | hwq->afu = cfg->afu; |
1947 | hwq->index = index; | |
d732d14f | 1948 | INIT_LIST_HEAD(&hwq->pending_cmds); |
a583d00a UK |
1949 | |
1950 | if (index == PRIMARY_HWQ) | |
1951 | ctx = cxl_get_context(cfg->dev); | |
1952 | else | |
1953 | ctx = cxl_dev_context_init(cfg->dev); | |
9526f360 MK |
1954 | if (unlikely(!ctx)) { |
1955 | rc = -ENOMEM; | |
a583d00a | 1956 | goto err1; |
9526f360 | 1957 | } |
a583d00a UK |
1958 | |
1959 | WARN_ON(hwq->ctx); | |
1960 | hwq->ctx = ctx; | |
9526f360 MK |
1961 | |
1962 | /* Set it up as a master with the CXL */ | |
1963 | cxl_set_master(ctx); | |
1964 | ||
a583d00a UK |
1965 | /* Reset AFU when initializing primary context */ |
1966 | if (index == PRIMARY_HWQ) { | |
1967 | rc = cxl_afu_reset(ctx); | |
1968 | if (unlikely(rc)) { | |
1969 | dev_err(dev, "%s: AFU reset failed rc=%d\n", | |
1970 | __func__, rc); | |
1971 | goto err1; | |
1972 | } | |
9526f360 MK |
1973 | } |
1974 | ||
a583d00a | 1975 | level = init_intr(cfg, hwq); |
9526f360 | 1976 | if (unlikely(level)) { |
88d33628 | 1977 | dev_err(dev, "%s: interrupt init failed rc=%d\n", __func__, rc); |
a583d00a | 1978 | goto err2; |
9526f360 | 1979 | } |
c21e0bbf MO |
1980 | |
1981 | /* This performs the equivalent of the CXL_IOCTL_START_WORK. | |
1982 | * The CXL_IOCTL_GET_PROCESS_ELEMENT is implicit in the process | |
1983 | * element (pe) that is embedded in the context (ctx) | |
1984 | */ | |
a583d00a | 1985 | rc = start_context(cfg, index); |
c21e0bbf MO |
1986 | if (unlikely(rc)) { |
1987 | dev_err(dev, "%s: start context failed rc=%d\n", __func__, rc); | |
1988 | level = UNMAP_THREE; | |
a583d00a | 1989 | goto err2; |
c21e0bbf | 1990 | } |
a583d00a UK |
1991 | |
1992 | out: | |
88d33628 | 1993 | dev_dbg(dev, "%s: returning rc=%d\n", __func__, rc); |
c21e0bbf | 1994 | return rc; |
a583d00a UK |
1995 | err2: |
1996 | term_intr(cfg, level, index); | |
1997 | if (index != PRIMARY_HWQ) | |
1998 | cxl_release_context(ctx); | |
1999 | err1: | |
2000 | hwq->ctx = NULL; | |
2001 | goto out; | |
c21e0bbf MO |
2002 | } |
2003 | ||
a290b480 MO |
2004 | /** |
2005 | * get_num_afu_ports() - determines and configures the number of AFU ports | |
2006 | * @cfg: Internal structure associated with the host. | |
2007 | * | |
2008 | * This routine determines the number of AFU ports by converting the global | |
2009 | * port selection mask. The converted value is only valid following an AFU | |
2010 | * reset (explicit or power-on). This routine must be invoked shortly after | |
2011 | * mapping as other routines are dependent on the number of ports during the | |
2012 | * initialization sequence. | |
2013 | * | |
2014 | * To support legacy AFUs that might not have reflected an initial global | |
2015 | * port mask (value read is 0), default to the number of ports originally | |
2016 | * supported by the cxlflash driver (2) before hardware with other port | |
2017 | * offerings was introduced. | |
2018 | */ | |
2019 | static void get_num_afu_ports(struct cxlflash_cfg *cfg) | |
2020 | { | |
2021 | struct afu *afu = cfg->afu; | |
2022 | struct device *dev = &cfg->dev->dev; | |
2023 | u64 port_mask; | |
2024 | int num_fc_ports = LEGACY_FC_PORTS; | |
2025 | ||
2026 | port_mask = readq_be(&afu->afu_map->global.regs.afu_port_sel); | |
2027 | if (port_mask != 0ULL) | |
2028 | num_fc_ports = min(ilog2(port_mask) + 1, MAX_FC_PORTS); | |
2029 | ||
2030 | dev_dbg(dev, "%s: port_mask=%016llx num_fc_ports=%d\n", | |
2031 | __func__, port_mask, num_fc_ports); | |
2032 | ||
2033 | cfg->num_fc_ports = num_fc_ports; | |
2034 | cfg->host->max_channel = PORTNUM2CHAN(num_fc_ports); | |
2035 | } | |
2036 | ||
c21e0bbf MO |
2037 | /** |
2038 | * init_afu() - setup as master context and start AFU | |
1284fb0c | 2039 | * @cfg: Internal structure associated with the host. |
c21e0bbf MO |
2040 | * |
2041 | * This routine is a higher level of control for configuring the | |
2042 | * AFU on probe and reset paths. | |
2043 | * | |
1284fb0c | 2044 | * Return: 0 on success, -errno on failure |
c21e0bbf MO |
2045 | */ |
2046 | static int init_afu(struct cxlflash_cfg *cfg) | |
2047 | { | |
2048 | u64 reg; | |
2049 | int rc = 0; | |
2050 | struct afu *afu = cfg->afu; | |
2051 | struct device *dev = &cfg->dev->dev; | |
a583d00a UK |
2052 | struct hwq *hwq; |
2053 | int i; | |
c21e0bbf | 2054 | |
5cdac81a MO |
2055 | cxl_perst_reloads_same_image(cfg->cxl_afu, true); |
2056 | ||
bb85ef68 MO |
2057 | afu->num_hwqs = afu->desired_hwqs; |
2058 | for (i = 0; i < afu->num_hwqs; i++) { | |
a583d00a UK |
2059 | rc = init_mc(cfg, i); |
2060 | if (rc) { | |
2061 | dev_err(dev, "%s: init_mc failed rc=%d index=%d\n", | |
2062 | __func__, rc, i); | |
2063 | goto err1; | |
2064 | } | |
c21e0bbf MO |
2065 | } |
2066 | ||
a583d00a UK |
2067 | /* Map the entire MMIO space of the AFU using the first context */ |
2068 | hwq = get_hwq(afu, PRIMARY_HWQ); | |
2069 | afu->afu_map = cxl_psa_map(hwq->ctx); | |
c21e0bbf | 2070 | if (!afu->afu_map) { |
88d33628 | 2071 | dev_err(dev, "%s: cxl_psa_map failed\n", __func__); |
ee3491ba | 2072 | rc = -ENOMEM; |
c21e0bbf MO |
2073 | goto err1; |
2074 | } | |
2075 | ||
e5ce067b MO |
2076 | /* No byte reverse on reading afu_version or string will be backwards */ |
2077 | reg = readq(&afu->afu_map->global.regs.afu_version); | |
2078 | memcpy(afu->version, ®, sizeof(reg)); | |
c21e0bbf MO |
2079 | afu->interface_version = |
2080 | readq_be(&afu->afu_map->global.regs.interface_version); | |
e5ce067b | 2081 | if ((afu->interface_version + 1) == 0) { |
88d33628 MO |
2082 | dev_err(dev, "Back level AFU, please upgrade. AFU version %s " |
2083 | "interface version %016llx\n", afu->version, | |
e5ce067b MO |
2084 | afu->interface_version); |
2085 | rc = -EINVAL; | |
d940f9ae | 2086 | goto err1; |
ee3491ba MO |
2087 | } |
2088 | ||
bae0ac69 MO |
2089 | if (afu_is_sq_cmd_mode(afu)) { |
2090 | afu->send_cmd = send_cmd_sq; | |
2091 | afu->context_reset = context_reset_sq; | |
2092 | } else { | |
2093 | afu->send_cmd = send_cmd_ioarrin; | |
2094 | afu->context_reset = context_reset_ioarrin; | |
2095 | } | |
48b4be36 | 2096 | |
88d33628 MO |
2097 | dev_dbg(dev, "%s: afu_ver=%s interface_ver=%016llx\n", __func__, |
2098 | afu->version, afu->interface_version); | |
c21e0bbf | 2099 | |
a290b480 MO |
2100 | get_num_afu_ports(cfg); |
2101 | ||
c21e0bbf MO |
2102 | rc = start_afu(cfg); |
2103 | if (rc) { | |
88d33628 | 2104 | dev_err(dev, "%s: start_afu failed, rc=%d\n", __func__, rc); |
d940f9ae | 2105 | goto err1; |
c21e0bbf MO |
2106 | } |
2107 | ||
2108 | afu_err_intr_init(cfg->afu); | |
bb85ef68 | 2109 | for (i = 0; i < afu->num_hwqs; i++) { |
a583d00a UK |
2110 | hwq = get_hwq(afu, i); |
2111 | ||
a583d00a UK |
2112 | hwq->room = readq_be(&hwq->host_map->cmd_room); |
2113 | } | |
c21e0bbf | 2114 | |
2cb79266 MO |
2115 | /* Restore the LUN mappings */ |
2116 | cxlflash_restore_luntable(cfg); | |
ee3491ba | 2117 | out: |
88d33628 | 2118 | dev_dbg(dev, "%s: returning rc=%d\n", __func__, rc); |
c21e0bbf | 2119 | return rc; |
ee3491ba | 2120 | |
ee3491ba | 2121 | err1: |
bb85ef68 | 2122 | for (i = afu->num_hwqs - 1; i >= 0; i--) { |
a583d00a UK |
2123 | term_intr(cfg, UNMAP_THREE, i); |
2124 | term_mc(cfg, i); | |
2125 | } | |
ee3491ba | 2126 | goto out; |
c21e0bbf MO |
2127 | } |
2128 | ||
3b4f03cd UK |
2129 | /** |
2130 | * afu_reset() - resets the AFU | |
2131 | * @cfg: Internal structure associated with the host. | |
2132 | * | |
2133 | * Return: 0 on success, -errno on failure | |
2134 | */ | |
2135 | static int afu_reset(struct cxlflash_cfg *cfg) | |
2136 | { | |
2137 | struct device *dev = &cfg->dev->dev; | |
2138 | int rc = 0; | |
2139 | ||
2140 | /* Stop the context before the reset. Since the context is | |
2141 | * no longer available restart it after the reset is complete | |
2142 | */ | |
2143 | term_afu(cfg); | |
2144 | ||
2145 | rc = init_afu(cfg); | |
2146 | ||
2147 | dev_dbg(dev, "%s: returning rc=%d\n", __func__, rc); | |
2148 | return rc; | |
2149 | } | |
2150 | ||
2151 | /** | |
2152 | * drain_ioctls() - wait until all currently executing ioctls have completed | |
2153 | * @cfg: Internal structure associated with the host. | |
2154 | * | |
2155 | * Obtain write access to read/write semaphore that wraps ioctl | |
2156 | * handling to 'drain' ioctls currently executing. | |
2157 | */ | |
2158 | static void drain_ioctls(struct cxlflash_cfg *cfg) | |
2159 | { | |
2160 | down_write(&cfg->ioctl_rwsem); | |
2161 | up_write(&cfg->ioctl_rwsem); | |
2162 | } | |
2163 | ||
2164 | /** | |
2165 | * cxlflash_async_reset_host() - asynchronous host reset handler | |
2166 | * @data: Private data provided while scheduling reset. | |
2167 | * @cookie: Cookie that can be used for checkpointing. | |
2168 | */ | |
2169 | static void cxlflash_async_reset_host(void *data, async_cookie_t cookie) | |
2170 | { | |
2171 | struct cxlflash_cfg *cfg = data; | |
2172 | struct device *dev = &cfg->dev->dev; | |
2173 | int rc = 0; | |
2174 | ||
2175 | if (cfg->state != STATE_RESET) { | |
2176 | dev_dbg(dev, "%s: Not performing a reset, state=%d\n", | |
2177 | __func__, cfg->state); | |
2178 | goto out; | |
2179 | } | |
2180 | ||
2181 | drain_ioctls(cfg); | |
2182 | cxlflash_mark_contexts_error(cfg); | |
2183 | rc = afu_reset(cfg); | |
2184 | if (rc) | |
2185 | cfg->state = STATE_FAILTERM; | |
2186 | else | |
2187 | cfg->state = STATE_NORMAL; | |
2188 | wake_up_all(&cfg->reset_waitq); | |
2189 | ||
2190 | out: | |
2191 | scsi_unblock_requests(cfg->host); | |
2192 | } | |
2193 | ||
2194 | /** | |
2195 | * cxlflash_schedule_async_reset() - schedule an asynchronous host reset | |
2196 | * @cfg: Internal structure associated with the host. | |
2197 | */ | |
2198 | static void cxlflash_schedule_async_reset(struct cxlflash_cfg *cfg) | |
2199 | { | |
2200 | struct device *dev = &cfg->dev->dev; | |
2201 | ||
2202 | if (cfg->state != STATE_NORMAL) { | |
2203 | dev_dbg(dev, "%s: Not performing reset state=%d\n", | |
2204 | __func__, cfg->state); | |
2205 | return; | |
2206 | } | |
2207 | ||
2208 | cfg->state = STATE_RESET; | |
2209 | scsi_block_requests(cfg->host); | |
2210 | cfg->async_reset_cookie = async_schedule(cxlflash_async_reset_host, | |
2211 | cfg); | |
2212 | } | |
2213 | ||
c21e0bbf | 2214 | /** |
b413ed3b | 2215 | * send_afu_cmd() - builds and sends an internal AFU command |
c21e0bbf | 2216 | * @afu: AFU associated with the host. |
b413ed3b | 2217 | * @rcb: Pre-populated IOARCB describing command to send. |
c21e0bbf | 2218 | * |
b413ed3b MO |
2219 | * The AFU can only take one internal AFU command at a time. This limitation is |
2220 | * enforced by using a mutex to provide exclusive access to the AFU during the | |
2221 | * operation. This design point requires calling threads to not be on interrupt | |
2222 | * context due to the possibility of sleeping during concurrent AFU operations. | |
c21e0bbf | 2223 | * |
b413ed3b MO |
2224 | * The command status is optionally passed back to the caller when the caller |
2225 | * populates the IOASA field of the IOARCB with a pointer to an IOASA structure. | |
5cdac81a | 2226 | * |
c21e0bbf | 2227 | * Return: |
91995b34 | 2228 | * 0 on success, -errno on failure |
c21e0bbf | 2229 | */ |
b413ed3b | 2230 | static int send_afu_cmd(struct afu *afu, struct sisl_ioarcb *rcb) |
c21e0bbf | 2231 | { |
5cdac81a | 2232 | struct cxlflash_cfg *cfg = afu->parent; |
4392ba49 | 2233 | struct device *dev = &cfg->dev->dev; |
c21e0bbf | 2234 | struct afu_cmd *cmd = NULL; |
a583d00a | 2235 | struct hwq *hwq = get_hwq(afu, PRIMARY_HWQ); |
350bb478 | 2236 | char *buf = NULL; |
c21e0bbf | 2237 | int rc = 0; |
ddc869e9 | 2238 | int nretry = 0; |
c21e0bbf MO |
2239 | static DEFINE_MUTEX(sync_active); |
2240 | ||
5cdac81a | 2241 | if (cfg->state != STATE_NORMAL) { |
88d33628 MO |
2242 | dev_dbg(dev, "%s: Sync not required state=%u\n", |
2243 | __func__, cfg->state); | |
5cdac81a MO |
2244 | return 0; |
2245 | } | |
2246 | ||
c21e0bbf | 2247 | mutex_lock(&sync_active); |
de01283b | 2248 | atomic_inc(&afu->cmds_active); |
2450a5e3 | 2249 | buf = kmalloc(sizeof(*cmd) + __alignof__(*cmd) - 1, GFP_KERNEL); |
350bb478 MO |
2250 | if (unlikely(!buf)) { |
2251 | dev_err(dev, "%s: no memory for command\n", __func__); | |
91995b34 | 2252 | rc = -ENOMEM; |
c21e0bbf MO |
2253 | goto out; |
2254 | } | |
2255 | ||
350bb478 | 2256 | cmd = (struct afu_cmd *)PTR_ALIGN(buf, __alignof__(*cmd)); |
ddc869e9 UK |
2257 | |
2258 | retry: | |
2450a5e3 | 2259 | memset(cmd, 0, sizeof(*cmd)); |
b413ed3b | 2260 | memcpy(&cmd->rcb, rcb, sizeof(*rcb)); |
2450a5e3 | 2261 | INIT_LIST_HEAD(&cmd->queue); |
350bb478 | 2262 | init_completion(&cmd->cevent); |
350bb478 | 2263 | cmd->parent = afu; |
a583d00a | 2264 | cmd->hwq_index = hwq->index; |
a583d00a | 2265 | cmd->rcb.ctx_id = hwq->ctx_hndl; |
c21e0bbf | 2266 | |
b413ed3b MO |
2267 | dev_dbg(dev, "%s: afu=%p cmd=%p type=%02x nretry=%d\n", |
2268 | __func__, afu, cmd, cmd->rcb.cdb[0], nretry); | |
c21e0bbf | 2269 | |
48b4be36 | 2270 | rc = afu->send_cmd(afu, cmd); |
91995b34 UK |
2271 | if (unlikely(rc)) { |
2272 | rc = -ENOBUFS; | |
c21e0bbf | 2273 | goto out; |
91995b34 | 2274 | } |
c21e0bbf | 2275 | |
9ba848ac | 2276 | rc = wait_resp(afu, cmd); |
2450a5e3 UK |
2277 | switch (rc) { |
2278 | case -ETIMEDOUT: | |
ddc869e9 | 2279 | rc = afu->context_reset(hwq); |
2450a5e3 UK |
2280 | if (rc) { |
2281 | cxlflash_schedule_async_reset(cfg); | |
2282 | break; | |
2283 | } | |
2284 | /* fall through to retry */ | |
2285 | case -EAGAIN: | |
2286 | if (++nretry < 2) | |
ddc869e9 | 2287 | goto retry; |
2450a5e3 UK |
2288 | /* fall through to exit */ |
2289 | default: | |
2290 | break; | |
ddc869e9 UK |
2291 | } |
2292 | ||
b413ed3b MO |
2293 | if (rcb->ioasa) |
2294 | *rcb->ioasa = cmd->sa; | |
c21e0bbf | 2295 | out: |
de01283b | 2296 | atomic_dec(&afu->cmds_active); |
c21e0bbf | 2297 | mutex_unlock(&sync_active); |
350bb478 | 2298 | kfree(buf); |
88d33628 | 2299 | dev_dbg(dev, "%s: returning rc=%d\n", __func__, rc); |
c21e0bbf MO |
2300 | return rc; |
2301 | } | |
2302 | ||
b413ed3b MO |
2303 | /** |
2304 | * cxlflash_afu_sync() - builds and sends an AFU sync command | |
2305 | * @afu: AFU associated with the host. | |
2306 | * @ctx: Identifies context requesting sync. | |
2307 | * @res: Identifies resource requesting sync. | |
2308 | * @mode: Type of sync to issue (lightweight, heavyweight, global). | |
2309 | * | |
2310 | * AFU sync operations are only necessary and allowed when the device is | |
2311 | * operating normally. When not operating normally, sync requests can occur as | |
2312 | * part of cleaning up resources associated with an adapter prior to removal. | |
2313 | * In this scenario, these requests are simply ignored (safe due to the AFU | |
2314 | * going away). | |
2315 | * | |
2316 | * Return: | |
2317 | * 0 on success, -errno on failure | |
2318 | */ | |
2319 | int cxlflash_afu_sync(struct afu *afu, ctx_hndl_t ctx, res_hndl_t res, u8 mode) | |
2320 | { | |
2321 | struct cxlflash_cfg *cfg = afu->parent; | |
2322 | struct device *dev = &cfg->dev->dev; | |
2323 | struct sisl_ioarcb rcb = { 0 }; | |
2324 | ||
2325 | dev_dbg(dev, "%s: afu=%p ctx=%u res=%u mode=%u\n", | |
2326 | __func__, afu, ctx, res, mode); | |
2327 | ||
2328 | rcb.req_flags = SISL_REQ_FLAGS_AFU_CMD; | |
2329 | rcb.msi = SISL_MSI_RRQ_UPDATED; | |
2330 | rcb.timeout = MC_AFU_SYNC_TIMEOUT; | |
2331 | ||
2332 | rcb.cdb[0] = SISL_AFU_CMD_SYNC; | |
2333 | rcb.cdb[1] = mode; | |
2334 | put_unaligned_be16(ctx, &rcb.cdb[2]); | |
2335 | put_unaligned_be32(res, &rcb.cdb[4]); | |
2336 | ||
2337 | return send_afu_cmd(afu, &rcb); | |
2338 | } | |
2339 | ||
4ab47257 UK |
2340 | /** |
2341 | * cxlflash_eh_abort_handler() - abort a SCSI command | |
2342 | * @scp: SCSI command to abort. | |
2343 | * | |
2344 | * CXL Flash devices do not support a single command abort. Reset the context | |
2345 | * as per SISLite specification. Flush any pending commands in the hardware | |
2346 | * queue before the reset. | |
2347 | * | |
2348 | * Return: SUCCESS/FAILED as defined in scsi/scsi.h | |
2349 | */ | |
2350 | static int cxlflash_eh_abort_handler(struct scsi_cmnd *scp) | |
2351 | { | |
2352 | int rc = FAILED; | |
2353 | struct Scsi_Host *host = scp->device->host; | |
2354 | struct cxlflash_cfg *cfg = shost_priv(host); | |
2355 | struct afu_cmd *cmd = sc_to_afuc(scp); | |
2356 | struct device *dev = &cfg->dev->dev; | |
2357 | struct afu *afu = cfg->afu; | |
2358 | struct hwq *hwq = get_hwq(afu, cmd->hwq_index); | |
2359 | ||
2360 | dev_dbg(dev, "%s: (scp=%p) %d/%d/%d/%llu " | |
2361 | "cdb=(%08x-%08x-%08x-%08x)\n", __func__, scp, host->host_no, | |
2362 | scp->device->channel, scp->device->id, scp->device->lun, | |
2363 | get_unaligned_be32(&((u32 *)scp->cmnd)[0]), | |
2364 | get_unaligned_be32(&((u32 *)scp->cmnd)[1]), | |
2365 | get_unaligned_be32(&((u32 *)scp->cmnd)[2]), | |
2366 | get_unaligned_be32(&((u32 *)scp->cmnd)[3])); | |
2367 | ||
2368 | /* When the state is not normal, another reset/reload is in progress. | |
2369 | * Return failed and the mid-layer will invoke host reset handler. | |
2370 | */ | |
2371 | if (cfg->state != STATE_NORMAL) { | |
2372 | dev_dbg(dev, "%s: Invalid state for abort, state=%d\n", | |
2373 | __func__, cfg->state); | |
2374 | goto out; | |
2375 | } | |
2376 | ||
2377 | rc = afu->context_reset(hwq); | |
2378 | if (unlikely(rc)) | |
2379 | goto out; | |
2380 | ||
2381 | rc = SUCCESS; | |
2382 | ||
2383 | out: | |
2384 | dev_dbg(dev, "%s: returning rc=%d\n", __func__, rc); | |
2385 | return rc; | |
2386 | } | |
2387 | ||
15305514 MO |
2388 | /** |
2389 | * cxlflash_eh_device_reset_handler() - reset a single LUN | |
2390 | * @scp: SCSI command to send. | |
2391 | * | |
2392 | * Return: | |
2393 | * SUCCESS as defined in scsi/scsi.h | |
2394 | * FAILED as defined in scsi/scsi.h | |
2395 | */ | |
2396 | static int cxlflash_eh_device_reset_handler(struct scsi_cmnd *scp) | |
2397 | { | |
2398 | int rc = SUCCESS; | |
2399 | struct Scsi_Host *host = scp->device->host; | |
88d33628 MO |
2400 | struct cxlflash_cfg *cfg = shost_priv(host); |
2401 | struct device *dev = &cfg->dev->dev; | |
15305514 MO |
2402 | struct afu *afu = cfg->afu; |
2403 | int rcr = 0; | |
2404 | ||
88d33628 MO |
2405 | dev_dbg(dev, "%s: (scp=%p) %d/%d/%d/%llu " |
2406 | "cdb=(%08x-%08x-%08x-%08x)\n", __func__, scp, host->host_no, | |
2407 | scp->device->channel, scp->device->id, scp->device->lun, | |
2408 | get_unaligned_be32(&((u32 *)scp->cmnd)[0]), | |
2409 | get_unaligned_be32(&((u32 *)scp->cmnd)[1]), | |
2410 | get_unaligned_be32(&((u32 *)scp->cmnd)[2]), | |
2411 | get_unaligned_be32(&((u32 *)scp->cmnd)[3])); | |
15305514 | 2412 | |
ed486daa | 2413 | retry: |
15305514 MO |
2414 | switch (cfg->state) { |
2415 | case STATE_NORMAL: | |
2416 | rcr = send_tmf(afu, scp, TMF_LUN_RESET); | |
2417 | if (unlikely(rcr)) | |
2418 | rc = FAILED; | |
2419 | break; | |
2420 | case STATE_RESET: | |
2421 | wait_event(cfg->reset_waitq, cfg->state != STATE_RESET); | |
ed486daa | 2422 | goto retry; |
15305514 MO |
2423 | default: |
2424 | rc = FAILED; | |
2425 | break; | |
2426 | } | |
2427 | ||
88d33628 | 2428 | dev_dbg(dev, "%s: returning rc=%d\n", __func__, rc); |
15305514 MO |
2429 | return rc; |
2430 | } | |
2431 | ||
2432 | /** | |
2433 | * cxlflash_eh_host_reset_handler() - reset the host adapter | |
2434 | * @scp: SCSI command from stack identifying host. | |
2435 | * | |
1d3324c3 MO |
2436 | * Following a reset, the state is evaluated again in case an EEH occurred |
2437 | * during the reset. In such a scenario, the host reset will either yield | |
2438 | * until the EEH recovery is complete or return success or failure based | |
2439 | * upon the current device state. | |
2440 | * | |
15305514 MO |
2441 | * Return: |
2442 | * SUCCESS as defined in scsi/scsi.h | |
2443 | * FAILED as defined in scsi/scsi.h | |
2444 | */ | |
2445 | static int cxlflash_eh_host_reset_handler(struct scsi_cmnd *scp) | |
2446 | { | |
2447 | int rc = SUCCESS; | |
2448 | int rcr = 0; | |
2449 | struct Scsi_Host *host = scp->device->host; | |
88d33628 MO |
2450 | struct cxlflash_cfg *cfg = shost_priv(host); |
2451 | struct device *dev = &cfg->dev->dev; | |
15305514 | 2452 | |
88d33628 MO |
2453 | dev_dbg(dev, "%s: (scp=%p) %d/%d/%d/%llu " |
2454 | "cdb=(%08x-%08x-%08x-%08x)\n", __func__, scp, host->host_no, | |
2455 | scp->device->channel, scp->device->id, scp->device->lun, | |
2456 | get_unaligned_be32(&((u32 *)scp->cmnd)[0]), | |
2457 | get_unaligned_be32(&((u32 *)scp->cmnd)[1]), | |
2458 | get_unaligned_be32(&((u32 *)scp->cmnd)[2]), | |
2459 | get_unaligned_be32(&((u32 *)scp->cmnd)[3])); | |
15305514 MO |
2460 | |
2461 | switch (cfg->state) { | |
2462 | case STATE_NORMAL: | |
2463 | cfg->state = STATE_RESET; | |
f411396d | 2464 | drain_ioctls(cfg); |
15305514 MO |
2465 | cxlflash_mark_contexts_error(cfg); |
2466 | rcr = afu_reset(cfg); | |
2467 | if (rcr) { | |
2468 | rc = FAILED; | |
2469 | cfg->state = STATE_FAILTERM; | |
2470 | } else | |
2471 | cfg->state = STATE_NORMAL; | |
2472 | wake_up_all(&cfg->reset_waitq); | |
1d3324c3 MO |
2473 | ssleep(1); |
2474 | /* fall through */ | |
15305514 MO |
2475 | case STATE_RESET: |
2476 | wait_event(cfg->reset_waitq, cfg->state != STATE_RESET); | |
2477 | if (cfg->state == STATE_NORMAL) | |
2478 | break; | |
2479 | /* fall through */ | |
2480 | default: | |
2481 | rc = FAILED; | |
2482 | break; | |
2483 | } | |
2484 | ||
88d33628 | 2485 | dev_dbg(dev, "%s: returning rc=%d\n", __func__, rc); |
15305514 MO |
2486 | return rc; |
2487 | } | |
2488 | ||
2489 | /** | |
2490 | * cxlflash_change_queue_depth() - change the queue depth for the device | |
2491 | * @sdev: SCSI device destined for queue depth change. | |
2492 | * @qdepth: Requested queue depth value to set. | |
2493 | * | |
2494 | * The requested queue depth is capped to the maximum supported value. | |
2495 | * | |
2496 | * Return: The actual queue depth set. | |
2497 | */ | |
2498 | static int cxlflash_change_queue_depth(struct scsi_device *sdev, int qdepth) | |
2499 | { | |
2500 | ||
2501 | if (qdepth > CXLFLASH_MAX_CMDS_PER_LUN) | |
2502 | qdepth = CXLFLASH_MAX_CMDS_PER_LUN; | |
2503 | ||
2504 | scsi_change_queue_depth(sdev, qdepth); | |
2505 | return sdev->queue_depth; | |
2506 | } | |
2507 | ||
2508 | /** | |
2509 | * cxlflash_show_port_status() - queries and presents the current port status | |
e0f01a21 | 2510 | * @port: Desired port for status reporting. |
90c9f8f4 | 2511 | * @cfg: Internal structure associated with the host. |
15305514 MO |
2512 | * @buf: Buffer of length PAGE_SIZE to report back port status in ASCII. |
2513 | * | |
66d4bce4 | 2514 | * Return: The size of the ASCII string returned in @buf or -EINVAL. |
15305514 | 2515 | */ |
90c9f8f4 MO |
2516 | static ssize_t cxlflash_show_port_status(u32 port, |
2517 | struct cxlflash_cfg *cfg, | |
2518 | char *buf) | |
15305514 | 2519 | { |
66d4bce4 | 2520 | struct device *dev = &cfg->dev->dev; |
15305514 | 2521 | char *disp_status; |
15305514 | 2522 | u64 status; |
c885d3fe | 2523 | __be64 __iomem *fc_port_regs; |
15305514 | 2524 | |
66d4bce4 MO |
2525 | WARN_ON(port >= MAX_FC_PORTS); |
2526 | ||
2527 | if (port >= cfg->num_fc_ports) { | |
2528 | dev_info(dev, "%s: Port %d not supported on this card.\n", | |
2529 | __func__, port); | |
2530 | return -EINVAL; | |
2531 | } | |
15305514 | 2532 | |
c885d3fe MO |
2533 | fc_port_regs = get_fc_port_regs(cfg, port); |
2534 | status = readq_be(&fc_port_regs[FC_MTIP_STATUS / 8]); | |
e0f01a21 | 2535 | status &= FC_MTIP_STATUS_MASK; |
15305514 MO |
2536 | |
2537 | if (status == FC_MTIP_STATUS_ONLINE) | |
2538 | disp_status = "online"; | |
2539 | else if (status == FC_MTIP_STATUS_OFFLINE) | |
2540 | disp_status = "offline"; | |
2541 | else | |
2542 | disp_status = "unknown"; | |
2543 | ||
e0f01a21 MO |
2544 | return scnprintf(buf, PAGE_SIZE, "%s\n", disp_status); |
2545 | } | |
2546 | ||
2547 | /** | |
2548 | * port0_show() - queries and presents the current status of port 0 | |
2549 | * @dev: Generic device associated with the host owning the port. | |
2550 | * @attr: Device attribute representing the port. | |
2551 | * @buf: Buffer of length PAGE_SIZE to report back port status in ASCII. | |
2552 | * | |
2553 | * Return: The size of the ASCII string returned in @buf. | |
2554 | */ | |
2555 | static ssize_t port0_show(struct device *dev, | |
2556 | struct device_attribute *attr, | |
2557 | char *buf) | |
2558 | { | |
88d33628 | 2559 | struct cxlflash_cfg *cfg = shost_priv(class_to_shost(dev)); |
e0f01a21 | 2560 | |
90c9f8f4 | 2561 | return cxlflash_show_port_status(0, cfg, buf); |
15305514 MO |
2562 | } |
2563 | ||
2564 | /** | |
e0f01a21 MO |
2565 | * port1_show() - queries and presents the current status of port 1 |
2566 | * @dev: Generic device associated with the host owning the port. | |
2567 | * @attr: Device attribute representing the port. | |
2568 | * @buf: Buffer of length PAGE_SIZE to report back port status in ASCII. | |
2569 | * | |
2570 | * Return: The size of the ASCII string returned in @buf. | |
2571 | */ | |
2572 | static ssize_t port1_show(struct device *dev, | |
2573 | struct device_attribute *attr, | |
2574 | char *buf) | |
2575 | { | |
88d33628 | 2576 | struct cxlflash_cfg *cfg = shost_priv(class_to_shost(dev)); |
e0f01a21 | 2577 | |
90c9f8f4 | 2578 | return cxlflash_show_port_status(1, cfg, buf); |
e0f01a21 MO |
2579 | } |
2580 | ||
bdcff1c5 MO |
2581 | /** |
2582 | * port2_show() - queries and presents the current status of port 2 | |
2583 | * @dev: Generic device associated with the host owning the port. | |
2584 | * @attr: Device attribute representing the port. | |
2585 | * @buf: Buffer of length PAGE_SIZE to report back port status in ASCII. | |
2586 | * | |
2587 | * Return: The size of the ASCII string returned in @buf. | |
2588 | */ | |
2589 | static ssize_t port2_show(struct device *dev, | |
2590 | struct device_attribute *attr, | |
2591 | char *buf) | |
2592 | { | |
2593 | struct cxlflash_cfg *cfg = shost_priv(class_to_shost(dev)); | |
2594 | ||
2595 | return cxlflash_show_port_status(2, cfg, buf); | |
2596 | } | |
2597 | ||
2598 | /** | |
2599 | * port3_show() - queries and presents the current status of port 3 | |
2600 | * @dev: Generic device associated with the host owning the port. | |
2601 | * @attr: Device attribute representing the port. | |
2602 | * @buf: Buffer of length PAGE_SIZE to report back port status in ASCII. | |
2603 | * | |
2604 | * Return: The size of the ASCII string returned in @buf. | |
2605 | */ | |
2606 | static ssize_t port3_show(struct device *dev, | |
2607 | struct device_attribute *attr, | |
2608 | char *buf) | |
2609 | { | |
2610 | struct cxlflash_cfg *cfg = shost_priv(class_to_shost(dev)); | |
2611 | ||
2612 | return cxlflash_show_port_status(3, cfg, buf); | |
2613 | } | |
2614 | ||
e0f01a21 MO |
2615 | /** |
2616 | * lun_mode_show() - presents the current LUN mode of the host | |
15305514 | 2617 | * @dev: Generic device associated with the host. |
e0f01a21 | 2618 | * @attr: Device attribute representing the LUN mode. |
15305514 MO |
2619 | * @buf: Buffer of length PAGE_SIZE to report back the LUN mode in ASCII. |
2620 | * | |
2621 | * Return: The size of the ASCII string returned in @buf. | |
2622 | */ | |
e0f01a21 MO |
2623 | static ssize_t lun_mode_show(struct device *dev, |
2624 | struct device_attribute *attr, char *buf) | |
15305514 | 2625 | { |
88d33628 | 2626 | struct cxlflash_cfg *cfg = shost_priv(class_to_shost(dev)); |
15305514 MO |
2627 | struct afu *afu = cfg->afu; |
2628 | ||
e0f01a21 | 2629 | return scnprintf(buf, PAGE_SIZE, "%u\n", afu->internal_lun); |
15305514 MO |
2630 | } |
2631 | ||
2632 | /** | |
e0f01a21 | 2633 | * lun_mode_store() - sets the LUN mode of the host |
15305514 | 2634 | * @dev: Generic device associated with the host. |
e0f01a21 | 2635 | * @attr: Device attribute representing the LUN mode. |
15305514 MO |
2636 | * @buf: Buffer of length PAGE_SIZE containing the LUN mode in ASCII. |
2637 | * @count: Length of data resizing in @buf. | |
2638 | * | |
2639 | * The CXL Flash AFU supports a dummy LUN mode where the external | |
2640 | * links and storage are not required. Space on the FPGA is used | |
2641 | * to create 1 or 2 small LUNs which are presented to the system | |
2642 | * as if they were a normal storage device. This feature is useful | |
2643 | * during development and also provides manufacturing with a way | |
2644 | * to test the AFU without an actual device. | |
2645 | * | |
2646 | * 0 = external LUN[s] (default) | |
2647 | * 1 = internal LUN (1 x 64K, 512B blocks, id 0) | |
2648 | * 2 = internal LUN (1 x 64K, 4K blocks, id 0) | |
2649 | * 3 = internal LUN (2 x 32K, 512B blocks, ids 0,1) | |
2650 | * 4 = internal LUN (2 x 32K, 4K blocks, ids 0,1) | |
2651 | * | |
2652 | * Return: The size of the ASCII string returned in @buf. | |
2653 | */ | |
e0f01a21 MO |
2654 | static ssize_t lun_mode_store(struct device *dev, |
2655 | struct device_attribute *attr, | |
2656 | const char *buf, size_t count) | |
15305514 MO |
2657 | { |
2658 | struct Scsi_Host *shost = class_to_shost(dev); | |
88d33628 | 2659 | struct cxlflash_cfg *cfg = shost_priv(shost); |
15305514 MO |
2660 | struct afu *afu = cfg->afu; |
2661 | int rc; | |
2662 | u32 lun_mode; | |
2663 | ||
2664 | rc = kstrtouint(buf, 10, &lun_mode); | |
2665 | if (!rc && (lun_mode < 5) && (lun_mode != afu->internal_lun)) { | |
2666 | afu->internal_lun = lun_mode; | |
603ecce9 MK |
2667 | |
2668 | /* | |
2669 | * When configured for internal LUN, there is only one channel, | |
66d4bce4 MO |
2670 | * channel number 0, else there will be one less than the number |
2671 | * of fc ports for this card. | |
603ecce9 MK |
2672 | */ |
2673 | if (afu->internal_lun) | |
2674 | shost->max_channel = 0; | |
2675 | else | |
e8e17ea6 | 2676 | shost->max_channel = PORTNUM2CHAN(cfg->num_fc_ports); |
603ecce9 | 2677 | |
15305514 MO |
2678 | afu_reset(cfg); |
2679 | scsi_scan_host(cfg->host); | |
2680 | } | |
2681 | ||
2682 | return count; | |
2683 | } | |
2684 | ||
2685 | /** | |
e0f01a21 | 2686 | * ioctl_version_show() - presents the current ioctl version of the host |
15305514 MO |
2687 | * @dev: Generic device associated with the host. |
2688 | * @attr: Device attribute representing the ioctl version. | |
2689 | * @buf: Buffer of length PAGE_SIZE to report back the ioctl version. | |
2690 | * | |
2691 | * Return: The size of the ASCII string returned in @buf. | |
2692 | */ | |
e0f01a21 MO |
2693 | static ssize_t ioctl_version_show(struct device *dev, |
2694 | struct device_attribute *attr, char *buf) | |
15305514 MO |
2695 | { |
2696 | return scnprintf(buf, PAGE_SIZE, "%u\n", DK_CXLFLASH_VERSION_0); | |
2697 | } | |
2698 | ||
2699 | /** | |
e0f01a21 MO |
2700 | * cxlflash_show_port_lun_table() - queries and presents the port LUN table |
2701 | * @port: Desired port for status reporting. | |
90c9f8f4 | 2702 | * @cfg: Internal structure associated with the host. |
e0f01a21 MO |
2703 | * @buf: Buffer of length PAGE_SIZE to report back port status in ASCII. |
2704 | * | |
66d4bce4 | 2705 | * Return: The size of the ASCII string returned in @buf or -EINVAL. |
e0f01a21 MO |
2706 | */ |
2707 | static ssize_t cxlflash_show_port_lun_table(u32 port, | |
90c9f8f4 | 2708 | struct cxlflash_cfg *cfg, |
e0f01a21 MO |
2709 | char *buf) |
2710 | { | |
66d4bce4 | 2711 | struct device *dev = &cfg->dev->dev; |
c885d3fe | 2712 | __be64 __iomem *fc_port_luns; |
e0f01a21 MO |
2713 | int i; |
2714 | ssize_t bytes = 0; | |
e0f01a21 | 2715 | |
66d4bce4 MO |
2716 | WARN_ON(port >= MAX_FC_PORTS); |
2717 | ||
2718 | if (port >= cfg->num_fc_ports) { | |
2719 | dev_info(dev, "%s: Port %d not supported on this card.\n", | |
2720 | __func__, port); | |
2721 | return -EINVAL; | |
2722 | } | |
e0f01a21 | 2723 | |
c885d3fe | 2724 | fc_port_luns = get_fc_port_luns(cfg, port); |
e0f01a21 MO |
2725 | |
2726 | for (i = 0; i < CXLFLASH_NUM_VLUNS; i++) | |
2727 | bytes += scnprintf(buf + bytes, PAGE_SIZE - bytes, | |
c885d3fe MO |
2728 | "%03d: %016llx\n", |
2729 | i, readq_be(&fc_port_luns[i])); | |
e0f01a21 MO |
2730 | return bytes; |
2731 | } | |
2732 | ||
2733 | /** | |
2734 | * port0_lun_table_show() - presents the current LUN table of port 0 | |
2735 | * @dev: Generic device associated with the host owning the port. | |
2736 | * @attr: Device attribute representing the port. | |
2737 | * @buf: Buffer of length PAGE_SIZE to report back port status in ASCII. | |
2738 | * | |
2739 | * Return: The size of the ASCII string returned in @buf. | |
2740 | */ | |
2741 | static ssize_t port0_lun_table_show(struct device *dev, | |
2742 | struct device_attribute *attr, | |
2743 | char *buf) | |
2744 | { | |
88d33628 | 2745 | struct cxlflash_cfg *cfg = shost_priv(class_to_shost(dev)); |
e0f01a21 | 2746 | |
90c9f8f4 | 2747 | return cxlflash_show_port_lun_table(0, cfg, buf); |
e0f01a21 MO |
2748 | } |
2749 | ||
2750 | /** | |
2751 | * port1_lun_table_show() - presents the current LUN table of port 1 | |
2752 | * @dev: Generic device associated with the host owning the port. | |
2753 | * @attr: Device attribute representing the port. | |
2754 | * @buf: Buffer of length PAGE_SIZE to report back port status in ASCII. | |
2755 | * | |
2756 | * Return: The size of the ASCII string returned in @buf. | |
2757 | */ | |
2758 | static ssize_t port1_lun_table_show(struct device *dev, | |
2759 | struct device_attribute *attr, | |
2760 | char *buf) | |
2761 | { | |
88d33628 | 2762 | struct cxlflash_cfg *cfg = shost_priv(class_to_shost(dev)); |
e0f01a21 | 2763 | |
90c9f8f4 | 2764 | return cxlflash_show_port_lun_table(1, cfg, buf); |
e0f01a21 MO |
2765 | } |
2766 | ||
bdcff1c5 MO |
2767 | /** |
2768 | * port2_lun_table_show() - presents the current LUN table of port 2 | |
2769 | * @dev: Generic device associated with the host owning the port. | |
2770 | * @attr: Device attribute representing the port. | |
2771 | * @buf: Buffer of length PAGE_SIZE to report back port status in ASCII. | |
2772 | * | |
2773 | * Return: The size of the ASCII string returned in @buf. | |
2774 | */ | |
2775 | static ssize_t port2_lun_table_show(struct device *dev, | |
2776 | struct device_attribute *attr, | |
2777 | char *buf) | |
2778 | { | |
2779 | struct cxlflash_cfg *cfg = shost_priv(class_to_shost(dev)); | |
2780 | ||
2781 | return cxlflash_show_port_lun_table(2, cfg, buf); | |
2782 | } | |
2783 | ||
2784 | /** | |
2785 | * port3_lun_table_show() - presents the current LUN table of port 3 | |
2786 | * @dev: Generic device associated with the host owning the port. | |
2787 | * @attr: Device attribute representing the port. | |
2788 | * @buf: Buffer of length PAGE_SIZE to report back port status in ASCII. | |
2789 | * | |
2790 | * Return: The size of the ASCII string returned in @buf. | |
2791 | */ | |
2792 | static ssize_t port3_lun_table_show(struct device *dev, | |
2793 | struct device_attribute *attr, | |
2794 | char *buf) | |
2795 | { | |
2796 | struct cxlflash_cfg *cfg = shost_priv(class_to_shost(dev)); | |
2797 | ||
2798 | return cxlflash_show_port_lun_table(3, cfg, buf); | |
2799 | } | |
2800 | ||
2588f222 MO |
2801 | /** |
2802 | * irqpoll_weight_show() - presents the current IRQ poll weight for the host | |
2803 | * @dev: Generic device associated with the host. | |
2804 | * @attr: Device attribute representing the IRQ poll weight. | |
2805 | * @buf: Buffer of length PAGE_SIZE to report back the current IRQ poll | |
2806 | * weight in ASCII. | |
2807 | * | |
2808 | * An IRQ poll weight of 0 indicates polling is disabled. | |
2809 | * | |
2810 | * Return: The size of the ASCII string returned in @buf. | |
2811 | */ | |
2812 | static ssize_t irqpoll_weight_show(struct device *dev, | |
2813 | struct device_attribute *attr, char *buf) | |
2814 | { | |
2815 | struct cxlflash_cfg *cfg = shost_priv(class_to_shost(dev)); | |
2816 | struct afu *afu = cfg->afu; | |
2817 | ||
2818 | return scnprintf(buf, PAGE_SIZE, "%u\n", afu->irqpoll_weight); | |
2819 | } | |
2820 | ||
2821 | /** | |
2822 | * irqpoll_weight_store() - sets the current IRQ poll weight for the host | |
2823 | * @dev: Generic device associated with the host. | |
2824 | * @attr: Device attribute representing the IRQ poll weight. | |
2825 | * @buf: Buffer of length PAGE_SIZE containing the desired IRQ poll | |
2826 | * weight in ASCII. | |
2827 | * @count: Length of data resizing in @buf. | |
2828 | * | |
2829 | * An IRQ poll weight of 0 indicates polling is disabled. | |
2830 | * | |
2831 | * Return: The size of the ASCII string returned in @buf. | |
2832 | */ | |
2833 | static ssize_t irqpoll_weight_store(struct device *dev, | |
2834 | struct device_attribute *attr, | |
2835 | const char *buf, size_t count) | |
2836 | { | |
2837 | struct cxlflash_cfg *cfg = shost_priv(class_to_shost(dev)); | |
2838 | struct device *cfgdev = &cfg->dev->dev; | |
2839 | struct afu *afu = cfg->afu; | |
a583d00a | 2840 | struct hwq *hwq; |
2588f222 | 2841 | u32 weight; |
a583d00a | 2842 | int rc, i; |
2588f222 MO |
2843 | |
2844 | rc = kstrtouint(buf, 10, &weight); | |
2845 | if (rc) | |
2846 | return -EINVAL; | |
2847 | ||
2848 | if (weight > 256) { | |
2849 | dev_info(cfgdev, | |
2850 | "Invalid IRQ poll weight. It must be 256 or less.\n"); | |
2851 | return -EINVAL; | |
2852 | } | |
2853 | ||
2854 | if (weight == afu->irqpoll_weight) { | |
2855 | dev_info(cfgdev, | |
2856 | "Current IRQ poll weight has the same weight.\n"); | |
2857 | return -EINVAL; | |
2858 | } | |
2859 | ||
a583d00a | 2860 | if (afu_is_irqpoll_enabled(afu)) { |
bb85ef68 | 2861 | for (i = 0; i < afu->num_hwqs; i++) { |
a583d00a UK |
2862 | hwq = get_hwq(afu, i); |
2863 | ||
2864 | irq_poll_disable(&hwq->irqpoll); | |
2865 | } | |
2866 | } | |
2588f222 MO |
2867 | |
2868 | afu->irqpoll_weight = weight; | |
2869 | ||
a583d00a | 2870 | if (weight > 0) { |
bb85ef68 | 2871 | for (i = 0; i < afu->num_hwqs; i++) { |
a583d00a UK |
2872 | hwq = get_hwq(afu, i); |
2873 | ||
2874 | irq_poll_init(&hwq->irqpoll, weight, cxlflash_irqpoll); | |
2875 | } | |
2876 | } | |
2588f222 MO |
2877 | |
2878 | return count; | |
2879 | } | |
2880 | ||
bb85ef68 MO |
2881 | /** |
2882 | * num_hwqs_show() - presents the number of hardware queues for the host | |
2883 | * @dev: Generic device associated with the host. | |
2884 | * @attr: Device attribute representing the number of hardware queues. | |
2885 | * @buf: Buffer of length PAGE_SIZE to report back the number of hardware | |
2886 | * queues in ASCII. | |
2887 | * | |
2888 | * Return: The size of the ASCII string returned in @buf. | |
2889 | */ | |
2890 | static ssize_t num_hwqs_show(struct device *dev, | |
2891 | struct device_attribute *attr, char *buf) | |
2892 | { | |
2893 | struct cxlflash_cfg *cfg = shost_priv(class_to_shost(dev)); | |
2894 | struct afu *afu = cfg->afu; | |
2895 | ||
2896 | return scnprintf(buf, PAGE_SIZE, "%u\n", afu->num_hwqs); | |
2897 | } | |
2898 | ||
2899 | /** | |
2900 | * num_hwqs_store() - sets the number of hardware queues for the host | |
2901 | * @dev: Generic device associated with the host. | |
2902 | * @attr: Device attribute representing the number of hardware queues. | |
2903 | * @buf: Buffer of length PAGE_SIZE containing the number of hardware | |
2904 | * queues in ASCII. | |
2905 | * @count: Length of data resizing in @buf. | |
2906 | * | |
2907 | * n > 0: num_hwqs = n | |
2908 | * n = 0: num_hwqs = num_online_cpus() | |
2909 | * n < 0: num_online_cpus() / abs(n) | |
2910 | * | |
2911 | * Return: The size of the ASCII string returned in @buf. | |
2912 | */ | |
2913 | static ssize_t num_hwqs_store(struct device *dev, | |
2914 | struct device_attribute *attr, | |
2915 | const char *buf, size_t count) | |
2916 | { | |
2917 | struct cxlflash_cfg *cfg = shost_priv(class_to_shost(dev)); | |
2918 | struct afu *afu = cfg->afu; | |
2919 | int rc; | |
2920 | int nhwqs, num_hwqs; | |
2921 | ||
2922 | rc = kstrtoint(buf, 10, &nhwqs); | |
2923 | if (rc) | |
2924 | return -EINVAL; | |
2925 | ||
2926 | if (nhwqs >= 1) | |
2927 | num_hwqs = nhwqs; | |
2928 | else if (nhwqs == 0) | |
2929 | num_hwqs = num_online_cpus(); | |
2930 | else | |
2931 | num_hwqs = num_online_cpus() / abs(nhwqs); | |
2932 | ||
2933 | afu->desired_hwqs = min(num_hwqs, CXLFLASH_MAX_HWQS); | |
2934 | WARN_ON_ONCE(afu->desired_hwqs == 0); | |
2935 | ||
2936 | retry: | |
2937 | switch (cfg->state) { | |
2938 | case STATE_NORMAL: | |
2939 | cfg->state = STATE_RESET; | |
2940 | drain_ioctls(cfg); | |
2941 | cxlflash_mark_contexts_error(cfg); | |
2942 | rc = afu_reset(cfg); | |
2943 | if (rc) | |
2944 | cfg->state = STATE_FAILTERM; | |
2945 | else | |
2946 | cfg->state = STATE_NORMAL; | |
2947 | wake_up_all(&cfg->reset_waitq); | |
2948 | break; | |
2949 | case STATE_RESET: | |
2950 | wait_event(cfg->reset_waitq, cfg->state != STATE_RESET); | |
2951 | if (cfg->state == STATE_NORMAL) | |
2952 | goto retry; | |
2953 | default: | |
2954 | /* Ideally should not happen */ | |
2955 | dev_err(dev, "%s: Device is not ready, state=%d\n", | |
2956 | __func__, cfg->state); | |
2957 | break; | |
2958 | } | |
2959 | ||
2960 | return count; | |
2961 | } | |
2962 | ||
8c052e9e MO |
2963 | static const char *hwq_mode_name[MAX_HWQ_MODE] = { "rr", "tag", "cpu" }; |
2964 | ||
2965 | /** | |
2966 | * hwq_mode_show() - presents the HWQ steering mode for the host | |
2967 | * @dev: Generic device associated with the host. | |
2968 | * @attr: Device attribute representing the HWQ steering mode. | |
2969 | * @buf: Buffer of length PAGE_SIZE to report back the HWQ steering mode | |
2970 | * as a character string. | |
2971 | * | |
2972 | * Return: The size of the ASCII string returned in @buf. | |
2973 | */ | |
2974 | static ssize_t hwq_mode_show(struct device *dev, | |
2975 | struct device_attribute *attr, char *buf) | |
2976 | { | |
2977 | struct cxlflash_cfg *cfg = shost_priv(class_to_shost(dev)); | |
2978 | struct afu *afu = cfg->afu; | |
2979 | ||
2980 | return scnprintf(buf, PAGE_SIZE, "%s\n", hwq_mode_name[afu->hwq_mode]); | |
2981 | } | |
2982 | ||
2983 | /** | |
2984 | * hwq_mode_store() - sets the HWQ steering mode for the host | |
2985 | * @dev: Generic device associated with the host. | |
2986 | * @attr: Device attribute representing the HWQ steering mode. | |
2987 | * @buf: Buffer of length PAGE_SIZE containing the HWQ steering mode | |
2988 | * as a character string. | |
2989 | * @count: Length of data resizing in @buf. | |
2990 | * | |
2991 | * rr = Round-Robin | |
2992 | * tag = Block MQ Tagging | |
2993 | * cpu = CPU Affinity | |
2994 | * | |
2995 | * Return: The size of the ASCII string returned in @buf. | |
2996 | */ | |
2997 | static ssize_t hwq_mode_store(struct device *dev, | |
2998 | struct device_attribute *attr, | |
2999 | const char *buf, size_t count) | |
3000 | { | |
3001 | struct Scsi_Host *shost = class_to_shost(dev); | |
3002 | struct cxlflash_cfg *cfg = shost_priv(shost); | |
3003 | struct device *cfgdev = &cfg->dev->dev; | |
3004 | struct afu *afu = cfg->afu; | |
3005 | int i; | |
3006 | u32 mode = MAX_HWQ_MODE; | |
3007 | ||
3008 | for (i = 0; i < MAX_HWQ_MODE; i++) { | |
3009 | if (!strncmp(hwq_mode_name[i], buf, strlen(hwq_mode_name[i]))) { | |
3010 | mode = i; | |
3011 | break; | |
3012 | } | |
3013 | } | |
3014 | ||
3015 | if (mode >= MAX_HWQ_MODE) { | |
3016 | dev_info(cfgdev, "Invalid HWQ steering mode.\n"); | |
3017 | return -EINVAL; | |
3018 | } | |
3019 | ||
3020 | if ((mode == HWQ_MODE_TAG) && !shost_use_blk_mq(shost)) { | |
3021 | dev_info(cfgdev, "SCSI-MQ is not enabled, use a different " | |
3022 | "HWQ steering mode.\n"); | |
3023 | return -EINVAL; | |
3024 | } | |
3025 | ||
3026 | afu->hwq_mode = mode; | |
3027 | ||
3028 | return count; | |
3029 | } | |
3030 | ||
e0f01a21 MO |
3031 | /** |
3032 | * mode_show() - presents the current mode of the device | |
15305514 MO |
3033 | * @dev: Generic device associated with the device. |
3034 | * @attr: Device attribute representing the device mode. | |
3035 | * @buf: Buffer of length PAGE_SIZE to report back the dev mode in ASCII. | |
3036 | * | |
3037 | * Return: The size of the ASCII string returned in @buf. | |
3038 | */ | |
e0f01a21 MO |
3039 | static ssize_t mode_show(struct device *dev, |
3040 | struct device_attribute *attr, char *buf) | |
15305514 MO |
3041 | { |
3042 | struct scsi_device *sdev = to_scsi_device(dev); | |
3043 | ||
e0f01a21 MO |
3044 | return scnprintf(buf, PAGE_SIZE, "%s\n", |
3045 | sdev->hostdata ? "superpipe" : "legacy"); | |
15305514 MO |
3046 | } |
3047 | ||
3048 | /* | |
3049 | * Host attributes | |
3050 | */ | |
e0f01a21 MO |
3051 | static DEVICE_ATTR_RO(port0); |
3052 | static DEVICE_ATTR_RO(port1); | |
bdcff1c5 MO |
3053 | static DEVICE_ATTR_RO(port2); |
3054 | static DEVICE_ATTR_RO(port3); | |
e0f01a21 MO |
3055 | static DEVICE_ATTR_RW(lun_mode); |
3056 | static DEVICE_ATTR_RO(ioctl_version); | |
3057 | static DEVICE_ATTR_RO(port0_lun_table); | |
3058 | static DEVICE_ATTR_RO(port1_lun_table); | |
bdcff1c5 MO |
3059 | static DEVICE_ATTR_RO(port2_lun_table); |
3060 | static DEVICE_ATTR_RO(port3_lun_table); | |
2588f222 | 3061 | static DEVICE_ATTR_RW(irqpoll_weight); |
bb85ef68 | 3062 | static DEVICE_ATTR_RW(num_hwqs); |
8c052e9e | 3063 | static DEVICE_ATTR_RW(hwq_mode); |
15305514 MO |
3064 | |
3065 | static struct device_attribute *cxlflash_host_attrs[] = { | |
3066 | &dev_attr_port0, | |
3067 | &dev_attr_port1, | |
bdcff1c5 MO |
3068 | &dev_attr_port2, |
3069 | &dev_attr_port3, | |
15305514 MO |
3070 | &dev_attr_lun_mode, |
3071 | &dev_attr_ioctl_version, | |
e0f01a21 MO |
3072 | &dev_attr_port0_lun_table, |
3073 | &dev_attr_port1_lun_table, | |
bdcff1c5 MO |
3074 | &dev_attr_port2_lun_table, |
3075 | &dev_attr_port3_lun_table, | |
2588f222 | 3076 | &dev_attr_irqpoll_weight, |
bb85ef68 | 3077 | &dev_attr_num_hwqs, |
8c052e9e | 3078 | &dev_attr_hwq_mode, |
15305514 MO |
3079 | NULL |
3080 | }; | |
3081 | ||
3082 | /* | |
3083 | * Device attributes | |
3084 | */ | |
e0f01a21 | 3085 | static DEVICE_ATTR_RO(mode); |
15305514 MO |
3086 | |
3087 | static struct device_attribute *cxlflash_dev_attrs[] = { | |
3088 | &dev_attr_mode, | |
3089 | NULL | |
3090 | }; | |
3091 | ||
3092 | /* | |
3093 | * Host template | |
3094 | */ | |
3095 | static struct scsi_host_template driver_template = { | |
3096 | .module = THIS_MODULE, | |
3097 | .name = CXLFLASH_ADAPTER_NAME, | |
3098 | .info = cxlflash_driver_info, | |
3099 | .ioctl = cxlflash_ioctl, | |
3100 | .proc_name = CXLFLASH_NAME, | |
3101 | .queuecommand = cxlflash_queuecommand, | |
4ab47257 | 3102 | .eh_abort_handler = cxlflash_eh_abort_handler, |
15305514 MO |
3103 | .eh_device_reset_handler = cxlflash_eh_device_reset_handler, |
3104 | .eh_host_reset_handler = cxlflash_eh_host_reset_handler, | |
3105 | .change_queue_depth = cxlflash_change_queue_depth, | |
83430833 | 3106 | .cmd_per_lun = CXLFLASH_MAX_CMDS_PER_LUN, |
15305514 | 3107 | .can_queue = CXLFLASH_MAX_CMDS, |
5fbb96c8 | 3108 | .cmd_size = sizeof(struct afu_cmd) + __alignof__(struct afu_cmd) - 1, |
15305514 | 3109 | .this_id = -1, |
68ab2d76 | 3110 | .sg_tablesize = 1, /* No scatter gather support */ |
15305514 MO |
3111 | .max_sectors = CXLFLASH_MAX_SECTORS, |
3112 | .use_clustering = ENABLE_CLUSTERING, | |
3113 | .shost_attrs = cxlflash_host_attrs, | |
3114 | .sdev_attrs = cxlflash_dev_attrs, | |
3115 | }; | |
3116 | ||
3117 | /* | |
3118 | * Device dependent values | |
3119 | */ | |
96e1b660 UK |
3120 | static struct dev_dependent_vals dev_corsa_vals = { CXLFLASH_MAX_SECTORS, |
3121 | 0ULL }; | |
3122 | static struct dev_dependent_vals dev_flash_gt_vals = { CXLFLASH_MAX_SECTORS, | |
704c4b0d | 3123 | CXLFLASH_NOTIFY_SHUTDOWN }; |
42f90a6b MO |
3124 | static struct dev_dependent_vals dev_briard_vals = { CXLFLASH_MAX_SECTORS, |
3125 | CXLFLASH_NOTIFY_SHUTDOWN }; | |
15305514 MO |
3126 | |
3127 | /* | |
3128 | * PCI device binding table | |
3129 | */ | |
3130 | static struct pci_device_id cxlflash_pci_table[] = { | |
3131 | {PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CORSA, | |
3132 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, (kernel_ulong_t)&dev_corsa_vals}, | |
a2746fb1 MK |
3133 | {PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_FLASH_GT, |
3134 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, (kernel_ulong_t)&dev_flash_gt_vals}, | |
42f90a6b MO |
3135 | {PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_BRIARD, |
3136 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, (kernel_ulong_t)&dev_briard_vals}, | |
15305514 MO |
3137 | {} |
3138 | }; | |
3139 | ||
3140 | MODULE_DEVICE_TABLE(pci, cxlflash_pci_table); | |
3141 | ||
c21e0bbf MO |
3142 | /** |
3143 | * cxlflash_worker_thread() - work thread handler for the AFU | |
3144 | * @work: Work structure contained within cxlflash associated with host. | |
3145 | * | |
3146 | * Handles the following events: | |
3147 | * - Link reset which cannot be performed on interrupt context due to | |
3148 | * blocking up to a few seconds | |
ef51074a | 3149 | * - Rescan the host |
c21e0bbf MO |
3150 | */ |
3151 | static void cxlflash_worker_thread(struct work_struct *work) | |
3152 | { | |
5cdac81a MO |
3153 | struct cxlflash_cfg *cfg = container_of(work, struct cxlflash_cfg, |
3154 | work_q); | |
c21e0bbf | 3155 | struct afu *afu = cfg->afu; |
4392ba49 | 3156 | struct device *dev = &cfg->dev->dev; |
c885d3fe | 3157 | __be64 __iomem *fc_port_regs; |
c21e0bbf MO |
3158 | int port; |
3159 | ulong lock_flags; | |
3160 | ||
5cdac81a MO |
3161 | /* Avoid MMIO if the device has failed */ |
3162 | ||
3163 | if (cfg->state != STATE_NORMAL) | |
3164 | return; | |
3165 | ||
c21e0bbf MO |
3166 | spin_lock_irqsave(cfg->host->host_lock, lock_flags); |
3167 | ||
3168 | if (cfg->lr_state == LINK_RESET_REQUIRED) { | |
3169 | port = cfg->lr_port; | |
3170 | if (port < 0) | |
4392ba49 MO |
3171 | dev_err(dev, "%s: invalid port index %d\n", |
3172 | __func__, port); | |
c21e0bbf MO |
3173 | else { |
3174 | spin_unlock_irqrestore(cfg->host->host_lock, | |
3175 | lock_flags); | |
3176 | ||
3177 | /* The reset can block... */ | |
c885d3fe MO |
3178 | fc_port_regs = get_fc_port_regs(cfg, port); |
3179 | afu_link_reset(afu, port, fc_port_regs); | |
c21e0bbf MO |
3180 | spin_lock_irqsave(cfg->host->host_lock, lock_flags); |
3181 | } | |
3182 | ||
3183 | cfg->lr_state = LINK_RESET_COMPLETE; | |
3184 | } | |
3185 | ||
c21e0bbf | 3186 | spin_unlock_irqrestore(cfg->host->host_lock, lock_flags); |
ef51074a MO |
3187 | |
3188 | if (atomic_dec_if_positive(&cfg->scan_host_needed) >= 0) | |
3189 | scsi_scan_host(cfg->host); | |
c21e0bbf MO |
3190 | } |
3191 | ||
f3d79b3e UK |
3192 | /** |
3193 | * cxlflash_chr_open() - character device open handler | |
3194 | * @inode: Device inode associated with this character device. | |
3195 | * @file: File pointer for this device. | |
3196 | * | |
3197 | * Only users with admin privileges are allowed to open the character device. | |
3198 | * | |
3199 | * Return: 0 on success, -errno on failure | |
3200 | */ | |
3201 | static int cxlflash_chr_open(struct inode *inode, struct file *file) | |
3202 | { | |
3203 | struct cxlflash_cfg *cfg; | |
3204 | ||
3205 | if (!capable(CAP_SYS_ADMIN)) | |
3206 | return -EACCES; | |
3207 | ||
3208 | cfg = container_of(inode->i_cdev, struct cxlflash_cfg, cdev); | |
3209 | file->private_data = cfg; | |
3210 | ||
3211 | return 0; | |
3212 | } | |
3213 | ||
3214 | /* | |
3215 | * Character device file operations | |
3216 | */ | |
3217 | static const struct file_operations cxlflash_chr_fops = { | |
3218 | .owner = THIS_MODULE, | |
3219 | .open = cxlflash_chr_open, | |
3220 | }; | |
3221 | ||
3222 | /** | |
3223 | * init_chrdev() - initialize the character device for the host | |
3224 | * @cfg: Internal structure associated with the host. | |
3225 | * | |
3226 | * Return: 0 on success, -errno on failure | |
3227 | */ | |
3228 | static int init_chrdev(struct cxlflash_cfg *cfg) | |
3229 | { | |
3230 | struct device *dev = &cfg->dev->dev; | |
3231 | struct device *char_dev; | |
3232 | dev_t devno; | |
3233 | int minor; | |
3234 | int rc = 0; | |
3235 | ||
3236 | minor = cxlflash_get_minor(); | |
3237 | if (unlikely(minor < 0)) { | |
3238 | dev_err(dev, "%s: Exhausted allowed adapters\n", __func__); | |
3239 | rc = -ENOSPC; | |
3240 | goto out; | |
3241 | } | |
3242 | ||
3243 | devno = MKDEV(cxlflash_major, minor); | |
3244 | cdev_init(&cfg->cdev, &cxlflash_chr_fops); | |
3245 | ||
3246 | rc = cdev_add(&cfg->cdev, devno, 1); | |
3247 | if (rc) { | |
3248 | dev_err(dev, "%s: cdev_add failed rc=%d\n", __func__, rc); | |
3249 | goto err1; | |
3250 | } | |
3251 | ||
3252 | char_dev = device_create(cxlflash_class, NULL, devno, | |
3253 | NULL, "cxlflash%d", minor); | |
3254 | if (IS_ERR(char_dev)) { | |
3255 | rc = PTR_ERR(char_dev); | |
3256 | dev_err(dev, "%s: device_create failed rc=%d\n", | |
3257 | __func__, rc); | |
3258 | goto err2; | |
3259 | } | |
3260 | ||
3261 | cfg->chardev = char_dev; | |
3262 | out: | |
3263 | dev_dbg(dev, "%s: returning rc=%d\n", __func__, rc); | |
3264 | return rc; | |
3265 | err2: | |
3266 | cdev_del(&cfg->cdev); | |
3267 | err1: | |
3268 | cxlflash_put_minor(minor); | |
3269 | goto out; | |
3270 | } | |
3271 | ||
c21e0bbf MO |
3272 | /** |
3273 | * cxlflash_probe() - PCI entry point to add host | |
3274 | * @pdev: PCI device associated with the host. | |
3275 | * @dev_id: PCI device id associated with device. | |
3276 | * | |
f92ba507 MO |
3277 | * The device will initially start out in a 'probing' state and |
3278 | * transition to the 'normal' state at the end of a successful | |
3279 | * probe. Should an EEH event occur during probe, the notification | |
3280 | * thread (error_detected()) will wait until the probe handler | |
3281 | * is nearly complete. At that time, the device will be moved to | |
3282 | * a 'probed' state and the EEH thread woken up to drive the slot | |
3283 | * reset and recovery (device moves to 'normal' state). Meanwhile, | |
3284 | * the probe will be allowed to exit successfully. | |
3285 | * | |
1284fb0c | 3286 | * Return: 0 on success, -errno on failure |
c21e0bbf MO |
3287 | */ |
3288 | static int cxlflash_probe(struct pci_dev *pdev, | |
3289 | const struct pci_device_id *dev_id) | |
3290 | { | |
3291 | struct Scsi_Host *host; | |
3292 | struct cxlflash_cfg *cfg = NULL; | |
88d33628 | 3293 | struct device *dev = &pdev->dev; |
c21e0bbf MO |
3294 | struct dev_dependent_vals *ddv; |
3295 | int rc = 0; | |
66d4bce4 | 3296 | int k; |
c21e0bbf MO |
3297 | |
3298 | dev_dbg(&pdev->dev, "%s: Found CXLFLASH with IRQ: %d\n", | |
3299 | __func__, pdev->irq); | |
3300 | ||
3301 | ddv = (struct dev_dependent_vals *)dev_id->driver_data; | |
3302 | driver_template.max_sectors = ddv->max_sectors; | |
3303 | ||
3304 | host = scsi_host_alloc(&driver_template, sizeof(struct cxlflash_cfg)); | |
3305 | if (!host) { | |
88d33628 | 3306 | dev_err(dev, "%s: scsi_host_alloc failed\n", __func__); |
c21e0bbf MO |
3307 | rc = -ENOMEM; |
3308 | goto out; | |
3309 | } | |
3310 | ||
3311 | host->max_id = CXLFLASH_MAX_NUM_TARGETS_PER_BUS; | |
3312 | host->max_lun = CXLFLASH_MAX_NUM_LUNS_PER_TARGET; | |
c21e0bbf MO |
3313 | host->unique_id = host->host_no; |
3314 | host->max_cmd_len = CXLFLASH_MAX_CDB_LEN; | |
3315 | ||
88d33628 | 3316 | cfg = shost_priv(host); |
c21e0bbf MO |
3317 | cfg->host = host; |
3318 | rc = alloc_mem(cfg); | |
3319 | if (rc) { | |
88d33628 | 3320 | dev_err(dev, "%s: alloc_mem failed\n", __func__); |
c21e0bbf | 3321 | rc = -ENOMEM; |
8b5b1e87 | 3322 | scsi_host_put(cfg->host); |
c21e0bbf MO |
3323 | goto out; |
3324 | } | |
3325 | ||
3326 | cfg->init_state = INIT_STATE_NONE; | |
3327 | cfg->dev = pdev; | |
17ead26f | 3328 | cfg->cxl_fops = cxlflash_cxl_fops; |
2cb79266 MO |
3329 | |
3330 | /* | |
66d4bce4 MO |
3331 | * Promoted LUNs move to the top of the LUN table. The rest stay on |
3332 | * the bottom half. The bottom half grows from the end (index = 255), | |
3333 | * whereas the top half grows from the beginning (index = 0). | |
3334 | * | |
3335 | * Initialize the last LUN index for all possible ports. | |
2cb79266 | 3336 | */ |
66d4bce4 MO |
3337 | cfg->promote_lun_index = 0; |
3338 | ||
3339 | for (k = 0; k < MAX_FC_PORTS; k++) | |
3340 | cfg->last_lun_index[k] = CXLFLASH_NUM_VLUNS/2 - 1; | |
2cb79266 | 3341 | |
c21e0bbf | 3342 | cfg->dev_id = (struct pci_device_id *)dev_id; |
c21e0bbf MO |
3343 | |
3344 | init_waitqueue_head(&cfg->tmf_waitq); | |
439e85c1 | 3345 | init_waitqueue_head(&cfg->reset_waitq); |
c21e0bbf MO |
3346 | |
3347 | INIT_WORK(&cfg->work_q, cxlflash_worker_thread); | |
3348 | cfg->lr_state = LINK_RESET_INVALID; | |
3349 | cfg->lr_port = -1; | |
0d73122c | 3350 | spin_lock_init(&cfg->tmf_slock); |
65be2c79 MO |
3351 | mutex_init(&cfg->ctx_tbl_list_mutex); |
3352 | mutex_init(&cfg->ctx_recovery_mutex); | |
0a27ae51 | 3353 | init_rwsem(&cfg->ioctl_rwsem); |
65be2c79 MO |
3354 | INIT_LIST_HEAD(&cfg->ctx_err_recovery); |
3355 | INIT_LIST_HEAD(&cfg->lluns); | |
c21e0bbf MO |
3356 | |
3357 | pci_set_drvdata(pdev, cfg); | |
3358 | ||
c21e0bbf MO |
3359 | cfg->cxl_afu = cxl_pci_to_afu(pdev); |
3360 | ||
3361 | rc = init_pci(cfg); | |
3362 | if (rc) { | |
88d33628 | 3363 | dev_err(dev, "%s: init_pci failed rc=%d\n", __func__, rc); |
c21e0bbf MO |
3364 | goto out_remove; |
3365 | } | |
3366 | cfg->init_state = INIT_STATE_PCI; | |
3367 | ||
3368 | rc = init_afu(cfg); | |
f92ba507 | 3369 | if (rc && !wq_has_sleeper(&cfg->reset_waitq)) { |
88d33628 | 3370 | dev_err(dev, "%s: init_afu failed rc=%d\n", __func__, rc); |
c21e0bbf MO |
3371 | goto out_remove; |
3372 | } | |
3373 | cfg->init_state = INIT_STATE_AFU; | |
3374 | ||
c21e0bbf MO |
3375 | rc = init_scsi(cfg); |
3376 | if (rc) { | |
88d33628 | 3377 | dev_err(dev, "%s: init_scsi failed rc=%d\n", __func__, rc); |
c21e0bbf MO |
3378 | goto out_remove; |
3379 | } | |
3380 | cfg->init_state = INIT_STATE_SCSI; | |
3381 | ||
f3d79b3e UK |
3382 | rc = init_chrdev(cfg); |
3383 | if (rc) { | |
3384 | dev_err(dev, "%s: init_chrdev failed rc=%d\n", __func__, rc); | |
3385 | goto out_remove; | |
3386 | } | |
3387 | cfg->init_state = INIT_STATE_CDEV; | |
3388 | ||
f92ba507 MO |
3389 | if (wq_has_sleeper(&cfg->reset_waitq)) { |
3390 | cfg->state = STATE_PROBED; | |
3391 | wake_up_all(&cfg->reset_waitq); | |
3392 | } else | |
3393 | cfg->state = STATE_NORMAL; | |
c21e0bbf | 3394 | out: |
88d33628 | 3395 | dev_dbg(dev, "%s: returning rc=%d\n", __func__, rc); |
c21e0bbf MO |
3396 | return rc; |
3397 | ||
3398 | out_remove: | |
3399 | cxlflash_remove(pdev); | |
3400 | goto out; | |
3401 | } | |
3402 | ||
5cdac81a MO |
3403 | /** |
3404 | * cxlflash_pci_error_detected() - called when a PCI error is detected | |
3405 | * @pdev: PCI device struct. | |
3406 | * @state: PCI channel state. | |
3407 | * | |
1d3324c3 MO |
3408 | * When an EEH occurs during an active reset, wait until the reset is |
3409 | * complete and then take action based upon the device state. | |
3410 | * | |
5cdac81a MO |
3411 | * Return: PCI_ERS_RESULT_NEED_RESET or PCI_ERS_RESULT_DISCONNECT |
3412 | */ | |
3413 | static pci_ers_result_t cxlflash_pci_error_detected(struct pci_dev *pdev, | |
3414 | pci_channel_state_t state) | |
3415 | { | |
65be2c79 | 3416 | int rc = 0; |
5cdac81a MO |
3417 | struct cxlflash_cfg *cfg = pci_get_drvdata(pdev); |
3418 | struct device *dev = &cfg->dev->dev; | |
3419 | ||
3420 | dev_dbg(dev, "%s: pdev=%p state=%u\n", __func__, pdev, state); | |
3421 | ||
3422 | switch (state) { | |
3423 | case pci_channel_io_frozen: | |
f92ba507 MO |
3424 | wait_event(cfg->reset_waitq, cfg->state != STATE_RESET && |
3425 | cfg->state != STATE_PROBING); | |
1d3324c3 MO |
3426 | if (cfg->state == STATE_FAILTERM) |
3427 | return PCI_ERS_RESULT_DISCONNECT; | |
3428 | ||
439e85c1 | 3429 | cfg->state = STATE_RESET; |
5cdac81a | 3430 | scsi_block_requests(cfg->host); |
0a27ae51 | 3431 | drain_ioctls(cfg); |
65be2c79 MO |
3432 | rc = cxlflash_mark_contexts_error(cfg); |
3433 | if (unlikely(rc)) | |
88d33628 | 3434 | dev_err(dev, "%s: Failed to mark user contexts rc=%d\n", |
65be2c79 | 3435 | __func__, rc); |
9526f360 | 3436 | term_afu(cfg); |
5cdac81a MO |
3437 | return PCI_ERS_RESULT_NEED_RESET; |
3438 | case pci_channel_io_perm_failure: | |
3439 | cfg->state = STATE_FAILTERM; | |
439e85c1 | 3440 | wake_up_all(&cfg->reset_waitq); |
5cdac81a MO |
3441 | scsi_unblock_requests(cfg->host); |
3442 | return PCI_ERS_RESULT_DISCONNECT; | |
3443 | default: | |
3444 | break; | |
3445 | } | |
3446 | return PCI_ERS_RESULT_NEED_RESET; | |
3447 | } | |
3448 | ||
3449 | /** | |
3450 | * cxlflash_pci_slot_reset() - called when PCI slot has been reset | |
3451 | * @pdev: PCI device struct. | |
3452 | * | |
3453 | * This routine is called by the pci error recovery code after the PCI | |
3454 | * slot has been reset, just before we should resume normal operations. | |
3455 | * | |
3456 | * Return: PCI_ERS_RESULT_RECOVERED or PCI_ERS_RESULT_DISCONNECT | |
3457 | */ | |
3458 | static pci_ers_result_t cxlflash_pci_slot_reset(struct pci_dev *pdev) | |
3459 | { | |
3460 | int rc = 0; | |
3461 | struct cxlflash_cfg *cfg = pci_get_drvdata(pdev); | |
3462 | struct device *dev = &cfg->dev->dev; | |
3463 | ||
3464 | dev_dbg(dev, "%s: pdev=%p\n", __func__, pdev); | |
3465 | ||
3466 | rc = init_afu(cfg); | |
3467 | if (unlikely(rc)) { | |
88d33628 | 3468 | dev_err(dev, "%s: EEH recovery failed rc=%d\n", __func__, rc); |
5cdac81a MO |
3469 | return PCI_ERS_RESULT_DISCONNECT; |
3470 | } | |
3471 | ||
3472 | return PCI_ERS_RESULT_RECOVERED; | |
3473 | } | |
3474 | ||
3475 | /** | |
3476 | * cxlflash_pci_resume() - called when normal operation can resume | |
3477 | * @pdev: PCI device struct | |
3478 | */ | |
3479 | static void cxlflash_pci_resume(struct pci_dev *pdev) | |
3480 | { | |
3481 | struct cxlflash_cfg *cfg = pci_get_drvdata(pdev); | |
3482 | struct device *dev = &cfg->dev->dev; | |
3483 | ||
3484 | dev_dbg(dev, "%s: pdev=%p\n", __func__, pdev); | |
3485 | ||
3486 | cfg->state = STATE_NORMAL; | |
439e85c1 | 3487 | wake_up_all(&cfg->reset_waitq); |
5cdac81a MO |
3488 | scsi_unblock_requests(cfg->host); |
3489 | } | |
3490 | ||
f3d79b3e UK |
3491 | /** |
3492 | * cxlflash_devnode() - provides devtmpfs for devices in the cxlflash class | |
3493 | * @dev: Character device. | |
3494 | * @mode: Mode that can be used to verify access. | |
3495 | * | |
3496 | * Return: Allocated string describing the devtmpfs structure. | |
3497 | */ | |
3498 | static char *cxlflash_devnode(struct device *dev, umode_t *mode) | |
3499 | { | |
3500 | return kasprintf(GFP_KERNEL, "cxlflash/%s", dev_name(dev)); | |
3501 | } | |
3502 | ||
3503 | /** | |
3504 | * cxlflash_class_init() - create character device class | |
3505 | * | |
3506 | * Return: 0 on success, -errno on failure | |
3507 | */ | |
3508 | static int cxlflash_class_init(void) | |
3509 | { | |
3510 | dev_t devno; | |
3511 | int rc = 0; | |
3512 | ||
3513 | rc = alloc_chrdev_region(&devno, 0, CXLFLASH_MAX_ADAPTERS, "cxlflash"); | |
3514 | if (unlikely(rc)) { | |
3515 | pr_err("%s: alloc_chrdev_region failed rc=%d\n", __func__, rc); | |
3516 | goto out; | |
3517 | } | |
3518 | ||
3519 | cxlflash_major = MAJOR(devno); | |
3520 | ||
3521 | cxlflash_class = class_create(THIS_MODULE, "cxlflash"); | |
3522 | if (IS_ERR(cxlflash_class)) { | |
3523 | rc = PTR_ERR(cxlflash_class); | |
3524 | pr_err("%s: class_create failed rc=%d\n", __func__, rc); | |
3525 | goto err; | |
3526 | } | |
3527 | ||
3528 | cxlflash_class->devnode = cxlflash_devnode; | |
3529 | out: | |
3530 | pr_debug("%s: returning rc=%d\n", __func__, rc); | |
3531 | return rc; | |
3532 | err: | |
3533 | unregister_chrdev_region(devno, CXLFLASH_MAX_ADAPTERS); | |
3534 | goto out; | |
3535 | } | |
3536 | ||
3537 | /** | |
3538 | * cxlflash_class_exit() - destroy character device class | |
3539 | */ | |
3540 | static void cxlflash_class_exit(void) | |
3541 | { | |
3542 | dev_t devno = MKDEV(cxlflash_major, 0); | |
3543 | ||
3544 | class_destroy(cxlflash_class); | |
3545 | unregister_chrdev_region(devno, CXLFLASH_MAX_ADAPTERS); | |
3546 | } | |
3547 | ||
5cdac81a MO |
3548 | static const struct pci_error_handlers cxlflash_err_handler = { |
3549 | .error_detected = cxlflash_pci_error_detected, | |
3550 | .slot_reset = cxlflash_pci_slot_reset, | |
3551 | .resume = cxlflash_pci_resume, | |
3552 | }; | |
3553 | ||
c21e0bbf MO |
3554 | /* |
3555 | * PCI device structure | |
3556 | */ | |
3557 | static struct pci_driver cxlflash_driver = { | |
3558 | .name = CXLFLASH_NAME, | |
3559 | .id_table = cxlflash_pci_table, | |
3560 | .probe = cxlflash_probe, | |
3561 | .remove = cxlflash_remove, | |
babf985d | 3562 | .shutdown = cxlflash_remove, |
5cdac81a | 3563 | .err_handler = &cxlflash_err_handler, |
c21e0bbf MO |
3564 | }; |
3565 | ||
3566 | /** | |
3567 | * init_cxlflash() - module entry point | |
3568 | * | |
1284fb0c | 3569 | * Return: 0 on success, -errno on failure |
c21e0bbf MO |
3570 | */ |
3571 | static int __init init_cxlflash(void) | |
3572 | { | |
f3d79b3e UK |
3573 | int rc; |
3574 | ||
db853d50 | 3575 | check_sizes(); |
65be2c79 | 3576 | cxlflash_list_init(); |
f3d79b3e UK |
3577 | rc = cxlflash_class_init(); |
3578 | if (unlikely(rc)) | |
3579 | goto out; | |
65be2c79 | 3580 | |
f3d79b3e UK |
3581 | rc = pci_register_driver(&cxlflash_driver); |
3582 | if (unlikely(rc)) | |
3583 | goto err; | |
3584 | out: | |
3585 | pr_debug("%s: returning rc=%d\n", __func__, rc); | |
3586 | return rc; | |
3587 | err: | |
3588 | cxlflash_class_exit(); | |
3589 | goto out; | |
c21e0bbf MO |
3590 | } |
3591 | ||
3592 | /** | |
3593 | * exit_cxlflash() - module exit point | |
3594 | */ | |
3595 | static void __exit exit_cxlflash(void) | |
3596 | { | |
65be2c79 MO |
3597 | cxlflash_term_global_luns(); |
3598 | cxlflash_free_errpage(); | |
3599 | ||
c21e0bbf | 3600 | pci_unregister_driver(&cxlflash_driver); |
f3d79b3e | 3601 | cxlflash_class_exit(); |
c21e0bbf MO |
3602 | } |
3603 | ||
3604 | module_init(init_cxlflash); | |
3605 | module_exit(exit_cxlflash); |