3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_GTDT if ACPI
6 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
7 select ACPI_MCFG if ACPI
8 select ACPI_SPCR_TABLE if ACPI
9 select ARCH_CLOCKSOURCE_DATA
10 select ARCH_HAS_DEVMEM_IS_ALLOWED
11 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
12 select ARCH_HAS_ELF_RANDOMIZE
13 select ARCH_HAS_GCOV_PROFILE_ALL
14 select ARCH_HAS_GIGANTIC_PAGE
16 select ARCH_HAS_SG_CHAIN
17 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
18 select ARCH_HAVE_NMI_SAFE_CMPXCHG if ACPI_APEI_SEA
19 select ARCH_USE_CMPXCHG_LOCKREF
20 select ARCH_SUPPORTS_MEMORY_FAILURE
21 select ARCH_SUPPORTS_ATOMIC_RMW
22 select ARCH_SUPPORTS_NUMA_BALANCING
23 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
24 select ARCH_WANT_FRAME_POINTERS
25 select ARCH_HAS_UBSAN_SANITIZE_ALL
29 select AUDIT_ARCH_COMPAT_GENERIC
30 select ARM_GIC_V2M if PCI
32 select ARM_GIC_V3_ITS if PCI
34 select BUILDTIME_EXTABLE_SORT
35 select CLONE_BACKWARDS
37 select CPU_PM if (SUSPEND || CPU_IDLE)
38 select DCACHE_WORD_ACCESS
41 select GENERIC_ALLOCATOR
42 select GENERIC_CLOCKEVENTS
43 select GENERIC_CLOCKEVENTS_BROADCAST
44 select GENERIC_CPU_AUTOPROBE
45 select GENERIC_EARLY_IOREMAP
46 select GENERIC_IDLE_POLL_SETUP
47 select GENERIC_IRQ_PROBE
48 select GENERIC_IRQ_SHOW
49 select GENERIC_IRQ_SHOW_LEVEL
50 select GENERIC_PCI_IOMAP
51 select GENERIC_SCHED_CLOCK
52 select GENERIC_SMP_IDLE_THREAD
53 select GENERIC_STRNCPY_FROM_USER
54 select GENERIC_STRNLEN_USER
55 select GENERIC_TIME_VSYSCALL
56 select HANDLE_DOMAIN_IRQ
57 select HARDIRQS_SW_RESEND
58 select HAVE_ACPI_APEI if (ACPI && EFI)
59 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
60 select HAVE_ARCH_AUDITSYSCALL
61 select HAVE_ARCH_BITREVERSE
62 select HAVE_ARCH_HARDENED_USERCOPY
63 select HAVE_ARCH_HUGE_VMAP
64 select HAVE_ARCH_JUMP_LABEL
65 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
67 select HAVE_ARCH_MMAP_RND_BITS
68 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
69 select HAVE_ARCH_SECCOMP_FILTER
70 select HAVE_ARCH_TRACEHOOK
71 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
74 select HAVE_C_RECORDMCOUNT
75 select HAVE_CC_STACKPROTECTOR
76 select HAVE_CMPXCHG_DOUBLE
77 select HAVE_CMPXCHG_LOCAL
78 select HAVE_CONTEXT_TRACKING
79 select HAVE_DEBUG_BUGVERBOSE
80 select HAVE_DEBUG_KMEMLEAK
81 select HAVE_DMA_API_DEBUG
82 select HAVE_DMA_CONTIGUOUS
83 select HAVE_DYNAMIC_FTRACE
84 select HAVE_EFFICIENT_UNALIGNED_ACCESS
85 select HAVE_FTRACE_MCOUNT_RECORD
86 select HAVE_FUNCTION_TRACER
87 select HAVE_FUNCTION_GRAPH_TRACER
88 select HAVE_GCC_PLUGINS
89 select HAVE_GENERIC_DMA_COHERENT
90 select HAVE_HW_BREAKPOINT if PERF_EVENTS
91 select HAVE_IRQ_TIME_ACCOUNTING
93 select HAVE_MEMBLOCK_NODE_MAP if NUMA
94 select HAVE_NMI if ACPI_APEI_SEA
95 select HAVE_PATA_PLATFORM
96 select HAVE_PERF_EVENTS
98 select HAVE_PERF_USER_STACK_DUMP
99 select HAVE_REGS_AND_STACK_ACCESS_API
100 select HAVE_RCU_TABLE_FREE
101 select HAVE_SYSCALL_TRACEPOINTS
103 select HAVE_KRETPROBES if HAVE_KPROBES
104 select IOMMU_DMA if IOMMU_SUPPORT
106 select IRQ_FORCED_THREADING
107 select MODULES_USE_ELF_RELA
110 select OF_EARLY_FLATTREE
111 select OF_RESERVED_MEM
112 select PCI_ECAM if ACPI
116 select SYSCTL_EXCEPTION_TRACE
117 select THREAD_INFO_IN_TASK
119 ARM 64-bit (AArch64) Linux support.
124 config ARCH_PHYS_ADDR_T_64BIT
133 config ARM64_PAGE_SHIFT
135 default 16 if ARM64_64K_PAGES
136 default 14 if ARM64_16K_PAGES
139 config ARM64_CONT_SHIFT
141 default 5 if ARM64_64K_PAGES
142 default 7 if ARM64_16K_PAGES
145 config ARCH_MMAP_RND_BITS_MIN
146 default 14 if ARM64_64K_PAGES
147 default 16 if ARM64_16K_PAGES
150 # max bits determined by the following formula:
151 # VA_BITS - PAGE_SHIFT - 3
152 config ARCH_MMAP_RND_BITS_MAX
153 default 19 if ARM64_VA_BITS=36
154 default 24 if ARM64_VA_BITS=39
155 default 27 if ARM64_VA_BITS=42
156 default 30 if ARM64_VA_BITS=47
157 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
158 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
159 default 33 if ARM64_VA_BITS=48
160 default 14 if ARM64_64K_PAGES
161 default 16 if ARM64_16K_PAGES
164 config ARCH_MMAP_RND_COMPAT_BITS_MIN
165 default 7 if ARM64_64K_PAGES
166 default 9 if ARM64_16K_PAGES
169 config ARCH_MMAP_RND_COMPAT_BITS_MAX
175 config STACKTRACE_SUPPORT
178 config ILLEGAL_POINTER_VALUE
180 default 0xdead000000000000
182 config LOCKDEP_SUPPORT
185 config TRACE_IRQFLAGS_SUPPORT
188 config RWSEM_XCHGADD_ALGORITHM
195 config GENERIC_BUG_RELATIVE_POINTERS
197 depends on GENERIC_BUG
199 config GENERIC_HWEIGHT
205 config GENERIC_CALIBRATE_DELAY
211 config HAVE_GENERIC_RCU_GUP
214 config ARCH_DMA_ADDR_T_64BIT
217 config NEED_DMA_MAP_STATE
220 config NEED_SG_DMA_LENGTH
232 config KERNEL_MODE_NEON
235 config FIX_EARLYCON_MEM
238 config PGTABLE_LEVELS
240 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
241 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
242 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
243 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
244 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
245 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
247 config ARCH_SUPPORTS_UPROBES
250 config ARCH_PROC_KCORE_TEXT
253 source "init/Kconfig"
255 source "kernel/Kconfig.freezer"
257 source "arch/arm64/Kconfig.platforms"
264 This feature enables support for PCI bus system. If you say Y
265 here, the kernel will include drivers and infrastructure code
266 to support PCI bus devices.
271 config PCI_DOMAINS_GENERIC
277 source "drivers/pci/Kconfig"
281 menu "Kernel Features"
283 menu "ARM errata workarounds via the alternatives framework"
285 config ARM64_ERRATUM_826319
286 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
289 This option adds an alternative code sequence to work around ARM
290 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
291 AXI master interface and an L2 cache.
293 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
294 and is unable to accept a certain write via this interface, it will
295 not progress on read data presented on the read data channel and the
298 The workaround promotes data cache clean instructions to
299 data cache clean-and-invalidate.
300 Please note that this does not necessarily enable the workaround,
301 as it depends on the alternative framework, which will only patch
302 the kernel if an affected CPU is detected.
306 config ARM64_ERRATUM_827319
307 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
310 This option adds an alternative code sequence to work around ARM
311 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
312 master interface and an L2 cache.
314 Under certain conditions this erratum can cause a clean line eviction
315 to occur at the same time as another transaction to the same address
316 on the AMBA 5 CHI interface, which can cause data corruption if the
317 interconnect reorders the two transactions.
319 The workaround promotes data cache clean instructions to
320 data cache clean-and-invalidate.
321 Please note that this does not necessarily enable the workaround,
322 as it depends on the alternative framework, which will only patch
323 the kernel if an affected CPU is detected.
327 config ARM64_ERRATUM_824069
328 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
331 This option adds an alternative code sequence to work around ARM
332 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
333 to a coherent interconnect.
335 If a Cortex-A53 processor is executing a store or prefetch for
336 write instruction at the same time as a processor in another
337 cluster is executing a cache maintenance operation to the same
338 address, then this erratum might cause a clean cache line to be
339 incorrectly marked as dirty.
341 The workaround promotes data cache clean instructions to
342 data cache clean-and-invalidate.
343 Please note that this option does not necessarily enable the
344 workaround, as it depends on the alternative framework, which will
345 only patch the kernel if an affected CPU is detected.
349 config ARM64_ERRATUM_819472
350 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
353 This option adds an alternative code sequence to work around ARM
354 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
355 present when it is connected to a coherent interconnect.
357 If the processor is executing a load and store exclusive sequence at
358 the same time as a processor in another cluster is executing a cache
359 maintenance operation to the same address, then this erratum might
360 cause data corruption.
362 The workaround promotes data cache clean instructions to
363 data cache clean-and-invalidate.
364 Please note that this does not necessarily enable the workaround,
365 as it depends on the alternative framework, which will only patch
366 the kernel if an affected CPU is detected.
370 config ARM64_ERRATUM_832075
371 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
374 This option adds an alternative code sequence to work around ARM
375 erratum 832075 on Cortex-A57 parts up to r1p2.
377 Affected Cortex-A57 parts might deadlock when exclusive load/store
378 instructions to Write-Back memory are mixed with Device loads.
380 The workaround is to promote device loads to use Load-Acquire
382 Please note that this does not necessarily enable the workaround,
383 as it depends on the alternative framework, which will only patch
384 the kernel if an affected CPU is detected.
388 config ARM64_ERRATUM_834220
389 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
393 This option adds an alternative code sequence to work around ARM
394 erratum 834220 on Cortex-A57 parts up to r1p2.
396 Affected Cortex-A57 parts might report a Stage 2 translation
397 fault as the result of a Stage 1 fault for load crossing a
398 page boundary when there is a permission or device memory
399 alignment fault at Stage 1 and a translation fault at Stage 2.
401 The workaround is to verify that the Stage 1 translation
402 doesn't generate a fault before handling the Stage 2 fault.
403 Please note that this does not necessarily enable the workaround,
404 as it depends on the alternative framework, which will only patch
405 the kernel if an affected CPU is detected.
409 config ARM64_ERRATUM_845719
410 bool "Cortex-A53: 845719: a load might read incorrect data"
414 This option adds an alternative code sequence to work around ARM
415 erratum 845719 on Cortex-A53 parts up to r0p4.
417 When running a compat (AArch32) userspace on an affected Cortex-A53
418 part, a load at EL0 from a virtual address that matches the bottom 32
419 bits of the virtual address used by a recent load at (AArch64) EL1
420 might return incorrect data.
422 The workaround is to write the contextidr_el1 register on exception
423 return to a 32-bit task.
424 Please note that this does not necessarily enable the workaround,
425 as it depends on the alternative framework, which will only patch
426 the kernel if an affected CPU is detected.
430 config ARM64_ERRATUM_843419
431 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
433 select ARM64_MODULE_CMODEL_LARGE if MODULES
435 This option links the kernel with '--fix-cortex-a53-843419' and
436 builds modules using the large memory model in order to avoid the use
437 of the ADRP instruction, which can cause a subsequent memory access
438 to use an incorrect address on Cortex-A53 parts up to r0p4.
442 config CAVIUM_ERRATUM_22375
443 bool "Cavium erratum 22375, 24313"
446 Enable workaround for erratum 22375, 24313.
448 This implements two gicv3-its errata workarounds for ThunderX. Both
449 with small impact affecting only ITS table allocation.
451 erratum 22375: only alloc 8MB table size
452 erratum 24313: ignore memory access type
454 The fixes are in ITS initialization and basically ignore memory access
455 type and table size provided by the TYPER and BASER registers.
459 config CAVIUM_ERRATUM_23144
460 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
464 ITS SYNC command hang for cross node io and collections/cpu mapping.
468 config CAVIUM_ERRATUM_23154
469 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
472 The gicv3 of ThunderX requires a modified version for
473 reading the IAR status to ensure data synchronization
474 (access to icc_iar1_el1 is not sync'ed before and after).
478 config CAVIUM_ERRATUM_27456
479 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
482 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
483 instructions may cause the icache to become corrupted if it
484 contains data for a non-current ASID. The fix is to
485 invalidate the icache when changing the mm context.
489 config CAVIUM_ERRATUM_30115
490 bool "Cavium erratum 30115: Guest may disable interrupts in host"
493 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
494 1.2, and T83 Pass 1.0, KVM guest execution may disable
495 interrupts in host. Trapping both GICv3 group-0 and group-1
496 accesses sidesteps the issue.
500 config QCOM_FALKOR_ERRATUM_1003
501 bool "Falkor E1003: Incorrect translation due to ASID change"
503 select ARM64_PAN if ARM64_SW_TTBR0_PAN
505 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
506 and BADDR are changed together in TTBRx_EL1. The workaround for this
507 issue is to use a reserved ASID in cpu_do_switch_mm() before
508 switching to the new ASID. Saying Y here selects ARM64_PAN if
509 ARM64_SW_TTBR0_PAN is selected. This is done because implementing and
510 maintaining the E1003 workaround in the software PAN emulation code
511 would be an unnecessary complication. The affected Falkor v1 CPU
512 implements ARMv8.1 hardware PAN support and using hardware PAN
513 support versus software PAN emulation is mutually exclusive at
518 config QCOM_FALKOR_ERRATUM_1009
519 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
522 On Falkor v1, the CPU may prematurely complete a DSB following a
523 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
524 one more time to fix the issue.
528 config QCOM_QDF2400_ERRATUM_0065
529 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
532 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
533 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
534 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
543 default ARM64_4K_PAGES
545 Page size (translation granule) configuration.
547 config ARM64_4K_PAGES
550 This feature enables 4KB pages support.
552 config ARM64_16K_PAGES
555 The system will use 16KB pages support. AArch32 emulation
556 requires applications compiled with 16K (or a multiple of 16K)
559 config ARM64_64K_PAGES
562 This feature enables 64KB pages support (4KB by default)
563 allowing only two levels of page tables and faster TLB
564 look-up. AArch32 emulation requires applications compiled
565 with 64K aligned segments.
570 prompt "Virtual address space size"
571 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
572 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
573 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
575 Allows choosing one of multiple possible virtual address
576 space sizes. The level of translation table is determined by
577 a combination of page size and virtual address space size.
579 config ARM64_VA_BITS_36
580 bool "36-bit" if EXPERT
581 depends on ARM64_16K_PAGES
583 config ARM64_VA_BITS_39
585 depends on ARM64_4K_PAGES
587 config ARM64_VA_BITS_42
589 depends on ARM64_64K_PAGES
591 config ARM64_VA_BITS_47
593 depends on ARM64_16K_PAGES
595 config ARM64_VA_BITS_48
602 default 36 if ARM64_VA_BITS_36
603 default 39 if ARM64_VA_BITS_39
604 default 42 if ARM64_VA_BITS_42
605 default 47 if ARM64_VA_BITS_47
606 default 48 if ARM64_VA_BITS_48
608 config CPU_BIG_ENDIAN
609 bool "Build big-endian kernel"
611 Say Y if you plan on running a kernel in big-endian mode.
614 bool "Multi-core scheduler support"
616 Multi-core scheduler support improves the CPU scheduler's decision
617 making when dealing with multi-core CPU chips at a cost of slightly
618 increased overhead in some places. If unsure say N here.
621 bool "SMT scheduler support"
623 Improves the CPU scheduler's decision making when dealing with
624 MultiThreading at a cost of slightly increased overhead in some
625 places. If unsure say N here.
628 int "Maximum number of CPUs (2-4096)"
630 # These have to remain sorted largest to smallest
634 bool "Support for hot-pluggable CPUs"
635 select GENERIC_IRQ_MIGRATION
637 Say Y here to experiment with turning CPUs off and on. CPUs
638 can be controlled through /sys/devices/system/cpu.
640 # Common NUMA Features
642 bool "Numa Memory Allocation and Scheduler Support"
643 select ACPI_NUMA if ACPI
646 Enable NUMA (Non Uniform Memory Access) support.
648 The kernel will try to allocate memory used by a CPU on the
649 local memory of the CPU and add some more
650 NUMA awareness to the kernel.
653 int "Maximum NUMA Nodes (as a power of 2)"
656 depends on NEED_MULTIPLE_NODES
658 Specify the maximum number of NUMA Nodes available on the target
659 system. Increases memory reserved to accommodate various tables.
661 config USE_PERCPU_NUMA_NODE_ID
665 config HAVE_SETUP_PER_CPU_AREA
669 config NEED_PER_CPU_EMBED_FIRST_CHUNK
673 source kernel/Kconfig.preempt
674 source kernel/Kconfig.hz
676 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
679 config ARCH_HAS_HOLES_MEMORYMODEL
680 def_bool y if SPARSEMEM
682 config ARCH_SPARSEMEM_ENABLE
684 select SPARSEMEM_VMEMMAP_ENABLE
686 config ARCH_SPARSEMEM_DEFAULT
687 def_bool ARCH_SPARSEMEM_ENABLE
689 config ARCH_SELECT_MEMORY_MODEL
690 def_bool ARCH_SPARSEMEM_ENABLE
692 config HAVE_ARCH_PFN_VALID
693 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
695 config HW_PERF_EVENTS
699 config SYS_SUPPORTS_HUGETLBFS
702 config ARCH_WANT_HUGE_PMD_SHARE
703 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
705 config ARCH_HAS_CACHE_LINE_SIZE
711 bool "Enable seccomp to safely compute untrusted bytecode"
713 This kernel feature is useful for number crunching applications
714 that may need to compute untrusted bytecode during their
715 execution. By using pipes or other transports made available to
716 the process as file descriptors supporting the read/write
717 syscalls, it's possible to isolate those applications in
718 their own address space using seccomp. Once seccomp is
719 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
720 and the task is only allowed to execute a few safe syscalls
721 defined by each seccomp mode.
724 bool "Enable paravirtualization code"
726 This changes the kernel so it can modify itself when it is run
727 under a hypervisor, potentially improving performance significantly
728 over full virtualization.
730 config PARAVIRT_TIME_ACCOUNTING
731 bool "Paravirtual steal time accounting"
735 Select this option to enable fine granularity task steal time
736 accounting. Time spent executing other tasks in parallel with
737 the current vCPU is discounted from the vCPU power. To account for
738 that, there can be a small performance impact.
740 If in doubt, say N here.
743 depends on PM_SLEEP_SMP
745 bool "kexec system call"
747 kexec is a system call that implements the ability to shutdown your
748 current kernel, and to start another kernel. It is like a reboot
749 but it is independent of the system firmware. And like a reboot
750 you can start any kernel with it, not just Linux.
753 bool "Build kdump crash kernel"
755 Generate crash dump after being started by kexec. This should
756 be normally only set in special crash dump kernels which are
757 loaded in the main kernel with kexec-tools into a specially
758 reserved region and then later executed after a crash by
761 For more details see Documentation/kdump/kdump.txt
768 bool "Xen guest support on ARM64"
769 depends on ARM64 && OF
773 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
775 config FORCE_MAX_ZONEORDER
777 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
778 default "13" if (ARCH_THUNDER && ARM64_4K_PAGES)
779 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
782 The kernel memory allocator divides physically contiguous memory
783 blocks into "zones", where each zone is a power of two number of
784 pages. This option selects the largest power of two that the kernel
785 keeps in the memory allocator. If you need to allocate very large
786 blocks of physically contiguous memory, then you may need to
789 This config option is actually maximum order plus one. For example,
790 a value of 11 means that the largest free memory block is 2^10 pages.
792 We make sure that we can allocate upto a HugePage size for each configuration.
794 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
796 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
797 4M allocations matching the default size used by generic code.
799 menuconfig ARMV8_DEPRECATED
800 bool "Emulate deprecated/obsolete ARMv8 instructions"
803 Legacy software support may require certain instructions
804 that have been deprecated or obsoleted in the architecture.
806 Enable this config to enable selective emulation of these
814 bool "Emulate SWP/SWPB instructions"
816 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
817 they are always undefined. Say Y here to enable software
818 emulation of these instructions for userspace using LDXR/STXR.
820 In some older versions of glibc [<=2.8] SWP is used during futex
821 trylock() operations with the assumption that the code will not
822 be preempted. This invalid assumption may be more likely to fail
823 with SWP emulation enabled, leading to deadlock of the user
826 NOTE: when accessing uncached shared regions, LDXR/STXR rely
827 on an external transaction monitoring block called a global
828 monitor to maintain update atomicity. If your system does not
829 implement a global monitor, this option can cause programs that
830 perform SWP operations to uncached memory to deadlock.
834 config CP15_BARRIER_EMULATION
835 bool "Emulate CP15 Barrier instructions"
837 The CP15 barrier instructions - CP15ISB, CP15DSB, and
838 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
839 strongly recommended to use the ISB, DSB, and DMB
840 instructions instead.
842 Say Y here to enable software emulation of these
843 instructions for AArch32 userspace code. When this option is
844 enabled, CP15 barrier usage is traced which can help
845 identify software that needs updating.
849 config SETEND_EMULATION
850 bool "Emulate SETEND instruction"
852 The SETEND instruction alters the data-endianness of the
853 AArch32 EL0, and is deprecated in ARMv8.
855 Say Y here to enable software emulation of the instruction
856 for AArch32 userspace code.
858 Note: All the cpus on the system must have mixed endian support at EL0
859 for this feature to be enabled. If a new CPU - which doesn't support mixed
860 endian - is hotplugged in after this feature has been enabled, there could
861 be unexpected results in the applications.
866 config ARM64_SW_TTBR0_PAN
867 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
869 Enabling this option prevents the kernel from accessing
870 user-space memory directly by pointing TTBR0_EL1 to a reserved
871 zeroed area and reserved ASID. The user access routines
872 restore the valid TTBR0_EL1 temporarily.
874 menu "ARMv8.1 architectural features"
876 config ARM64_HW_AFDBM
877 bool "Support for hardware updates of the Access and Dirty page flags"
880 The ARMv8.1 architecture extensions introduce support for
881 hardware updates of the access and dirty information in page
882 table entries. When enabled in TCR_EL1 (HA and HD bits) on
883 capable processors, accesses to pages with PTE_AF cleared will
884 set this bit instead of raising an access flag fault.
885 Similarly, writes to read-only pages with the DBM bit set will
886 clear the read-only bit (AP[2]) instead of raising a
889 Kernels built with this configuration option enabled continue
890 to work on pre-ARMv8.1 hardware and the performance impact is
891 minimal. If unsure, say Y.
894 bool "Enable support for Privileged Access Never (PAN)"
897 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
898 prevents the kernel or hypervisor from accessing user-space (EL0)
901 Choosing this option will cause any unprotected (not using
902 copy_to_user et al) memory access to fail with a permission fault.
904 The feature is detected at runtime, and will remain as a 'nop'
905 instruction if the cpu does not implement the feature.
907 config ARM64_LSE_ATOMICS
908 bool "Atomic instructions"
910 As part of the Large System Extensions, ARMv8.1 introduces new
911 atomic instructions that are designed specifically to scale in
914 Say Y here to make use of these instructions for the in-kernel
915 atomic routines. This incurs a small overhead on CPUs that do
916 not support these instructions and requires the kernel to be
917 built with binutils >= 2.25.
920 bool "Enable support for Virtualization Host Extensions (VHE)"
923 Virtualization Host Extensions (VHE) allow the kernel to run
924 directly at EL2 (instead of EL1) on processors that support
925 it. This leads to better performance for KVM, as they reduce
926 the cost of the world switch.
928 Selecting this option allows the VHE feature to be detected
929 at runtime, and does not affect processors that do not
930 implement this feature.
934 menu "ARMv8.2 architectural features"
937 bool "Enable support for User Access Override (UAO)"
940 User Access Override (UAO; part of the ARMv8.2 Extensions)
941 causes the 'unprivileged' variant of the load/store instructions to
942 be overriden to be privileged.
944 This option changes get_user() and friends to use the 'unprivileged'
945 variant of the load/store instructions. This ensures that user-space
946 really did have access to the supplied memory. When addr_limit is
947 set to kernel memory the UAO bit will be set, allowing privileged
948 access to kernel memory.
950 Choosing this option will cause copy_to_user() et al to use user-space
953 The feature is detected at runtime, the kernel will use the
954 regular load/store instructions if the cpu does not implement the
959 config ARM64_MODULE_CMODEL_LARGE
962 config ARM64_MODULE_PLTS
964 select ARM64_MODULE_CMODEL_LARGE
965 select HAVE_MOD_ARCH_SPECIFIC
970 This builds the kernel as a Position Independent Executable (PIE),
971 which retains all relocation metadata required to relocate the
972 kernel binary at runtime to a different virtual address than the
973 address it was linked at.
974 Since AArch64 uses the RELA relocation format, this requires a
975 relocation pass at runtime even if the kernel is loaded at the
976 same address it was linked at.
978 config RANDOMIZE_BASE
979 bool "Randomize the address of the kernel image"
980 select ARM64_MODULE_PLTS if MODULES
983 Randomizes the virtual address at which the kernel image is
984 loaded, as a security feature that deters exploit attempts
985 relying on knowledge of the location of kernel internals.
987 It is the bootloader's job to provide entropy, by passing a
988 random u64 value in /chosen/kaslr-seed at kernel entry.
990 When booting via the UEFI stub, it will invoke the firmware's
991 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
992 to the kernel proper. In addition, it will randomise the physical
993 location of the kernel Image as well.
997 config RANDOMIZE_MODULE_REGION_FULL
998 bool "Randomize the module region independently from the core kernel"
999 depends on RANDOMIZE_BASE && !DYNAMIC_FTRACE
1002 Randomizes the location of the module region without considering the
1003 location of the core kernel. This way, it is impossible for modules
1004 to leak information about the location of core kernel data structures
1005 but it does imply that function calls between modules and the core
1006 kernel will need to be resolved via veneers in the module PLT.
1008 When this option is not set, the module region will be randomized over
1009 a limited range that contains the [_stext, _etext] interval of the
1010 core kernel, so branch relocations are always in range.
1016 config ARM64_ACPI_PARKING_PROTOCOL
1017 bool "Enable support for the ARM64 ACPI parking protocol"
1020 Enable support for the ARM64 ACPI parking protocol. If disabled
1021 the kernel will not allow booting through the ARM64 ACPI parking
1022 protocol even if the corresponding data is present in the ACPI
1026 string "Default kernel command string"
1029 Provide a set of default command-line options at build time by
1030 entering them here. As a minimum, you should specify the the
1031 root device (e.g. root=/dev/nfs).
1033 config CMDLINE_FORCE
1034 bool "Always use the default kernel command string"
1036 Always use the default kernel command string, even if the boot
1037 loader passes other arguments to the kernel.
1038 This is useful if you cannot or don't want to change the
1039 command-line options your boot loader passes to the kernel.
1045 bool "UEFI runtime support"
1046 depends on OF && !CPU_BIG_ENDIAN
1049 select EFI_PARAMS_FROM_FDT
1050 select EFI_RUNTIME_WRAPPERS
1055 This option provides support for runtime services provided
1056 by UEFI firmware (such as non-volatile variables, realtime
1057 clock, and platform reset). A UEFI stub is also provided to
1058 allow the kernel to be booted as an EFI application. This
1059 is only useful on systems that have UEFI firmware.
1062 bool "Enable support for SMBIOS (DMI) tables"
1066 This enables SMBIOS/DMI feature for systems.
1068 This option is only useful on systems that have UEFI firmware.
1069 However, even with this option, the resultant kernel should
1070 continue to boot on existing non-UEFI platforms.
1074 menu "Userspace binary formats"
1076 source "fs/Kconfig.binfmt"
1079 bool "Kernel support for 32-bit EL0"
1080 depends on ARM64_4K_PAGES || EXPERT
1081 select COMPAT_BINFMT_ELF
1083 select OLD_SIGSUSPEND3
1084 select COMPAT_OLD_SIGACTION
1086 This option enables support for a 32-bit EL0 running under a 64-bit
1087 kernel at EL1. AArch32-specific components such as system calls,
1088 the user helper functions, VFP support and the ptrace interface are
1089 handled appropriately by the kernel.
1091 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1092 that you will only be able to execute AArch32 binaries that were compiled
1093 with page size aligned segments.
1095 If you want to execute 32-bit userspace applications, say Y.
1097 config SYSVIPC_COMPAT
1099 depends on COMPAT && SYSVIPC
1103 menu "Power management options"
1105 source "kernel/power/Kconfig"
1107 config ARCH_HIBERNATION_POSSIBLE
1111 config ARCH_HIBERNATION_HEADER
1113 depends on HIBERNATION
1115 config ARCH_SUSPEND_POSSIBLE
1120 menu "CPU Power Management"
1122 source "drivers/cpuidle/Kconfig"
1124 source "drivers/cpufreq/Kconfig"
1128 source "net/Kconfig"
1130 source "drivers/Kconfig"
1132 source "ubuntu/Kconfig"
1134 source "drivers/firmware/Kconfig"
1136 source "drivers/acpi/Kconfig"
1140 source "arch/arm64/kvm/Kconfig"
1142 source "arch/arm64/Kconfig.debug"
1144 source "security/Kconfig"
1146 source "crypto/Kconfig"
1148 source "arch/arm64/crypto/Kconfig"
1151 source "lib/Kconfig"