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Commit | Line | Data |
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4ce7ff6e AJ |
1 | /* |
2 | * QEMU MIPS Jazz support | |
3 | * | |
4 | * Copyright (c) 2007-2008 Hervé Poussineau | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
83c9f4ca | 25 | #include "hw/hw.h" |
0d09e41a PB |
26 | #include "hw/mips/mips.h" |
27 | #include "hw/mips/cpudevs.h" | |
28 | #include "hw/i386/pc.h" | |
29 | #include "hw/char/serial.h" | |
30 | #include "hw/isa/isa.h" | |
31 | #include "hw/block/fdc.h" | |
9c17d615 PB |
32 | #include "sysemu/sysemu.h" |
33 | #include "sysemu/arch_init.h" | |
83c9f4ca | 34 | #include "hw/boards.h" |
1422e32d | 35 | #include "net/net.h" |
0d09e41a PB |
36 | #include "hw/scsi/esp.h" |
37 | #include "hw/mips/bios.h" | |
83c9f4ca | 38 | #include "hw/loader.h" |
0d09e41a PB |
39 | #include "hw/timer/mc146818rtc.h" |
40 | #include "hw/timer/i8254.h" | |
41 | #include "hw/audio/pcspk.h" | |
9c17d615 | 42 | #include "sysemu/blockdev.h" |
83c9f4ca | 43 | #include "hw/sysbus.h" |
022c62cb | 44 | #include "exec/address-spaces.h" |
38c8894f | 45 | #include "sysemu/qtest.h" |
2e985fe0 | 46 | #include "qemu/error-report.h" |
4ce7ff6e | 47 | |
4ce7ff6e AJ |
48 | enum jazz_model_e |
49 | { | |
50 | JAZZ_MAGNUM, | |
c171148c | 51 | JAZZ_PICA61, |
4ce7ff6e AJ |
52 | }; |
53 | ||
54 | static void main_cpu_reset(void *opaque) | |
55 | { | |
f37f435a AF |
56 | MIPSCPU *cpu = opaque; |
57 | ||
58 | cpu_reset(CPU(cpu)); | |
4ce7ff6e AJ |
59 | } |
60 | ||
a8170e5e | 61 | static uint64_t rtc_read(void *opaque, hwaddr addr, unsigned size) |
4ce7ff6e | 62 | { |
afcea8cb | 63 | return cpu_inw(0x71); |
4ce7ff6e AJ |
64 | } |
65 | ||
a8170e5e | 66 | static void rtc_write(void *opaque, hwaddr addr, |
60581b37 | 67 | uint64_t val, unsigned size) |
4ce7ff6e | 68 | { |
afcea8cb | 69 | cpu_outw(0x71, val & 0xff); |
4ce7ff6e AJ |
70 | } |
71 | ||
60581b37 AK |
72 | static const MemoryRegionOps rtc_ops = { |
73 | .read = rtc_read, | |
74 | .write = rtc_write, | |
75 | .endianness = DEVICE_NATIVE_ENDIAN, | |
4ce7ff6e AJ |
76 | }; |
77 | ||
a8170e5e | 78 | static uint64_t dma_dummy_read(void *opaque, hwaddr addr, |
60581b37 | 79 | unsigned size) |
c6945b15 AJ |
80 | { |
81 | /* Nothing to do. That is only to ensure that | |
82 | * the current DMA acknowledge cycle is completed. */ | |
60581b37 | 83 | return 0xff; |
c6945b15 AJ |
84 | } |
85 | ||
a8170e5e | 86 | static void dma_dummy_write(void *opaque, hwaddr addr, |
60581b37 AK |
87 | uint64_t val, unsigned size) |
88 | { | |
89 | /* Nothing to do. That is only to ensure that | |
90 | * the current DMA acknowledge cycle is completed. */ | |
91 | } | |
c6945b15 | 92 | |
60581b37 AK |
93 | static const MemoryRegionOps dma_dummy_ops = { |
94 | .read = dma_dummy_read, | |
95 | .write = dma_dummy_write, | |
96 | .endianness = DEVICE_NATIVE_ENDIAN, | |
c6945b15 AJ |
97 | }; |
98 | ||
4ce7ff6e AJ |
99 | #define MAGNUM_BIOS_SIZE_MAX 0x7e000 |
100 | #define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX) | |
101 | ||
4556bd8b BS |
102 | static void cpu_request_exit(void *opaque, int irq, int level) |
103 | { | |
4917cf44 | 104 | CPUState *cpu = current_cpu; |
4556bd8b | 105 | |
4917cf44 AF |
106 | if (cpu && level) { |
107 | cpu_exit(cpu); | |
4556bd8b BS |
108 | } |
109 | } | |
110 | ||
b6a06e72 HP |
111 | static CPUUnassignedAccess real_do_unassigned_access; |
112 | static void mips_jazz_do_unassigned_access(CPUState *cpu, hwaddr addr, | |
113 | bool is_write, bool is_exec, | |
114 | int opaque, unsigned size) | |
115 | { | |
116 | if (!is_exec) { | |
117 | /* ignore invalid access (ie do not raise exception) */ | |
118 | return; | |
119 | } | |
120 | (*real_do_unassigned_access)(cpu, addr, is_write, is_exec, opaque, size); | |
121 | } | |
122 | ||
c2d0d012 RH |
123 | static void mips_jazz_init(MemoryRegion *address_space, |
124 | MemoryRegion *address_space_io, | |
125 | ram_addr_t ram_size, | |
126 | const char *cpu_model, | |
127 | enum jazz_model_e jazz_model) | |
4ce7ff6e | 128 | { |
5cea8590 | 129 | char *filename; |
4ce7ff6e | 130 | int bios_size, n; |
6bd8da65 | 131 | MIPSCPU *cpu; |
b6a06e72 | 132 | CPUClass *cc; |
61c56c8c | 133 | CPUMIPSState *env; |
4ce7ff6e | 134 | qemu_irq *rc4030, *i8259; |
c6945b15 | 135 | rc4030_dma *dmas; |
68238a9e | 136 | void* rc4030_opaque; |
f51100cc | 137 | MemoryRegion *isa = g_new(MemoryRegion, 1); |
60581b37 | 138 | MemoryRegion *rtc = g_new(MemoryRegion, 1); |
dbff76ac | 139 | MemoryRegion *i8042 = g_new(MemoryRegion, 1); |
60581b37 | 140 | MemoryRegion *dma_dummy = g_new(MemoryRegion, 1); |
a65f56ee | 141 | NICInfo *nd; |
cd3e2409 HP |
142 | DeviceState *dev; |
143 | SysBusDevice *sysbus; | |
48a18b3c | 144 | ISABus *isa_bus; |
64d7e9a4 | 145 | ISADevice *pit; |
fd8014e1 | 146 | DriveInfo *fds[MAX_FD]; |
73d74342 | 147 | qemu_irq esp_reset, dma_enable; |
4556bd8b | 148 | qemu_irq *cpu_exit_irq; |
60581b37 AK |
149 | MemoryRegion *ram = g_new(MemoryRegion, 1); |
150 | MemoryRegion *bios = g_new(MemoryRegion, 1); | |
151 | MemoryRegion *bios2 = g_new(MemoryRegion, 1); | |
4ce7ff6e AJ |
152 | |
153 | /* init CPUs */ | |
154 | if (cpu_model == NULL) { | |
155 | #ifdef TARGET_MIPS64 | |
156 | cpu_model = "R4000"; | |
157 | #else | |
158 | /* FIXME: All wrong, this maybe should be R3000 for the older JAZZs. */ | |
159 | cpu_model = "24Kf"; | |
160 | #endif | |
161 | } | |
6bd8da65 AF |
162 | cpu = cpu_mips_init(cpu_model); |
163 | if (cpu == NULL) { | |
4ce7ff6e AJ |
164 | fprintf(stderr, "Unable to find CPU definition\n"); |
165 | exit(1); | |
166 | } | |
6bd8da65 | 167 | env = &cpu->env; |
f37f435a | 168 | qemu_register_reset(main_cpu_reset, cpu); |
4ce7ff6e | 169 | |
b6a06e72 HP |
170 | /* Chipset returns 0 in invalid reads and do not raise data exceptions. |
171 | * However, we can't simply add a global memory region to catch | |
172 | * everything, as memory core directly call unassigned_mem_read/write | |
173 | * on some invalid accesses, which call do_unassigned_access on the | |
174 | * CPU, which raise an exception. | |
175 | * Handle that case by hijacking the do_unassigned_access method on | |
176 | * the CPU, and do not raise exceptions for data access. */ | |
177 | cc = CPU_GET_CLASS(cpu); | |
178 | real_do_unassigned_access = cc->do_unassigned_access; | |
179 | cc->do_unassigned_access = mips_jazz_do_unassigned_access; | |
180 | ||
4ce7ff6e | 181 | /* allocate RAM */ |
2c9b15ca | 182 | memory_region_init_ram(ram, NULL, "mips_jazz.ram", ram_size); |
c5705a77 | 183 | vmstate_register_ram_global(ram); |
60581b37 | 184 | memory_region_add_subregion(address_space, 0, ram); |
dcac9679 | 185 | |
2c9b15ca | 186 | memory_region_init_ram(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE); |
c5705a77 | 187 | vmstate_register_ram_global(bios); |
60581b37 | 188 | memory_region_set_readonly(bios, true); |
2c9b15ca | 189 | memory_region_init_alias(bios2, NULL, "mips_jazz.bios", bios, |
60581b37 AK |
190 | 0, MAGNUM_BIOS_SIZE); |
191 | memory_region_add_subregion(address_space, 0x1fc00000LL, bios); | |
192 | memory_region_add_subregion(address_space, 0xfff00000LL, bios2); | |
4ce7ff6e AJ |
193 | |
194 | /* load the BIOS image. */ | |
c6945b15 AJ |
195 | if (bios_name == NULL) |
196 | bios_name = BIOS_FILENAME; | |
5cea8590 PB |
197 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
198 | if (filename) { | |
199 | bios_size = load_image_targphys(filename, 0xfff00000LL, | |
200 | MAGNUM_BIOS_SIZE); | |
7267c094 | 201 | g_free(filename); |
5cea8590 PB |
202 | } else { |
203 | bios_size = -1; | |
204 | } | |
38c8894f | 205 | if ((bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) && !qtest_enabled()) { |
2e985fe0 AJ |
206 | error_report("Could not load MIPS bios '%s'", bios_name); |
207 | exit(1); | |
4ce7ff6e AJ |
208 | } |
209 | ||
4ce7ff6e AJ |
210 | /* Init CPU internal devices */ |
211 | cpu_mips_irq_init_cpu(env); | |
212 | cpu_mips_clock_init(env); | |
213 | ||
214 | /* Chipset */ | |
3054434d AK |
215 | rc4030_opaque = rc4030_init(env->irq[6], env->irq[3], &rc4030, &dmas, |
216 | address_space); | |
2c9b15ca | 217 | memory_region_init_io(dma_dummy, NULL, &dma_dummy_ops, NULL, "dummy_dma", 0x1000); |
60581b37 | 218 | memory_region_add_subregion(address_space, 0x8000d000, dma_dummy); |
4ce7ff6e AJ |
219 | |
220 | /* ISA devices */ | |
48a18b3c HP |
221 | isa_bus = isa_bus_new(NULL, address_space_io); |
222 | i8259 = i8259_init(isa_bus, env->irq[4]); | |
223 | isa_bus_irqs(isa_bus, i8259); | |
4556bd8b BS |
224 | cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); |
225 | DMA_init(0, cpu_exit_irq); | |
319ba9f5 | 226 | pit = pit_init(isa_bus, 0x40, 0, NULL); |
302fe51b | 227 | pcspk_init(isa_bus, pit); |
4ce7ff6e AJ |
228 | |
229 | /* ISA IO space at 0x90000000 */ | |
f51100cc PB |
230 | memory_region_init_alias(isa, NULL, "isa_mmio", |
231 | get_system_io(), 0, 0x01000000); | |
232 | memory_region_add_subregion(address_space, 0x90000000, isa); | |
4ce7ff6e AJ |
233 | isa_mem_base = 0x11000000; |
234 | ||
235 | /* Video card */ | |
236 | switch (jazz_model) { | |
237 | case JAZZ_MAGNUM: | |
97a3f6ff HP |
238 | dev = qdev_create(NULL, "sysbus-g364"); |
239 | qdev_init_nofail(dev); | |
1356b98d | 240 | sysbus = SYS_BUS_DEVICE(dev); |
97a3f6ff HP |
241 | sysbus_mmio_map(sysbus, 0, 0x60080000); |
242 | sysbus_mmio_map(sysbus, 1, 0x40000000); | |
243 | sysbus_connect_irq(sysbus, 0, rc4030[3]); | |
244 | { | |
245 | /* Simple ROM, so user doesn't have to provide one */ | |
60581b37 | 246 | MemoryRegion *rom_mr = g_new(MemoryRegion, 1); |
2c9b15ca | 247 | memory_region_init_ram(rom_mr, NULL, "g364fb.rom", 0x80000); |
c5705a77 | 248 | vmstate_register_ram_global(rom_mr); |
60581b37 AK |
249 | memory_region_set_readonly(rom_mr, true); |
250 | uint8_t *rom = memory_region_get_ram_ptr(rom_mr); | |
251 | memory_region_add_subregion(address_space, 0x60000000, rom_mr); | |
97a3f6ff HP |
252 | rom[0] = 0x10; /* Mips G364 */ |
253 | } | |
4ce7ff6e | 254 | break; |
c171148c | 255 | case JAZZ_PICA61: |
be20f9e9 | 256 | isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory()); |
c171148c | 257 | break; |
4ce7ff6e AJ |
258 | default: |
259 | break; | |
260 | } | |
261 | ||
262 | /* Network controller */ | |
a65f56ee AJ |
263 | for (n = 0; n < nb_nics; n++) { |
264 | nd = &nd_table[n]; | |
265 | if (!nd->model) | |
7267c094 | 266 | nd->model = g_strdup("dp83932"); |
a65f56ee | 267 | if (strcmp(nd->model, "dp83932") == 0) { |
024e5bb6 | 268 | dp83932_init(nd, 0x80001000, 2, get_system_memory(), rc4030[4], |
a65f56ee AJ |
269 | rc4030_opaque, rc4030_dma_memory_rw); |
270 | break; | |
c8057f95 | 271 | } else if (is_help_option(nd->model)) { |
a65f56ee AJ |
272 | fprintf(stderr, "qemu: Supported NICs: dp83932\n"); |
273 | exit(1); | |
274 | } else { | |
275 | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model); | |
276 | exit(1); | |
277 | } | |
278 | } | |
4ce7ff6e AJ |
279 | |
280 | /* SCSI adapter */ | |
cfb9de9c PB |
281 | esp_init(0x80002000, 0, |
282 | rc4030_dma_read, rc4030_dma_write, dmas[0], | |
73d74342 | 283 | rc4030[5], &esp_reset, &dma_enable); |
4ce7ff6e AJ |
284 | |
285 | /* Floppy */ | |
286 | if (drive_get_max_bus(IF_FLOPPY) >= MAX_FD) { | |
287 | fprintf(stderr, "qemu: too many floppy drives\n"); | |
288 | exit(1); | |
289 | } | |
290 | for (n = 0; n < MAX_FD; n++) { | |
fd8014e1 | 291 | fds[n] = drive_get(IF_FLOPPY, 0, n); |
4ce7ff6e | 292 | } |
2091ba23 | 293 | fdctrl_init_sysbus(rc4030[1], 0, 0x80003000, fds); |
4ce7ff6e AJ |
294 | |
295 | /* Real time clock */ | |
48a18b3c | 296 | rtc_init(isa_bus, 1980, NULL); |
2c9b15ca | 297 | memory_region_init_io(rtc, NULL, &rtc_ops, NULL, "rtc", 0x1000); |
60581b37 | 298 | memory_region_add_subregion(address_space, 0x80004000, rtc); |
4ce7ff6e AJ |
299 | |
300 | /* Keyboard (i8042) */ | |
dbff76ac RH |
301 | i8042_mm_init(rc4030[6], rc4030[7], i8042, 0x1000, 0x1); |
302 | memory_region_add_subregion(address_space, 0x80005000, i8042); | |
4ce7ff6e AJ |
303 | |
304 | /* Serial ports */ | |
2d48377a | 305 | if (serial_hds[0]) { |
39186d8a RH |
306 | serial_mm_init(address_space, 0x80006000, 0, rc4030[8], 8000000/16, |
307 | serial_hds[0], DEVICE_NATIVE_ENDIAN); | |
2d48377a BS |
308 | } |
309 | if (serial_hds[1]) { | |
39186d8a RH |
310 | serial_mm_init(address_space, 0x80007000, 0, rc4030[9], 8000000/16, |
311 | serial_hds[1], DEVICE_NATIVE_ENDIAN); | |
2d48377a | 312 | } |
4ce7ff6e AJ |
313 | |
314 | /* Parallel port */ | |
315 | if (parallel_hds[0]) | |
63858cd9 AK |
316 | parallel_mm_init(address_space, 0x80008000, 0, rc4030[0], |
317 | parallel_hds[0]); | |
4ce7ff6e | 318 | |
4ce7ff6e | 319 | /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */ |
4ce7ff6e | 320 | |
cd3e2409 HP |
321 | /* NVRAM */ |
322 | dev = qdev_create(NULL, "ds1225y"); | |
323 | qdev_init_nofail(dev); | |
1356b98d | 324 | sysbus = SYS_BUS_DEVICE(dev); |
cd3e2409 | 325 | sysbus_mmio_map(sysbus, 0, 0x80009000); |
4ce7ff6e AJ |
326 | |
327 | /* LED indicator */ | |
b39506e4 | 328 | sysbus_create_simple("jazz-led", 0x8000f000, NULL); |
4ce7ff6e AJ |
329 | } |
330 | ||
331 | static | |
5f072e1f | 332 | void mips_magnum_init(QEMUMachineInitArgs *args) |
4ce7ff6e | 333 | { |
5f072e1f EH |
334 | ram_addr_t ram_size = args->ram_size; |
335 | const char *cpu_model = args->cpu_model; | |
c2d0d012 RH |
336 | mips_jazz_init(get_system_memory(), get_system_io(), |
337 | ram_size, cpu_model, JAZZ_MAGNUM); | |
4ce7ff6e AJ |
338 | } |
339 | ||
c171148c | 340 | static |
5f072e1f | 341 | void mips_pica61_init(QEMUMachineInitArgs *args) |
c171148c | 342 | { |
5f072e1f EH |
343 | ram_addr_t ram_size = args->ram_size; |
344 | const char *cpu_model = args->cpu_model; | |
c2d0d012 RH |
345 | mips_jazz_init(get_system_memory(), get_system_io(), |
346 | ram_size, cpu_model, JAZZ_PICA61); | |
c171148c AJ |
347 | } |
348 | ||
f80f9ec9 | 349 | static QEMUMachine mips_magnum_machine = { |
eec2743e TS |
350 | .name = "magnum", |
351 | .desc = "MIPS Magnum", | |
352 | .init = mips_magnum_init, | |
2d0d2837 | 353 | .block_default_type = IF_SCSI, |
4ce7ff6e | 354 | }; |
c171148c | 355 | |
f80f9ec9 | 356 | static QEMUMachine mips_pica61_machine = { |
eec2743e TS |
357 | .name = "pica61", |
358 | .desc = "Acer Pica 61", | |
359 | .init = mips_pica61_init, | |
2d0d2837 | 360 | .block_default_type = IF_SCSI, |
c171148c | 361 | }; |
f80f9ec9 AL |
362 | |
363 | static void mips_jazz_machine_init(void) | |
364 | { | |
365 | qemu_register_machine(&mips_magnum_machine); | |
366 | qemu_register_machine(&mips_pica61_machine); | |
367 | } | |
368 | ||
369 | machine_init(mips_jazz_machine_init); |