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1/*
2 * QEMU CPU model
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
19 */
20#ifndef QEMU_CPU_H
21#define QEMU_CPU_H
22
fcd7d003 23#include <signal.h>
961f8395 24#include "hw/qdev-core.h"
c658b94f 25#include "exec/hwaddr.h"
1de7afc9 26#include "qemu/thread.h"
4917cf44 27#include "qemu/tls.h"
a23bbfda 28#include "qemu/typedefs.h"
dd83b06a 29
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30typedef int (*WriteCoreDumpFunction)(void *buf, size_t size, void *opaque);
31
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32/**
33 * vaddr:
34 * Type wide enough to contain any #target_ulong virtual address.
35 */
36typedef uint64_t vaddr;
37#define VADDR_PRId PRId64
38#define VADDR_PRIu PRIu64
39#define VADDR_PRIo PRIo64
40#define VADDR_PRIx PRIx64
41#define VADDR_PRIX PRIX64
42#define VADDR_MAX UINT64_MAX
43
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44/**
45 * SECTION:cpu
46 * @section_id: QEMU-cpu
47 * @title: CPU Class
48 * @short_description: Base class for all CPUs
49 */
50
51#define TYPE_CPU "cpu"
52
53#define CPU(obj) OBJECT_CHECK(CPUState, (obj), TYPE_CPU)
54#define CPU_CLASS(class) OBJECT_CLASS_CHECK(CPUClass, (class), TYPE_CPU)
55#define CPU_GET_CLASS(obj) OBJECT_GET_CLASS(CPUClass, (obj), TYPE_CPU)
56
57typedef struct CPUState CPUState;
58
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59typedef void (*CPUUnassignedAccess)(CPUState *cpu, hwaddr addr,
60 bool is_write, bool is_exec, int opaque,
61 unsigned size);
62
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63struct TranslationBlock;
64
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65/**
66 * CPUClass:
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67 * @class_by_name: Callback to map -cpu command line model name to an
68 * instantiatable CPU type.
f5df5baf 69 * @reset: Callback to reset the #CPUState to its initial state.
91b1df8c 70 * @reset_dump_flags: #CPUDumpFlags to use for reset logging.
97a8ea5a 71 * @do_interrupt: Callback for interrupt handling.
c658b94f 72 * @do_unassigned_access: Callback for unassigned access handling.
f3659eee 73 * @memory_rw_debug: Callback for GDB memory access.
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74 * @dump_state: Callback for dumping state.
75 * @dump_statistics: Callback for dumping statistics.
997395d3 76 * @get_arch_id: Callback for getting architecture-dependent CPU ID.
444d5590 77 * @get_paging_enabled: Callback for inquiring whether paging is enabled.
a23bbfda 78 * @get_memory_mapping: Callback for obtaining the memory mappings.
f45748f1 79 * @set_pc: Callback for setting the Program Counter register.
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80 * @synchronize_from_tb: Callback for synchronizing state from a TCG
81 * #TranslationBlock.
00b941e5 82 * @get_phys_page_debug: Callback for obtaining a physical address.
b170fce3 83 * @vmsd: State description for migration.
a0e372f0 84 * @gdb_num_core_regs: Number of core registers accessible to GDB.
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85 *
86 * Represents a CPU family or model.
87 */
88typedef struct CPUClass {
89 /*< private >*/
961f8395 90 DeviceClass parent_class;
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91 /*< public >*/
92
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93 ObjectClass *(*class_by_name)(const char *cpu_model);
94
dd83b06a 95 void (*reset)(CPUState *cpu);
91b1df8c 96 int reset_dump_flags;
97a8ea5a 97 void (*do_interrupt)(CPUState *cpu);
c658b94f 98 CPUUnassignedAccess do_unassigned_access;
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99 int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
100 uint8_t *buf, int len, bool is_write);
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101 void (*dump_state)(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
102 int flags);
103 void (*dump_statistics)(CPUState *cpu, FILE *f,
104 fprintf_function cpu_fprintf, int flags);
997395d3 105 int64_t (*get_arch_id)(CPUState *cpu);
444d5590 106 bool (*get_paging_enabled)(const CPUState *cpu);
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107 void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
108 Error **errp);
f45748f1 109 void (*set_pc)(CPUState *cpu, vaddr value);
bdf7ae5b 110 void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb);
00b941e5 111 hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
b170fce3 112
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113 int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
114 int cpuid, void *opaque);
115 int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
116 void *opaque);
117 int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu,
118 int cpuid, void *opaque);
119 int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
120 void *opaque);
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121
122 const struct VMStateDescription *vmsd;
123 int gdb_num_core_regs;
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124} CPUClass;
125
a60f24b5 126struct KVMState;
f7575c96 127struct kvm_run;
a60f24b5 128
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129/**
130 * CPUState:
55e5c285 131 * @cpu_index: CPU index (informative).
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132 * @nr_cores: Number of cores within this CPU package.
133 * @nr_threads: Number of threads within this CPU.
1b1ed8dc 134 * @numa_node: NUMA node this CPU is belonging to.
0d34282f 135 * @host_tid: Host thread ID.
0315c31c 136 * @running: #true if CPU is currently running (usermode).
61a46217 137 * @created: Indicates whether the CPU thread has been successfully created.
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138 * @interrupt_request: Indicates a pending interrupt request.
139 * @halted: Nonzero if the CPU is in suspended state.
4fdeee7c 140 * @stop: Indicates a pending stop request.
f324e766 141 * @stopped: Indicates the CPU has been artificially stopped.
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142 * @tcg_exit_req: Set to force TCG to stop executing linked TBs for this
143 * CPU and return to its top level loop.
ed2803da 144 * @singlestep_enabled: Flags for single-stepping.
c05efcb1 145 * @env_ptr: Pointer to subclass-specific CPUArchState field.
d77953b9 146 * @current_tb: Currently executing TB.
eac8b355 147 * @gdb_regs: Additional GDB registers.
a0e372f0 148 * @gdb_num_regs: Number of total registers accessible to GDB.
182735ef 149 * @next_cpu: Next CPU sharing TB cache.
8737c51c 150 * @kvm_fd: vCPU file descriptor for KVM.
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151 *
152 * State of one CPU core or thread.
153 */
154struct CPUState {
155 /*< private >*/
961f8395 156 DeviceState parent_obj;
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157 /*< public >*/
158
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159 int nr_cores;
160 int nr_threads;
1b1ed8dc 161 int numa_node;
ce3960eb 162
814e612e 163 struct QemuThread *thread;
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164#ifdef _WIN32
165 HANDLE hThread;
166#endif
9f09e18a 167 int thread_id;
0d34282f 168 uint32_t host_tid;
0315c31c 169 bool running;
f5c121b8 170 struct QemuCond *halt_cond;
c64ca814 171 struct qemu_work_item *queued_work_first, *queued_work_last;
216fc9a4 172 bool thread_kicked;
61a46217 173 bool created;
4fdeee7c 174 bool stop;
f324e766 175 bool stopped;
fcd7d003 176 volatile sig_atomic_t exit_request;
378df4b2 177 volatile sig_atomic_t tcg_exit_req;
259186a7 178 uint32_t interrupt_request;
ed2803da 179 int singlestep_enabled;
bcba2a72 180
c05efcb1 181 void *env_ptr; /* CPUArchState */
d77953b9 182 struct TranslationBlock *current_tb;
eac8b355 183 struct GDBRegisterState *gdb_regs;
a0e372f0 184 int gdb_num_regs;
182735ef 185 CPUState *next_cpu;
d77953b9 186
8737c51c 187 int kvm_fd;
20d695a9 188 bool kvm_vcpu_dirty;
a60f24b5 189 struct KVMState *kvm_state;
f7575c96 190 struct kvm_run *kvm_run;
8737c51c 191
f5df5baf 192 /* TODO Move common fields from CPUArchState here. */
55e5c285 193 int cpu_index; /* used by alpha TCG */
259186a7 194 uint32_t halted; /* used by alpha, cris, ppc TCG */
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195};
196
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197extern CPUState *first_cpu;
198
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199DECLARE_TLS(CPUState *, current_cpu);
200#define current_cpu tls_var(current_cpu)
201
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202/**
203 * cpu_paging_enabled:
204 * @cpu: The CPU whose state is to be inspected.
205 *
206 * Returns: %true if paging is enabled, %false otherwise.
207 */
208bool cpu_paging_enabled(const CPUState *cpu);
209
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210/**
211 * cpu_get_memory_mapping:
212 * @cpu: The CPU whose memory mappings are to be obtained.
213 * @list: Where to write the memory mappings to.
214 * @errp: Pointer for reporting an #Error.
215 */
216void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
217 Error **errp);
218
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219/**
220 * cpu_write_elf64_note:
221 * @f: pointer to a function that writes memory to a file
222 * @cpu: The CPU whose memory is to be dumped
223 * @cpuid: ID number of the CPU
224 * @opaque: pointer to the CPUState struct
225 */
226int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
227 int cpuid, void *opaque);
228
229/**
230 * cpu_write_elf64_qemunote:
231 * @f: pointer to a function that writes memory to a file
232 * @cpu: The CPU whose memory is to be dumped
233 * @cpuid: ID number of the CPU
234 * @opaque: pointer to the CPUState struct
235 */
236int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
237 void *opaque);
238
239/**
240 * cpu_write_elf32_note:
241 * @f: pointer to a function that writes memory to a file
242 * @cpu: The CPU whose memory is to be dumped
243 * @cpuid: ID number of the CPU
244 * @opaque: pointer to the CPUState struct
245 */
246int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
247 int cpuid, void *opaque);
248
249/**
250 * cpu_write_elf32_qemunote:
251 * @f: pointer to a function that writes memory to a file
252 * @cpu: The CPU whose memory is to be dumped
253 * @cpuid: ID number of the CPU
254 * @opaque: pointer to the CPUState struct
255 */
256int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
257 void *opaque);
dd83b06a 258
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259/**
260 * CPUDumpFlags:
261 * @CPU_DUMP_CODE:
262 * @CPU_DUMP_FPU: dump FPU register state, not just integer
263 * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state
264 */
265enum CPUDumpFlags {
266 CPU_DUMP_CODE = 0x00010000,
267 CPU_DUMP_FPU = 0x00020000,
268 CPU_DUMP_CCOP = 0x00040000,
269};
270
271/**
272 * cpu_dump_state:
273 * @cpu: The CPU whose state is to be dumped.
274 * @f: File to dump to.
275 * @cpu_fprintf: Function to dump with.
276 * @flags: Flags what to dump.
277 *
278 * Dumps CPU state.
279 */
280void cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
281 int flags);
282
283/**
284 * cpu_dump_statistics:
285 * @cpu: The CPU whose state is to be dumped.
286 * @f: File to dump to.
287 * @cpu_fprintf: Function to dump with.
288 * @flags: Flags what to dump.
289 *
290 * Dumps CPU statistics.
291 */
292void cpu_dump_statistics(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
293 int flags);
294
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295#ifndef CONFIG_USER_ONLY
296/**
297 * cpu_get_phys_page_debug:
298 * @cpu: The CPU to obtain the physical page address for.
299 * @addr: The virtual address.
300 *
301 * Obtains the physical page corresponding to a virtual one.
302 * Use it only for debugging because no protection checks are done.
303 *
304 * Returns: Corresponding physical page address or -1 if no page found.
305 */
306static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
307{
308 CPUClass *cc = CPU_GET_CLASS(cpu);
309
310 return cc->get_phys_page_debug(cpu, addr);
311}
312#endif
313
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314/**
315 * cpu_reset:
316 * @cpu: The CPU whose state is to be reset.
317 */
318void cpu_reset(CPUState *cpu);
319
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320/**
321 * cpu_class_by_name:
322 * @typename: The CPU base type.
323 * @cpu_model: The model string without any parameters.
324 *
325 * Looks up a CPU #ObjectClass matching name @cpu_model.
326 *
327 * Returns: A #CPUClass or %NULL if not matching class is found.
328 */
329ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model);
330
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331/**
332 * qemu_cpu_has_work:
333 * @cpu: The vCPU to check.
334 *
335 * Checks whether the CPU has work to do.
336 *
337 * Returns: %true if the CPU has work, %false otherwise.
338 */
339bool qemu_cpu_has_work(CPUState *cpu);
340
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341/**
342 * qemu_cpu_is_self:
343 * @cpu: The vCPU to check against.
344 *
345 * Checks whether the caller is executing on the vCPU thread.
346 *
347 * Returns: %true if called from @cpu's thread, %false otherwise.
348 */
349bool qemu_cpu_is_self(CPUState *cpu);
350
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351/**
352 * qemu_cpu_kick:
353 * @cpu: The vCPU to kick.
354 *
355 * Kicks @cpu's thread.
356 */
357void qemu_cpu_kick(CPUState *cpu);
358
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359/**
360 * cpu_is_stopped:
361 * @cpu: The CPU to check.
362 *
363 * Checks whether the CPU is stopped.
364 *
365 * Returns: %true if run state is not running or if artificially stopped;
366 * %false otherwise.
367 */
368bool cpu_is_stopped(CPUState *cpu);
369
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370/**
371 * run_on_cpu:
372 * @cpu: The vCPU to run on.
373 * @func: The function to be executed.
374 * @data: Data to pass to the function.
375 *
376 * Schedules the function @func for execution on the vCPU @cpu.
377 */
378void run_on_cpu(CPUState *cpu, void (*func)(void *data), void *data);
379
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380/**
381 * async_run_on_cpu:
382 * @cpu: The vCPU to run on.
383 * @func: The function to be executed.
384 * @data: Data to pass to the function.
385 *
386 * Schedules the function @func for execution on the vCPU @cpu asynchronously.
387 */
388void async_run_on_cpu(CPUState *cpu, void (*func)(void *data), void *data);
389
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390/**
391 * qemu_for_each_cpu:
392 * @func: The function to be executed.
393 * @data: Data to pass to the function.
394 *
395 * Executes @func for each CPU.
396 */
397void qemu_for_each_cpu(void (*func)(CPUState *cpu, void *data), void *data);
398
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399/**
400 * qemu_get_cpu:
401 * @index: The CPUState@cpu_index value of the CPU to obtain.
402 *
403 * Gets a CPU matching @index.
404 *
405 * Returns: The CPU or %NULL if there is no matching CPU.
406 */
407CPUState *qemu_get_cpu(int index);
408
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409/**
410 * cpu_exists:
411 * @id: Guest-exposed CPU ID to lookup.
412 *
413 * Search for CPU with specified ID.
414 *
415 * Returns: %true - CPU is found, %false - CPU isn't found.
416 */
417bool cpu_exists(int64_t id);
418
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419#ifndef CONFIG_USER_ONLY
420
421typedef void (*CPUInterruptHandler)(CPUState *, int);
422
423extern CPUInterruptHandler cpu_interrupt_handler;
424
425/**
426 * cpu_interrupt:
427 * @cpu: The CPU to set an interrupt on.
428 * @mask: The interupts to set.
429 *
430 * Invokes the interrupt handler.
431 */
432static inline void cpu_interrupt(CPUState *cpu, int mask)
433{
434 cpu_interrupt_handler(cpu, mask);
435}
436
437#else /* USER_ONLY */
438
439void cpu_interrupt(CPUState *cpu, int mask);
440
441#endif /* USER_ONLY */
442
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443#ifndef CONFIG_USER_ONLY
444
445static inline void cpu_unassigned_access(CPUState *cpu, hwaddr addr,
446 bool is_write, bool is_exec,
447 int opaque, unsigned size)
448{
449 CPUClass *cc = CPU_GET_CLASS(cpu);
450
451 if (cc->do_unassigned_access) {
452 cc->do_unassigned_access(cpu, addr, is_write, is_exec, opaque, size);
453 }
454}
455
456#endif
457
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458/**
459 * cpu_reset_interrupt:
460 * @cpu: The CPU to clear the interrupt on.
461 * @mask: The interrupt mask to clear.
462 *
463 * Resets interrupts on the vCPU @cpu.
464 */
465void cpu_reset_interrupt(CPUState *cpu, int mask);
466
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467/**
468 * cpu_exit:
469 * @cpu: The CPU to exit.
470 *
471 * Requests the CPU @cpu to exit execution.
472 */
473void cpu_exit(CPUState *cpu);
474
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475/**
476 * cpu_resume:
477 * @cpu: The CPU to resume.
478 *
479 * Resumes CPU, i.e. puts CPU into runnable state.
480 */
481void cpu_resume(CPUState *cpu);
dd83b06a 482
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483/**
484 * qemu_init_vcpu:
485 * @cpu: The vCPU to initialize.
486 *
487 * Initializes a vCPU.
488 */
489void qemu_init_vcpu(CPUState *cpu);
490
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491#define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */
492#define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */
493#define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */
494
495/**
496 * cpu_single_step:
497 * @cpu: CPU to the flags for.
498 * @enabled: Flags to enable.
499 *
500 * Enables or disables single-stepping for @cpu.
501 */
502void cpu_single_step(CPUState *cpu, int enabled);
503
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504#ifdef CONFIG_SOFTMMU
505extern const struct VMStateDescription vmstate_cpu_common;
506#else
507#define vmstate_cpu_common vmstate_dummy
508#endif
509
510#define VMSTATE_CPU() { \
511 .name = "parent_obj", \
512 .size = sizeof(CPUState), \
513 .vmsd = &vmstate_cpu_common, \
514 .flags = VMS_STRUCT, \
515 .offset = 0, \
516}
517
dd83b06a 518#endif