cpu: Introduce CPUState::gdb_num_regs and CPUClass::gdb_num_core_regs

CPUState::gdb_num_regs replaces num_g_regs.
CPUClass::gdb_num_core_regs replaces NUM_CORE_REGS.

Allows building gdb_register_coprocessor() for xtensa, too.

As a side effect this should fix coprocessor register numbering for SMP.

Acked-by: Michael Walle <michael@walle.cc> (for lm32)
Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa)
Signed-off-by: Andreas Färber <afaerber@suse.de>

diff --git a/gdbstub.c b/gdbstub.c
index 9ede3de7aec6fe2873b2d05005446231def13d04..4879055c604642efe0dd4e9ac21dd22d7a0186aa 100644 (file)
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -530,8 +530,6 @@ static const int gpr_map[16] = {
 #endif
 static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
 
-#define NUM_CORE_REGS (CPU_NB_REGS * 2 + 25)
-
 #define IDX_IP_REG      CPU_NB_REGS
 #define IDX_FLAGS_REG   (IDX_IP_REG + 1)
 #define IDX_SEG_REGS    (IDX_FLAGS_REG + 1)
@@ -732,7 +730,6 @@ static int cpu_gdb_write_register(CPUX86State *env, uint8_t *mem_buf, int n)
    historical mishap the FP registers appear in between core integer
    regs and PC, MSR, CR, and so forth.  We hack round this by giving the
    FP regs zero size when talking to a newer gdb.  */
-#define NUM_CORE_REGS 71
 #if defined (TARGET_PPC64)
 #define GDB_CORE_XML "power64-core.xml"
 #else
@@ -837,12 +834,6 @@ static int cpu_gdb_write_register(CPUPPCState *env, uint8_t *mem_buf, int n)
 
 #elif defined (TARGET_SPARC)
 
-#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
-#define NUM_CORE_REGS 86
-#else
-#define NUM_CORE_REGS 72
-#endif
-
 #ifdef TARGET_ABI32
 #define GET_REGA(val) GET_REG32(val)
 #else
@@ -1030,7 +1021,6 @@ static int cpu_gdb_write_register(CPUSPARCState *env, uint8_t *mem_buf, int n)
    the FPA registers appear in between core integer regs and the CPSR.
    We hack round this by giving the FPA regs zero size when talking to a
    newer gdb.  */
-#define NUM_CORE_REGS 26
 #define GDB_CORE_XML "arm-core.xml"
 
 static int cpu_gdb_read_register(CPUARMState *env, uint8_t *mem_buf, int n)
@@ -1104,8 +1094,6 @@ static int cpu_gdb_write_register(CPUARMState *env, uint8_t *mem_buf, int n)
 
 #elif defined (TARGET_M68K)
 
-#define NUM_CORE_REGS 18
-
 #define GDB_CORE_XML "cf-core.xml"
 
 static int cpu_gdb_read_register(CPUM68KState *env, uint8_t *mem_buf, int n)
@@ -1157,8 +1145,6 @@ static int cpu_gdb_write_register(CPUM68KState *env, uint8_t *mem_buf, int n)
 }
 #elif defined (TARGET_MIPS)
 
-#define NUM_CORE_REGS 73
-
 static int cpu_gdb_read_register(CPUMIPSState *env, uint8_t *mem_buf, int n)
 {
     if (n < 32) {
@@ -1285,8 +1271,6 @@ static int cpu_gdb_write_register(CPUMIPSState *env, uint8_t *mem_buf, int n)
 }
 #elif defined(TARGET_OPENRISC)
 
-#define NUM_CORE_REGS (32 + 3)
-
 static int cpu_gdb_read_register(CPUOpenRISCState *env, uint8_t *mem_buf, int n)
 {
     if (n < 32) {
@@ -1312,9 +1296,11 @@ static int cpu_gdb_read_register(CPUOpenRISCState *env, uint8_t *mem_buf, int n)
 static int cpu_gdb_write_register(CPUOpenRISCState *env,
                                   uint8_t *mem_buf, int n)
 {
+    OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
+    CPUClass *cc = CPU_GET_CLASS(cpu);
     uint32_t tmp;
 
-    if (n > NUM_CORE_REGS) {
+    if (n > cc->gdb_num_core_regs) {
         return 0;
     }
 
@@ -1347,8 +1333,6 @@ static int cpu_gdb_write_register(CPUOpenRISCState *env,
 /* Hint: Use "set architecture sh4" in GDB to see fpu registers */
 /* FIXME: We should use XML for this.  */
 
-#define NUM_CORE_REGS 59
-
 static int cpu_gdb_read_register(CPUSH4State *env, uint8_t *mem_buf, int n)
 {
     switch (n) {
@@ -1465,8 +1449,6 @@ static int cpu_gdb_write_register(CPUSH4State *env, uint8_t *mem_buf, int n)
 }
 #elif defined (TARGET_MICROBLAZE)
 
-#define NUM_CORE_REGS (32 + 5)
-
 static int cpu_gdb_read_register(CPUMBState *env, uint8_t *mem_buf, int n)
 {
     if (n < 32) {
@@ -1479,9 +1461,11 @@ static int cpu_gdb_read_register(CPUMBState *env, uint8_t *mem_buf, int n)
 
 static int cpu_gdb_write_register(CPUMBState *env, uint8_t *mem_buf, int n)
 {
+    MicroBlazeCPU *cpu = mb_env_get_cpu(env);
+    CPUClass *cc = CPU_GET_CLASS(cpu);
     uint32_t tmp;
 
-    if (n > NUM_CORE_REGS) {
+    if (n > cc->gdb_num_core_regs) {
         return 0;
     }
 
@@ -1496,8 +1480,6 @@ static int cpu_gdb_write_register(CPUMBState *env, uint8_t *mem_buf, int n)
 }
 #elif defined (TARGET_CRIS)
 
-#define NUM_CORE_REGS 49
-
 static int
 read_register_crisv10(CPUCRISState *env, uint8_t *mem_buf, int n)
 {
@@ -1605,8 +1587,6 @@ static int cpu_gdb_write_register(CPUCRISState *env, uint8_t *mem_buf, int n)
 }
 #elif defined (TARGET_ALPHA)
 
-#define NUM_CORE_REGS 67
-
 static int cpu_gdb_read_register(CPUAlphaState *env, uint8_t *mem_buf, int n)
 {
     uint64_t val;
@@ -1675,8 +1655,6 @@ static int cpu_gdb_write_register(CPUAlphaState *env, uint8_t *mem_buf, int n)
 }
 #elif defined (TARGET_S390X)
 
-#define NUM_CORE_REGS  S390_NUM_REGS
-
 static int cpu_gdb_read_register(CPUS390XState *env, uint8_t *mem_buf, int n)
 {
     uint64_t val;
@@ -1740,7 +1718,6 @@ static int cpu_gdb_write_register(CPUS390XState *env, uint8_t *mem_buf, int n)
 #elif defined (TARGET_LM32)
 
 #include "hw/lm32/lm32_pic.h"
-#define NUM_CORE_REGS (32 + 7)
 
 static int cpu_gdb_read_register(CPULM32State *env, uint8_t *mem_buf, int n)
 {
@@ -1770,9 +1747,11 @@ static int cpu_gdb_read_register(CPULM32State *env, uint8_t *mem_buf, int n)
 
 static int cpu_gdb_write_register(CPULM32State *env, uint8_t *mem_buf, int n)
 {
+    LM32CPU *cpu = lm32_env_get_cpu(env);
+    CPUClass *cc = CPU_GET_CLASS(cpu);
     uint32_t tmp;
 
-    if (n > NUM_CORE_REGS) {
+    if (n > cc->gdb_num_core_regs) {
         return 0;
     }
 
@@ -1806,14 +1785,6 @@ static int cpu_gdb_write_register(CPULM32State *env, uint8_t *mem_buf, int n)
 }
 #elif defined(TARGET_XTENSA)
 
-/* Use num_core_regs to see only non-privileged registers in an unmodified gdb.
- * Use num_regs to see all registers. gdb modification is required for that:
- * reset bit 0 in the 'flags' field of the registers definitions in the
- * gdb/xtensa-config.c inside gdb source tree or inside gdb overlay.
- */
-#define NUM_CORE_REGS (env->config->gdb_regmap.num_regs)
-#define num_g_regs NUM_CORE_REGS
-
 static int cpu_gdb_read_register(CPUXtensaState *env, uint8_t *mem_buf, int n)
 {
     const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
@@ -1896,8 +1867,6 @@ static int cpu_gdb_write_register(CPUXtensaState *env, uint8_t *mem_buf, int n)
 }
 #else
 
-#define NUM_CORE_REGS 0
-
 static int cpu_gdb_read_register(CPUArchState *env, uint8_t *mem_buf, int n)
 {
     return 0;
@@ -1910,10 +1879,6 @@ static int cpu_gdb_write_register(CPUArchState *env, uint8_t *mem_buf, int n)
 
 #endif
 
-#if !defined(TARGET_XTENSA)
-static int num_g_regs = NUM_CORE_REGS;
-#endif
-
 #ifdef GDB_CORE_XML
 /* Encode data using the encoding for 'x' packets.  */
 static int memtox(char *buf, const char *mem, int len)
@@ -1982,11 +1947,13 @@ static const char *get_feature_xml(const char *p, const char **newp)
 
 static int gdb_read_register(CPUState *cpu, uint8_t *mem_buf, int reg)
 {
+    CPUClass *cc = CPU_GET_CLASS(cpu);
     CPUArchState *env = cpu->env_ptr;
     GDBRegisterState *r;
 
-    if (reg < NUM_CORE_REGS)
+    if (reg < cc->gdb_num_core_regs) {
         return cpu_gdb_read_register(env, mem_buf, reg);
+    }
 
     for (r = cpu->gdb_regs; r; r = r->next) {
         if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
@@ -1998,11 +1965,13 @@ static int gdb_read_register(CPUState *cpu, uint8_t *mem_buf, int reg)
 
 static int gdb_write_register(CPUState *cpu, uint8_t *mem_buf, int reg)
 {
+    CPUClass *cc = CPU_GET_CLASS(cpu);
     CPUArchState *env = cpu->env_ptr;
     GDBRegisterState *r;
 
-    if (reg < NUM_CORE_REGS)
+    if (reg < cc->gdb_num_core_regs) {
         return cpu_gdb_write_register(env, mem_buf, reg);
+    }
 
     for (r = cpu->gdb_regs; r; r = r->next) {
         if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
@@ -2012,7 +1981,6 @@ static int gdb_write_register(CPUState *cpu, uint8_t *mem_buf, int reg)
     return 0;
 }
 
-#if !defined(TARGET_XTENSA)
 /* Register a supplemental set of CPU registers.  If g_pos is nonzero it
    specifies the first register number and these registers are included in
    a standard "g" packet.  Direction is relative to gdb, i.e. get_reg is
@@ -2025,7 +1993,6 @@ void gdb_register_coprocessor(CPUState *cpu,
 {
     GDBRegisterState *s;
     GDBRegisterState **p;
-    static int last_reg = NUM_CORE_REGS;
 
     p = &cpu->gdb_regs;
     while (*p) {
@@ -2036,25 +2003,22 @@ void gdb_register_coprocessor(CPUState *cpu,
     }
 
     s = g_new0(GDBRegisterState, 1);
-    s->base_reg = last_reg;
+    s->base_reg = cpu->gdb_num_regs;
     s->num_regs = num_regs;
     s->get_reg = get_reg;
     s->set_reg = set_reg;
     s->xml = xml;
 
     /* Add to end of list.  */
-    last_reg += num_regs;
+    cpu->gdb_num_regs += num_regs;
     *p = s;
     if (g_pos) {
         if (g_pos != s->base_reg) {
             fprintf(stderr, "Error: Bad gdb register numbering for '%s'\n"
                     "Expected %d got %d\n", xml, g_pos, s->base_reg);
-        } else {
-            num_g_regs = last_reg;
         }
     }
 }
-#endif
 
 #ifndef CONFIG_USER_ONLY
 static const int xlat_gdb_type[] = {
@@ -2184,9 +2148,6 @@ static CPUState *find_cpu(uint32_t thread_id)
 
 static int gdb_handle_packet(GDBState *s, const char *line_buf)
 {
-#ifdef TARGET_XTENSA
-    CPUArchState *env;
-#endif
     CPUState *cpu;
     const char *p;
     uint32_t thread;
@@ -2334,11 +2295,8 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf)
         break;
     case 'g':
         cpu_synchronize_state(s->g_cpu);
-#ifdef TARGET_XTENSA
-        env = s->g_cpu->env_ptr;
-#endif
         len = 0;
-        for (addr = 0; addr < num_g_regs; addr++) {
+        for (addr = 0; addr < s->g_cpu->gdb_num_regs; addr++) {
             reg_size = gdb_read_register(s->g_cpu, mem_buf + len, addr);
             len += reg_size;
         }
@@ -2347,13 +2305,10 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf)
         break;
     case 'G':
         cpu_synchronize_state(s->g_cpu);
-#ifdef TARGET_XTENSA
-        env = s->g_cpu->env_ptr;
-#endif
         registers = mem_buf;
         len = strlen(p) / 2;
         hextomem((uint8_t *)registers, p, len);
-        for (addr = 0; addr < num_g_regs && len > 0; addr++) {
+        for (addr = 0; addr < s->g_cpu->gdb_num_regs && len > 0; addr++) {
             reg_size = gdb_write_register(s->g_cpu, registers, addr);
             len -= reg_size;
             registers += reg_size;

diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index daf1835c1a03f2d62ca474c1cf5c1188431cc3a5..195fe593ea0c13fd660f95f0ac2f4eebc84c4fe4 100644 (file)
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -81,6 +81,7 @@ struct TranslationBlock;
  * #TranslationBlock.
  * @get_phys_page_debug: Callback for obtaining a physical address.
  * @vmsd: State description for migration.
+ * @gdb_num_core_regs: Number of core registers accessible to GDB.
  *
  * Represents a CPU family or model.
  */
@@ -109,7 +110,6 @@ typedef struct CPUClass {
     void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb);
     hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
 
-    const struct VMStateDescription *vmsd;
     int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
                             int cpuid, void *opaque);
     int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
@@ -118,6 +118,9 @@ typedef struct CPUClass {
                             int cpuid, void *opaque);
     int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
                                 void *opaque);
+
+    const struct VMStateDescription *vmsd;
+    int gdb_num_core_regs;
 } CPUClass;
 
 struct KVMState;
@@ -142,6 +145,7 @@ struct kvm_run;
  * @env_ptr: Pointer to subclass-specific CPUArchState field.
  * @current_tb: Currently executing TB.
  * @gdb_regs: Additional GDB registers.
+ * @gdb_num_regs: Number of total registers accessible to GDB.
  * @next_cpu: Next CPU sharing TB cache.
  * @kvm_fd: vCPU file descriptor for KVM.
  *
@@ -177,6 +181,7 @@ struct CPUState {
     void *env_ptr; /* CPUArchState */
     struct TranslationBlock *current_tb;
     struct GDBRegisterState *gdb_regs;
+    int gdb_num_regs;
     CPUState *next_cpu;
 
     int kvm_fd;

diff --git a/qom/cpu.c b/qom/cpu.c
index 5c45ab533338d411a2bd3d2bcc88a0c5f5200b8c..2839ddf65079442afa0c5b4d365ebd911318371d 100644 (file)
--- a/qom/cpu.c
+++ b/qom/cpu.c
@@ -226,6 +226,14 @@ static void cpu_common_realizefn(DeviceState *dev, Error **errp)
     }
 }
 
+static void cpu_common_initfn(Object *obj)
+{
+    CPUState *cpu = CPU(obj);
+    CPUClass *cc = CPU_GET_CLASS(obj);
+
+    cpu->gdb_num_regs = cc->gdb_num_core_regs;
+}
+
 static int64_t cpu_common_get_arch_id(CPUState *cpu)
 {
     return cpu->cpu_index;
@@ -253,6 +261,7 @@ static const TypeInfo cpu_type_info = {
     .name = TYPE_CPU,
     .parent = TYPE_DEVICE,
     .instance_size = sizeof(CPUState),
+    .instance_init = cpu_common_initfn,
     .abstract = true,
     .class_size = sizeof(CPUClass),
     .class_init = cpu_class_init,

diff --git a/target-alpha/cpu.c b/target-alpha/cpu.c
index c8c8c2c86158d37c0edf7ce0abc6c106ed1f348a..cc0f69a84a292c9955cfa40d4b3c6267286483ec 100644 (file)
--- a/target-alpha/cpu.c
+++ b/target-alpha/cpu.c
@@ -276,6 +276,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
     cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
     dc->vmsd = &vmstate_alpha_cpu;
 #endif
+    cc->gdb_num_core_regs = 67;
 }
 
 static const TypeInfo alpha_cpu_type_info = {

diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index d3906a4829a00d67f8b13618a7dd1e4b80b26064..f39c19f16214b3ea36c57290ddcb5c6d00a5295f 100644 (file)
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -828,6 +828,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
     cc->get_phys_page_debug = arm_cpu_get_phys_page_debug;
     cc->vmsd = &vmstate_arm_cpu;
 #endif
+    cc->gdb_num_core_regs = 26;
 }
 
 static void cpu_register(const ARMCPUInfo *info)

diff --git a/target-cris/cpu.c b/target-cris/cpu.c
index ba095e75a5e4d629fa07636ab59776c4c13ccc6c..31eeddf822f26ae9727cb4f49dfff441398d5f24 100644 (file)
--- a/target-cris/cpu.c
+++ b/target-cris/cpu.c
@@ -258,6 +258,8 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
 #ifndef CONFIG_USER_ONLY
     cc->get_phys_page_debug = cris_cpu_get_phys_page_debug;
 #endif
+
+    cc->gdb_num_core_regs = 49;
 }
 
 static const TypeInfo cris_cpu_type_info = {

diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index cd350cb8e44693367e06abf97e9f56d11aaa29fd..df9832e1519b8468cba0b2c94def0897f958858a 100644 (file)
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -2549,6 +2549,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
     cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
     cc->vmsd = &vmstate_x86_cpu;
 #endif
+    cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
 }
 
 static const TypeInfo x86_cpu_type_info = {

diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c
index ce55e4807d8e846374f1bef9a43374e1df0cdc49..aa52696cda653530c4297f46b7440428c7a51dab 100644 (file)
--- a/target-lm32/cpu.c
+++ b/target-lm32/cpu.c
@@ -91,6 +91,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
     cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug;
     cc->vmsd = &vmstate_lm32_cpu;
 #endif
+    cc->gdb_num_core_regs = 32 + 7;
 }
 
 static const TypeInfo lm32_cpu_type_info = {

diff --git a/target-m68k/cpu.c b/target-m68k/cpu.c
index 988f4762573e72ec75d00d53d1ccce6cd48186dc..93200d9964809637f01e2600013e895973f1d4a7 100644 (file)
--- a/target-m68k/cpu.c
+++ b/target-m68k/cpu.c
@@ -194,6 +194,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
     cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug;
 #endif
     dc->vmsd = &vmstate_m68k_cpu;
+    cc->gdb_num_core_regs = 18;
 }
 
 static void register_cpu_type(const M68kCPUInfo *info)

diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
index 9f10c8c778d2eab3db8f4451c6bad440d94f1663..758b0cb07d36f1606772ec27615896386aee4df1 100644 (file)
--- a/target-microblaze/cpu.c
+++ b/target-microblaze/cpu.c
@@ -147,6 +147,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
 #endif
     dc->vmsd = &vmstate_mb_cpu;
     dc->props = mb_properties;
+    cc->gdb_num_core_regs = 32 + 5;
 }
 
 static const TypeInfo mb_cpu_type_info = {

diff --git a/target-mips/cpu.c b/target-mips/cpu.c
index 4834c86d021048afc343c6cb1ef3a321eb15ca60..e667fb7b7c765f8e2bbf9f054bf6e2d5edccfb10 100644 (file)
--- a/target-mips/cpu.c
+++ b/target-mips/cpu.c
@@ -104,6 +104,8 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
     cc->do_unassigned_access = mips_cpu_unassigned_access;
     cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
 #endif
+
+    cc->gdb_num_core_regs = 73;
 }
 
 static const TypeInfo mips_cpu_type_info = {

diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
index 7718820eccb09d95ebe8e7778b8370603f667ee9..9b042e14b0053e315c2279947368145959e3f355 100644 (file)
--- a/target-openrisc/cpu.c
+++ b/target-openrisc/cpu.c
@@ -159,6 +159,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
     cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
     dc->vmsd = &vmstate_openrisc_cpu;
 #endif
+    cc->gdb_num_core_regs = 32 + 3;
 }
 
 static void cpu_register(const OpenRISCCPUInfo *info)

diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 0b0844f467508c8f4f737f03b380d85add594843..91161939c048a66edece4ed564ad04781f5c368e 100644 (file)
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8461,6 +8461,8 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
 #ifndef CONFIG_USER_ONLY
     cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
 #endif
+
+    cc->gdb_num_core_regs = 71;
 }
 
 static const TypeInfo ppc_cpu_type_info = {

diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c
index cb89d1a46b3fdd53f5a01d17ea840eeaccbd112a..8f99d7c86c989b1f2e96ae8423be0835c05fd988 100644 (file)
--- a/target-s390x/cpu.c
+++ b/target-s390x/cpu.c
@@ -177,6 +177,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
     cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
 #endif
     dc->vmsd = &vmstate_s390_cpu;
+    cc->gdb_num_core_regs = S390_NUM_REGS;
 }
 
 static const TypeInfo s390_cpu_type_info = {

diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c
index 51a77576fbfc08b7c02850bebd076bf531cb303e..35f0535436594f294463b81678b346bffcc725b6 100644 (file)
--- a/target-sh4/cpu.c
+++ b/target-sh4/cpu.c
@@ -290,6 +290,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
     cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
 #endif
     dc->vmsd = &vmstate_sh_cpu;
+    cc->gdb_num_core_regs = 59;
 }
 
 static const TypeInfo superh_cpu_type_info = {

diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c
index d1d03396efdd91b200fdb5ff3074473915d8b6ec..388a632d186a8695ed797aab22131512bffb9483 100644 (file)
--- a/target-sparc/cpu.c
+++ b/target-sparc/cpu.c
@@ -791,6 +791,12 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
     cc->do_unassigned_access = sparc_cpu_unassigned_access;
     cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
 #endif
+
+#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
+    cc->gdb_num_core_regs = 86;
+#else
+    cc->gdb_num_core_regs = 72;
+#endif
 }
 
 static const TypeInfo sparc_cpu_type_info = {

diff --git a/target-xtensa/cpu.c b/target-xtensa/cpu.c
index 5a39971d2c0a0727c7788e02b8c0fdfdd77be4ee..560fa0c05842c60bfe6b4f2dfdfe4d66bff7910d 100644 (file)
--- a/target-xtensa/cpu.c
+++ b/target-xtensa/cpu.c
@@ -85,8 +85,11 @@ static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model)
 
 static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp)
 {
+    CPUState *cs = CPU(dev);
     XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(dev);
 
+    cs->gdb_num_regs = xcc->config->gdb_regmap.num_regs;
+
     xcc->parent_realize(dev, errp);
 }
 

diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c
index e3098798af48ede8ad8e0cabe76cf26f62e449c5..a0f9993b2d1aeb09993d3def5d2bb9da0bae5f62 100644 (file)
--- a/target-xtensa/helper.c
+++ b/target-xtensa/helper.c
@@ -37,10 +37,18 @@ static struct XtensaConfigList *xtensa_cores;
 
 static void xtensa_core_class_init(ObjectClass *oc, void *data)
 {
+    CPUClass *cc = CPU_CLASS(oc);
     XtensaCPUClass *xcc = XTENSA_CPU_CLASS(oc);
     const XtensaConfig *config = data;
 
     xcc->config = config;
+
+    /* Use num_core_regs to see only non-privileged registers in an unmodified
+     * gdb. Use num_regs to see all registers. gdb modification is required
+     * for that: reset bit 0 in the 'flags' field of the registers definitions
+     * in the gdb/xtensa-config.c inside gdb source tree or inside gdb overlay.
+     */
+    cc->gdb_num_core_regs = config->gdb_regmap.num_regs;
 }
 
 void xtensa_register_core(XtensaConfigList *node)