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softfloat: Implement fused multiply-add
[qemu.git] / target-arm / helper.c
CommitLineData
b5ff1b31
FB		 1#include <stdio.h>
2#include <stdlib.h>
3#include <string.h>
4
5#include "cpu.h"
9ee6e8bb 6#include "gdbstub.h"
7b59220e 7#include "helper.h"
ca10f867 8#include "qemu-common.h"
7bbcb0af 9#include "host-utils.h"
4f78c9ad 10#if !defined(CONFIG_USER_ONLY)
983fe826 11#include "hw/loader.h"
4f78c9ad 12#endif
9ee6e8bb 13
10055562
PB		 14static uint32_t cortexa9_cp15_c0_c1[8] =
15{ 0x1031, 0x11, 0x000, 0, 0x00100103, 0x20000000, 0x01230000, 0x00002111 };
16
17static uint32_t cortexa9_cp15_c0_c2[8] =
18{ 0x00101111, 0x13112111, 0x21232041, 0x11112131, 0x00111142, 0, 0, 0 };
19
9ee6e8bb
PB		 20static uint32_t cortexa8_cp15_c0_c1[8] =
21{ 0x1031, 0x11, 0x400, 0, 0x31100003, 0x20000000, 0x01202000, 0x11 };
22
23static uint32_t cortexa8_cp15_c0_c2[8] =
24{ 0x00101111, 0x12112111, 0x21232031, 0x11112131, 0x00111142, 0, 0, 0 };
25
26static uint32_t mpcore_cp15_c0_c1[8] =
27{ 0x111, 0x1, 0, 0x2, 0x01100103, 0x10020302, 0x01222000, 0 };
28
29static uint32_t mpcore_cp15_c0_c2[8] =
30{ 0x00100011, 0x12002111, 0x11221011, 0x01102131, 0x141, 0, 0, 0 };
31
32static uint32_t arm1136_cp15_c0_c1[8] =
33{ 0x111, 0x1, 0x2, 0x3, 0x01130003, 0x10030302, 0x01222110, 0 };
34
35static uint32_t arm1136_cp15_c0_c2[8] =
36{ 0x00140011, 0x12002111, 0x11231111, 0x01102131, 0x141, 0, 0, 0 };
b5ff1b31 37
7807eed9
JI		 38static uint32_t arm1176_cp15_c0_c1[8] =
39{ 0x111, 0x11, 0x33, 0, 0x01130003, 0x10030302, 0x01222100, 0 };
40
41static uint32_t arm1176_cp15_c0_c2[8] =
42{ 0x0140011, 0x12002111, 0x11231121, 0x01102131, 0x01141, 0, 0, 0 };
43
aaed909a
FB		 44static uint32_t cpu_arm_find_by_name(const char *name);
45
f3d6b95e
PB		 46static inline void set_feature(CPUARMState *env, int feature)
47{
48 env->features |= 1u << feature;
49}
50
51static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
52{
53 env->cp15.c0_cpuid = id;
54 switch (id) {
55 case ARM_CPUID_ARM926:
be5e7a76
DES		 56 set_feature(env, ARM_FEATURE_V4T);
57 set_feature(env, ARM_FEATURE_V5);
f3d6b95e
PB		 58 set_feature(env, ARM_FEATURE_VFP);
59 env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090;
c1713132 60 env->cp15.c0_cachetype = 0x1dd20d2;
610c3c8a 61 env->cp15.c1_sys = 0x00090078;
f3d6b95e 62 break;
ce819861 63 case ARM_CPUID_ARM946:
be5e7a76
DES		 64 set_feature(env, ARM_FEATURE_V4T);
65 set_feature(env, ARM_FEATURE_V5);
ce819861
PB		 66 set_feature(env, ARM_FEATURE_MPU);
67 env->cp15.c0_cachetype = 0x0f004006;
610c3c8a 68 env->cp15.c1_sys = 0x00000078;
ce819861 69 break;
f3d6b95e 70 case ARM_CPUID_ARM1026:
be5e7a76
DES		 71 set_feature(env, ARM_FEATURE_V4T);
72 set_feature(env, ARM_FEATURE_V5);
f3d6b95e
PB		 73 set_feature(env, ARM_FEATURE_VFP);
74 set_feature(env, ARM_FEATURE_AUXCR);
75 env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0;
c1713132 76 env->cp15.c0_cachetype = 0x1dd20d2;
610c3c8a 77 env->cp15.c1_sys = 0x00090078;
c1713132 78 break;
9ee6e8bb 79 case ARM_CPUID_ARM1136:
906879a9
PM		 80 /* This is the 1136 r1, which is a v6K core */
81 set_feature(env, ARM_FEATURE_V6K);
82 /* Fall through */
83 case ARM_CPUID_ARM1136_R2:
84 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
85 * older core than plain "arm1136". In particular this does not
86 * have the v6K features.
87 */
be5e7a76
DES		 88 set_feature(env, ARM_FEATURE_V4T);
89 set_feature(env, ARM_FEATURE_V5);
9ee6e8bb
PB		 90 set_feature(env, ARM_FEATURE_V6);
91 set_feature(env, ARM_FEATURE_VFP);
92 set_feature(env, ARM_FEATURE_AUXCR);
906879a9
PM		 93 /* These ID register values are correct for 1136 but may be wrong
94 * for 1136_r2 (in particular r0p2 does not actually implement most
95 * of the ID registers).
96 */
9ee6e8bb
PB		 97 env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
98 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
99 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
100 memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t));
22478e79 101 memcpy(env->cp15.c0_c2, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t));
9ee6e8bb 102 env->cp15.c0_cachetype = 0x1dd20d2;
16440c5f 103 env->cp15.c1_sys = 0x00050078;
9ee6e8bb 104 break;
7807eed9
JI		 105 case ARM_CPUID_ARM1176:
106 set_feature(env, ARM_FEATURE_V4T);
107 set_feature(env, ARM_FEATURE_V5);
108 set_feature(env, ARM_FEATURE_V6);
109 set_feature(env, ARM_FEATURE_V6K);
110 set_feature(env, ARM_FEATURE_VFP);
111 set_feature(env, ARM_FEATURE_AUXCR);
906879a9 112 set_feature(env, ARM_FEATURE_VAPA);
7807eed9
JI		 113 env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b5;
114 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
115 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
116 memcpy(env->cp15.c0_c1, arm1176_cp15_c0_c1, 8 * sizeof(uint32_t));
117 memcpy(env->cp15.c0_c2, arm1176_cp15_c0_c2, 8 * sizeof(uint32_t));
118 env->cp15.c0_cachetype = 0x1dd20d2;
119 env->cp15.c1_sys = 0x00050078;
120 break;
9ee6e8bb 121 case ARM_CPUID_ARM11MPCORE:
be5e7a76
DES		 122 set_feature(env, ARM_FEATURE_V4T);
123 set_feature(env, ARM_FEATURE_V5);
9ee6e8bb
PB		 124 set_feature(env, ARM_FEATURE_V6);
125 set_feature(env, ARM_FEATURE_V6K);
126 set_feature(env, ARM_FEATURE_VFP);
127 set_feature(env, ARM_FEATURE_AUXCR);
906879a9 128 set_feature(env, ARM_FEATURE_VAPA);
9ee6e8bb
PB		 129 env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
130 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
131 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
132 memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t));
22478e79 133 memcpy(env->cp15.c0_c2, mpcore_cp15_c0_c2, 8 * sizeof(uint32_t));
9ee6e8bb
PB		 134 env->cp15.c0_cachetype = 0x1dd20d2;
135 break;
136 case ARM_CPUID_CORTEXA8:
be5e7a76
DES		 137 set_feature(env, ARM_FEATURE_V4T);
138 set_feature(env, ARM_FEATURE_V5);
9ee6e8bb
PB		 139 set_feature(env, ARM_FEATURE_V6);
140 set_feature(env, ARM_FEATURE_V6K);
141 set_feature(env, ARM_FEATURE_V7);
142 set_feature(env, ARM_FEATURE_AUXCR);
143 set_feature(env, ARM_FEATURE_THUMB2);
144 set_feature(env, ARM_FEATURE_VFP);
145 set_feature(env, ARM_FEATURE_VFP3);
146 set_feature(env, ARM_FEATURE_NEON);
fe1479c3 147 set_feature(env, ARM_FEATURE_THUMB2EE);
9ee6e8bb
PB		 148 env->vfp.xregs[ARM_VFP_FPSID] = 0x410330c0;
149 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
150 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
151 memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t));
22478e79 152 memcpy(env->cp15.c0_c2, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t));
a49ea279
PB		 153 env->cp15.c0_cachetype = 0x82048004;
154 env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3;
155 env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
156 env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */
157 env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */
9c486ad6 158 env->cp15.c1_sys = 0x00c50078;
9ee6e8bb 159 break;
10055562 160 case ARM_CPUID_CORTEXA9:
be5e7a76
DES		 161 set_feature(env, ARM_FEATURE_V4T);
162 set_feature(env, ARM_FEATURE_V5);
10055562
PB		 163 set_feature(env, ARM_FEATURE_V6);
164 set_feature(env, ARM_FEATURE_V6K);
165 set_feature(env, ARM_FEATURE_V7);
166 set_feature(env, ARM_FEATURE_AUXCR);
167 set_feature(env, ARM_FEATURE_THUMB2);
168 set_feature(env, ARM_FEATURE_VFP);
169 set_feature(env, ARM_FEATURE_VFP3);
170 set_feature(env, ARM_FEATURE_VFP_FP16);
171 set_feature(env, ARM_FEATURE_NEON);
172 set_feature(env, ARM_FEATURE_THUMB2EE);
e1bbf446
PM		 173 /* Note that A9 supports the MP extensions even for
174 * A9UP and single-core A9MP (which are both different
175 * and valid configurations; we don't model A9UP).
176 */
177 set_feature(env, ARM_FEATURE_V7MP);
10055562
PB		 178 env->vfp.xregs[ARM_VFP_FPSID] = 0x41034000; /* Guess */
179 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
180 env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111;
181 memcpy(env->cp15.c0_c1, cortexa9_cp15_c0_c1, 8 * sizeof(uint32_t));
182 memcpy(env->cp15.c0_c2, cortexa9_cp15_c0_c2, 8 * sizeof(uint32_t));
183 env->cp15.c0_cachetype = 0x80038003;
184 env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3;
185 env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */
186 env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */
16440c5f 187 env->cp15.c1_sys = 0x00c50078;
10055562 188 break;
9ee6e8bb 189 case ARM_CPUID_CORTEXM3:
be5e7a76
DES		 190 set_feature(env, ARM_FEATURE_V4T);
191 set_feature(env, ARM_FEATURE_V5);
9ee6e8bb
PB		 192 set_feature(env, ARM_FEATURE_V6);
193 set_feature(env, ARM_FEATURE_THUMB2);
194 set_feature(env, ARM_FEATURE_V7);
195 set_feature(env, ARM_FEATURE_M);
47789990 196 set_feature(env, ARM_FEATURE_THUMB_DIV);
9ee6e8bb
PB		 197 break;
198 case ARM_CPUID_ANY: /* For userspace emulation. */
be5e7a76
DES		 199 set_feature(env, ARM_FEATURE_V4T);
200 set_feature(env, ARM_FEATURE_V5);
9ee6e8bb
PB		 201 set_feature(env, ARM_FEATURE_V6);
202 set_feature(env, ARM_FEATURE_V6K);
203 set_feature(env, ARM_FEATURE_V7);
204 set_feature(env, ARM_FEATURE_THUMB2);
205 set_feature(env, ARM_FEATURE_VFP);
206 set_feature(env, ARM_FEATURE_VFP3);
60011498 207 set_feature(env, ARM_FEATURE_VFP_FP16);
9ee6e8bb 208 set_feature(env, ARM_FEATURE_NEON);
fe1479c3 209 set_feature(env, ARM_FEATURE_THUMB2EE);
b8b8ea05 210 set_feature(env, ARM_FEATURE_ARM_DIV);
e1bbf446 211 set_feature(env, ARM_FEATURE_V7MP);
9ee6e8bb 212 break;
c3d2689d
AZ		 213 case ARM_CPUID_TI915T:
214 case ARM_CPUID_TI925T:
be5e7a76 215 set_feature(env, ARM_FEATURE_V4T);
c3d2689d
AZ		 216 set_feature(env, ARM_FEATURE_OMAPCP);
217 env->cp15.c0_cpuid = ARM_CPUID_TI925T; /* Depends on wiring. */
218 env->cp15.c0_cachetype = 0x5109149;
219 env->cp15.c1_sys = 0x00000070;
220 env->cp15.c15_i_max = 0x000;
221 env->cp15.c15_i_min = 0xff0;
222 break;
c1713132
AZ		 223 case ARM_CPUID_PXA250:
224 case ARM_CPUID_PXA255:
225 case ARM_CPUID_PXA260:
226 case ARM_CPUID_PXA261:
227 case ARM_CPUID_PXA262:
be5e7a76
DES		 228 set_feature(env, ARM_FEATURE_V4T);
229 set_feature(env, ARM_FEATURE_V5);
c1713132
AZ		 230 set_feature(env, ARM_FEATURE_XSCALE);
231 /* JTAG_ID is ((id << 28) | 0x09265013) */
232 env->cp15.c0_cachetype = 0xd172172;
610c3c8a 233 env->cp15.c1_sys = 0x00000078;
c1713132
AZ		 234 break;
235 case ARM_CPUID_PXA270_A0:
236 case ARM_CPUID_PXA270_A1:
237 case ARM_CPUID_PXA270_B0:
238 case ARM_CPUID_PXA270_B1:
239 case ARM_CPUID_PXA270_C0:
240 case ARM_CPUID_PXA270_C5:
be5e7a76
DES		 241 set_feature(env, ARM_FEATURE_V4T);
242 set_feature(env, ARM_FEATURE_V5);
c1713132
AZ		 243 set_feature(env, ARM_FEATURE_XSCALE);
244 /* JTAG_ID is ((id << 28) | 0x09265013) */
18c9b560
AZ		 245 set_feature(env, ARM_FEATURE_IWMMXT);
246 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
c1713132 247 env->cp15.c0_cachetype = 0xd172172;
610c3c8a 248 env->cp15.c1_sys = 0x00000078;
f3d6b95e 249 break;
5bc95aa2
DES		 250 case ARM_CPUID_SA1100:
251 case ARM_CPUID_SA1110:
252 set_feature(env, ARM_FEATURE_STRONGARM);
253 env->cp15.c1_sys = 0x00000070;
254 break;
f3d6b95e
PB		 255 default:
256 cpu_abort(env, "Bad CPU ID: %x\n", id);
257 break;
258 }
906879a9
PM		 259
260 /* Some features automatically imply others: */
261 if (arm_feature(env, ARM_FEATURE_V7)) {
262 set_feature(env, ARM_FEATURE_VAPA);
263 }
b8b8ea05
PM		 264 if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
265 set_feature(env, ARM_FEATURE_THUMB_DIV);
266 }
f3d6b95e
PB		 267}
268
40f137e1
PB		 269void cpu_reset(CPUARMState *env)
270{
f3d6b95e 271 uint32_t id;
eca1bdf4
AL		 272
273 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
274 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
275 log_cpu_state(env, 0);
276 }
277
f3d6b95e
PB		 278 id = env->cp15.c0_cpuid;
279 memset(env, 0, offsetof(CPUARMState, breakpoints));
280 if (id)
281 cpu_reset_model_id(env, id);
40f137e1
PB		 282#if defined (CONFIG_USER_ONLY)
283 env->uncached_cpsr = ARM_CPU_MODE_USR;
3a807dec 284 /* For user mode we must enable access to coprocessors */
40f137e1 285 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
3a807dec
PM		 286 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
287 env->cp15.c15_cpar = 3;
288 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
289 env->cp15.c15_cpar = 1;
290 }
40f137e1
PB		 291#else
292 /* SVC mode with interrupts disabled. */
293 env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
9ee6e8bb 294 /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
983fe826
PB		 295 clear at reset. Initial SP and PC are loaded from ROM. */
296 if (IS_M(env)) {
297 uint32_t pc;
298 uint8_t *rom;
9ee6e8bb 299 env->uncached_cpsr &= ~CPSR_I;
983fe826
PB		 300 rom = rom_ptr(0);
301 if (rom) {
302 /* We should really use ldl_phys here, in case the guest
303 modified flash and reset itself. However images
297d1b4e 304 loaded via -kernel have not been copied yet, so load the
983fe826
PB		 305 values directly from there. */
306 env->regs[13] = ldl_p(rom);
307 pc = ldl_p(rom + 4);
308 env->thumb = pc & 1;
309 env->regs[15] = pc & ~1;
310 }
311 }
40f137e1 312 env->vfp.xregs[ARM_VFP_FPEXC] = 0;
b2fa1797 313 env->cp15.c2_base_mask = 0xffffc000u;
74594c9d
PM		 314 /* v7 performance monitor control register: same implementor
315 * field as main ID register, and we implement no event counters.
316 */
317 env->cp15.c9_pmcr = (id & 0xff000000);
40f137e1 318#endif
3a492f3a
PM		 319 set_flush_to_zero(1, &env->vfp.standard_fp_status);
320 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
321 set_default_nan_mode(1, &env->vfp.standard_fp_status);
9df38c47
PM		 322 set_float_detect_tininess(float_tininess_before_rounding,
323 &env->vfp.fp_status);
324 set_float_detect_tininess(float_tininess_before_rounding,
325 &env->vfp.standard_fp_status);
f3d6b95e 326 tlb_flush(env, 1);
40f137e1
PB		 327}
328
56aebc89
PB		 329static int vfp_gdb_get_reg(CPUState *env, uint8_t *buf, int reg)
330{
331 int nregs;
332
333 /* VFP data registers are always little-endian. */
334 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
335 if (reg < nregs) {
336 stfq_le_p(buf, env->vfp.regs[reg]);
337 return 8;
338 }
339 if (arm_feature(env, ARM_FEATURE_NEON)) {
340 /* Aliases for Q regs. */
341 nregs += 16;
342 if (reg < nregs) {
343 stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
344 stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
345 return 16;
346 }
347 }
348 switch (reg - nregs) {
349 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
350 case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
351 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
352 }
353 return 0;
354}
355
356static int vfp_gdb_set_reg(CPUState *env, uint8_t *buf, int reg)
357{
358 int nregs;
359
360 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
361 if (reg < nregs) {
362 env->vfp.regs[reg] = ldfq_le_p(buf);
363 return 8;
364 }
365 if (arm_feature(env, ARM_FEATURE_NEON)) {
366 nregs += 16;
367 if (reg < nregs) {
368 env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
369 env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
370 return 16;
371 }
372 }
373 switch (reg - nregs) {
374 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
375 case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
71b3c3de 376 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
56aebc89
PB		 377 }
378 return 0;
379}
380
aaed909a 381CPUARMState *cpu_arm_init(const char *cpu_model)
40f137e1
PB		 382{
383 CPUARMState *env;
aaed909a 384 uint32_t id;
b26eefb6 385 static int inited = 0;
40f137e1 386
aaed909a
FB		 387 id = cpu_arm_find_by_name(cpu_model);
388 if (id == 0)
389 return NULL;
7267c094 390 env = g_malloc0(sizeof(CPUARMState));
40f137e1 391 cpu_exec_init(env);
b26eefb6
PB		 392 if (!inited) {
393 inited = 1;
394 arm_translate_init();
395 }
396
01ba9816 397 env->cpu_model_str = cpu_model;
aaed909a 398 env->cp15.c0_cpuid = id;
40f137e1 399 cpu_reset(env);
56aebc89
PB		 400 if (arm_feature(env, ARM_FEATURE_NEON)) {
401 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
402 51, "arm-neon.xml", 0);
403 } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
404 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
405 35, "arm-vfp3.xml", 0);
406 } else if (arm_feature(env, ARM_FEATURE_VFP)) {
407 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
408 19, "arm-vfp.xml", 0);
409 }
0bf46a40 410 qemu_init_vcpu(env);
40f137e1
PB		 411 return env;
412}
413
3371d272
PB		 414struct arm_cpu_t {
415 uint32_t id;
416 const char *name;
417};
418
419static const struct arm_cpu_t arm_cpu_names[] = {
420 { ARM_CPUID_ARM926, "arm926"},
ce819861 421 { ARM_CPUID_ARM946, "arm946"},
3371d272 422 { ARM_CPUID_ARM1026, "arm1026"},
9ee6e8bb 423 { ARM_CPUID_ARM1136, "arm1136"},
827df9f3 424 { ARM_CPUID_ARM1136_R2, "arm1136-r2"},
7807eed9 425 { ARM_CPUID_ARM1176, "arm1176"},
9ee6e8bb
PB		 426 { ARM_CPUID_ARM11MPCORE, "arm11mpcore"},
427 { ARM_CPUID_CORTEXM3, "cortex-m3"},
428 { ARM_CPUID_CORTEXA8, "cortex-a8"},
10055562 429 { ARM_CPUID_CORTEXA9, "cortex-a9"},
c3d2689d 430 { ARM_CPUID_TI925T, "ti925t" },
c1713132 431 { ARM_CPUID_PXA250, "pxa250" },
5bc95aa2
DES		 432 { ARM_CPUID_SA1100, "sa1100" },
433 { ARM_CPUID_SA1110, "sa1110" },
c1713132
AZ		 434 { ARM_CPUID_PXA255, "pxa255" },
435 { ARM_CPUID_PXA260, "pxa260" },
436 { ARM_CPUID_PXA261, "pxa261" },
437 { ARM_CPUID_PXA262, "pxa262" },
438 { ARM_CPUID_PXA270, "pxa270" },
439 { ARM_CPUID_PXA270_A0, "pxa270-a0" },
440 { ARM_CPUID_PXA270_A1, "pxa270-a1" },
441 { ARM_CPUID_PXA270_B0, "pxa270-b0" },
442 { ARM_CPUID_PXA270_B1, "pxa270-b1" },
443 { ARM_CPUID_PXA270_C0, "pxa270-c0" },
444 { ARM_CPUID_PXA270_C5, "pxa270-c5" },
9ee6e8bb 445 { ARM_CPUID_ANY, "any"},
3371d272
PB		 446 { 0, NULL}
447};
448
9a78eead 449void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
5adb4839
PB		 450{
451 int i;
452
c732abe2 453 (*cpu_fprintf)(f, "Available CPUs:\n");
5adb4839 454 for (i = 0; arm_cpu_names[i].name; i++) {
c732abe2 455 (*cpu_fprintf)(f, " %s\n", arm_cpu_names[i].name);
5adb4839
PB		 456 }
457}
458
aaed909a
FB		 459/* return 0 if not found */
460static uint32_t cpu_arm_find_by_name(const char *name)
40f137e1 461{
3371d272
PB		 462 int i;
463 uint32_t id;
464
465 id = 0;
3371d272
PB		 466 for (i = 0; arm_cpu_names[i].name; i++) {
467 if (strcmp(name, arm_cpu_names[i].name) == 0) {
468 id = arm_cpu_names[i].id;
469 break;
470 }
471 }
aaed909a 472 return id;
40f137e1
PB		 473}
474
475void cpu_arm_close(CPUARMState *env)
476{
477 free(env);
478}
479
2f4a40e5
AZ		 480uint32_t cpsr_read(CPUARMState *env)
481{
482 int ZF;
6fbe23d5
PB		 483 ZF = (env->ZF == 0);
484 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
2f4a40e5
AZ		 485 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
486 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
487 | ((env->condexec_bits & 0xfc) << 8)
488 | (env->GE << 16);
489}
490
491void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
492{
2f4a40e5 493 if (mask & CPSR_NZCV) {
6fbe23d5
PB		 494 env->ZF = (~val) & CPSR_Z;
495 env->NF = val;
2f4a40e5
AZ		 496 env->CF = (val >> 29) & 1;
497 env->VF = (val << 3) & 0x80000000;
498 }
499 if (mask & CPSR_Q)
500 env->QF = ((val & CPSR_Q) != 0);
501 if (mask & CPSR_T)
502 env->thumb = ((val & CPSR_T) != 0);
503 if (mask & CPSR_IT_0_1) {
504 env->condexec_bits &= ~3;
505 env->condexec_bits |= (val >> 25) & 3;
506 }
507 if (mask & CPSR_IT_2_7) {
508 env->condexec_bits &= 3;
509 env->condexec_bits |= (val >> 8) & 0xfc;
510 }
511 if (mask & CPSR_GE) {
512 env->GE = (val >> 16) & 0xf;
513 }
514
515 if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
516 switch_mode(env, val & CPSR_M);
517 }
518 mask &= ~CACHED_CPSR_BITS;
519 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
520}
521
b26eefb6
PB		 522/* Sign/zero extend */
523uint32_t HELPER(sxtb16)(uint32_t x)
524{
525 uint32_t res;
526 res = (uint16_t)(int8_t)x;
527 res |= (uint32_t)(int8_t)(x >> 16) << 16;
528 return res;
529}
530
531uint32_t HELPER(uxtb16)(uint32_t x)
532{
533 uint32_t res;
534 res = (uint16_t)(uint8_t)x;
535 res |= (uint32_t)(uint8_t)(x >> 16) << 16;
536 return res;
537}
538
f51bbbfe
PB		 539uint32_t HELPER(clz)(uint32_t x)
540{
7bbcb0af 541 return clz32(x);
f51bbbfe
PB		 542}
543
3670669c
PB		 544int32_t HELPER(sdiv)(int32_t num, int32_t den)
545{
546 if (den == 0)
547 return 0;
686eeb93
AJ		 548 if (num == INT_MIN && den == -1)
549 return INT_MIN;
3670669c
PB		 550 return num / den;
551}
552
553uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
554{
555 if (den == 0)
556 return 0;
557 return num / den;
558}
559
560uint32_t HELPER(rbit)(uint32_t x)
561{
562 x = ((x & 0xff000000) >> 24)
563 | ((x & 0x00ff0000) >> 8)
564 | ((x & 0x0000ff00) << 8)
565 | ((x & 0x000000ff) << 24);
566 x = ((x & 0xf0f0f0f0) >> 4)
567 | ((x & 0x0f0f0f0f) << 4);
568 x = ((x & 0x88888888) >> 3)
569 | ((x & 0x44444444) >> 1)
570 | ((x & 0x22222222) << 1)
571 | ((x & 0x11111111) << 3);
572 return x;
573}
574
ad69471c
PB		 575uint32_t HELPER(abs)(uint32_t x)
576{
577 return ((int32_t)x < 0) ? -x : x;
578}
579
5fafdf24 580#if defined(CONFIG_USER_ONLY)
b5ff1b31
FB		 581
582void do_interrupt (CPUState *env)
583{
584 env->exception_index = -1;
585}
586
587int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
97b348e7 588 int mmu_idx)
b5ff1b31
FB		 589{
590 if (rw == 2) {
591 env->exception_index = EXCP_PREFETCH_ABORT;
592 env->cp15.c6_insn = address;
593 } else {
594 env->exception_index = EXCP_DATA_ABORT;
595 env->cp15.c6_data = address;
596 }
597 return 1;
598}
599
b5ff1b31 600/* These should probably raise undefined insn exceptions. */
8984bd2e 601void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
c1713132
AZ		 602{
603 int op1 = (insn >> 8) & 0xf;
604 cpu_abort(env, "cp%i insn %08x\n", op1, insn);
605 return;
606}
607
8984bd2e 608uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn)
c1713132
AZ		 609{
610 int op1 = (insn >> 8) & 0xf;
611 cpu_abort(env, "cp%i insn %08x\n", op1, insn);
612 return 0;
613}
614
8984bd2e 615void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
b5ff1b31
FB		 616{
617 cpu_abort(env, "cp15 insn %08x\n", insn);
618}
619
8984bd2e 620uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
b5ff1b31
FB		 621{
622 cpu_abort(env, "cp15 insn %08x\n", insn);
b5ff1b31
FB		 623}
624
9ee6e8bb 625/* These should probably raise undefined insn exceptions. */
8984bd2e 626void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
9ee6e8bb
PB		 627{
628 cpu_abort(env, "v7m_mrs %d\n", reg);
629}
630
8984bd2e 631uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg)
9ee6e8bb
PB		 632{
633 cpu_abort(env, "v7m_mrs %d\n", reg);
634 return 0;
635}
636
b5ff1b31
FB		 637void switch_mode(CPUState *env, int mode)
638{
639 if (mode != ARM_CPU_MODE_USR)
640 cpu_abort(env, "Tried to switch out of user mode\n");
641}
642
b0109805 643void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
9ee6e8bb
PB		 644{
645 cpu_abort(env, "banked r13 write\n");
646}
647
b0109805 648uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode)
9ee6e8bb
PB		 649{
650 cpu_abort(env, "banked r13 read\n");
651 return 0;
652}
653
b5ff1b31
FB		 654#else
655
8e71621f
PB		 656extern int semihosting_enabled;
657
b5ff1b31
FB		 658/* Map CPU modes onto saved register banks. */
659static inline int bank_number (int mode)
660{
661 switch (mode) {
662 case ARM_CPU_MODE_USR:
663 case ARM_CPU_MODE_SYS:
664 return 0;
665 case ARM_CPU_MODE_SVC:
666 return 1;
667 case ARM_CPU_MODE_ABT:
668 return 2;
669 case ARM_CPU_MODE_UND:
670 return 3;
671 case ARM_CPU_MODE_IRQ:
672 return 4;
673 case ARM_CPU_MODE_FIQ:
674 return 5;
675 }
676 cpu_abort(cpu_single_env, "Bad mode %x\n", mode);
677 return -1;
678}
679
680void switch_mode(CPUState *env, int mode)
681{
682 int old_mode;
683 int i;
684
685 old_mode = env->uncached_cpsr & CPSR_M;
686 if (mode == old_mode)
687 return;
688
689 if (old_mode == ARM_CPU_MODE_FIQ) {
690 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 691 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 692 } else if (mode == ARM_CPU_MODE_FIQ) {
693 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 694 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 695 }
696
697 i = bank_number(old_mode);
698 env->banked_r13[i] = env->regs[13];
699 env->banked_r14[i] = env->regs[14];
700 env->banked_spsr[i] = env->spsr;
701
702 i = bank_number(mode);
703 env->regs[13] = env->banked_r13[i];
704 env->regs[14] = env->banked_r14[i];
705 env->spsr = env->banked_spsr[i];
706}
707
9ee6e8bb
PB		 708static void v7m_push(CPUARMState *env, uint32_t val)
709{
710 env->regs[13] -= 4;
711 stl_phys(env->regs[13], val);
712}
713
714static uint32_t v7m_pop(CPUARMState *env)
715{
716 uint32_t val;
717 val = ldl_phys(env->regs[13]);
718 env->regs[13] += 4;
719 return val;
720}
721
722/* Switch to V7M main or process stack pointer. */
723static void switch_v7m_sp(CPUARMState *env, int process)
724{
725 uint32_t tmp;
726 if (env->v7m.current_sp != process) {
727 tmp = env->v7m.other_sp;
728 env->v7m.other_sp = env->regs[13];
729 env->regs[13] = tmp;
730 env->v7m.current_sp = process;
731 }
732}
733
734static void do_v7m_exception_exit(CPUARMState *env)
735{
736 uint32_t type;
737 uint32_t xpsr;
738
739 type = env->regs[15];
740 if (env->v7m.exception != 0)
983fe826 741 armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
9ee6e8bb
PB		 742
743 /* Switch to the target stack. */
744 switch_v7m_sp(env, (type & 4) != 0);
745 /* Pop registers. */
746 env->regs[0] = v7m_pop(env);
747 env->regs[1] = v7m_pop(env);
748 env->regs[2] = v7m_pop(env);
749 env->regs[3] = v7m_pop(env);
750 env->regs[12] = v7m_pop(env);
751 env->regs[14] = v7m_pop(env);
752 env->regs[15] = v7m_pop(env);
753 xpsr = v7m_pop(env);
754 xpsr_write(env, xpsr, 0xfffffdff);
755 /* Undo stack alignment. */
756 if (xpsr & 0x200)
757 env->regs[13] |= 4;
758 /* ??? The exception return type specifies Thread/Handler mode. However
759 this is also implied by the xPSR value. Not sure what to do
760 if there is a mismatch. */
761 /* ??? Likewise for mismatches between the CONTROL register and the stack
762 pointer. */
763}
764
2b3ea315 765static void do_interrupt_v7m(CPUARMState *env)
9ee6e8bb
PB		 766{
767 uint32_t xpsr = xpsr_read(env);
768 uint32_t lr;
769 uint32_t addr;
770
771 lr = 0xfffffff1;
772 if (env->v7m.current_sp)
773 lr |= 4;
774 if (env->v7m.exception == 0)
775 lr |= 8;
776
777 /* For exceptions we just mark as pending on the NVIC, and let that
778 handle it. */
779 /* TODO: Need to escalate if the current priority is higher than the
780 one we're raising. */
781 switch (env->exception_index) {
782 case EXCP_UDEF:
983fe826 783 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
9ee6e8bb
PB		 784 return;
785 case EXCP_SWI:
786 env->regs[15] += 2;
983fe826 787 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
9ee6e8bb
PB		 788 return;
789 case EXCP_PREFETCH_ABORT:
790 case EXCP_DATA_ABORT:
983fe826 791 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
9ee6e8bb
PB		 792 return;
793 case EXCP_BKPT:
2ad207d4
PB		 794 if (semihosting_enabled) {
795 int nr;
796 nr = lduw_code(env->regs[15]) & 0xff;
797 if (nr == 0xab) {
798 env->regs[15] += 2;
799 env->regs[0] = do_arm_semihosting(env);
800 return;
801 }
802 }
983fe826 803 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
9ee6e8bb
PB		 804 return;
805 case EXCP_IRQ:
983fe826 806 env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
9ee6e8bb
PB		 807 break;
808 case EXCP_EXCEPTION_EXIT:
809 do_v7m_exception_exit(env);
810 return;
811 default:
812 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
813 return; /* Never happens. Keep compiler happy. */
814 }
815
816 /* Align stack pointer. */
817 /* ??? Should only do this if Configuration Control Register
818 STACKALIGN bit is set. */
819 if (env->regs[13] & 4) {
ab19b0ec 820 env->regs[13] -= 4;
9ee6e8bb
PB		 821 xpsr |= 0x200;
822 }
6c95676b 823 /* Switch to the handler mode. */
9ee6e8bb
PB		 824 v7m_push(env, xpsr);
825 v7m_push(env, env->regs[15]);
826 v7m_push(env, env->regs[14]);
827 v7m_push(env, env->regs[12]);
828 v7m_push(env, env->regs[3]);
829 v7m_push(env, env->regs[2]);
830 v7m_push(env, env->regs[1]);
831 v7m_push(env, env->regs[0]);
832 switch_v7m_sp(env, 0);
833 env->uncached_cpsr &= ~CPSR_IT;
834 env->regs[14] = lr;
835 addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
836 env->regs[15] = addr & 0xfffffffe;
837 env->thumb = addr & 1;
838}
839
b5ff1b31
FB		 840/* Handle a CPU exception. */
841void do_interrupt(CPUARMState *env)
842{
843 uint32_t addr;
844 uint32_t mask;
845 int new_mode;
846 uint32_t offset;
847
9ee6e8bb
PB		 848 if (IS_M(env)) {
849 do_interrupt_v7m(env);
850 return;
851 }
b5ff1b31
FB		 852 /* TODO: Vectored interrupt controller. */
853 switch (env->exception_index) {
854 case EXCP_UDEF:
855 new_mode = ARM_CPU_MODE_UND;
856 addr = 0x04;
857 mask = CPSR_I;
858 if (env->thumb)
859 offset = 2;
860 else
861 offset = 4;
862 break;
863 case EXCP_SWI:
8e71621f
PB		 864 if (semihosting_enabled) {
865 /* Check for semihosting interrupt. */
866 if (env->thumb) {
867 mask = lduw_code(env->regs[15] - 2) & 0xff;
868 } else {
869 mask = ldl_code(env->regs[15] - 4) & 0xffffff;
870 }
871 /* Only intercept calls from privileged modes, to provide some
872 semblance of security. */
873 if (((mask == 0x123456 && !env->thumb)
874 || (mask == 0xab && env->thumb))
875 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
876 env->regs[0] = do_arm_semihosting(env);
877 return;
878 }
879 }
b5ff1b31
FB		 880 new_mode = ARM_CPU_MODE_SVC;
881 addr = 0x08;
882 mask = CPSR_I;
601d70b9 883 /* The PC already points to the next instruction. */
b5ff1b31
FB		 884 offset = 0;
885 break;
06c949e6 886 case EXCP_BKPT:
9ee6e8bb 887 /* See if this is a semihosting syscall. */
2ad207d4 888 if (env->thumb && semihosting_enabled) {
9ee6e8bb
PB		 889 mask = lduw_code(env->regs[15]) & 0xff;
890 if (mask == 0xab
891 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
892 env->regs[15] += 2;
893 env->regs[0] = do_arm_semihosting(env);
894 return;
895 }
896 }
81c05daf 897 env->cp15.c5_insn = 2;
9ee6e8bb
PB		 898 /* Fall through to prefetch abort. */
899 case EXCP_PREFETCH_ABORT:
b5ff1b31
FB		 900 new_mode = ARM_CPU_MODE_ABT;
901 addr = 0x0c;
902 mask = CPSR_A | CPSR_I;
903 offset = 4;
904 break;
905 case EXCP_DATA_ABORT:
906 new_mode = ARM_CPU_MODE_ABT;
907 addr = 0x10;
908 mask = CPSR_A | CPSR_I;
909 offset = 8;
910 break;
911 case EXCP_IRQ:
912 new_mode = ARM_CPU_MODE_IRQ;
913 addr = 0x18;
914 /* Disable IRQ and imprecise data aborts. */
915 mask = CPSR_A | CPSR_I;
916 offset = 4;
917 break;
918 case EXCP_FIQ:
919 new_mode = ARM_CPU_MODE_FIQ;
920 addr = 0x1c;
921 /* Disable FIQ, IRQ and imprecise data aborts. */
922 mask = CPSR_A | CPSR_I | CPSR_F;
923 offset = 4;
924 break;
925 default:
926 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
927 return; /* Never happens. Keep compiler happy. */
928 }
929 /* High vectors. */
930 if (env->cp15.c1_sys & (1 << 13)) {
931 addr += 0xffff0000;
932 }
933 switch_mode (env, new_mode);
934 env->spsr = cpsr_read(env);
9ee6e8bb
PB		 935 /* Clear IT bits. */
936 env->condexec_bits = 0;
30a8cac1 937 /* Switch to the new mode, and to the correct instruction set. */
6d7e6326 938 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
b5ff1b31 939 env->uncached_cpsr |= mask;
be5e7a76
DES		 940 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
941 * and we should just guard the thumb mode on V4 */
942 if (arm_feature(env, ARM_FEATURE_V4T)) {
943 env->thumb = (env->cp15.c1_sys & (1 << 30)) != 0;
944 }
b5ff1b31
FB		 945 env->regs[14] = env->regs[15] + offset;
946 env->regs[15] = addr;
947 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
948}
949
950/* Check section/page access permissions.
951 Returns the page protection flags, or zero if the access is not
952 permitted. */
953static inline int check_ap(CPUState *env, int ap, int domain, int access_type,
954 int is_user)
955{
9ee6e8bb
PB		 956 int prot_ro;
957
b5ff1b31
FB		 958 if (domain == 3)
959 return PAGE_READ | PAGE_WRITE;
960
9ee6e8bb
PB		 961 if (access_type == 1)
962 prot_ro = 0;
963 else
964 prot_ro = PAGE_READ;
965
b5ff1b31
FB		 966 switch (ap) {
967 case 0:
78600320 968 if (access_type == 1)
b5ff1b31
FB		 969 return 0;
970 switch ((env->cp15.c1_sys >> 8) & 3) {
971 case 1:
972 return is_user ? 0 : PAGE_READ;
973 case 2:
974 return PAGE_READ;
975 default:
976 return 0;
977 }
978 case 1:
979 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
980 case 2:
981 if (is_user)
9ee6e8bb 982 return prot_ro;
b5ff1b31
FB		 983 else
984 return PAGE_READ | PAGE_WRITE;
985 case 3:
986 return PAGE_READ | PAGE_WRITE;
d4934d18 987 case 4: /* Reserved. */
9ee6e8bb
PB		 988 return 0;
989 case 5:
990 return is_user ? 0 : prot_ro;
991 case 6:
992 return prot_ro;
d4934d18 993 case 7:
0ab06d83 994 if (!arm_feature (env, ARM_FEATURE_V6K))
d4934d18
PB		 995 return 0;
996 return prot_ro;
b5ff1b31
FB		 997 default:
998 abort();
999 }
1000}
1001
b2fa1797
PB		 1002static uint32_t get_level1_table_address(CPUState *env, uint32_t address)
1003{
1004 uint32_t table;
1005
1006 if (address & env->cp15.c2_mask)
1007 table = env->cp15.c2_base1 & 0xffffc000;
1008 else
1009 table = env->cp15.c2_base0 & env->cp15.c2_base_mask;
1010
1011 table |= (address >> 18) & 0x3ffc;
1012 return table;
1013}
1014
9ee6e8bb 1015static int get_phys_addr_v5(CPUState *env, uint32_t address, int access_type,
d4c430a8
PB		 1016 int is_user, uint32_t *phys_ptr, int *prot,
1017 target_ulong *page_size)
b5ff1b31
FB		 1018{
1019 int code;
1020 uint32_t table;
1021 uint32_t desc;
1022 int type;
1023 int ap;
1024 int domain;
1025 uint32_t phys_addr;
1026
9ee6e8bb
PB		 1027 /* Pagetable walk. */
1028 /* Lookup l1 descriptor. */
b2fa1797 1029 table = get_level1_table_address(env, address);
9ee6e8bb
PB		 1030 desc = ldl_phys(table);
1031 type = (desc & 3);
1032 domain = (env->cp15.c3 >> ((desc >> 4) & 0x1e)) & 3;
1033 if (type == 0) {
601d70b9 1034 /* Section translation fault. */
9ee6e8bb
PB		 1035 code = 5;
1036 goto do_fault;
1037 }
1038 if (domain == 0 || domain == 2) {
1039 if (type == 2)
1040 code = 9; /* Section domain fault. */
1041 else
1042 code = 11; /* Page domain fault. */
1043 goto do_fault;
1044 }
1045 if (type == 2) {
1046 /* 1Mb section. */
1047 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
1048 ap = (desc >> 10) & 3;
1049 code = 13;
d4c430a8 1050 *page_size = 1024 * 1024;
9ee6e8bb
PB		 1051 } else {
1052 /* Lookup l2 entry. */
1053 if (type == 1) {
1054 /* Coarse pagetable. */
1055 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
1056 } else {
1057 /* Fine pagetable. */
1058 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
1059 }
1060 desc = ldl_phys(table);
1061 switch (desc & 3) {
1062 case 0: /* Page translation fault. */
1063 code = 7;
1064 goto do_fault;
1065 case 1: /* 64k page. */
1066 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
1067 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
d4c430a8 1068 *page_size = 0x10000;
ce819861 1069 break;
9ee6e8bb
PB		 1070 case 2: /* 4k page. */
1071 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1072 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
d4c430a8 1073 *page_size = 0x1000;
ce819861 1074 break;
9ee6e8bb
PB		 1075 case 3: /* 1k page. */
1076 if (type == 1) {
1077 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1078 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1079 } else {
1080 /* Page translation fault. */
1081 code = 7;
1082 goto do_fault;
1083 }
1084 } else {
1085 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
1086 }
1087 ap = (desc >> 4) & 3;
d4c430a8 1088 *page_size = 0x400;
ce819861
PB		 1089 break;
1090 default:
9ee6e8bb
PB		 1091 /* Never happens, but compiler isn't smart enough to tell. */
1092 abort();
ce819861 1093 }
9ee6e8bb
PB		 1094 code = 15;
1095 }
1096 *prot = check_ap(env, ap, domain, access_type, is_user);
1097 if (!*prot) {
1098 /* Access permission fault. */
1099 goto do_fault;
1100 }
3ad493fc 1101 *prot |= PAGE_EXEC;
9ee6e8bb
PB		 1102 *phys_ptr = phys_addr;
1103 return 0;
1104do_fault:
1105 return code | (domain << 4);
1106}
1107
1108static int get_phys_addr_v6(CPUState *env, uint32_t address, int access_type,
d4c430a8
PB		 1109 int is_user, uint32_t *phys_ptr, int *prot,
1110 target_ulong *page_size)
9ee6e8bb
PB		 1111{
1112 int code;
1113 uint32_t table;
1114 uint32_t desc;
1115 uint32_t xn;
1116 int type;
1117 int ap;
1118 int domain;
1119 uint32_t phys_addr;
1120
1121 /* Pagetable walk. */
1122 /* Lookup l1 descriptor. */
b2fa1797 1123 table = get_level1_table_address(env, address);
9ee6e8bb
PB		 1124 desc = ldl_phys(table);
1125 type = (desc & 3);
1126 if (type == 0) {
601d70b9 1127 /* Section translation fault. */
9ee6e8bb
PB		 1128 code = 5;
1129 domain = 0;
1130 goto do_fault;
1131 } else if (type == 2 && (desc & (1 << 18))) {
1132 /* Supersection. */
1133 domain = 0;
b5ff1b31 1134 } else {
9ee6e8bb
PB		 1135 /* Section or page. */
1136 domain = (desc >> 4) & 0x1e;
1137 }
1138 domain = (env->cp15.c3 >> domain) & 3;
1139 if (domain == 0 || domain == 2) {
1140 if (type == 2)
1141 code = 9; /* Section domain fault. */
1142 else
1143 code = 11; /* Page domain fault. */
1144 goto do_fault;
1145 }
1146 if (type == 2) {
1147 if (desc & (1 << 18)) {
1148 /* Supersection. */
1149 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
d4c430a8 1150 *page_size = 0x1000000;
b5ff1b31 1151 } else {
9ee6e8bb
PB		 1152 /* Section. */
1153 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
d4c430a8 1154 *page_size = 0x100000;
b5ff1b31 1155 }
9ee6e8bb
PB		 1156 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
1157 xn = desc & (1 << 4);
1158 code = 13;
1159 } else {
1160 /* Lookup l2 entry. */
1161 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
1162 desc = ldl_phys(table);
1163 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
1164 switch (desc & 3) {
1165 case 0: /* Page translation fault. */
1166 code = 7;
b5ff1b31 1167 goto do_fault;
9ee6e8bb
PB		 1168 case 1: /* 64k page. */
1169 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
1170 xn = desc & (1 << 15);
d4c430a8 1171 *page_size = 0x10000;
9ee6e8bb
PB		 1172 break;
1173 case 2: case 3: /* 4k page. */
1174 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1175 xn = desc & 1;
d4c430a8 1176 *page_size = 0x1000;
9ee6e8bb
PB		 1177 break;
1178 default:
1179 /* Never happens, but compiler isn't smart enough to tell. */
1180 abort();
b5ff1b31 1181 }
9ee6e8bb
PB		 1182 code = 15;
1183 }
c0034328
JR		 1184 if (domain == 3) {
1185 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
1186 } else {
1187 if (xn && access_type == 2)
1188 goto do_fault;
9ee6e8bb 1189
c0034328
JR		 1190 /* The simplified model uses AP[0] as an access control bit. */
1191 if ((env->cp15.c1_sys & (1 << 29)) && (ap & 1) == 0) {
1192 /* Access flag fault. */
1193 code = (code == 15) ? 6 : 3;
1194 goto do_fault;
1195 }
1196 *prot = check_ap(env, ap, domain, access_type, is_user);
1197 if (!*prot) {
1198 /* Access permission fault. */
1199 goto do_fault;
1200 }
1201 if (!xn) {
1202 *prot |= PAGE_EXEC;
1203 }
3ad493fc 1204 }
9ee6e8bb 1205 *phys_ptr = phys_addr;
b5ff1b31
FB		 1206 return 0;
1207do_fault:
1208 return code | (domain << 4);
1209}
1210
9ee6e8bb
PB		 1211static int get_phys_addr_mpu(CPUState *env, uint32_t address, int access_type,
1212 int is_user, uint32_t *phys_ptr, int *prot)
1213{
1214 int n;
1215 uint32_t mask;
1216 uint32_t base;
1217
1218 *phys_ptr = address;
1219 for (n = 7; n >= 0; n--) {
1220 base = env->cp15.c6_region[n];
1221 if ((base & 1) == 0)
1222 continue;
1223 mask = 1 << ((base >> 1) & 0x1f);
1224 /* Keep this shift separate from the above to avoid an
1225 (undefined) << 32. */
1226 mask = (mask << 1) - 1;
1227 if (((base ^ address) & ~mask) == 0)
1228 break;
1229 }
1230 if (n < 0)
1231 return 2;
1232
1233 if (access_type == 2) {
1234 mask = env->cp15.c5_insn;
1235 } else {
1236 mask = env->cp15.c5_data;
1237 }
1238 mask = (mask >> (n * 4)) & 0xf;
1239 switch (mask) {
1240 case 0:
1241 return 1;
1242 case 1:
1243 if (is_user)
1244 return 1;
1245 *prot = PAGE_READ | PAGE_WRITE;
1246 break;
1247 case 2:
1248 *prot = PAGE_READ;
1249 if (!is_user)
1250 *prot |= PAGE_WRITE;
1251 break;
1252 case 3:
1253 *prot = PAGE_READ | PAGE_WRITE;
1254 break;
1255 case 5:
1256 if (is_user)
1257 return 1;
1258 *prot = PAGE_READ;
1259 break;
1260 case 6:
1261 *prot = PAGE_READ;
1262 break;
1263 default:
1264 /* Bad permission. */
1265 return 1;
1266 }
3ad493fc 1267 *prot |= PAGE_EXEC;
9ee6e8bb
PB		 1268 return 0;
1269}
1270
1271static inline int get_phys_addr(CPUState *env, uint32_t address,
1272 int access_type, int is_user,
d4c430a8
PB		 1273 uint32_t *phys_ptr, int *prot,
1274 target_ulong *page_size)
9ee6e8bb
PB		 1275{
1276 /* Fast Context Switch Extension. */
1277 if (address < 0x02000000)
1278 address += env->cp15.c13_fcse;
1279
1280 if ((env->cp15.c1_sys & 1) == 0) {
1281 /* MMU/MPU disabled. */
1282 *phys_ptr = address;
3ad493fc 1283 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
d4c430a8 1284 *page_size = TARGET_PAGE_SIZE;
9ee6e8bb
PB		 1285 return 0;
1286 } else if (arm_feature(env, ARM_FEATURE_MPU)) {
d4c430a8 1287 *page_size = TARGET_PAGE_SIZE;
9ee6e8bb
PB		 1288 return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
1289 prot);
1290 } else if (env->cp15.c1_sys & (1 << 23)) {
1291 return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
d4c430a8 1292 prot, page_size);
9ee6e8bb
PB		 1293 } else {
1294 return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
d4c430a8 1295 prot, page_size);
9ee6e8bb
PB		 1296 }
1297}
1298
b5ff1b31 1299int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address,
97b348e7 1300 int access_type, int mmu_idx)
b5ff1b31
FB		 1301{
1302 uint32_t phys_addr;
d4c430a8 1303 target_ulong page_size;
b5ff1b31 1304 int prot;
6ebbf390 1305 int ret, is_user;
b5ff1b31 1306
6ebbf390 1307 is_user = mmu_idx == MMU_USER_IDX;
d4c430a8
PB		 1308 ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
1309 &page_size);
b5ff1b31
FB		 1310 if (ret == 0) {
1311 /* Map a single [sub]page. */
1312 phys_addr &= ~(uint32_t)0x3ff;
1313 address &= ~(uint32_t)0x3ff;
3ad493fc 1314 tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size);
d4c430a8 1315 return 0;
b5ff1b31
FB		 1316 }
1317
1318 if (access_type == 2) {
1319 env->cp15.c5_insn = ret;
1320 env->cp15.c6_insn = address;
1321 env->exception_index = EXCP_PREFETCH_ABORT;
1322 } else {
1323 env->cp15.c5_data = ret;
9ee6e8bb
PB		 1324 if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6))
1325 env->cp15.c5_data |= (1 << 11);
b5ff1b31
FB		 1326 env->cp15.c6_data = address;
1327 env->exception_index = EXCP_DATA_ABORT;
1328 }
1329 return 1;
1330}
1331
c227f099 1332target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
b5ff1b31
FB		 1333{
1334 uint32_t phys_addr;
d4c430a8 1335 target_ulong page_size;
b5ff1b31
FB		 1336 int prot;
1337 int ret;
1338
d4c430a8 1339 ret = get_phys_addr(env, addr, 0, 0, &phys_addr, &prot, &page_size);
b5ff1b31
FB		 1340
1341 if (ret != 0)
1342 return -1;
1343
1344 return phys_addr;
1345}
1346
8984bd2e 1347void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
c1713132
AZ		 1348{
1349 int cp_num = (insn >> 8) & 0xf;
1350 int cp_info = (insn >> 5) & 7;
1351 int src = (insn >> 16) & 0xf;
1352 int operand = insn & 0xf;
1353
1354 if (env->cp[cp_num].cp_write)
1355 env->cp[cp_num].cp_write(env->cp[cp_num].opaque,
1356 cp_info, src, operand, val);
1357}
1358
8984bd2e 1359uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn)
c1713132
AZ		 1360{
1361 int cp_num = (insn >> 8) & 0xf;
1362 int cp_info = (insn >> 5) & 7;
1363 int dest = (insn >> 16) & 0xf;
1364 int operand = insn & 0xf;
1365
1366 if (env->cp[cp_num].cp_read)
1367 return env->cp[cp_num].cp_read(env->cp[cp_num].opaque,
1368 cp_info, dest, operand);
1369 return 0;
1370}
1371
ce819861
PB		 1372/* Return basic MPU access permission bits. */
1373static uint32_t simple_mpu_ap_bits(uint32_t val)
1374{
1375 uint32_t ret;
1376 uint32_t mask;
1377 int i;
1378 ret = 0;
1379 mask = 3;
1380 for (i = 0; i < 16; i += 2) {
1381 ret |= (val >> i) & mask;
1382 mask <<= 2;
1383 }
1384 return ret;
1385}
1386
1387/* Pad basic MPU access permission bits to extended format. */
1388static uint32_t extended_mpu_ap_bits(uint32_t val)
1389{
1390 uint32_t ret;
1391 uint32_t mask;
1392 int i;
1393 ret = 0;
1394 mask = 3;
1395 for (i = 0; i < 16; i += 2) {
1396 ret |= (val & mask) << i;
1397 mask <<= 2;
1398 }
1399 return ret;
1400}
1401
8984bd2e 1402void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
b5ff1b31 1403{
9ee6e8bb
PB		 1404 int op1;
1405 int op2;
1406 int crm;
b5ff1b31 1407
9ee6e8bb 1408 op1 = (insn >> 21) & 7;
b5ff1b31 1409 op2 = (insn >> 5) & 7;
ce819861 1410 crm = insn & 0xf;
b5ff1b31 1411 switch ((insn >> 16) & 0xf) {
9ee6e8bb 1412 case 0:
9ee6e8bb 1413 /* ID codes. */
610c3c8a
AZ		 1414 if (arm_feature(env, ARM_FEATURE_XSCALE))
1415 break;
c3d2689d
AZ		 1416 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1417 break;
a49ea279
PB		 1418 if (arm_feature(env, ARM_FEATURE_V7)
1419 && op1 == 2 && crm == 0 && op2 == 0) {
1420 env->cp15.c0_cssel = val & 0xf;
1421 break;
1422 }
b5ff1b31
FB		 1423 goto bad_reg;
1424 case 1: /* System configuration. */
c3d2689d
AZ		 1425 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1426 op2 = 0;
b5ff1b31
FB		 1427 switch (op2) {
1428 case 0:
ce819861 1429 if (!arm_feature(env, ARM_FEATURE_XSCALE) || crm == 0)
c1713132 1430 env->cp15.c1_sys = val;
b5ff1b31
FB		 1431 /* ??? Lots of these bits are not implemented. */
1432 /* This may enable/disable the MMU, so do a TLB flush. */
1433 tlb_flush(env, 1);
1434 break;
61cc8701 1435 case 1: /* Auxiliary control register. */
610c3c8a
AZ		 1436 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1437 env->cp15.c1_xscaleauxcr = val;
c1713132 1438 break;
610c3c8a 1439 }
9ee6e8bb
PB		 1440 /* Not implemented. */
1441 break;
b5ff1b31 1442 case 2:
610c3c8a
AZ		 1443 if (arm_feature(env, ARM_FEATURE_XSCALE))
1444 goto bad_reg;
4be27dbb
PB		 1445 if (env->cp15.c1_coproc != val) {
1446 env->cp15.c1_coproc = val;
1447 /* ??? Is this safe when called from within a TB? */
1448 tb_flush(env);
1449 }
c1713132 1450 break;
b5ff1b31
FB		 1451 default:
1452 goto bad_reg;
1453 }
1454 break;
ce819861
PB		 1455 case 2: /* MMU Page table control / MPU cache control. */
1456 if (arm_feature(env, ARM_FEATURE_MPU)) {
1457 switch (op2) {
1458 case 0:
1459 env->cp15.c2_data = val;
1460 break;
1461 case 1:
1462 env->cp15.c2_insn = val;
1463 break;
1464 default:
1465 goto bad_reg;
1466 }
1467 } else {
9ee6e8bb
PB		 1468 switch (op2) {
1469 case 0:
1470 env->cp15.c2_base0 = val;
1471 break;
1472 case 1:
1473 env->cp15.c2_base1 = val;
1474 break;
1475 case 2:
b2fa1797
PB		 1476 val &= 7;
1477 env->cp15.c2_control = val;
9ee6e8bb 1478 env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> val);
b2fa1797 1479 env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> val);
9ee6e8bb
PB		 1480 break;
1481 default:
1482 goto bad_reg;
1483 }
ce819861 1484 }
b5ff1b31 1485 break;
ce819861 1486 case 3: /* MMU Domain access control / MPU write buffer control. */
b5ff1b31 1487 env->cp15.c3 = val;
405ee3ad 1488 tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
b5ff1b31
FB		 1489 break;
1490 case 4: /* Reserved. */
1491 goto bad_reg;
ce819861 1492 case 5: /* MMU Fault status / MPU access permission. */
c3d2689d
AZ		 1493 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1494 op2 = 0;
b5ff1b31
FB		 1495 switch (op2) {
1496 case 0:
ce819861
PB		 1497 if (arm_feature(env, ARM_FEATURE_MPU))
1498 val = extended_mpu_ap_bits(val);
b5ff1b31
FB		 1499 env->cp15.c5_data = val;
1500 break;
1501 case 1:
ce819861
PB		 1502 if (arm_feature(env, ARM_FEATURE_MPU))
1503 val = extended_mpu_ap_bits(val);
b5ff1b31
FB		 1504 env->cp15.c5_insn = val;
1505 break;
ce819861
PB		 1506 case 2:
1507 if (!arm_feature(env, ARM_FEATURE_MPU))
1508 goto bad_reg;
1509 env->cp15.c5_data = val;
b5ff1b31 1510 break;
ce819861
PB		 1511 case 3:
1512 if (!arm_feature(env, ARM_FEATURE_MPU))
1513 goto bad_reg;
1514 env->cp15.c5_insn = val;
b5ff1b31
FB		 1515 break;
1516 default:
1517 goto bad_reg;
1518 }
1519 break;
ce819861
PB		 1520 case 6: /* MMU Fault address / MPU base/size. */
1521 if (arm_feature(env, ARM_FEATURE_MPU)) {
1522 if (crm >= 8)
1523 goto bad_reg;
1524 env->cp15.c6_region[crm] = val;
1525 } else {
c3d2689d
AZ		 1526 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1527 op2 = 0;
ce819861
PB		 1528 switch (op2) {
1529 case 0:
1530 env->cp15.c6_data = val;
1531 break;
9ee6e8bb
PB		 1532 case 1: /* ??? This is WFAR on armv6 */
1533 case 2:
ce819861
PB		 1534 env->cp15.c6_insn = val;
1535 break;
1536 default:
1537 goto bad_reg;
1538 }
1539 }
1540 break;
b5ff1b31 1541 case 7: /* Cache control. */
c3d2689d
AZ		 1542 env->cp15.c15_i_max = 0x000;
1543 env->cp15.c15_i_min = 0xff0;
f8bf8606
AL		 1544 if (op1 != 0) {
1545 goto bad_reg;
1546 }
1547 /* No cache, so nothing to do except VA->PA translations. */
906879a9 1548 if (arm_feature(env, ARM_FEATURE_VAPA)) {
f8bf8606
AL		 1549 switch (crm) {
1550 case 4:
1551 if (arm_feature(env, ARM_FEATURE_V7)) {
1552 env->cp15.c7_par = val & 0xfffff6ff;
1553 } else {
1554 env->cp15.c7_par = val & 0xfffff1ff;
1555 }
1556 break;
1557 case 8: {
1558 uint32_t phys_addr;
1559 target_ulong page_size;
1560 int prot;
1561 int ret, is_user = op2 & 2;
1562 int access_type = op2 & 1;
1563
1564 if (op2 & 4) {
1565 /* Other states are only available with TrustZone */
1566 goto bad_reg;
1567 }
1568 ret = get_phys_addr(env, val, access_type, is_user,
1569 &phys_addr, &prot, &page_size);
1570 if (ret == 0) {
1571 /* We do not set any attribute bits in the PAR */
1572 if (page_size == (1 << 24)
1573 && arm_feature(env, ARM_FEATURE_V7)) {
1574 env->cp15.c7_par = (phys_addr & 0xff000000) | 1 << 1;
1575 } else {
1576 env->cp15.c7_par = phys_addr & 0xfffff000;
1577 }
1578 } else {
1579 env->cp15.c7_par = ((ret & (10 << 1)) >> 5) |
1580 ((ret & (12 << 1)) >> 6) |
1581 ((ret & 0xf) << 1) | 1;
1582 }
1583 break;
1584 }
1585 }
1586 }
b5ff1b31
FB		 1587 break;
1588 case 8: /* MMU TLB control. */
1589 switch (op2) {
1590 case 0: /* Invalidate all. */
1591 tlb_flush(env, 0);
1592 break;
1593 case 1: /* Invalidate single TLB entry. */
d4c430a8 1594 tlb_flush_page(env, val & TARGET_PAGE_MASK);
b5ff1b31 1595 break;
9ee6e8bb
PB		 1596 case 2: /* Invalidate on ASID. */
1597 tlb_flush(env, val == 0);
1598 break;
1599 case 3: /* Invalidate single entry on MVA. */
1600 /* ??? This is like case 1, but ignores ASID. */
1601 tlb_flush(env, 1);
1602 break;
b5ff1b31
FB		 1603 default:
1604 goto bad_reg;
1605 }
1606 break;
ce819861 1607 case 9:
c3d2689d
AZ		 1608 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1609 break;
5bc95aa2
DES		 1610 if (arm_feature(env, ARM_FEATURE_STRONGARM))
1611 break; /* Ignore ReadBuffer access */
ce819861
PB		 1612 switch (crm) {
1613 case 0: /* Cache lockdown. */
9ee6e8bb
PB		 1614 switch (op1) {
1615 case 0: /* L1 cache. */
1616 switch (op2) {
1617 case 0:
1618 env->cp15.c9_data = val;
1619 break;
1620 case 1:
1621 env->cp15.c9_insn = val;
1622 break;
1623 default:
1624 goto bad_reg;
1625 }
1626 break;
1627 case 1: /* L2 cache. */
1628 /* Ignore writes to L2 lockdown/auxiliary registers. */
1629 break;
1630 default:
1631 goto bad_reg;
1632 }
1633 break;
ce819861
PB		 1634 case 1: /* TCM memory region registers. */
1635 /* Not implemented. */
1636 goto bad_reg;
74594c9d
PM		 1637 case 12: /* Performance monitor control */
1638 /* Performance monitors are implementation defined in v7,
1639 * but with an ARM recommended set of registers, which we
1640 * follow (although we don't actually implement any counters)
1641 */
1642 if (!arm_feature(env, ARM_FEATURE_V7)) {
1643 goto bad_reg;
1644 }
1645 switch (op2) {
1646 case 0: /* performance monitor control register */
1647 /* only the DP, X, D and E bits are writable */
1648 env->cp15.c9_pmcr &= ~0x39;
1649 env->cp15.c9_pmcr |= (val & 0x39);
1650 break;
1651 case 1: /* Count enable set register */
1652 val &= (1 << 31);
1653 env->cp15.c9_pmcnten |= val;
1654 break;
1655 case 2: /* Count enable clear */
1656 val &= (1 << 31);
1657 env->cp15.c9_pmcnten &= ~val;
1658 break;
1659 case 3: /* Overflow flag status */
1660 env->cp15.c9_pmovsr &= ~val;
1661 break;
1662 case 4: /* Software increment */
1663 /* RAZ/WI since we don't implement the software-count event */
1664 break;
1665 case 5: /* Event counter selection register */
1666 /* Since we don't implement any events, writing to this register
1667 * is actually UNPREDICTABLE. So we choose to RAZ/WI.
1668 */
1669 break;
1670 default:
1671 goto bad_reg;
1672 }
1673 break;
1674 case 13: /* Performance counters */
1675 if (!arm_feature(env, ARM_FEATURE_V7)) {
1676 goto bad_reg;
1677 }
1678 switch (op2) {
1679 case 0: /* Cycle count register: not implemented, so RAZ/WI */
1680 break;
1681 case 1: /* Event type select */
1682 env->cp15.c9_pmxevtyper = val & 0xff;
1683 break;
1684 case 2: /* Event count register */
1685 /* Unimplemented (we have no events), RAZ/WI */
1686 break;
1687 default:
1688 goto bad_reg;
1689 }
1690 break;
1691 case 14: /* Performance monitor control */
1692 if (!arm_feature(env, ARM_FEATURE_V7)) {
1693 goto bad_reg;
1694 }
1695 switch (op2) {
1696 case 0: /* user enable */
1697 env->cp15.c9_pmuserenr = val & 1;
1698 /* changes access rights for cp registers, so flush tbs */
1699 tb_flush(env);
1700 break;
1701 case 1: /* interrupt enable set */
1702 /* We have no event counters so only the C bit can be changed */
1703 val &= (1 << 31);
1704 env->cp15.c9_pminten |= val;
1705 break;
1706 case 2: /* interrupt enable clear */
1707 val &= (1 << 31);
1708 env->cp15.c9_pminten &= ~val;
1709 break;
1710 }
1711 break;
b5ff1b31
FB		 1712 default:
1713 goto bad_reg;
1714 }
1715 break;
1716 case 10: /* MMU TLB lockdown. */
1717 /* ??? TLB lockdown not implemented. */
1718 break;
b5ff1b31
FB		 1719 case 12: /* Reserved. */
1720 goto bad_reg;
1721 case 13: /* Process ID. */
1722 switch (op2) {
1723 case 0:
d07edbfa
PB		 1724 /* Unlike real hardware the qemu TLB uses virtual addresses,
1725 not modified virtual addresses, so this causes a TLB flush.
1726 */
1727 if (env->cp15.c13_fcse != val)
1728 tlb_flush(env, 1);
1729 env->cp15.c13_fcse = val;
b5ff1b31
FB		 1730 break;
1731 case 1:
d07edbfa 1732 /* This changes the ASID, so do a TLB flush. */
ce819861
PB		 1733 if (env->cp15.c13_context != val
1734 && !arm_feature(env, ARM_FEATURE_MPU))
d07edbfa
PB		 1735 tlb_flush(env, 0);
1736 env->cp15.c13_context = val;
b5ff1b31
FB		 1737 break;
1738 default:
1739 goto bad_reg;
1740 }
1741 break;
1742 case 14: /* Reserved. */
1743 goto bad_reg;
1744 case 15: /* Implementation specific. */
c1713132 1745 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
ce819861 1746 if (op2 == 0 && crm == 1) {
2e23213f
AZ		 1747 if (env->cp15.c15_cpar != (val & 0x3fff)) {
1748 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1749 tb_flush(env);
1750 env->cp15.c15_cpar = val & 0x3fff;
1751 }
c1713132
AZ		 1752 break;
1753 }
1754 goto bad_reg;
1755 }
c3d2689d
AZ		 1756 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1757 switch (crm) {
1758 case 0:
1759 break;
1760 case 1: /* Set TI925T configuration. */
1761 env->cp15.c15_ticonfig = val & 0xe7;
1762 env->cp15.c0_cpuid = (val & (1 << 5)) ? /* OS_TYPE bit */
1763 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
1764 break;
1765 case 2: /* Set I_max. */
1766 env->cp15.c15_i_max = val;
1767 break;
1768 case 3: /* Set I_min. */
1769 env->cp15.c15_i_min = val;
1770 break;
1771 case 4: /* Set thread-ID. */
1772 env->cp15.c15_threadid = val & 0xffff;
1773 break;
1774 case 8: /* Wait-for-interrupt (deprecated). */
1775 cpu_interrupt(env, CPU_INTERRUPT_HALT);
1776 break;
1777 default:
1778 goto bad_reg;
1779 }
1780 }
b5ff1b31
FB		 1781 break;
1782 }
1783 return;
1784bad_reg:
1785 /* ??? For debugging only. Should raise illegal instruction exception. */
9ee6e8bb
PB		 1786 cpu_abort(env, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
1787 (insn >> 16) & 0xf, crm, op1, op2);
b5ff1b31
FB		 1788}
1789
8984bd2e 1790uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
b5ff1b31 1791{
9ee6e8bb
PB		 1792 int op1;
1793 int op2;
1794 int crm;
b5ff1b31 1795
9ee6e8bb 1796 op1 = (insn >> 21) & 7;
b5ff1b31 1797 op2 = (insn >> 5) & 7;
c3d2689d 1798 crm = insn & 0xf;
b5ff1b31
FB		 1799 switch ((insn >> 16) & 0xf) {
1800 case 0: /* ID codes. */
9ee6e8bb
PB		 1801 switch (op1) {
1802 case 0:
1803 switch (crm) {
1804 case 0:
1805 switch (op2) {
1806 case 0: /* Device ID. */
1807 return env->cp15.c0_cpuid;
1808 case 1: /* Cache Type. */
1809 return env->cp15.c0_cachetype;
1810 case 2: /* TCM status. */
1811 return 0;
1812 case 3: /* TLB type register. */
1813 return 0; /* No lockable TLB entries. */
607b4b08
PM		 1814 case 5: /* MPIDR */
1815 /* The MPIDR was standardised in v7; prior to
1816 * this it was implemented only in the 11MPCore.
1817 * For all other pre-v7 cores it does not exist.
1818 */
1819 if (arm_feature(env, ARM_FEATURE_V7) ||
1820 ARM_CPUID(env) == ARM_CPUID_ARM11MPCORE) {
1821 int mpidr = env->cpu_index;
1822 /* We don't support setting cluster ID ([8..11])
1823 * so these bits always RAZ.
1824 */
1825 if (arm_feature(env, ARM_FEATURE_V7MP)) {
1826 mpidr |= (1 << 31);
1827 /* Cores which are uniprocessor (non-coherent)
1828 * but still implement the MP extensions set
1829 * bit 30. (For instance, A9UP.) However we do
1830 * not currently model any of those cores.
1831 */
1832 }
1833 return mpidr;
10055562 1834 }
607b4b08 1835 /* otherwise fall through to the unimplemented-reg case */
9ee6e8bb
PB		 1836 default:
1837 goto bad_reg;
1838 }
1839 case 1:
1840 if (!arm_feature(env, ARM_FEATURE_V6))
1841 goto bad_reg;
1842 return env->cp15.c0_c1[op2];
1843 case 2:
1844 if (!arm_feature(env, ARM_FEATURE_V6))
1845 goto bad_reg;
1846 return env->cp15.c0_c2[op2];
1847 case 3: case 4: case 5: case 6: case 7:
1848 return 0;
1849 default:
1850 goto bad_reg;
1851 }
1852 case 1:
1853 /* These registers aren't documented on arm11 cores. However
1854 Linux looks at them anyway. */
1855 if (!arm_feature(env, ARM_FEATURE_V6))
1856 goto bad_reg;
1857 if (crm != 0)
1858 goto bad_reg;
a49ea279
PB		 1859 if (!arm_feature(env, ARM_FEATURE_V7))
1860 return 0;
1861
1862 switch (op2) {
1863 case 0:
1864 return env->cp15.c0_ccsid[env->cp15.c0_cssel];
1865 case 1:
1866 return env->cp15.c0_clid;
1867 case 7:
1868 return 0;
1869 }
1870 goto bad_reg;
1871 case 2:
1872 if (op2 != 0 || crm != 0)
610c3c8a 1873 goto bad_reg;
a49ea279 1874 return env->cp15.c0_cssel;
9ee6e8bb
PB		 1875 default:
1876 goto bad_reg;
b5ff1b31
FB		 1877 }
1878 case 1: /* System configuration. */
c3d2689d
AZ		 1879 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1880 op2 = 0;
b5ff1b31
FB		 1881 switch (op2) {
1882 case 0: /* Control register. */
1883 return env->cp15.c1_sys;
1884 case 1: /* Auxiliary control register. */
c1713132 1885 if (arm_feature(env, ARM_FEATURE_XSCALE))
610c3c8a 1886 return env->cp15.c1_xscaleauxcr;
9ee6e8bb
PB		 1887 if (!arm_feature(env, ARM_FEATURE_AUXCR))
1888 goto bad_reg;
1889 switch (ARM_CPUID(env)) {
1890 case ARM_CPUID_ARM1026:
1891 return 1;
1892 case ARM_CPUID_ARM1136:
827df9f3 1893 case ARM_CPUID_ARM1136_R2:
7807eed9 1894 case ARM_CPUID_ARM1176:
9ee6e8bb
PB		 1895 return 7;
1896 case ARM_CPUID_ARM11MPCORE:
1897 return 1;
1898 case ARM_CPUID_CORTEXA8:
533d177a 1899 return 2;
10055562
PB		 1900 case ARM_CPUID_CORTEXA9:
1901 return 0;
9ee6e8bb
PB		 1902 default:
1903 goto bad_reg;
1904 }
b5ff1b31 1905 case 2: /* Coprocessor access register. */
610c3c8a
AZ		 1906 if (arm_feature(env, ARM_FEATURE_XSCALE))
1907 goto bad_reg;
b5ff1b31
FB		 1908 return env->cp15.c1_coproc;
1909 default:
1910 goto bad_reg;
1911 }
ce819861
PB		 1912 case 2: /* MMU Page table control / MPU cache control. */
1913 if (arm_feature(env, ARM_FEATURE_MPU)) {
1914 switch (op2) {
1915 case 0:
1916 return env->cp15.c2_data;
1917 break;
1918 case 1:
1919 return env->cp15.c2_insn;
1920 break;
1921 default:
1922 goto bad_reg;
1923 }
1924 } else {
9ee6e8bb
PB		 1925 switch (op2) {
1926 case 0:
1927 return env->cp15.c2_base0;
1928 case 1:
1929 return env->cp15.c2_base1;
1930 case 2:
b2fa1797 1931 return env->cp15.c2_control;
9ee6e8bb
PB		 1932 default:
1933 goto bad_reg;
1934 }
1935 }
ce819861 1936 case 3: /* MMU Domain access control / MPU write buffer control. */
b5ff1b31
FB		 1937 return env->cp15.c3;
1938 case 4: /* Reserved. */
1939 goto bad_reg;
ce819861 1940 case 5: /* MMU Fault status / MPU access permission. */
c3d2689d
AZ		 1941 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1942 op2 = 0;
b5ff1b31
FB		 1943 switch (op2) {
1944 case 0:
ce819861
PB		 1945 if (arm_feature(env, ARM_FEATURE_MPU))
1946 return simple_mpu_ap_bits(env->cp15.c5_data);
b5ff1b31
FB		 1947 return env->cp15.c5_data;
1948 case 1:
ce819861
PB		 1949 if (arm_feature(env, ARM_FEATURE_MPU))
1950 return simple_mpu_ap_bits(env->cp15.c5_data);
1951 return env->cp15.c5_insn;
1952 case 2:
1953 if (!arm_feature(env, ARM_FEATURE_MPU))
1954 goto bad_reg;
1955 return env->cp15.c5_data;
1956 case 3:
1957 if (!arm_feature(env, ARM_FEATURE_MPU))
1958 goto bad_reg;
b5ff1b31
FB		 1959 return env->cp15.c5_insn;
1960 default:
1961 goto bad_reg;
1962 }
9ee6e8bb 1963 case 6: /* MMU Fault address. */
ce819861 1964 if (arm_feature(env, ARM_FEATURE_MPU)) {
9ee6e8bb 1965 if (crm >= 8)
ce819861 1966 goto bad_reg;
9ee6e8bb 1967 return env->cp15.c6_region[crm];
ce819861 1968 } else {
c3d2689d
AZ		 1969 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1970 op2 = 0;
9ee6e8bb
PB		 1971 switch (op2) {
1972 case 0:
1973 return env->cp15.c6_data;
1974 case 1:
1975 if (arm_feature(env, ARM_FEATURE_V6)) {
1976 /* Watchpoint Fault Adrress. */
1977 return 0; /* Not implemented. */
1978 } else {
1979 /* Instruction Fault Adrress. */
1980 /* Arm9 doesn't have an IFAR, but implementing it anyway
1981 shouldn't do any harm. */
1982 return env->cp15.c6_insn;
1983 }
1984 case 2:
1985 if (arm_feature(env, ARM_FEATURE_V6)) {
1986 /* Instruction Fault Adrress. */
1987 return env->cp15.c6_insn;
1988 } else {
1989 goto bad_reg;
1990 }
1991 default:
1992 goto bad_reg;
1993 }
b5ff1b31
FB		 1994 }
1995 case 7: /* Cache control. */
f8bf8606
AL		 1996 if (crm == 4 && op1 == 0 && op2 == 0) {
1997 return env->cp15.c7_par;
1998 }
6fbe23d5
PB		 1999 /* FIXME: Should only clear Z flag if destination is r15. */
2000 env->ZF = 0;
b5ff1b31
FB		 2001 return 0;
2002 case 8: /* MMU TLB control. */
2003 goto bad_reg;
74594c9d
PM		 2004 case 9:
2005 switch (crm) {
2006 case 0: /* Cache lockdown */
2007 switch (op1) {
2008 case 0: /* L1 cache. */
2009 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
2010 return 0;
2011 }
2012 switch (op2) {
2013 case 0:
2014 return env->cp15.c9_data;
2015 case 1:
2016 return env->cp15.c9_insn;
2017 default:
2018 goto bad_reg;
2019 }
2020 case 1: /* L2 cache */
2021 if (crm != 0) {
2022 goto bad_reg;
2023 }
2024 /* L2 Lockdown and Auxiliary control. */
2025 return 0;
2026 default:
2027 goto bad_reg;
2028 }
2029 break;
2030 case 12: /* Performance monitor control */
2031 if (!arm_feature(env, ARM_FEATURE_V7)) {
2032 goto bad_reg;
2033 }
9ee6e8bb 2034 switch (op2) {
74594c9d
PM		 2035 case 0: /* performance monitor control register */
2036 return env->cp15.c9_pmcr;
2037 case 1: /* count enable set */
2038 case 2: /* count enable clear */
2039 return env->cp15.c9_pmcnten;
2040 case 3: /* overflow flag status */
2041 return env->cp15.c9_pmovsr;
2042 case 4: /* software increment */
2043 case 5: /* event counter selection register */
2044 return 0; /* Unimplemented, RAZ/WI */
9ee6e8bb
PB		 2045 default:
2046 goto bad_reg;
2047 }
74594c9d
PM		 2048 case 13: /* Performance counters */
2049 if (!arm_feature(env, ARM_FEATURE_V7)) {
2050 goto bad_reg;
2051 }
2052 switch (op2) {
2053 case 1: /* Event type select */
2054 return env->cp15.c9_pmxevtyper;
2055 case 0: /* Cycle count register */
2056 case 2: /* Event count register */
2057 /* Unimplemented, so RAZ/WI */
2058 return 0;
2059 default:
9ee6e8bb 2060 goto bad_reg;
74594c9d
PM		 2061 }
2062 case 14: /* Performance monitor control */
2063 if (!arm_feature(env, ARM_FEATURE_V7)) {
2064 goto bad_reg;
2065 }
2066 switch (op2) {
2067 case 0: /* user enable */
2068 return env->cp15.c9_pmuserenr;
2069 case 1: /* interrupt enable set */
2070 case 2: /* interrupt enable clear */
2071 return env->cp15.c9_pminten;
2072 default:
2073 goto bad_reg;
2074 }
b5ff1b31
FB		 2075 default:
2076 goto bad_reg;
2077 }
74594c9d 2078 break;
b5ff1b31
FB		 2079 case 10: /* MMU TLB lockdown. */
2080 /* ??? TLB lockdown not implemented. */
2081 return 0;
2082 case 11: /* TCM DMA control. */
2083 case 12: /* Reserved. */
2084 goto bad_reg;
2085 case 13: /* Process ID. */
2086 switch (op2) {
2087 case 0:
2088 return env->cp15.c13_fcse;
2089 case 1:
2090 return env->cp15.c13_context;
2091 default:
2092 goto bad_reg;
2093 }
2094 case 14: /* Reserved. */
2095 goto bad_reg;
2096 case 15: /* Implementation specific. */
c1713132 2097 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
c3d2689d 2098 if (op2 == 0 && crm == 1)
c1713132
AZ		 2099 return env->cp15.c15_cpar;
2100
2101 goto bad_reg;
2102 }
c3d2689d
AZ		 2103 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
2104 switch (crm) {
2105 case 0:
2106 return 0;
2107 case 1: /* Read TI925T configuration. */
2108 return env->cp15.c15_ticonfig;
2109 case 2: /* Read I_max. */
2110 return env->cp15.c15_i_max;
2111 case 3: /* Read I_min. */
2112 return env->cp15.c15_i_min;
2113 case 4: /* Read thread-ID. */
2114 return env->cp15.c15_threadid;
2115 case 8: /* TI925T_status */
2116 return 0;
2117 }
827df9f3
AZ		 2118 /* TODO: Peripheral port remap register:
2119 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt
2120 * controller base address at $rn & ~0xfff and map size of
2121 * 0x200 << ($rn & 0xfff), when MMU is off. */
c3d2689d
AZ		 2122 goto bad_reg;
2123 }
b5ff1b31
FB		 2124 return 0;
2125 }
2126bad_reg:
2127 /* ??? For debugging only. Should raise illegal instruction exception. */
9ee6e8bb
PB		 2128 cpu_abort(env, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
2129 (insn >> 16) & 0xf, crm, op1, op2);
b5ff1b31
FB		 2130 return 0;
2131}
2132
b0109805 2133void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
9ee6e8bb 2134{
39ea3d4e
PM		 2135 if ((env->uncached_cpsr & CPSR_M) == mode) {
2136 env->regs[13] = val;
2137 } else {
2138 env->banked_r13[bank_number(mode)] = val;
2139 }
9ee6e8bb
PB		 2140}
2141
b0109805 2142uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode)
9ee6e8bb 2143{
39ea3d4e
PM		 2144 if ((env->uncached_cpsr & CPSR_M) == mode) {
2145 return env->regs[13];
2146 } else {
2147 return env->banked_r13[bank_number(mode)];
2148 }
9ee6e8bb
PB		 2149}
2150
8984bd2e 2151uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg)
9ee6e8bb
PB		 2152{
2153 switch (reg) {
2154 case 0: /* APSR */
2155 return xpsr_read(env) & 0xf8000000;
2156 case 1: /* IAPSR */
2157 return xpsr_read(env) & 0xf80001ff;
2158 case 2: /* EAPSR */
2159 return xpsr_read(env) & 0xff00fc00;
2160 case 3: /* xPSR */
2161 return xpsr_read(env) & 0xff00fdff;
2162 case 5: /* IPSR */
2163 return xpsr_read(env) & 0x000001ff;
2164 case 6: /* EPSR */
2165 return xpsr_read(env) & 0x0700fc00;
2166 case 7: /* IEPSR */
2167 return xpsr_read(env) & 0x0700edff;
2168 case 8: /* MSP */
2169 return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
2170 case 9: /* PSP */
2171 return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
2172 case 16: /* PRIMASK */
2173 return (env->uncached_cpsr & CPSR_I) != 0;
82845826
SH		 2174 case 17: /* BASEPRI */
2175 case 18: /* BASEPRI_MAX */
9ee6e8bb 2176 return env->v7m.basepri;
82845826
SH		 2177 case 19: /* FAULTMASK */
2178 return (env->uncached_cpsr & CPSR_F) != 0;
9ee6e8bb
PB		 2179 case 20: /* CONTROL */
2180 return env->v7m.control;
2181 default:
2182 /* ??? For debugging only. */
2183 cpu_abort(env, "Unimplemented system register read (%d)\n", reg);
2184 return 0;
2185 }
2186}
2187
8984bd2e 2188void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
9ee6e8bb
PB		 2189{
2190 switch (reg) {
2191 case 0: /* APSR */
2192 xpsr_write(env, val, 0xf8000000);
2193 break;
2194 case 1: /* IAPSR */
2195 xpsr_write(env, val, 0xf8000000);
2196 break;
2197 case 2: /* EAPSR */
2198 xpsr_write(env, val, 0xfe00fc00);
2199 break;
2200 case 3: /* xPSR */
2201 xpsr_write(env, val, 0xfe00fc00);
2202 break;
2203 case 5: /* IPSR */
2204 /* IPSR bits are readonly. */
2205 break;
2206 case 6: /* EPSR */
2207 xpsr_write(env, val, 0x0600fc00);
2208 break;
2209 case 7: /* IEPSR */
2210 xpsr_write(env, val, 0x0600fc00);
2211 break;
2212 case 8: /* MSP */
2213 if (env->v7m.current_sp)
2214 env->v7m.other_sp = val;
2215 else
2216 env->regs[13] = val;
2217 break;
2218 case 9: /* PSP */
2219 if (env->v7m.current_sp)
2220 env->regs[13] = val;
2221 else
2222 env->v7m.other_sp = val;
2223 break;
2224 case 16: /* PRIMASK */
2225 if (val & 1)
2226 env->uncached_cpsr |= CPSR_I;
2227 else
2228 env->uncached_cpsr &= ~CPSR_I;
2229 break;
82845826 2230 case 17: /* BASEPRI */
9ee6e8bb
PB		 2231 env->v7m.basepri = val & 0xff;
2232 break;
82845826 2233 case 18: /* BASEPRI_MAX */
9ee6e8bb
PB		 2234 val &= 0xff;
2235 if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
2236 env->v7m.basepri = val;
2237 break;
82845826
SH		 2238 case 19: /* FAULTMASK */
2239 if (val & 1)
2240 env->uncached_cpsr |= CPSR_F;
2241 else
2242 env->uncached_cpsr &= ~CPSR_F;
2243 break;
9ee6e8bb
PB		 2244 case 20: /* CONTROL */
2245 env->v7m.control = val & 3;
2246 switch_v7m_sp(env, (val & 2) != 0);
2247 break;
2248 default:
2249 /* ??? For debugging only. */
2250 cpu_abort(env, "Unimplemented system register write (%d)\n", reg);
2251 return;
2252 }
2253}
2254
c1713132
AZ		 2255void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
2256 ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
2257 void *opaque)
2258{
2259 if (cpnum < 0 || cpnum > 14) {
2260 cpu_abort(env, "Bad coprocessor number: %i\n", cpnum);
2261 return;
2262 }
2263
2264 env->cp[cpnum].cp_read = cp_read;
2265 env->cp[cpnum].cp_write = cp_write;
2266 env->cp[cpnum].opaque = opaque;
2267}
2268
b5ff1b31 2269#endif
6ddbc6e4
PB		 2270
2271/* Note that signed overflow is undefined in C. The following routines are
2272 careful to use unsigned types where modulo arithmetic is required.
2273 Failure to do so _will_ break on newer gcc. */
2274
2275/* Signed saturating arithmetic. */
2276
1654b2d6 2277/* Perform 16-bit signed saturating addition. */
6ddbc6e4
PB		 2278static inline uint16_t add16_sat(uint16_t a, uint16_t b)
2279{
2280 uint16_t res;
2281
2282 res = a + b;
2283 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
2284 if (a & 0x8000)
2285 res = 0x8000;
2286 else
2287 res = 0x7fff;
2288 }
2289 return res;
2290}
2291
1654b2d6 2292/* Perform 8-bit signed saturating addition. */
6ddbc6e4
PB		 2293static inline uint8_t add8_sat(uint8_t a, uint8_t b)
2294{
2295 uint8_t res;
2296
2297 res = a + b;
2298 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
2299 if (a & 0x80)
2300 res = 0x80;
2301 else
2302 res = 0x7f;
2303 }
2304 return res;
2305}
2306
1654b2d6 2307/* Perform 16-bit signed saturating subtraction. */
6ddbc6e4
PB		 2308static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
2309{
2310 uint16_t res;
2311
2312 res = a - b;
2313 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
2314 if (a & 0x8000)
2315 res = 0x8000;
2316 else
2317 res = 0x7fff;
2318 }
2319 return res;
2320}
2321
1654b2d6 2322/* Perform 8-bit signed saturating subtraction. */
6ddbc6e4
PB		 2323static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
2324{
2325 uint8_t res;
2326
2327 res = a - b;
2328 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
2329 if (a & 0x80)
2330 res = 0x80;
2331 else
2332 res = 0x7f;
2333 }
2334 return res;
2335}
2336
2337#define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2338#define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2339#define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
2340#define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
2341#define PFX q
2342
2343#include "op_addsub.h"
2344
2345/* Unsigned saturating arithmetic. */
460a09c1 2346static inline uint16_t add16_usat(uint16_t a, uint16_t b)
6ddbc6e4
PB		 2347{
2348 uint16_t res;
2349 res = a + b;
2350 if (res < a)
2351 res = 0xffff;
2352 return res;
2353}
2354
460a09c1 2355static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
6ddbc6e4 2356{
4c4fd3f8 2357 if (a > b)
6ddbc6e4
PB		 2358 return a - b;
2359 else
2360 return 0;
2361}
2362
2363static inline uint8_t add8_usat(uint8_t a, uint8_t b)
2364{
2365 uint8_t res;
2366 res = a + b;
2367 if (res < a)
2368 res = 0xff;
2369 return res;
2370}
2371
2372static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
2373{
4c4fd3f8 2374 if (a > b)
6ddbc6e4
PB		 2375 return a - b;
2376 else
2377 return 0;
2378}
2379
2380#define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2381#define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2382#define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
2383#define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
2384#define PFX uq
2385
2386#include "op_addsub.h"
2387
2388/* Signed modulo arithmetic. */
2389#define SARITH16(a, b, n, op) do { \
2390 int32_t sum; \
db6e2e65 2391 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
6ddbc6e4
PB		 2392 RESULT(sum, n, 16); \
2393 if (sum >= 0) \
2394 ge |= 3 << (n * 2); \
2395 } while(0)
2396
2397#define SARITH8(a, b, n, op) do { \
2398 int32_t sum; \
db6e2e65 2399 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
6ddbc6e4
PB		 2400 RESULT(sum, n, 8); \
2401 if (sum >= 0) \
2402 ge |= 1 << n; \
2403 } while(0)
2404
2405
2406#define ADD16(a, b, n) SARITH16(a, b, n, +)
2407#define SUB16(a, b, n) SARITH16(a, b, n, -)
2408#define ADD8(a, b, n) SARITH8(a, b, n, +)
2409#define SUB8(a, b, n) SARITH8(a, b, n, -)
2410#define PFX s
2411#define ARITH_GE
2412
2413#include "op_addsub.h"
2414
2415/* Unsigned modulo arithmetic. */
2416#define ADD16(a, b, n) do { \
2417 uint32_t sum; \
2418 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2419 RESULT(sum, n, 16); \
a87aa10b 2420 if ((sum >> 16) == 1) \
6ddbc6e4
PB		 2421 ge |= 3 << (n * 2); \
2422 } while(0)
2423
2424#define ADD8(a, b, n) do { \
2425 uint32_t sum; \
2426 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2427 RESULT(sum, n, 8); \
a87aa10b
AZ		 2428 if ((sum >> 8) == 1) \
2429 ge |= 1 << n; \
6ddbc6e4
PB		 2430 } while(0)
2431
2432#define SUB16(a, b, n) do { \
2433 uint32_t sum; \
2434 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2435 RESULT(sum, n, 16); \
2436 if ((sum >> 16) == 0) \
2437 ge |= 3 << (n * 2); \
2438 } while(0)
2439
2440#define SUB8(a, b, n) do { \
2441 uint32_t sum; \
2442 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2443 RESULT(sum, n, 8); \
2444 if ((sum >> 8) == 0) \
a87aa10b 2445 ge |= 1 << n; \
6ddbc6e4
PB		 2446 } while(0)
2447
2448#define PFX u
2449#define ARITH_GE
2450
2451#include "op_addsub.h"
2452
2453/* Halved signed arithmetic. */
2454#define ADD16(a, b, n) \
2455 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2456#define SUB16(a, b, n) \
2457 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2458#define ADD8(a, b, n) \
2459 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2460#define SUB8(a, b, n) \
2461 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2462#define PFX sh
2463
2464#include "op_addsub.h"
2465
2466/* Halved unsigned arithmetic. */
2467#define ADD16(a, b, n) \
2468 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2469#define SUB16(a, b, n) \
2470 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2471#define ADD8(a, b, n) \
2472 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2473#define SUB8(a, b, n) \
2474 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2475#define PFX uh
2476
2477#include "op_addsub.h"
2478
2479static inline uint8_t do_usad(uint8_t a, uint8_t b)
2480{
2481 if (a > b)
2482 return a - b;
2483 else
2484 return b - a;
2485}
2486
2487/* Unsigned sum of absolute byte differences. */
2488uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
2489{
2490 uint32_t sum;
2491 sum = do_usad(a, b);
2492 sum += do_usad(a >> 8, b >> 8);
2493 sum += do_usad(a >> 16, b >>16);
2494 sum += do_usad(a >> 24, b >> 24);
2495 return sum;
2496}
2497
2498/* For ARMv6 SEL instruction. */
2499uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
2500{
2501 uint32_t mask;
2502
2503 mask = 0;
2504 if (flags & 1)
2505 mask |= 0xff;
2506 if (flags & 2)
2507 mask |= 0xff00;
2508 if (flags & 4)
2509 mask |= 0xff0000;
2510 if (flags & 8)
2511 mask |= 0xff000000;
2512 return (a & mask) | (b & ~mask);
2513}
2514
5e3f878a
PB		 2515uint32_t HELPER(logicq_cc)(uint64_t val)
2516{
2517 return (val >> 32) | (val != 0);
2518}
4373f3ce
PB		 2519
2520/* VFP support. We follow the convention used for VFP instrunctions:
2521 Single precition routines have a "s" suffix, double precision a
2522 "d" suffix. */
2523
2524/* Convert host exception flags to vfp form. */
2525static inline int vfp_exceptbits_from_host(int host_bits)
2526{
2527 int target_bits = 0;
2528
2529 if (host_bits & float_flag_invalid)
2530 target_bits |= 1;
2531 if (host_bits & float_flag_divbyzero)
2532 target_bits |= 2;
2533 if (host_bits & float_flag_overflow)
2534 target_bits |= 4;
36802b6b 2535 if (host_bits & (float_flag_underflow | float_flag_output_denormal))
4373f3ce
PB		 2536 target_bits |= 8;
2537 if (host_bits & float_flag_inexact)
2538 target_bits |= 0x10;
cecd8504
PM		 2539 if (host_bits & float_flag_input_denormal)
2540 target_bits |= 0x80;
4373f3ce
PB		 2541 return target_bits;
2542}
2543
2544uint32_t HELPER(vfp_get_fpscr)(CPUState *env)
2545{
2546 int i;
2547 uint32_t fpscr;
2548
2549 fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
2550 | (env->vfp.vec_len << 16)
2551 | (env->vfp.vec_stride << 20);
2552 i = get_float_exception_flags(&env->vfp.fp_status);
3a492f3a 2553 i |= get_float_exception_flags(&env->vfp.standard_fp_status);
4373f3ce
PB		 2554 fpscr |= vfp_exceptbits_from_host(i);
2555 return fpscr;
2556}
2557
01653295
PM		 2558uint32_t vfp_get_fpscr(CPUState *env)
2559{
2560 return HELPER(vfp_get_fpscr)(env);
2561}
2562
4373f3ce
PB		 2563/* Convert vfp exception flags to target form. */
2564static inline int vfp_exceptbits_to_host(int target_bits)
2565{
2566 int host_bits = 0;
2567
2568 if (target_bits & 1)
2569 host_bits |= float_flag_invalid;
2570 if (target_bits & 2)
2571 host_bits |= float_flag_divbyzero;
2572 if (target_bits & 4)
2573 host_bits |= float_flag_overflow;
2574 if (target_bits & 8)
2575 host_bits |= float_flag_underflow;
2576 if (target_bits & 0x10)
2577 host_bits |= float_flag_inexact;
cecd8504
PM		 2578 if (target_bits & 0x80)
2579 host_bits |= float_flag_input_denormal;
4373f3ce
PB		 2580 return host_bits;
2581}
2582
2583void HELPER(vfp_set_fpscr)(CPUState *env, uint32_t val)
2584{
2585 int i;
2586 uint32_t changed;
2587
2588 changed = env->vfp.xregs[ARM_VFP_FPSCR];
2589 env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
2590 env->vfp.vec_len = (val >> 16) & 7;
2591 env->vfp.vec_stride = (val >> 20) & 3;
2592
2593 changed ^= val;
2594 if (changed & (3 << 22)) {
2595 i = (val >> 22) & 3;
2596 switch (i) {
2597 case 0:
2598 i = float_round_nearest_even;
2599 break;
2600 case 1:
2601 i = float_round_up;
2602 break;
2603 case 2:
2604 i = float_round_down;
2605 break;
2606 case 3:
2607 i = float_round_to_zero;
2608 break;
2609 }
2610 set_float_rounding_mode(i, &env->vfp.fp_status);
2611 }
cecd8504 2612 if (changed & (1 << 24)) {
fe76d976 2613 set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
cecd8504
PM		 2614 set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
2615 }
5c7908ed
PB		 2616 if (changed & (1 << 25))
2617 set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
4373f3ce 2618
b12c390b 2619 i = vfp_exceptbits_to_host(val);
4373f3ce 2620 set_float_exception_flags(i, &env->vfp.fp_status);
3a492f3a 2621 set_float_exception_flags(0, &env->vfp.standard_fp_status);
4373f3ce
PB		 2622}
2623
01653295
PM		 2624void vfp_set_fpscr(CPUState *env, uint32_t val)
2625{
2626 HELPER(vfp_set_fpscr)(env, val);
2627}
2628
4373f3ce
PB		 2629#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
2630
2631#define VFP_BINOP(name) \
ae1857ec 2632float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
4373f3ce 2633{ \
ae1857ec
PM		 2634 float_status *fpst = fpstp; \
2635 return float32_ ## name(a, b, fpst); \
4373f3ce 2636} \
ae1857ec 2637float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
4373f3ce 2638{ \
ae1857ec
PM		 2639 float_status *fpst = fpstp; \
2640 return float64_ ## name(a, b, fpst); \
4373f3ce
PB		 2641}
2642VFP_BINOP(add)
2643VFP_BINOP(sub)
2644VFP_BINOP(mul)
2645VFP_BINOP(div)
2646#undef VFP_BINOP
2647
2648float32 VFP_HELPER(neg, s)(float32 a)
2649{
2650 return float32_chs(a);
2651}
2652
2653float64 VFP_HELPER(neg, d)(float64 a)
2654{
66230e0d 2655 return float64_chs(a);
4373f3ce
PB		 2656}
2657
2658float32 VFP_HELPER(abs, s)(float32 a)
2659{
2660 return float32_abs(a);
2661}
2662
2663float64 VFP_HELPER(abs, d)(float64 a)
2664{
66230e0d 2665 return float64_abs(a);
4373f3ce
PB		 2666}
2667
2668float32 VFP_HELPER(sqrt, s)(float32 a, CPUState *env)
2669{
2670 return float32_sqrt(a, &env->vfp.fp_status);
2671}
2672
2673float64 VFP_HELPER(sqrt, d)(float64 a, CPUState *env)
2674{
2675 return float64_sqrt(a, &env->vfp.fp_status);
2676}
2677
2678/* XXX: check quiet/signaling case */
2679#define DO_VFP_cmp(p, type) \
2680void VFP_HELPER(cmp, p)(type a, type b, CPUState *env) \
2681{ \
2682 uint32_t flags; \
2683 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
2684 case 0: flags = 0x6; break; \
2685 case -1: flags = 0x8; break; \
2686 case 1: flags = 0x2; break; \
2687 default: case 2: flags = 0x3; break; \
2688 } \
2689 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2690 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2691} \
2692void VFP_HELPER(cmpe, p)(type a, type b, CPUState *env) \
2693{ \
2694 uint32_t flags; \
2695 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
2696 case 0: flags = 0x6; break; \
2697 case -1: flags = 0x8; break; \
2698 case 1: flags = 0x2; break; \
2699 default: case 2: flags = 0x3; break; \
2700 } \
2701 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2702 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2703}
2704DO_VFP_cmp(s, float32)
2705DO_VFP_cmp(d, float64)
2706#undef DO_VFP_cmp
2707
5500b06c 2708/* Integer to float and float to integer conversions */
4373f3ce 2709
5500b06c
PM		 2710#define CONV_ITOF(name, fsz, sign) \
2711 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
2712{ \
2713 float_status *fpst = fpstp; \
2714 return sign##int32_to_##float##fsz(x, fpst); \
4373f3ce
PB		 2715}
2716
5500b06c
PM		 2717#define CONV_FTOI(name, fsz, sign, round) \
2718uint32_t HELPER(name)(float##fsz x, void *fpstp) \
2719{ \
2720 float_status *fpst = fpstp; \
2721 if (float##fsz##_is_any_nan(x)) { \
2722 float_raise(float_flag_invalid, fpst); \
2723 return 0; \
2724 } \
2725 return float##fsz##_to_##sign##int32##round(x, fpst); \
4373f3ce
PB		 2726}
2727
5500b06c
PM		 2728#define FLOAT_CONVS(name, p, fsz, sign) \
2729CONV_ITOF(vfp_##name##to##p, fsz, sign) \
2730CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
2731CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
4373f3ce 2732
5500b06c
PM		 2733FLOAT_CONVS(si, s, 32, )
2734FLOAT_CONVS(si, d, 64, )
2735FLOAT_CONVS(ui, s, 32, u)
2736FLOAT_CONVS(ui, d, 64, u)
4373f3ce 2737
5500b06c
PM		 2738#undef CONV_ITOF
2739#undef CONV_FTOI
2740#undef FLOAT_CONVS
4373f3ce
PB		 2741
2742/* floating point conversion */
2743float64 VFP_HELPER(fcvtd, s)(float32 x, CPUState *env)
2744{
2d627737
PM		 2745 float64 r = float32_to_float64(x, &env->vfp.fp_status);
2746 /* ARM requires that S<->D conversion of any kind of NaN generates
2747 * a quiet NaN by forcing the most significant frac bit to 1.
2748 */
2749 return float64_maybe_silence_nan(r);
4373f3ce
PB		 2750}
2751
2752float32 VFP_HELPER(fcvts, d)(float64 x, CPUState *env)
2753{
2d627737
PM		 2754 float32 r = float64_to_float32(x, &env->vfp.fp_status);
2755 /* ARM requires that S<->D conversion of any kind of NaN generates
2756 * a quiet NaN by forcing the most significant frac bit to 1.
2757 */
2758 return float32_maybe_silence_nan(r);
4373f3ce
PB		 2759}
2760
2761/* VFP3 fixed point conversion. */
622465e1 2762#define VFP_CONV_FIX(name, p, fsz, itype, sign) \
5500b06c
PM		 2763float##fsz HELPER(vfp_##name##to##p)(uint##fsz##_t x, uint32_t shift, \
2764 void *fpstp) \
4373f3ce 2765{ \
5500b06c 2766 float_status *fpst = fpstp; \
622465e1 2767 float##fsz tmp; \
5500b06c
PM		 2768 tmp = sign##int32_to_##float##fsz((itype##_t)x, fpst); \
2769 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
4373f3ce 2770} \
5500b06c
PM		 2771uint##fsz##_t HELPER(vfp_to##name##p)(float##fsz x, uint32_t shift, \
2772 void *fpstp) \
4373f3ce 2773{ \
5500b06c 2774 float_status *fpst = fpstp; \
622465e1
PM		 2775 float##fsz tmp; \
2776 if (float##fsz##_is_any_nan(x)) { \
5500b06c 2777 float_raise(float_flag_invalid, fpst); \
622465e1 2778 return 0; \
09d9487f 2779 } \
5500b06c
PM		 2780 tmp = float##fsz##_scalbn(x, shift, fpst); \
2781 return float##fsz##_to_##itype##_round_to_zero(tmp, fpst); \
622465e1
PM		 2782}
2783
2784VFP_CONV_FIX(sh, d, 64, int16, )
2785VFP_CONV_FIX(sl, d, 64, int32, )
2786VFP_CONV_FIX(uh, d, 64, uint16, u)
2787VFP_CONV_FIX(ul, d, 64, uint32, u)
2788VFP_CONV_FIX(sh, s, 32, int16, )
2789VFP_CONV_FIX(sl, s, 32, int32, )
2790VFP_CONV_FIX(uh, s, 32, uint16, u)
2791VFP_CONV_FIX(ul, s, 32, uint32, u)
4373f3ce
PB		 2792#undef VFP_CONV_FIX
2793
60011498 2794/* Half precision conversions. */
2d981da7 2795static float32 do_fcvt_f16_to_f32(uint32_t a, CPUState *env, float_status *s)
60011498 2796{
60011498 2797 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
fb91678d
PM		 2798 float32 r = float16_to_float32(make_float16(a), ieee, s);
2799 if (ieee) {
2800 return float32_maybe_silence_nan(r);
2801 }
2802 return r;
60011498
PB		 2803}
2804
2d981da7 2805static uint32_t do_fcvt_f32_to_f16(float32 a, CPUState *env, float_status *s)
60011498 2806{
60011498 2807 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
fb91678d
PM		 2808 float16 r = float32_to_float16(a, ieee, s);
2809 if (ieee) {
2810 r = float16_maybe_silence_nan(r);
2811 }
2812 return float16_val(r);
60011498
PB		 2813}
2814
2d981da7
PM		 2815float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUState *env)
2816{
2817 return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
2818}
2819
2820uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUState *env)
2821{
2822 return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
2823}
2824
2825float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUState *env)
2826{
2827 return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
2828}
2829
2830uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUState *env)
2831{
2832 return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
2833}
2834
dda3ec49 2835#define float32_two make_float32(0x40000000)
6aae3df1
PM		 2836#define float32_three make_float32(0x40400000)
2837#define float32_one_point_five make_float32(0x3fc00000)
dda3ec49 2838
4373f3ce
PB		 2839float32 HELPER(recps_f32)(float32 a, float32 b, CPUState *env)
2840{
dda3ec49
PM		 2841 float_status *s = &env->vfp.standard_fp_status;
2842 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
2843 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
43fe9bdb
PM		 2844 if (!(float32_is_zero(a) || float32_is_zero(b))) {
2845 float_raise(float_flag_input_denormal, s);
2846 }
dda3ec49
PM		 2847 return float32_two;
2848 }
2849 return float32_sub(float32_two, float32_mul(a, b, s), s);
4373f3ce
PB		 2850}
2851
2852float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUState *env)
2853{
71826966 2854 float_status *s = &env->vfp.standard_fp_status;
9ea62f57
PM		 2855 float32 product;
2856 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
2857 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
43fe9bdb
PM		 2858 if (!(float32_is_zero(a) || float32_is_zero(b))) {
2859 float_raise(float_flag_input_denormal, s);
2860 }
6aae3df1 2861 return float32_one_point_five;
9ea62f57 2862 }
6aae3df1
PM		 2863 product = float32_mul(a, b, s);
2864 return float32_div(float32_sub(float32_three, product, s), float32_two, s);
4373f3ce
PB		 2865}
2866
8f8e3aa4
PB		 2867/* NEON helpers. */
2868
56bf4fe2
CL		 2869/* Constants 256 and 512 are used in some helpers; we avoid relying on
2870 * int->float conversions at run-time. */
2871#define float64_256 make_float64(0x4070000000000000LL)
2872#define float64_512 make_float64(0x4080000000000000LL)
2873
fe0e4872
CL		 2874/* The algorithm that must be used to calculate the estimate
2875 * is specified by the ARM ARM.
2876 */
2877static float64 recip_estimate(float64 a, CPUState *env)
2878{
1146a817
PM		 2879 /* These calculations mustn't set any fp exception flags,
2880 * so we use a local copy of the fp_status.
2881 */
2882 float_status dummy_status = env->vfp.standard_fp_status;
2883 float_status *s = &dummy_status;
fe0e4872
CL		 2884 /* q = (int)(a * 512.0) */
2885 float64 q = float64_mul(float64_512, a, s);
2886 int64_t q_int = float64_to_int64_round_to_zero(q, s);
2887
2888 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
2889 q = int64_to_float64(q_int, s);
2890 q = float64_add(q, float64_half, s);
2891 q = float64_div(q, float64_512, s);
2892 q = float64_div(float64_one, q, s);
2893
2894 /* s = (int)(256.0 * r + 0.5) */
2895 q = float64_mul(q, float64_256, s);
2896 q = float64_add(q, float64_half, s);
2897 q_int = float64_to_int64_round_to_zero(q, s);
2898
2899 /* return (double)s / 256.0 */
2900 return float64_div(int64_to_float64(q_int, s), float64_256, s);
2901}
2902
4373f3ce
PB		 2903float32 HELPER(recpe_f32)(float32 a, CPUState *env)
2904{
fe0e4872
CL		 2905 float_status *s = &env->vfp.standard_fp_status;
2906 float64 f64;
2907 uint32_t val32 = float32_val(a);
2908
2909 int result_exp;
2910 int a_exp = (val32 & 0x7f800000) >> 23;
2911 int sign = val32 & 0x80000000;
2912
2913 if (float32_is_any_nan(a)) {
2914 if (float32_is_signaling_nan(a)) {
2915 float_raise(float_flag_invalid, s);
2916 }
2917 return float32_default_nan;
2918 } else if (float32_is_infinity(a)) {
2919 return float32_set_sign(float32_zero, float32_is_neg(a));
2920 } else if (float32_is_zero_or_denormal(a)) {
43fe9bdb
PM		 2921 if (!float32_is_zero(a)) {
2922 float_raise(float_flag_input_denormal, s);
2923 }
fe0e4872
CL		 2924 float_raise(float_flag_divbyzero, s);
2925 return float32_set_sign(float32_infinity, float32_is_neg(a));
2926 } else if (a_exp >= 253) {
2927 float_raise(float_flag_underflow, s);
2928 return float32_set_sign(float32_zero, float32_is_neg(a));
2929 }
2930
2931 f64 = make_float64((0x3feULL << 52)
2932 | ((int64_t)(val32 & 0x7fffff) << 29));
2933
2934 result_exp = 253 - a_exp;
2935
2936 f64 = recip_estimate(f64, env);
2937
2938 val32 = sign
2939 | ((result_exp & 0xff) << 23)
2940 | ((float64_val(f64) >> 29) & 0x7fffff);
2941 return make_float32(val32);
4373f3ce
PB		 2942}
2943
e07be5d2
CL		 2944/* The algorithm that must be used to calculate the estimate
2945 * is specified by the ARM ARM.
2946 */
2947static float64 recip_sqrt_estimate(float64 a, CPUState *env)
2948{
1146a817
PM		 2949 /* These calculations mustn't set any fp exception flags,
2950 * so we use a local copy of the fp_status.
2951 */
2952 float_status dummy_status = env->vfp.standard_fp_status;
2953 float_status *s = &dummy_status;
e07be5d2
CL		 2954 float64 q;
2955 int64_t q_int;
2956
2957 if (float64_lt(a, float64_half, s)) {
2958 /* range 0.25 <= a < 0.5 */
2959
2960 /* a in units of 1/512 rounded down */
2961 /* q0 = (int)(a * 512.0); */
2962 q = float64_mul(float64_512, a, s);
2963 q_int = float64_to_int64_round_to_zero(q, s);
2964
2965 /* reciprocal root r */
2966 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
2967 q = int64_to_float64(q_int, s);
2968 q = float64_add(q, float64_half, s);
2969 q = float64_div(q, float64_512, s);
2970 q = float64_sqrt(q, s);
2971 q = float64_div(float64_one, q, s);
2972 } else {
2973 /* range 0.5 <= a < 1.0 */
2974
2975 /* a in units of 1/256 rounded down */
2976 /* q1 = (int)(a * 256.0); */
2977 q = float64_mul(float64_256, a, s);
2978 int64_t q_int = float64_to_int64_round_to_zero(q, s);
2979
2980 /* reciprocal root r */
2981 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
2982 q = int64_to_float64(q_int, s);
2983 q = float64_add(q, float64_half, s);
2984 q = float64_div(q, float64_256, s);
2985 q = float64_sqrt(q, s);
2986 q = float64_div(float64_one, q, s);
2987 }
2988 /* r in units of 1/256 rounded to nearest */
2989 /* s = (int)(256.0 * r + 0.5); */
2990
2991 q = float64_mul(q, float64_256,s );
2992 q = float64_add(q, float64_half, s);
2993 q_int = float64_to_int64_round_to_zero(q, s);
2994
2995 /* return (double)s / 256.0;*/
2996 return float64_div(int64_to_float64(q_int, s), float64_256, s);
2997}
2998
4373f3ce
PB		 2999float32 HELPER(rsqrte_f32)(float32 a, CPUState *env)
3000{
e07be5d2
CL		 3001 float_status *s = &env->vfp.standard_fp_status;
3002 int result_exp;
3003 float64 f64;
3004 uint32_t val;
3005 uint64_t val64;
3006
3007 val = float32_val(a);
3008
3009 if (float32_is_any_nan(a)) {
3010 if (float32_is_signaling_nan(a)) {
3011 float_raise(float_flag_invalid, s);
3012 }
3013 return float32_default_nan;
3014 } else if (float32_is_zero_or_denormal(a)) {
43fe9bdb
PM		 3015 if (!float32_is_zero(a)) {
3016 float_raise(float_flag_input_denormal, s);
3017 }
e07be5d2
CL		 3018 float_raise(float_flag_divbyzero, s);
3019 return float32_set_sign(float32_infinity, float32_is_neg(a));
3020 } else if (float32_is_neg(a)) {
3021 float_raise(float_flag_invalid, s);
3022 return float32_default_nan;
3023 } else if (float32_is_infinity(a)) {
3024 return float32_zero;
3025 }
3026
3027 /* Normalize to a double-precision value between 0.25 and 1.0,
3028 * preserving the parity of the exponent. */
3029 if ((val & 0x800000) == 0) {
3030 f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
3031 | (0x3feULL << 52)
3032 | ((uint64_t)(val & 0x7fffff) << 29));
3033 } else {
3034 f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
3035 | (0x3fdULL << 52)
3036 | ((uint64_t)(val & 0x7fffff) << 29));
3037 }
3038
3039 result_exp = (380 - ((val & 0x7f800000) >> 23)) / 2;
3040
3041 f64 = recip_sqrt_estimate(f64, env);
3042
3043 val64 = float64_val(f64);
3044
26cc6abf 3045 val = ((result_exp & 0xff) << 23)
e07be5d2
CL		 3046 | ((val64 >> 29) & 0x7fffff);
3047 return make_float32(val);
4373f3ce
PB		 3048}
3049
3050uint32_t HELPER(recpe_u32)(uint32_t a, CPUState *env)
3051{
fe0e4872
CL		 3052 float64 f64;
3053
3054 if ((a & 0x80000000) == 0) {
3055 return 0xffffffff;
3056 }
3057
3058 f64 = make_float64((0x3feULL << 52)
3059 | ((int64_t)(a & 0x7fffffff) << 21));
3060
3061 f64 = recip_estimate (f64, env);
3062
3063 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4373f3ce
PB		 3064}
3065
3066uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUState *env)
3067{
e07be5d2
CL		 3068 float64 f64;
3069
3070 if ((a & 0xc0000000) == 0) {
3071 return 0xffffffff;
3072 }
3073
3074 if (a & 0x80000000) {
3075 f64 = make_float64((0x3feULL << 52)
3076 | ((uint64_t)(a & 0x7fffffff) << 21));
3077 } else { /* bits 31-30 == '01' */
3078 f64 = make_float64((0x3fdULL << 52)
3079 | ((uint64_t)(a & 0x3fffffff) << 22));
3080 }
3081
3082 f64 = recip_sqrt_estimate(f64, env);
3083
3084 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4373f3ce 3085}
fe1479c3
PB		 3086
3087void HELPER(set_teecr)(CPUState *env, uint32_t val)
3088{
3089 val &= 1;
3090 if (env->teecr != val) {
3091 env->teecr = val;
3092 tb_flush(env);
3093 }
3094}
Qemu copy for testing