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[qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <string.h>
22#include <inttypes.h>
23
24#include "cpu.h"
25#include "kvm.h"
26
27#include "qemu-option.h"
28#include "qemu-config.h"
29
71ad61d3 30#include "qapi/qapi-visit-core.h"
76b64a7a 31#include "arch_init.h"
71ad61d3 32
28f52cc0
VR		 33#include "hyperv.h"
34
65dee380 35#include "hw/hw.h"
ef8621b1 36#include <linux/kvm_para.h>
65dee380 37
c6dc6f63
AP		 38/* feature flags taken from "Intel Processor Identification and the CPUID
39 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
40 * between feature naming conventions, aliases may be added.
41 */
42static const char *feature_name[] = {
43 "fpu", "vme", "de", "pse",
44 "tsc", "msr", "pae", "mce",
45 "cx8", "apic", NULL, "sep",
46 "mtrr", "pge", "mca", "cmov",
47 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
48 NULL, "ds" /* Intel dts */, "acpi", "mmx",
49 "fxsr", "sse", "sse2", "ss",
50 "ht" /* Intel htt */, "tm", "ia64", "pbe",
51};
52static const char *ext_feature_name[] = {
f370be3c 53 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 54 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 55 "tm2", "ssse3", "cid", NULL,
e117f772 56 "fma", "cx16", "xtpr", "pdcm",
434acb81 57 NULL, "pcid", "dca", "sse4.1|sse4_1",
e117f772 58 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
eaf3f097 59 "tsc-deadline", "aes", "xsave", "osxsave",
e117f772 60 "avx", NULL, NULL, "hypervisor",
c6dc6f63
AP		 61};
62static const char *ext2_feature_name[] = {
63 "fpu", "vme", "de", "pse",
64 "tsc", "msr", "pae", "mce",
65 "cx8" /* AMD CMPXCHG8B */, "apic", NULL, "syscall",
66 "mtrr", "pge", "mca", "cmov",
67 "pat", "pse36", NULL, NULL /* Linux mp */,
3ac8ebfe 68 "nx|xd", NULL, "mmxext", "mmx",
f370be3c 69 "fxsr", "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
3ac8ebfe 70 NULL, "lm|i64", "3dnowext", "3dnow",
c6dc6f63
AP		 71};
72static const char *ext3_feature_name[] = {
73 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
74 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 75 "3dnowprefetch", "osvw", "ibs", "xop",
c6dc6f63 76 "skinit", "wdt", NULL, NULL,
e117f772 77 "fma4", NULL, "cvt16", "nodeid_msr",
c6dc6f63
AP		 78 NULL, NULL, NULL, NULL,
79 NULL, NULL, NULL, NULL,
80 NULL, NULL, NULL, NULL,
81};
82
83static const char *kvm_feature_name[] = {
bfee7546 84 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock", "kvm_asyncpf", NULL, "kvm_pv_eoi", NULL,
c6dc6f63
AP		 85 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
86 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
87 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
88};
89
296acb64
JR		 90static const char *svm_feature_name[] = {
91 "npt", "lbrv", "svm_lock", "nrip_save",
92 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
93 NULL, NULL, "pause_filter", NULL,
94 "pfthreshold", NULL, NULL, NULL,
95 NULL, NULL, NULL, NULL,
96 NULL, NULL, NULL, NULL,
97 NULL, NULL, NULL, NULL,
98 NULL, NULL, NULL, NULL,
99};
100
c6dc6f63
AP		 101/* collects per-function cpuid data
102 */
103typedef struct model_features_t {
104 uint32_t *guest_feat;
105 uint32_t *host_feat;
106 uint32_t check_feat;
107 const char **flag_names;
108 uint32_t cpuid;
109 } model_features_t;
110
111int check_cpuid = 0;
112int enforce_cpuid = 0;
113
bb44e0d1
JK		 114void host_cpuid(uint32_t function, uint32_t count,
115 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a
AP		 116{
117#if defined(CONFIG_KVM)
a1fd24af
AL		 118 uint32_t vec[4];
119
120#ifdef __x86_64__
121 asm volatile("cpuid"
122 : "=a"(vec[0]), "=b"(vec[1]),
123 "=c"(vec[2]), "=d"(vec[3])
124 : "0"(function), "c"(count) : "cc");
125#else
126 asm volatile("pusha \n\t"
127 "cpuid \n\t"
128 "mov %%eax, 0(%2) \n\t"
129 "mov %%ebx, 4(%2) \n\t"
130 "mov %%ecx, 8(%2) \n\t"
131 "mov %%edx, 12(%2) \n\t"
132 "popa"
133 : : "a"(function), "c"(count), "S"(vec)
134 : "memory", "cc");
135#endif
136
bdde476a 137 if (eax)
a1fd24af 138 *eax = vec[0];
bdde476a 139 if (ebx)
a1fd24af 140 *ebx = vec[1];
bdde476a 141 if (ecx)
a1fd24af 142 *ecx = vec[2];
bdde476a 143 if (edx)
a1fd24af 144 *edx = vec[3];
bdde476a
AP		 145#endif
146}
c6dc6f63
AP		 147
148#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
149
150/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
151 * a substring. ex if !NULL points to the first char after a substring,
152 * otherwise the string is assumed to sized by a terminating nul.
153 * Return lexical ordering of *s1:*s2.
154 */
155static int sstrcmp(const char *s1, const char *e1, const char *s2,
156 const char *e2)
157{
158 for (;;) {
159 if (!*s1 || !*s2 || *s1 != *s2)
160 return (*s1 - *s2);
161 ++s1, ++s2;
162 if (s1 == e1 && s2 == e2)
163 return (0);
164 else if (s1 == e1)
165 return (*s2);
166 else if (s2 == e2)
167 return (*s1);
168 }
169}
170
171/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
172 * '|' delimited (possibly empty) strings in which case search for a match
173 * within the alternatives proceeds left to right. Return 0 for success,
174 * non-zero otherwise.
175 */
176static int altcmp(const char *s, const char *e, const char *altstr)
177{
178 const char *p, *q;
179
180 for (q = p = altstr; ; ) {
181 while (*p && *p != '|')
182 ++p;
183 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
184 return (0);
185 if (!*p)
186 return (1);
187 else
188 q = ++p;
189 }
190}
191
192/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 193 * *pval and return true, otherwise return false
c6dc6f63 194 */
e41e0fc6
JK		 195static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
196 const char **featureset)
c6dc6f63
AP		 197{
198 uint32_t mask;
199 const char **ppc;
e41e0fc6 200 bool found = false;
c6dc6f63 201
e41e0fc6 202 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 203 if (*ppc && !altcmp(s, e, *ppc)) {
204 *pval |= mask;
e41e0fc6 205 found = true;
c6dc6f63 206 }
e41e0fc6
JK		 207 }
208 return found;
c6dc6f63
AP		 209}
210
211static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features,
212 uint32_t *ext_features,
213 uint32_t *ext2_features,
214 uint32_t *ext3_features,
296acb64
JR		 215 uint32_t *kvm_features,
216 uint32_t *svm_features)
c6dc6f63
AP		 217{
218 if (!lookup_feature(features, flagname, NULL, feature_name) &&
219 !lookup_feature(ext_features, flagname, NULL, ext_feature_name) &&
220 !lookup_feature(ext2_features, flagname, NULL, ext2_feature_name) &&
221 !lookup_feature(ext3_features, flagname, NULL, ext3_feature_name) &&
296acb64
JR		 222 !lookup_feature(kvm_features, flagname, NULL, kvm_feature_name) &&
223 !lookup_feature(svm_features, flagname, NULL, svm_feature_name))
c6dc6f63
AP		 224 fprintf(stderr, "CPU feature %s not found\n", flagname);
225}
226
227typedef struct x86_def_t {
228 struct x86_def_t *next;
229 const char *name;
230 uint32_t level;
231 uint32_t vendor1, vendor2, vendor3;
232 int family;
233 int model;
234 int stepping;
b862d1fe 235 int tsc_khz;
296acb64
JR		 236 uint32_t features, ext_features, ext2_features, ext3_features;
237 uint32_t kvm_features, svm_features;
c6dc6f63
AP		 238 uint32_t xlevel;
239 char model_id[48];
240 int vendor_override;
241 uint32_t flags;
b3baa152 242 /* Store the results of Centaur's CPUID instructions */
243 uint32_t ext4_features;
244 uint32_t xlevel2;
13526728
EH		 245 /* The feature bits on CPUID[EAX=7,ECX=0].EBX */
246 uint32_t cpuid_7_0_ebx_features;
c6dc6f63
AP		 247} x86_def_t;
248
249#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
250#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
251 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
252#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
253 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
254 CPUID_PSE36 | CPUID_FXSR)
255#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
256#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
257 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
258 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
259 CPUID_PAE | CPUID_SEP | CPUID_APIC)
42673936 260#define EXT2_FEATURE_MASK 0x0183F3FF
c6dc6f63 261
551a2dec
AP		 262#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
263 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
264 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
265 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
266 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
8560efed
AJ		 267 /* partly implemented:
268 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
269 CPUID_PSE36 (needed for Solaris) */
270 /* missing:
271 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
551a2dec 272#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
8713f8ff 273 CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
551a2dec 274 CPUID_EXT_HYPERVISOR)
8560efed
AJ		 275 /* missing:
276 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
8713f8ff 277 CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
551a2dec
AP		 278#define TCG_EXT2_FEATURES ((TCG_FEATURES & EXT2_FEATURE_MASK) | \
279 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
280 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
8560efed
AJ		 281 /* missing:
282 CPUID_EXT2_PDPE1GB */
551a2dec
AP		 283#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
284 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
296acb64 285#define TCG_SVM_FEATURES 0
551a2dec 286
c6dc6f63
AP		 287/* maintains list of cpu model definitions
288 */
289static x86_def_t *x86_defs = {NULL};
290
291/* built-in cpu model definitions (deprecated)
292 */
293static x86_def_t builtin_x86_defs[] = {
c6dc6f63
AP		 294 {
295 .name = "qemu64",
296 .level = 4,
297 .vendor1 = CPUID_VENDOR_AMD_1,
298 .vendor2 = CPUID_VENDOR_AMD_2,
299 .vendor3 = CPUID_VENDOR_AMD_3,
300 .family = 6,
301 .model = 2,
302 .stepping = 3,
303 .features = PPRO_FEATURES |
c6dc6f63 304 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63
AP		 305 CPUID_PSE36,
306 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
42673936 307 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) |
c6dc6f63
AP		 308 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
309 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
310 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
311 .xlevel = 0x8000000A,
c6dc6f63
AP		 312 },
313 {
314 .name = "phenom",
315 .level = 5,
316 .vendor1 = CPUID_VENDOR_AMD_1,
317 .vendor2 = CPUID_VENDOR_AMD_2,
318 .vendor3 = CPUID_VENDOR_AMD_3,
319 .family = 16,
320 .model = 2,
321 .stepping = 3,
c6dc6f63
AP		 322 .features = PPRO_FEATURES |
323 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed 324 CPUID_PSE36 | CPUID_VME | CPUID_HT,
c6dc6f63
AP		 325 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
326 CPUID_EXT_POPCNT,
42673936 327 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) |
c6dc6f63
AP		 328 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
329 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 330 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 331 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
332 CPUID_EXT3_CR8LEG,
333 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
334 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
335 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
336 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
296acb64 337 .svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV,
c6dc6f63
AP		 338 .xlevel = 0x8000001A,
339 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
340 },
341 {
342 .name = "core2duo",
343 .level = 10,
344 .family = 6,
345 .model = 15,
346 .stepping = 11,
c6dc6f63
AP		 347 .features = PPRO_FEATURES |
348 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed
AJ		 349 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
350 CPUID_HT | CPUID_TM | CPUID_PBE,
351 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
352 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
353 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
c6dc6f63
AP		 354 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
355 .ext3_features = CPUID_EXT3_LAHF_LM,
356 .xlevel = 0x80000008,
357 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
358 },
359 {
360 .name = "kvm64",
361 .level = 5,
362 .vendor1 = CPUID_VENDOR_INTEL_1,
363 .vendor2 = CPUID_VENDOR_INTEL_2,
364 .vendor3 = CPUID_VENDOR_INTEL_3,
365 .family = 15,
366 .model = 6,
367 .stepping = 1,
368 /* Missing: CPUID_VME, CPUID_HT */
369 .features = PPRO_FEATURES |
370 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
371 CPUID_PSE36,
372 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
373 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
374 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
42673936 375 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) |
c6dc6f63
AP		 376 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
377 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
378 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
379 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
380 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
381 .ext3_features = 0,
382 .xlevel = 0x80000008,
383 .model_id = "Common KVM processor"
384 },
c6dc6f63
AP		 385 {
386 .name = "qemu32",
387 .level = 4,
388 .family = 6,
389 .model = 3,
390 .stepping = 3,
391 .features = PPRO_FEATURES,
392 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
58012d66 393 .xlevel = 0x80000004,
c6dc6f63 394 },
eafaf1e5
AP		 395 {
396 .name = "kvm32",
397 .level = 5,
398 .family = 15,
399 .model = 6,
400 .stepping = 1,
401 .features = PPRO_FEATURES |
402 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
403 .ext_features = CPUID_EXT_SSE3,
404 .ext2_features = PPRO_FEATURES & EXT2_FEATURE_MASK,
405 .ext3_features = 0,
406 .xlevel = 0x80000008,
407 .model_id = "Common 32-bit KVM processor"
408 },
c6dc6f63
AP		 409 {
410 .name = "coreduo",
411 .level = 10,
412 .family = 6,
413 .model = 14,
414 .stepping = 8,
c6dc6f63 415 .features = PPRO_FEATURES | CPUID_VME |
8560efed
AJ		 416 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
417 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
418 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
419 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
c6dc6f63
AP		 420 .ext2_features = CPUID_EXT2_NX,
421 .xlevel = 0x80000008,
422 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
423 },
424 {
425 .name = "486",
58012d66 426 .level = 1,
c6dc6f63
AP		 427 .family = 4,
428 .model = 0,
429 .stepping = 0,
430 .features = I486_FEATURES,
431 .xlevel = 0,
432 },
433 {
434 .name = "pentium",
435 .level = 1,
436 .family = 5,
437 .model = 4,
438 .stepping = 3,
439 .features = PENTIUM_FEATURES,
440 .xlevel = 0,
441 },
442 {
443 .name = "pentium2",
444 .level = 2,
445 .family = 6,
446 .model = 5,
447 .stepping = 2,
448 .features = PENTIUM2_FEATURES,
449 .xlevel = 0,
450 },
451 {
452 .name = "pentium3",
453 .level = 2,
454 .family = 6,
455 .model = 7,
456 .stepping = 3,
457 .features = PENTIUM3_FEATURES,
458 .xlevel = 0,
459 },
460 {
461 .name = "athlon",
462 .level = 2,
463 .vendor1 = CPUID_VENDOR_AMD_1,
464 .vendor2 = CPUID_VENDOR_AMD_2,
465 .vendor3 = CPUID_VENDOR_AMD_3,
466 .family = 6,
467 .model = 2,
468 .stepping = 3,
469 .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | CPUID_MCA,
42673936 470 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) | CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 471 .xlevel = 0x80000008,
c6dc6f63
AP		 472 },
473 {
474 .name = "n270",
475 /* original is on level 10 */
476 .level = 5,
477 .family = 6,
478 .model = 28,
479 .stepping = 2,
480 .features = PPRO_FEATURES |
8560efed
AJ		 481 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
482 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
c6dc6f63 483 /* Some CPUs got no CPUID_SEP */
8560efed
AJ		 484 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
485 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
42673936 486 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) | CPUID_EXT2_NX,
8560efed 487 .ext3_features = CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 488 .xlevel = 0x8000000A,
489 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
490 },
491};
492
493static int cpu_x86_fill_model_id(char *str)
494{
495 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
496 int i;
497
498 for (i = 0; i < 3; i++) {
499 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
500 memcpy(str + i * 16 + 0, &eax, 4);
501 memcpy(str + i * 16 + 4, &ebx, 4);
502 memcpy(str + i * 16 + 8, &ecx, 4);
503 memcpy(str + i * 16 + 12, &edx, 4);
504 }
505 return 0;
506}
507
508static int cpu_x86_fill_host(x86_def_t *x86_cpu_def)
509{
510 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
511
512 x86_cpu_def->name = "host";
513 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
514 x86_cpu_def->level = eax;
515 x86_cpu_def->vendor1 = ebx;
516 x86_cpu_def->vendor2 = edx;
517 x86_cpu_def->vendor3 = ecx;
518
519 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
520 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
521 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
522 x86_cpu_def->stepping = eax & 0x0F;
523 x86_cpu_def->ext_features = ecx;
524 x86_cpu_def->features = edx;
525
13526728
EH		 526 if (kvm_enabled() && x86_cpu_def->level >= 7) {
527 x86_cpu_def->cpuid_7_0_ebx_features = kvm_arch_get_supported_cpuid(kvm_state, 0x7, 0, R_EBX);
528 } else {
529 x86_cpu_def->cpuid_7_0_ebx_features = 0;
530 }
531
c6dc6f63
AP		 532 host_cpuid(0x80000000, 0, &eax, &ebx, &ecx, &edx);
533 x86_cpu_def->xlevel = eax;
534
535 host_cpuid(0x80000001, 0, &eax, &ebx, &ecx, &edx);
536 x86_cpu_def->ext2_features = edx;
537 x86_cpu_def->ext3_features = ecx;
538 cpu_x86_fill_model_id(x86_cpu_def->model_id);
539 x86_cpu_def->vendor_override = 0;
540
b3baa152 541 /* Call Centaur's CPUID instruction. */
542 if (x86_cpu_def->vendor1 == CPUID_VENDOR_VIA_1 &&
543 x86_cpu_def->vendor2 == CPUID_VENDOR_VIA_2 &&
544 x86_cpu_def->vendor3 == CPUID_VENDOR_VIA_3) {
545 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
546 if (eax >= 0xC0000001) {
547 /* Support VIA max extended level */
548 x86_cpu_def->xlevel2 = eax;
549 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
550 x86_cpu_def->ext4_features = edx;
551 }
552 }
296acb64
JR		 553
554 /*
555 * Every SVM feature requires emulation support in KVM - so we can't just
556 * read the host features here. KVM might even support SVM features not
557 * available on the host hardware. Just set all bits and mask out the
558 * unsupported ones later.
559 */
560 x86_cpu_def->svm_features = -1;
561
c6dc6f63
AP		 562 return 0;
563}
564
565static int unavailable_host_feature(struct model_features_t *f, uint32_t mask)
566{
567 int i;
568
569 for (i = 0; i < 32; ++i)
570 if (1 << i & mask) {
571 fprintf(stderr, "warning: host cpuid %04x_%04x lacks requested"
572 " flag '%s' [0x%08x]\n",
573 f->cpuid >> 16, f->cpuid & 0xffff,
574 f->flag_names[i] ? f->flag_names[i] : "[reserved]", mask);
575 break;
576 }
577 return 0;
578}
579
580/* best effort attempt to inform user requested cpu flags aren't making
581 * their way to the guest. Note: ft[].check_feat ideally should be
582 * specified via a guest_def field to suppress report of extraneous flags.
583 */
584static int check_features_against_host(x86_def_t *guest_def)
585{
586 x86_def_t host_def;
587 uint32_t mask;
588 int rv, i;
589 struct model_features_t ft[] = {
590 {&guest_def->features, &host_def.features,
591 ~0, feature_name, 0x00000000},
592 {&guest_def->ext_features, &host_def.ext_features,
593 ~CPUID_EXT_HYPERVISOR, ext_feature_name, 0x00000001},
594 {&guest_def->ext2_features, &host_def.ext2_features,
595 ~PPRO_FEATURES, ext2_feature_name, 0x80000000},
596 {&guest_def->ext3_features, &host_def.ext3_features,
597 ~CPUID_EXT3_SVM, ext3_feature_name, 0x80000001}};
598
599 cpu_x86_fill_host(&host_def);
66fe09ee 600 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i)
c6dc6f63
AP		 601 for (mask = 1; mask; mask <<= 1)
602 if (ft[i].check_feat & mask && *ft[i].guest_feat & mask &&
603 !(*ft[i].host_feat & mask)) {
604 unavailable_host_feature(&ft[i], mask);
605 rv = 1;
606 }
607 return rv;
608}
609
95b8519d
AF		 610static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
611 const char *name, Error **errp)
612{
613 X86CPU *cpu = X86_CPU(obj);
614 CPUX86State *env = &cpu->env;
615 int64_t value;
616
617 value = (env->cpuid_version >> 8) & 0xf;
618 if (value == 0xf) {
619 value += (env->cpuid_version >> 20) & 0xff;
620 }
621 visit_type_int(v, &value, name, errp);
622}
623
71ad61d3
AF		 624static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
625 const char *name, Error **errp)
ed5e1ec3 626{
71ad61d3
AF		 627 X86CPU *cpu = X86_CPU(obj);
628 CPUX86State *env = &cpu->env;
629 const int64_t min = 0;
630 const int64_t max = 0xff + 0xf;
631 int64_t value;
632
633 visit_type_int(v, &value, name, errp);
634 if (error_is_set(errp)) {
635 return;
636 }
637 if (value < min || value > max) {
638 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
639 name ? name : "null", value, min, max);
640 return;
641 }
642
ed5e1ec3 643 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 644 if (value > 0x0f) {
645 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 646 } else {
71ad61d3 647 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 648 }
649}
650
67e30c83
AF		 651static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
652 const char *name, Error **errp)
653{
654 X86CPU *cpu = X86_CPU(obj);
655 CPUX86State *env = &cpu->env;
656 int64_t value;
657
658 value = (env->cpuid_version >> 4) & 0xf;
659 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
660 visit_type_int(v, &value, name, errp);
661}
662
c5291a4f
AF		 663static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
664 const char *name, Error **errp)
b0704cbd 665{
c5291a4f
AF		 666 X86CPU *cpu = X86_CPU(obj);
667 CPUX86State *env = &cpu->env;
668 const int64_t min = 0;
669 const int64_t max = 0xff;
670 int64_t value;
671
672 visit_type_int(v, &value, name, errp);
673 if (error_is_set(errp)) {
674 return;
675 }
676 if (value < min || value > max) {
677 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
678 name ? name : "null", value, min, max);
679 return;
680 }
681
b0704cbd 682 env->cpuid_version &= ~0xf00f0;
c5291a4f 683 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 684}
685
35112e41
AF		 686static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
687 void *opaque, const char *name,
688 Error **errp)
689{
690 X86CPU *cpu = X86_CPU(obj);
691 CPUX86State *env = &cpu->env;
692 int64_t value;
693
694 value = env->cpuid_version & 0xf;
695 visit_type_int(v, &value, name, errp);
696}
697
036e2222
AF		 698static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
699 void *opaque, const char *name,
700 Error **errp)
38c3dc46 701{
036e2222
AF		 702 X86CPU *cpu = X86_CPU(obj);
703 CPUX86State *env = &cpu->env;
704 const int64_t min = 0;
705 const int64_t max = 0xf;
706 int64_t value;
707
708 visit_type_int(v, &value, name, errp);
709 if (error_is_set(errp)) {
710 return;
711 }
712 if (value < min || value > max) {
713 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
714 name ? name : "null", value, min, max);
715 return;
716 }
717
38c3dc46 718 env->cpuid_version &= ~0xf;
036e2222 719 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 720}
721
8e1898bf
AF		 722static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
723 const char *name, Error **errp)
724{
725 X86CPU *cpu = X86_CPU(obj);
8e1898bf 726
fa029887 727 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 728}
729
730static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
731 const char *name, Error **errp)
732{
733 X86CPU *cpu = X86_CPU(obj);
8e1898bf 734
fa029887 735 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 736}
737
16b93aa8
AF		 738static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
739 const char *name, Error **errp)
740{
741 X86CPU *cpu = X86_CPU(obj);
16b93aa8 742
fa029887 743 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 744}
745
746static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
747 const char *name, Error **errp)
748{
749 X86CPU *cpu = X86_CPU(obj);
16b93aa8 750
fa029887 751 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 752}
753
d480e1af
AF		 754static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
755{
756 X86CPU *cpu = X86_CPU(obj);
757 CPUX86State *env = &cpu->env;
758 char *value;
759 int i;
760
761 value = (char *)g_malloc(12 + 1);
762 for (i = 0; i < 4; i++) {
763 value[i ] = env->cpuid_vendor1 >> (8 * i);
764 value[i + 4] = env->cpuid_vendor2 >> (8 * i);
765 value[i + 8] = env->cpuid_vendor3 >> (8 * i);
766 }
767 value[12] = '\0';
768 return value;
769}
770
771static void x86_cpuid_set_vendor(Object *obj, const char *value,
772 Error **errp)
773{
774 X86CPU *cpu = X86_CPU(obj);
775 CPUX86State *env = &cpu->env;
776 int i;
777
778 if (strlen(value) != 12) {
779 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
780 "vendor", value);
781 return;
782 }
783
784 env->cpuid_vendor1 = 0;
785 env->cpuid_vendor2 = 0;
786 env->cpuid_vendor3 = 0;
787 for (i = 0; i < 4; i++) {
788 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
789 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
790 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
791 }
792 env->cpuid_vendor_override = 1;
793}
794
63e886eb
AF		 795static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
796{
797 X86CPU *cpu = X86_CPU(obj);
798 CPUX86State *env = &cpu->env;
799 char *value;
800 int i;
801
802 value = g_malloc(48 + 1);
803 for (i = 0; i < 48; i++) {
804 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
805 }
806 value[48] = '\0';
807 return value;
808}
809
938d4c25
AF		 810static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
811 Error **errp)
dcce6675 812{
938d4c25
AF		 813 X86CPU *cpu = X86_CPU(obj);
814 CPUX86State *env = &cpu->env;
dcce6675
AF		 815 int c, len, i;
816
817 if (model_id == NULL) {
818 model_id = "";
819 }
820 len = strlen(model_id);
d0a6acf4 821 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 822 for (i = 0; i < 48; i++) {
823 if (i >= len) {
824 c = '\0';
825 } else {
826 c = (uint8_t)model_id[i];
827 }
828 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
829 }
830}
831
89e48965
AF		 832static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
833 const char *name, Error **errp)
834{
835 X86CPU *cpu = X86_CPU(obj);
836 int64_t value;
837
838 value = cpu->env.tsc_khz * 1000;
839 visit_type_int(v, &value, name, errp);
840}
841
842static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
843 const char *name, Error **errp)
844{
845 X86CPU *cpu = X86_CPU(obj);
846 const int64_t min = 0;
847 const int64_t max = INT_MAX;
848 int64_t value;
849
850 visit_type_int(v, &value, name, errp);
851 if (error_is_set(errp)) {
852 return;
853 }
854 if (value < min || value > max) {
855 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
856 name ? name : "null", value, min, max);
857 return;
858 }
859
860 cpu->env.tsc_khz = value / 1000;
861}
862
c6dc6f63
AP		 863static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *cpu_model)
864{
865 unsigned int i;
866 x86_def_t *def;
867
d3c481b3 868 char *s = g_strdup(cpu_model);
c6dc6f63 869 char *featurestr, *name = strtok(s, ",");
296acb64
JR		 870 /* Features to be added*/
871 uint32_t plus_features = 0, plus_ext_features = 0;
872 uint32_t plus_ext2_features = 0, plus_ext3_features = 0;
873 uint32_t plus_kvm_features = 0, plus_svm_features = 0;
874 /* Features to be removed */
875 uint32_t minus_features = 0, minus_ext_features = 0;
876 uint32_t minus_ext2_features = 0, minus_ext3_features = 0;
877 uint32_t minus_kvm_features = 0, minus_svm_features = 0;
c6dc6f63
AP		 878 uint32_t numvalue;
879
880 for (def = x86_defs; def; def = def->next)
04c5b17a 881 if (name && !strcmp(name, def->name))
c6dc6f63 882 break;
04c5b17a 883 if (kvm_enabled() && name && strcmp(name, "host") == 0) {
c6dc6f63
AP		 884 cpu_x86_fill_host(x86_cpu_def);
885 } else if (!def) {
886 goto error;
887 } else {
888 memcpy(x86_cpu_def, def, sizeof(*def));
889 }
890
ef8621b1
AL		 891#if defined(CONFIG_KVM)
892 plus_kvm_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
893 (1 << KVM_FEATURE_NOP_IO_DELAY) |
894 (1 << KVM_FEATURE_MMU_OP) |
895 (1 << KVM_FEATURE_CLOCKSOURCE2) |
896 (1 << KVM_FEATURE_ASYNC_PF) |
897 (1 << KVM_FEATURE_STEAL_TIME) |
898 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
899#else
900 plus_kvm_features = 0;
901#endif
c6dc6f63
AP		 902
903 add_flagname_to_bitmaps("hypervisor", &plus_features,
904 &plus_ext_features, &plus_ext2_features, &plus_ext3_features,
296acb64 905 &plus_kvm_features, &plus_svm_features);
c6dc6f63
AP		 906
907 featurestr = strtok(NULL, ",");
908
909 while (featurestr) {
910 char *val;
911 if (featurestr[0] == '+') {
296acb64
JR		 912 add_flagname_to_bitmaps(featurestr + 1, &plus_features,
913 &plus_ext_features, &plus_ext2_features,
914 &plus_ext3_features, &plus_kvm_features,
915 &plus_svm_features);
c6dc6f63 916 } else if (featurestr[0] == '-') {
296acb64
JR		 917 add_flagname_to_bitmaps(featurestr + 1, &minus_features,
918 &minus_ext_features, &minus_ext2_features,
919 &minus_ext3_features, &minus_kvm_features,
920 &minus_svm_features);
c6dc6f63
AP		 921 } else if ((val = strchr(featurestr, '='))) {
922 *val = 0; val++;
923 if (!strcmp(featurestr, "family")) {
924 char *err;
925 numvalue = strtoul(val, &err, 0);
a88a677f 926 if (!*val || *err || numvalue > 0xff + 0xf) {
c6dc6f63
AP		 927 fprintf(stderr, "bad numerical value %s\n", val);
928 goto error;
929 }
930 x86_cpu_def->family = numvalue;
931 } else if (!strcmp(featurestr, "model")) {
932 char *err;
933 numvalue = strtoul(val, &err, 0);
934 if (!*val || *err || numvalue > 0xff) {
935 fprintf(stderr, "bad numerical value %s\n", val);
936 goto error;
937 }
938 x86_cpu_def->model = numvalue;
939 } else if (!strcmp(featurestr, "stepping")) {
940 char *err;
941 numvalue = strtoul(val, &err, 0);
942 if (!*val || *err || numvalue > 0xf) {
943 fprintf(stderr, "bad numerical value %s\n", val);
944 goto error;
945 }
946 x86_cpu_def->stepping = numvalue ;
947 } else if (!strcmp(featurestr, "level")) {
948 char *err;
949 numvalue = strtoul(val, &err, 0);
950 if (!*val || *err) {
951 fprintf(stderr, "bad numerical value %s\n", val);
952 goto error;
953 }
954 x86_cpu_def->level = numvalue;
955 } else if (!strcmp(featurestr, "xlevel")) {
956 char *err;
957 numvalue = strtoul(val, &err, 0);
958 if (!*val || *err) {
959 fprintf(stderr, "bad numerical value %s\n", val);
960 goto error;
961 }
962 if (numvalue < 0x80000000) {
2f7a21c4 963 numvalue += 0x80000000;
c6dc6f63
AP		 964 }
965 x86_cpu_def->xlevel = numvalue;
966 } else if (!strcmp(featurestr, "vendor")) {
967 if (strlen(val) != 12) {
968 fprintf(stderr, "vendor string must be 12 chars long\n");
969 goto error;
970 }
971 x86_cpu_def->vendor1 = 0;
972 x86_cpu_def->vendor2 = 0;
973 x86_cpu_def->vendor3 = 0;
974 for(i = 0; i < 4; i++) {
975 x86_cpu_def->vendor1 |= ((uint8_t)val[i ]) << (8 * i);
976 x86_cpu_def->vendor2 |= ((uint8_t)val[i + 4]) << (8 * i);
977 x86_cpu_def->vendor3 |= ((uint8_t)val[i + 8]) << (8 * i);
978 }
979 x86_cpu_def->vendor_override = 1;
980 } else if (!strcmp(featurestr, "model_id")) {
981 pstrcpy(x86_cpu_def->model_id, sizeof(x86_cpu_def->model_id),
982 val);
b862d1fe
JR		 983 } else if (!strcmp(featurestr, "tsc_freq")) {
984 int64_t tsc_freq;
985 char *err;
986
987 tsc_freq = strtosz_suffix_unit(val, &err,
988 STRTOSZ_DEFSUFFIX_B, 1000);
45009a30 989 if (tsc_freq < 0 || *err) {
b862d1fe
JR		 990 fprintf(stderr, "bad numerical value %s\n", val);
991 goto error;
992 }
993 x86_cpu_def->tsc_khz = tsc_freq / 1000;
28f52cc0
VR		 994 } else if (!strcmp(featurestr, "hv_spinlocks")) {
995 char *err;
996 numvalue = strtoul(val, &err, 0);
997 if (!*val || *err) {
998 fprintf(stderr, "bad numerical value %s\n", val);
999 goto error;
1000 }
1001 hyperv_set_spinlock_retries(numvalue);
c6dc6f63
AP		 1002 } else {
1003 fprintf(stderr, "unrecognized feature %s\n", featurestr);
1004 goto error;
1005 }
1006 } else if (!strcmp(featurestr, "check")) {
1007 check_cpuid = 1;
1008 } else if (!strcmp(featurestr, "enforce")) {
1009 check_cpuid = enforce_cpuid = 1;
28f52cc0
VR		 1010 } else if (!strcmp(featurestr, "hv_relaxed")) {
1011 hyperv_enable_relaxed_timing(true);
1012 } else if (!strcmp(featurestr, "hv_vapic")) {
1013 hyperv_enable_vapic_recommended(true);
c6dc6f63
AP		 1014 } else {
1015 fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
1016 goto error;
1017 }
1018 featurestr = strtok(NULL, ",");
1019 }
1020 x86_cpu_def->features |= plus_features;
1021 x86_cpu_def->ext_features |= plus_ext_features;
1022 x86_cpu_def->ext2_features |= plus_ext2_features;
1023 x86_cpu_def->ext3_features |= plus_ext3_features;
1024 x86_cpu_def->kvm_features |= plus_kvm_features;
296acb64 1025 x86_cpu_def->svm_features |= plus_svm_features;
c6dc6f63
AP		 1026 x86_cpu_def->features &= ~minus_features;
1027 x86_cpu_def->ext_features &= ~minus_ext_features;
1028 x86_cpu_def->ext2_features &= ~minus_ext2_features;
1029 x86_cpu_def->ext3_features &= ~minus_ext3_features;
1030 x86_cpu_def->kvm_features &= ~minus_kvm_features;
296acb64 1031 x86_cpu_def->svm_features &= ~minus_svm_features;
c6dc6f63
AP		 1032 if (check_cpuid) {
1033 if (check_features_against_host(x86_cpu_def) && enforce_cpuid)
1034 goto error;
1035 }
d3c481b3 1036 g_free(s);
c6dc6f63
AP		 1037 return 0;
1038
1039error:
d3c481b3 1040 g_free(s);
c6dc6f63
AP		 1041 return -1;
1042}
1043
1044/* generate a composite string into buf of all cpuid names in featureset
1045 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1046 * if flags, suppress names undefined in featureset.
1047 */
1048static void listflags(char *buf, int bufsize, uint32_t fbits,
1049 const char **featureset, uint32_t flags)
1050{
1051 const char **p = &featureset[31];
1052 char *q, *b, bit;
1053 int nc;
1054
1055 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1056 *buf = '\0';
1057 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1058 if (fbits & 1 << bit && (*p || !flags)) {
1059 if (*p)
1060 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1061 else
1062 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1063 if (bufsize <= nc) {
1064 if (b) {
1065 memcpy(b, "...", sizeof("..."));
1066 }
1067 return;
1068 }
1069 q += nc;
1070 bufsize -= nc;
1071 }
1072}
1073
1074/* generate CPU information:
1075 * -? list model names
1076 * -?model list model names/IDs
1077 * -?dump output all model (x86_def_t) data
1078 * -?cpuid list all recognized cpuid flag names
1079 */
9a78eead 1080void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf, const char *optarg)
c6dc6f63
AP		 1081{
1082 unsigned char model = !strcmp("?model", optarg);
1083 unsigned char dump = !strcmp("?dump", optarg);
1084 unsigned char cpuid = !strcmp("?cpuid", optarg);
1085 x86_def_t *def;
1086 char buf[256];
1087
1088 if (cpuid) {
1089 (*cpu_fprintf)(f, "Recognized CPUID flags:\n");
1090 listflags(buf, sizeof (buf), (uint32_t)~0, feature_name, 1);
1091 (*cpu_fprintf)(f, " f_edx: %s\n", buf);
1092 listflags(buf, sizeof (buf), (uint32_t)~0, ext_feature_name, 1);
1093 (*cpu_fprintf)(f, " f_ecx: %s\n", buf);
1094 listflags(buf, sizeof (buf), (uint32_t)~0, ext2_feature_name, 1);
1095 (*cpu_fprintf)(f, " extf_edx: %s\n", buf);
1096 listflags(buf, sizeof (buf), (uint32_t)~0, ext3_feature_name, 1);
1097 (*cpu_fprintf)(f, " extf_ecx: %s\n", buf);
1098 return;
1099 }
1100 for (def = x86_defs; def; def = def->next) {
1101 snprintf(buf, sizeof (buf), def->flags ? "[%s]": "%s", def->name);
1102 if (model || dump) {
1103 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
1104 } else {
1105 (*cpu_fprintf)(f, "x86 %16s\n", buf);
1106 }
1107 if (dump) {
1108 memcpy(buf, &def->vendor1, sizeof (def->vendor1));
1109 memcpy(buf + 4, &def->vendor2, sizeof (def->vendor2));
1110 memcpy(buf + 8, &def->vendor3, sizeof (def->vendor3));
1111 buf[12] = '\0';
1112 (*cpu_fprintf)(f,
1113 " family %d model %d stepping %d level %d xlevel 0x%x"
1114 " vendor \"%s\"\n",
1115 def->family, def->model, def->stepping, def->level,
1116 def->xlevel, buf);
1117 listflags(buf, sizeof (buf), def->features, feature_name, 0);
1118 (*cpu_fprintf)(f, " feature_edx %08x (%s)\n", def->features,
1119 buf);
1120 listflags(buf, sizeof (buf), def->ext_features, ext_feature_name,
1121 0);
1122 (*cpu_fprintf)(f, " feature_ecx %08x (%s)\n", def->ext_features,
1123 buf);
1124 listflags(buf, sizeof (buf), def->ext2_features, ext2_feature_name,
1125 0);
1126 (*cpu_fprintf)(f, " extfeature_edx %08x (%s)\n",
1127 def->ext2_features, buf);
1128 listflags(buf, sizeof (buf), def->ext3_features, ext3_feature_name,
1129 0);
1130 (*cpu_fprintf)(f, " extfeature_ecx %08x (%s)\n",
1131 def->ext3_features, buf);
1132 (*cpu_fprintf)(f, "\n");
1133 }
1134 }
ed2c54d4
AP		 1135 if (kvm_enabled()) {
1136 (*cpu_fprintf)(f, "x86 %16s\n", "[host]");
1137 }
c6dc6f63
AP		 1138}
1139
76b64a7a 1140CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 1141{
1142 CpuDefinitionInfoList *cpu_list = NULL;
1143 x86_def_t *def;
1144
1145 for (def = x86_defs; def; def = def->next) {
1146 CpuDefinitionInfoList *entry;
1147 CpuDefinitionInfo *info;
1148
1149 info = g_malloc0(sizeof(*info));
1150 info->name = g_strdup(def->name);
1151
1152 entry = g_malloc0(sizeof(*entry));
1153 entry->value = info;
1154 entry->next = cpu_list;
1155 cpu_list = entry;
1156 }
1157
1158 return cpu_list;
1159}
1160
61dcd775 1161int cpu_x86_register(X86CPU *cpu, const char *cpu_model)
c6dc6f63 1162{
61dcd775 1163 CPUX86State *env = &cpu->env;
c6dc6f63 1164 x86_def_t def1, *def = &def1;
71ad61d3 1165 Error *error = NULL;
c6dc6f63 1166
db0ad1ba
JR		 1167 memset(def, 0, sizeof(*def));
1168
c6dc6f63
AP		 1169 if (cpu_x86_find_by_name(def, cpu_model) < 0)
1170 return -1;
1171 if (def->vendor1) {
1172 env->cpuid_vendor1 = def->vendor1;
1173 env->cpuid_vendor2 = def->vendor2;
1174 env->cpuid_vendor3 = def->vendor3;
1175 } else {
1176 env->cpuid_vendor1 = CPUID_VENDOR_INTEL_1;
1177 env->cpuid_vendor2 = CPUID_VENDOR_INTEL_2;
1178 env->cpuid_vendor3 = CPUID_VENDOR_INTEL_3;
1179 }
1180 env->cpuid_vendor_override = def->vendor_override;
8e1898bf 1181 object_property_set_int(OBJECT(cpu), def->level, "level", &error);
71ad61d3 1182 object_property_set_int(OBJECT(cpu), def->family, "family", &error);
c5291a4f 1183 object_property_set_int(OBJECT(cpu), def->model, "model", &error);
036e2222 1184 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", &error);
c6dc6f63 1185 env->cpuid_features = def->features;
c6dc6f63
AP		 1186 env->cpuid_ext_features = def->ext_features;
1187 env->cpuid_ext2_features = def->ext2_features;
4d067ed7 1188 env->cpuid_ext3_features = def->ext3_features;
16b93aa8 1189 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", &error);
c6dc6f63 1190 env->cpuid_kvm_features = def->kvm_features;
296acb64 1191 env->cpuid_svm_features = def->svm_features;
b3baa152 1192 env->cpuid_ext4_features = def->ext4_features;
13526728 1193 env->cpuid_7_0_ebx = def->cpuid_7_0_ebx_features;
b3baa152 1194 env->cpuid_xlevel2 = def->xlevel2;
89e48965
AF		 1195 object_property_set_int(OBJECT(cpu), (int64_t)def->tsc_khz * 1000,
1196 "tsc-frequency", &error);
551a2dec
AP		 1197 if (!kvm_enabled()) {
1198 env->cpuid_features &= TCG_FEATURES;
1199 env->cpuid_ext_features &= TCG_EXT_FEATURES;
1200 env->cpuid_ext2_features &= (TCG_EXT2_FEATURES
1201#ifdef TARGET_X86_64
1202 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
1203#endif
1204 );
1205 env->cpuid_ext3_features &= TCG_EXT3_FEATURES;
296acb64 1206 env->cpuid_svm_features &= TCG_SVM_FEATURES;
551a2dec 1207 }
938d4c25 1208 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", &error);
71ad61d3
AF		 1209 if (error_is_set(&error)) {
1210 error_free(error);
1211 return -1;
1212 }
c6dc6f63
AP		 1213 return 0;
1214}
1215
1216#if !defined(CONFIG_USER_ONLY)
1217/* copy vendor id string to 32 bit register, nul pad as needed
1218 */
1219static void cpyid(const char *s, uint32_t *id)
1220{
1221 char *d = (char *)id;
1222 char i;
1223
1224 for (i = sizeof (*id); i--; )
1225 *d++ = *s ? *s++ : '\0';
1226}
1227
1228/* interpret radix and convert from string to arbitrary scalar,
1229 * otherwise flag failure
1230 */
1231#define setscalar(pval, str, perr) \
1232{ \
1233 char *pend; \
1234 unsigned long ul; \
1235 \
1236 ul = strtoul(str, &pend, 0); \
1237 *str && !*pend ? (*pval = ul) : (*perr = 1); \
1238}
1239
1240/* map cpuid options to feature bits, otherwise return failure
1241 * (option tags in *str are delimited by whitespace)
1242 */
1243static void setfeatures(uint32_t *pval, const char *str,
1244 const char **featureset, int *perr)
1245{
1246 const char *p, *q;
1247
1248 for (q = p = str; *p || *q; q = p) {
1249 while (iswhite(*p))
1250 q = ++p;
1251 while (*p && !iswhite(*p))
1252 ++p;
1253 if (!*q && !*p)
1254 return;
1255 if (!lookup_feature(pval, q, p, featureset)) {
1256 fprintf(stderr, "error: feature \"%.*s\" not available in set\n",
1257 (int)(p - q), q);
1258 *perr = 1;
1259 return;
1260 }
1261 }
1262}
1263
1264/* map config file options to x86_def_t form
1265 */
1266static int cpudef_setfield(const char *name, const char *str, void *opaque)
1267{
1268 x86_def_t *def = opaque;
1269 int err = 0;
1270
1271 if (!strcmp(name, "name")) {
99e1dec0 1272 g_free((void *)def->name);
d3c481b3 1273 def->name = g_strdup(str);
c6dc6f63
AP		 1274 } else if (!strcmp(name, "model_id")) {
1275 strncpy(def->model_id, str, sizeof (def->model_id));
1276 } else if (!strcmp(name, "level")) {
1277 setscalar(&def->level, str, &err)
1278 } else if (!strcmp(name, "vendor")) {
1279 cpyid(&str[0], &def->vendor1);
1280 cpyid(&str[4], &def->vendor2);
1281 cpyid(&str[8], &def->vendor3);
1282 } else if (!strcmp(name, "family")) {
1283 setscalar(&def->family, str, &err)
1284 } else if (!strcmp(name, "model")) {
1285 setscalar(&def->model, str, &err)
1286 } else if (!strcmp(name, "stepping")) {
1287 setscalar(&def->stepping, str, &err)
1288 } else if (!strcmp(name, "feature_edx")) {
1289 setfeatures(&def->features, str, feature_name, &err);
1290 } else if (!strcmp(name, "feature_ecx")) {
1291 setfeatures(&def->ext_features, str, ext_feature_name, &err);
1292 } else if (!strcmp(name, "extfeature_edx")) {
1293 setfeatures(&def->ext2_features, str, ext2_feature_name, &err);
1294 } else if (!strcmp(name, "extfeature_ecx")) {
1295 setfeatures(&def->ext3_features, str, ext3_feature_name, &err);
1296 } else if (!strcmp(name, "xlevel")) {
1297 setscalar(&def->xlevel, str, &err)
1298 } else {
1299 fprintf(stderr, "error: unknown option [%s = %s]\n", name, str);
1300 return (1);
1301 }
1302 if (err) {
1303 fprintf(stderr, "error: bad option value [%s = %s]\n", name, str);
1304 return (1);
1305 }
1306 return (0);
1307}
1308
1309/* register config file entry as x86_def_t
1310 */
1311static int cpudef_register(QemuOpts *opts, void *opaque)
1312{
7267c094 1313 x86_def_t *def = g_malloc0(sizeof (x86_def_t));
c6dc6f63
AP		 1314
1315 qemu_opt_foreach(opts, cpudef_setfield, def, 1);
1316 def->next = x86_defs;
1317 x86_defs = def;
1318 return (0);
1319}
0e26b7b8
BS		 1320
1321void cpu_clear_apic_feature(CPUX86State *env)
1322{
1323 env->cpuid_features &= ~CPUID_APIC;
1324}
1325
c6dc6f63
AP		 1326#endif /* !CONFIG_USER_ONLY */
1327
1328/* register "cpudef" models defined in configuration file. Here we first
1329 * preload any built-in definitions
1330 */
1331void x86_cpudef_setup(void)
1332{
93bfef4c
CV		 1333 int i, j;
1334 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
c6dc6f63
AP		 1335
1336 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
1337 builtin_x86_defs[i].next = x86_defs;
1338 builtin_x86_defs[i].flags = 1;
93bfef4c
CV		 1339
1340 /* Look for specific "cpudef" models that */
09faecf2 1341 /* have the QEMU version in .model_id */
93bfef4c
CV		 1342 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
1343 if (strcmp(model_with_versions[j], builtin_x86_defs[i].name) == 0) {
1344 pstrcpy(builtin_x86_defs[i].model_id, sizeof(builtin_x86_defs[i].model_id), "QEMU Virtual CPU version ");
1345 pstrcat(builtin_x86_defs[i].model_id, sizeof(builtin_x86_defs[i].model_id), qemu_get_version());
1346 break;
1347 }
1348 }
1349
c6dc6f63
AP		 1350 x86_defs = &builtin_x86_defs[i];
1351 }
1352#if !defined(CONFIG_USER_ONLY)
3329f07b 1353 qemu_opts_foreach(qemu_find_opts("cpudef"), cpudef_register, NULL, 0);
c6dc6f63
AP		 1354#endif
1355}
1356
c6dc6f63
AP		 1357static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
1358 uint32_t *ecx, uint32_t *edx)
1359{
1360 *ebx = env->cpuid_vendor1;
1361 *edx = env->cpuid_vendor2;
1362 *ecx = env->cpuid_vendor3;
1363
1364 /* sysenter isn't supported on compatibility mode on AMD, syscall
1365 * isn't supported in compatibility mode on Intel.
1366 * Normally we advertise the actual cpu vendor, but you can override
1367 * this if you want to use KVM's sysenter/syscall emulation
1368 * in compatibility mode and when doing cross vendor migration
1369 */
89354998 1370 if (kvm_enabled() && ! env->cpuid_vendor_override) {
c6dc6f63
AP		 1371 host_cpuid(0, 0, NULL, ebx, ecx, edx);
1372 }
1373}
1374
1375void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1376 uint32_t *eax, uint32_t *ebx,
1377 uint32_t *ecx, uint32_t *edx)
1378{
1379 /* test if maximum index reached */
1380 if (index & 0x80000000) {
b3baa152 1381 if (index > env->cpuid_xlevel) {
1382 if (env->cpuid_xlevel2 > 0) {
1383 /* Handle the Centaur's CPUID instruction. */
1384 if (index > env->cpuid_xlevel2) {
1385 index = env->cpuid_xlevel2;
1386 } else if (index < 0xC0000000) {
1387 index = env->cpuid_xlevel;
1388 }
1389 } else {
1390 index = env->cpuid_xlevel;
1391 }
1392 }
c6dc6f63
AP		 1393 } else {
1394 if (index > env->cpuid_level)
1395 index = env->cpuid_level;
1396 }
1397
1398 switch(index) {
1399 case 0:
1400 *eax = env->cpuid_level;
1401 get_cpuid_vendor(env, ebx, ecx, edx);
1402 break;
1403 case 1:
1404 *eax = env->cpuid_version;
1405 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1406 *ecx = env->cpuid_ext_features;
1407 *edx = env->cpuid_features;
1408 if (env->nr_cores * env->nr_threads > 1) {
1409 *ebx |= (env->nr_cores * env->nr_threads) << 16;
1410 *edx |= 1 << 28; /* HTT bit */
1411 }
1412 break;
1413 case 2:
1414 /* cache info: needed for Pentium Pro compatibility */
1415 *eax = 1;
1416 *ebx = 0;
1417 *ecx = 0;
1418 *edx = 0x2c307d;
1419 break;
1420 case 4:
1421 /* cache info: needed for Core compatibility */
1422 if (env->nr_cores > 1) {
2f7a21c4 1423 *eax = (env->nr_cores - 1) << 26;
c6dc6f63 1424 } else {
2f7a21c4 1425 *eax = 0;
c6dc6f63
AP		 1426 }
1427 switch (count) {
1428 case 0: /* L1 dcache info */
1429 *eax |= 0x0000121;
1430 *ebx = 0x1c0003f;
1431 *ecx = 0x000003f;
1432 *edx = 0x0000001;
1433 break;
1434 case 1: /* L1 icache info */
1435 *eax |= 0x0000122;
1436 *ebx = 0x1c0003f;
1437 *ecx = 0x000003f;
1438 *edx = 0x0000001;
1439 break;
1440 case 2: /* L2 cache info */
1441 *eax |= 0x0000143;
1442 if (env->nr_threads > 1) {
1443 *eax |= (env->nr_threads - 1) << 14;
1444 }
1445 *ebx = 0x3c0003f;
1446 *ecx = 0x0000fff;
1447 *edx = 0x0000001;
1448 break;
1449 default: /* end of info */
1450 *eax = 0;
1451 *ebx = 0;
1452 *ecx = 0;
1453 *edx = 0;
1454 break;
1455 }
1456 break;
1457 case 5:
1458 /* mwait info: needed for Core compatibility */
1459 *eax = 0; /* Smallest monitor-line size in bytes */
1460 *ebx = 0; /* Largest monitor-line size in bytes */
1461 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1462 *edx = 0;
1463 break;
1464 case 6:
1465 /* Thermal and Power Leaf */
1466 *eax = 0;
1467 *ebx = 0;
1468 *ecx = 0;
1469 *edx = 0;
1470 break;
f7911686 1471 case 7:
13526728
EH		 1472 /* Structured Extended Feature Flags Enumeration Leaf */
1473 if (count == 0) {
1474 *eax = 0; /* Maximum ECX value for sub-leaves */
1475 *ebx = env->cpuid_7_0_ebx; /* Feature flags */
1476 *ecx = 0; /* Reserved */
1477 *edx = 0; /* Reserved */
f7911686
YW		 1478 } else {
1479 *eax = 0;
1480 *ebx = 0;
1481 *ecx = 0;
1482 *edx = 0;
1483 }
1484 break;
c6dc6f63
AP		 1485 case 9:
1486 /* Direct Cache Access Information Leaf */
1487 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1488 *ebx = 0;
1489 *ecx = 0;
1490 *edx = 0;
1491 break;
1492 case 0xA:
1493 /* Architectural Performance Monitoring Leaf */
a0fa8208
GN		 1494 if (kvm_enabled()) {
1495 KVMState *s = env->kvm_state;
1496
1497 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
1498 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
1499 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
1500 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
1501 } else {
1502 *eax = 0;
1503 *ebx = 0;
1504 *ecx = 0;
1505 *edx = 0;
1506 }
c6dc6f63 1507 break;
51e49430
SY		 1508 case 0xD:
1509 /* Processor Extended State */
1510 if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) {
1511 *eax = 0;
1512 *ebx = 0;
1513 *ecx = 0;
1514 *edx = 0;
1515 break;
1516 }
1517 if (kvm_enabled()) {
ba9bc59e
JK		 1518 KVMState *s = env->kvm_state;
1519
1520 *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
1521 *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
1522 *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
1523 *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
51e49430
SY		 1524 } else {
1525 *eax = 0;
1526 *ebx = 0;
1527 *ecx = 0;
1528 *edx = 0;
1529 }
1530 break;
c6dc6f63
AP		 1531 case 0x80000000:
1532 *eax = env->cpuid_xlevel;
1533 *ebx = env->cpuid_vendor1;
1534 *edx = env->cpuid_vendor2;
1535 *ecx = env->cpuid_vendor3;
1536 break;
1537 case 0x80000001:
1538 *eax = env->cpuid_version;
1539 *ebx = 0;
1540 *ecx = env->cpuid_ext3_features;
1541 *edx = env->cpuid_ext2_features;
1542
1543 /* The Linux kernel checks for the CMPLegacy bit and
1544 * discards multiple thread information if it is set.
1545 * So dont set it here for Intel to make Linux guests happy.
1546 */
1547 if (env->nr_cores * env->nr_threads > 1) {
1548 uint32_t tebx, tecx, tedx;
1549 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
1550 if (tebx != CPUID_VENDOR_INTEL_1 ||
1551 tedx != CPUID_VENDOR_INTEL_2 ||
1552 tecx != CPUID_VENDOR_INTEL_3) {
1553 *ecx |= 1 << 1; /* CmpLegacy bit */
1554 }
1555 }
c6dc6f63
AP		 1556 break;
1557 case 0x80000002:
1558 case 0x80000003:
1559 case 0x80000004:
1560 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1561 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1562 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1563 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1564 break;
1565 case 0x80000005:
1566 /* cache info (L1 cache) */
1567 *eax = 0x01ff01ff;
1568 *ebx = 0x01ff01ff;
1569 *ecx = 0x40020140;
1570 *edx = 0x40020140;
1571 break;
1572 case 0x80000006:
1573 /* cache info (L2 cache) */
1574 *eax = 0;
1575 *ebx = 0x42004200;
1576 *ecx = 0x02008140;
1577 *edx = 0;
1578 break;
1579 case 0x80000008:
1580 /* virtual & phys address size in low 2 bytes. */
1581/* XXX: This value must match the one used in the MMU code. */
1582 if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
1583 /* 64 bit processor */
1584/* XXX: The physical address space is limited to 42 bits in exec.c. */
1585 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
1586 } else {
1587 if (env->cpuid_features & CPUID_PSE36)
1588 *eax = 0x00000024; /* 36 bits physical */
1589 else
1590 *eax = 0x00000020; /* 32 bits physical */
1591 }
1592 *ebx = 0;
1593 *ecx = 0;
1594 *edx = 0;
1595 if (env->nr_cores * env->nr_threads > 1) {
1596 *ecx |= (env->nr_cores * env->nr_threads) - 1;
1597 }
1598 break;
1599 case 0x8000000A:
296acb64
JR		 1600 if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
1601 *eax = 0x00000001; /* SVM Revision */
1602 *ebx = 0x00000010; /* nr of ASIDs */
1603 *ecx = 0;
1604 *edx = env->cpuid_svm_features; /* optional features */
1605 } else {
1606 *eax = 0;
1607 *ebx = 0;
1608 *ecx = 0;
1609 *edx = 0;
1610 }
c6dc6f63 1611 break;
b3baa152 1612 case 0xC0000000:
1613 *eax = env->cpuid_xlevel2;
1614 *ebx = 0;
1615 *ecx = 0;
1616 *edx = 0;
1617 break;
1618 case 0xC0000001:
1619 /* Support for VIA CPU's CPUID instruction */
1620 *eax = env->cpuid_version;
1621 *ebx = 0;
1622 *ecx = 0;
1623 *edx = env->cpuid_ext4_features;
1624 break;
1625 case 0xC0000002:
1626 case 0xC0000003:
1627 case 0xC0000004:
1628 /* Reserved for the future, and now filled with zero */
1629 *eax = 0;
1630 *ebx = 0;
1631 *ecx = 0;
1632 *edx = 0;
1633 break;
c6dc6f63
AP		 1634 default:
1635 /* reserved values: zero */
1636 *eax = 0;
1637 *ebx = 0;
1638 *ecx = 0;
1639 *edx = 0;
1640 break;
1641 }
1642}
5fd2087a
AF		 1643
1644/* CPUClass::reset() */
1645static void x86_cpu_reset(CPUState *s)
1646{
1647 X86CPU *cpu = X86_CPU(s);
1648 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
1649 CPUX86State *env = &cpu->env;
c1958aea
AF		 1650 int i;
1651
1652 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
1653 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
1654 log_cpu_state(env, X86_DUMP_FPU | X86_DUMP_CCOP);
1655 }
5fd2087a
AF		 1656
1657 xcc->parent_reset(s);
1658
c1958aea
AF		 1659
1660 memset(env, 0, offsetof(CPUX86State, breakpoints));
1661
1662 tlb_flush(env, 1);
1663
1664 env->old_exception = -1;
1665
1666 /* init to reset state */
1667
1668#ifdef CONFIG_SOFTMMU
1669 env->hflags |= HF_SOFTMMU_MASK;
1670#endif
1671 env->hflags2 |= HF2_GIF_MASK;
1672
1673 cpu_x86_update_cr0(env, 0x60000010);
1674 env->a20_mask = ~0x0;
1675 env->smbase = 0x30000;
1676
1677 env->idt.limit = 0xffff;
1678 env->gdt.limit = 0xffff;
1679 env->ldt.limit = 0xffff;
1680 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
1681 env->tr.limit = 0xffff;
1682 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
1683
1684 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
1685 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
1686 DESC_R_MASK | DESC_A_MASK);
1687 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
1688 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1689 DESC_A_MASK);
1690 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
1691 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1692 DESC_A_MASK);
1693 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
1694 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1695 DESC_A_MASK);
1696 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
1697 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1698 DESC_A_MASK);
1699 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
1700 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1701 DESC_A_MASK);
1702
1703 env->eip = 0xfff0;
1704 env->regs[R_EDX] = env->cpuid_version;
1705
1706 env->eflags = 0x2;
1707
1708 /* FPU init */
1709 for (i = 0; i < 8; i++) {
1710 env->fptags[i] = 1;
1711 }
1712 env->fpuc = 0x37f;
1713
1714 env->mxcsr = 0x1f80;
1715
1716 env->pat = 0x0007040600070406ULL;
1717 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
1718
1719 memset(env->dr, 0, sizeof(env->dr));
1720 env->dr[6] = DR6_FIXED_1;
1721 env->dr[7] = DR7_FIXED_1;
1722 cpu_breakpoint_remove_all(env, BP_CPU);
1723 cpu_watchpoint_remove_all(env, BP_CPU);
dd673288
IM		 1724
1725#if !defined(CONFIG_USER_ONLY)
1726 /* We hard-wire the BSP to the first CPU. */
1727 if (env->cpu_index == 0) {
1728 apic_designate_bsp(env->apic_state);
1729 }
1730
1731 env->halted = !cpu_is_bsp(cpu);
1732#endif
5fd2087a
AF		 1733}
1734
dd673288
IM		 1735#ifndef CONFIG_USER_ONLY
1736bool cpu_is_bsp(X86CPU *cpu)
1737{
1738 return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
1739}
65dee380
IM		 1740
1741/* TODO: remove me, when reset over QOM tree is implemented */
1742static void x86_cpu_machine_reset_cb(void *opaque)
1743{
1744 X86CPU *cpu = opaque;
1745 cpu_reset(CPU(cpu));
1746}
dd673288
IM		 1747#endif
1748
de024815
AF		 1749static void mce_init(X86CPU *cpu)
1750{
1751 CPUX86State *cenv = &cpu->env;
1752 unsigned int bank;
1753
1754 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
1755 && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) ==
1756 (CPUID_MCE | CPUID_MCA)) {
1757 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
1758 cenv->mcg_ctl = ~(uint64_t)0;
1759 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
1760 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
1761 }
1762 }
1763}
1764
7a059953
AF		 1765void x86_cpu_realize(Object *obj, Error **errp)
1766{
1767 X86CPU *cpu = X86_CPU(obj);
1768
65dee380
IM		 1769#ifndef CONFIG_USER_ONLY
1770 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
1771#endif
1772
7a059953
AF		 1773 mce_init(cpu);
1774 qemu_init_vcpu(&cpu->env);
65dee380 1775 cpu_reset(CPU(cpu));
7a059953
AF		 1776}
1777
de024815
AF		 1778static void x86_cpu_initfn(Object *obj)
1779{
1780 X86CPU *cpu = X86_CPU(obj);
1781 CPUX86State *env = &cpu->env;
d65e9815 1782 static int inited;
de024815
AF		 1783
1784 cpu_exec_init(env);
71ad61d3
AF		 1785
1786 object_property_add(obj, "family", "int",
95b8519d 1787 x86_cpuid_version_get_family,
71ad61d3 1788 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 1789 object_property_add(obj, "model", "int",
67e30c83 1790 x86_cpuid_version_get_model,
c5291a4f 1791 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 1792 object_property_add(obj, "stepping", "int",
35112e41 1793 x86_cpuid_version_get_stepping,
036e2222 1794 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
8e1898bf
AF		 1795 object_property_add(obj, "level", "int",
1796 x86_cpuid_get_level,
1797 x86_cpuid_set_level, NULL, NULL, NULL);
16b93aa8
AF		 1798 object_property_add(obj, "xlevel", "int",
1799 x86_cpuid_get_xlevel,
1800 x86_cpuid_set_xlevel, NULL, NULL, NULL);
d480e1af
AF		 1801 object_property_add_str(obj, "vendor",
1802 x86_cpuid_get_vendor,
1803 x86_cpuid_set_vendor, NULL);
938d4c25 1804 object_property_add_str(obj, "model-id",
63e886eb 1805 x86_cpuid_get_model_id,
938d4c25 1806 x86_cpuid_set_model_id, NULL);
89e48965
AF		 1807 object_property_add(obj, "tsc-frequency", "int",
1808 x86_cpuid_get_tsc_freq,
1809 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
71ad61d3 1810
de024815 1811 env->cpuid_apic_id = env->cpu_index;
d65e9815
IM		 1812
1813 /* init various static tables used in TCG mode */
1814 if (tcg_enabled() && !inited) {
1815 inited = 1;
1816 optimize_flags_init();
1817#ifndef CONFIG_USER_ONLY
1818 cpu_set_debug_excp_handler(breakpoint_handler);
1819#endif
1820 }
de024815
AF		 1821}
1822
5fd2087a
AF		 1823static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
1824{
1825 X86CPUClass *xcc = X86_CPU_CLASS(oc);
1826 CPUClass *cc = CPU_CLASS(oc);
1827
1828 xcc->parent_reset = cc->reset;
1829 cc->reset = x86_cpu_reset;
1830}
1831
1832static const TypeInfo x86_cpu_type_info = {
1833 .name = TYPE_X86_CPU,
1834 .parent = TYPE_CPU,
1835 .instance_size = sizeof(X86CPU),
de024815 1836 .instance_init = x86_cpu_initfn,
5fd2087a
AF		 1837 .abstract = false,
1838 .class_size = sizeof(X86CPUClass),
1839 .class_init = x86_cpu_common_class_init,
1840};
1841
1842static void x86_cpu_register_types(void)
1843{
1844 type_register_static(&x86_cpu_type_info);
1845}
1846
1847type_init(x86_cpu_register_types)
Qemu copy for testing