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tcg-ia64: Move AREG0 to R32
[qemu.git] / target-lm32 / translate.c
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17c0fa3d
MW		 1/*
2 * LatticeMico32 main translation routines.
3 *
4 * Copyright (c) 2010 Michael Walle <michael@walle.cc>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
17c0fa3d 20#include "cpu.h"
76cad711 21#include "disas/disas.h"
17c0fa3d
MW		 22#include "helper.h"
23#include "tcg-op.h"
17c0fa3d 24
0d09e41a 25#include "hw/lm32/lm32_pic.h"
17c0fa3d
MW		 26
27#define GEN_HELPER 1
28#include "helper.h"
29
30#define DISAS_LM32 1
31#if DISAS_LM32
32# define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
33#else
34# define LOG_DIS(...) do { } while (0)
35#endif
36
37#define EXTRACT_FIELD(src, start, end) \
38 (((src) >> start) & ((1 << (end - start + 1)) - 1))
39
40#define MEM_INDEX 0
41
42static TCGv_ptr cpu_env;
43static TCGv cpu_R[32];
44static TCGv cpu_pc;
45static TCGv cpu_ie;
46static TCGv cpu_icc;
47static TCGv cpu_dcc;
48static TCGv cpu_cc;
49static TCGv cpu_cfg;
50static TCGv cpu_eba;
51static TCGv cpu_dc;
52static TCGv cpu_deba;
53static TCGv cpu_bp[4];
54static TCGv cpu_wp[4];
55
022c62cb 56#include "exec/gen-icount.h"
17c0fa3d
MW		 57
58enum {
59 OP_FMT_RI,
60 OP_FMT_RR,
61 OP_FMT_CR,
62 OP_FMT_I
63};
64
65/* This is the state at translation time. */
66typedef struct DisasContext {
6393c08d 67 CPULM32State *env;
17c0fa3d
MW		 68 target_ulong pc;
69
70 /* Decoder. */
71 int format;
72 uint32_t ir;
73 uint8_t opcode;
74 uint8_t r0, r1, r2, csr;
75 uint16_t imm5;
76 uint16_t imm16;
77 uint32_t imm26;
78
79 unsigned int delayed_branch;
80 unsigned int tb_flags, synced_flags; /* tb dependent flags. */
81 int is_jmp;
82
83 int nr_nops;
84 struct TranslationBlock *tb;
85 int singlestep_enabled;
86} DisasContext;
87
88static const char *regnames[] = {
89 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
90 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
91 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
92 "r24", "r25", "r26/gp", "r27/fp", "r28/sp", "r29/ra",
93 "r30/ea", "r31/ba", "bp0", "bp1", "bp2", "bp3", "wp0",
94 "wp1", "wp2", "wp3"
95};
96
97static inline int zero_extend(unsigned int val, int width)
98{
99 return val & ((1 << width) - 1);
100}
101
102static inline int sign_extend(unsigned int val, int width)
103{
104 int sval;
105
106 /* LSL. */
107 val <<= 32 - width;
108 sval = val;
109 /* ASR. */
110 sval >>= 32 - width;
111
112 return sval;
113}
114
115static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index)
116{
117 TCGv_i32 tmp = tcg_const_i32(index);
118
32ac0ca2 119 gen_helper_raise_exception(cpu_env, tmp);
17c0fa3d
MW		 120 tcg_temp_free_i32(tmp);
121}
122
123static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
124{
125 TranslationBlock *tb;
126
127 tb = dc->tb;
128 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
129 likely(!dc->singlestep_enabled)) {
130 tcg_gen_goto_tb(n);
131 tcg_gen_movi_tl(cpu_pc, dest);
8cfd0495 132 tcg_gen_exit_tb((uintptr_t)tb + n);
17c0fa3d
MW		 133 } else {
134 tcg_gen_movi_tl(cpu_pc, dest);
135 if (dc->singlestep_enabled) {
136 t_gen_raise_exception(dc, EXCP_DEBUG);
137 }
138 tcg_gen_exit_tb(0);
139 }
140}
141
142static void dec_add(DisasContext *dc)
143{
144 if (dc->format == OP_FMT_RI) {
145 if (dc->r0 == R_R0) {
146 if (dc->r1 == R_R0 && dc->imm16 == 0) {
147 LOG_DIS("nop\n");
148 } else {
149 LOG_DIS("mvi r%d, %d\n", dc->r1, sign_extend(dc->imm16, 16));
150 }
151 } else {
152 LOG_DIS("addi r%d, r%d, %d\n", dc->r1, dc->r0,
153 sign_extend(dc->imm16, 16));
154 }
155 } else {
156 LOG_DIS("add r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
157 }
158
159 if (dc->format == OP_FMT_RI) {
160 tcg_gen_addi_tl(cpu_R[dc->r1], cpu_R[dc->r0],
161 sign_extend(dc->imm16, 16));
162 } else {
163 tcg_gen_add_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
164 }
165}
166
167static void dec_and(DisasContext *dc)
168{
169 if (dc->format == OP_FMT_RI) {
170 LOG_DIS("andi r%d, r%d, %d\n", dc->r1, dc->r0,
171 zero_extend(dc->imm16, 16));
172 } else {
173 LOG_DIS("and r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
174 }
175
176 if (dc->format == OP_FMT_RI) {
177 tcg_gen_andi_tl(cpu_R[dc->r1], cpu_R[dc->r0],
178 zero_extend(dc->imm16, 16));
179 } else {
180 if (dc->r0 == 0 && dc->r1 == 0 && dc->r2 == 0) {
181 tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
32ac0ca2 182 gen_helper_hlt(cpu_env);
17c0fa3d
MW		 183 } else {
184 tcg_gen_and_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
185 }
186 }
187}
188
189static void dec_andhi(DisasContext *dc)
190{
191 LOG_DIS("andhi r%d, r%d, %d\n", dc->r2, dc->r0, dc->imm16);
192
193 tcg_gen_andi_tl(cpu_R[dc->r1], cpu_R[dc->r0], (dc->imm16 << 16));
194}
195
196static void dec_b(DisasContext *dc)
197{
198 if (dc->r0 == R_RA) {
199 LOG_DIS("ret\n");
200 } else if (dc->r0 == R_EA) {
201 LOG_DIS("eret\n");
202 } else if (dc->r0 == R_BA) {
203 LOG_DIS("bret\n");
204 } else {
205 LOG_DIS("b r%d\n", dc->r0);
206 }
207
208 /* restore IE.IE in case of an eret */
209 if (dc->r0 == R_EA) {
210 TCGv t0 = tcg_temp_new();
211 int l1 = gen_new_label();
212 tcg_gen_andi_tl(t0, cpu_ie, IE_EIE);
213 tcg_gen_ori_tl(cpu_ie, cpu_ie, IE_IE);
214 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, IE_EIE, l1);
215 tcg_gen_andi_tl(cpu_ie, cpu_ie, ~IE_IE);
216 gen_set_label(l1);
217 tcg_temp_free(t0);
218 } else if (dc->r0 == R_BA) {
219 TCGv t0 = tcg_temp_new();
220 int l1 = gen_new_label();
221 tcg_gen_andi_tl(t0, cpu_ie, IE_BIE);
222 tcg_gen_ori_tl(cpu_ie, cpu_ie, IE_IE);
223 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, IE_BIE, l1);
224 tcg_gen_andi_tl(cpu_ie, cpu_ie, ~IE_IE);
225 gen_set_label(l1);
226 tcg_temp_free(t0);
227 }
228 tcg_gen_mov_tl(cpu_pc, cpu_R[dc->r0]);
229
230 dc->is_jmp = DISAS_JUMP;
231}
232
233static void dec_bi(DisasContext *dc)
234{
235 LOG_DIS("bi %d\n", sign_extend(dc->imm26 << 2, 26));
236
237 gen_goto_tb(dc, 0, dc->pc + (sign_extend(dc->imm26 << 2, 26)));
238
239 dc->is_jmp = DISAS_TB_JUMP;
240}
241
242static inline void gen_cond_branch(DisasContext *dc, int cond)
243{
244 int l1;
245
246 l1 = gen_new_label();
247 tcg_gen_brcond_tl(cond, cpu_R[dc->r0], cpu_R[dc->r1], l1);
248 gen_goto_tb(dc, 0, dc->pc + 4);
249 gen_set_label(l1);
250 gen_goto_tb(dc, 1, dc->pc + (sign_extend(dc->imm16 << 2, 16)));
251 dc->is_jmp = DISAS_TB_JUMP;
252}
253
254static void dec_be(DisasContext *dc)
255{
256 LOG_DIS("be r%d, r%d, %d\n", dc->r0, dc->r1,
257 sign_extend(dc->imm16, 16) * 4);
258
259 gen_cond_branch(dc, TCG_COND_EQ);
260}
261
262static void dec_bg(DisasContext *dc)
263{
264 LOG_DIS("bg r%d, r%d, %d\n", dc->r0, dc->r1,
265 sign_extend(dc->imm16, 16 * 4));
266
267 gen_cond_branch(dc, TCG_COND_GT);
268}
269
270static void dec_bge(DisasContext *dc)
271{
272 LOG_DIS("bge r%d, r%d, %d\n", dc->r0, dc->r1,
273 sign_extend(dc->imm16, 16) * 4);
274
275 gen_cond_branch(dc, TCG_COND_GE);
276}
277
278static void dec_bgeu(DisasContext *dc)
279{
280 LOG_DIS("bgeu r%d, r%d, %d\n", dc->r0, dc->r1,
281 sign_extend(dc->imm16, 16) * 4);
282
283 gen_cond_branch(dc, TCG_COND_GEU);
284}
285
286static void dec_bgu(DisasContext *dc)
287{
288 LOG_DIS("bgu r%d, r%d, %d\n", dc->r0, dc->r1,
289 sign_extend(dc->imm16, 16) * 4);
290
291 gen_cond_branch(dc, TCG_COND_GTU);
292}
293
294static void dec_bne(DisasContext *dc)
295{
296 LOG_DIS("bne r%d, r%d, %d\n", dc->r0, dc->r1,
297 sign_extend(dc->imm16, 16) * 4);
298
299 gen_cond_branch(dc, TCG_COND_NE);
300}
301
302static void dec_call(DisasContext *dc)
303{
304 LOG_DIS("call r%d\n", dc->r0);
305
306 tcg_gen_movi_tl(cpu_R[R_RA], dc->pc + 4);
307 tcg_gen_mov_tl(cpu_pc, cpu_R[dc->r0]);
308
309 dc->is_jmp = DISAS_JUMP;
310}
311
312static void dec_calli(DisasContext *dc)
313{
314 LOG_DIS("calli %d\n", sign_extend(dc->imm26, 26) * 4);
315
316 tcg_gen_movi_tl(cpu_R[R_RA], dc->pc + 4);
317 gen_goto_tb(dc, 0, dc->pc + (sign_extend(dc->imm26 << 2, 26)));
318
319 dc->is_jmp = DISAS_TB_JUMP;
320}
321
322static inline void gen_compare(DisasContext *dc, int cond)
323{
324 int rX = (dc->format == OP_FMT_RR) ? dc->r2 : dc->r1;
325 int rY = (dc->format == OP_FMT_RR) ? dc->r0 : dc->r0;
326 int rZ = (dc->format == OP_FMT_RR) ? dc->r1 : -1;
df5eb7d2 327 int i;
17c0fa3d
MW		 328
329 if (dc->format == OP_FMT_RI) {
df5eb7d2
MW		 330 switch (cond) {
331 case TCG_COND_GEU:
332 case TCG_COND_GTU:
333 i = zero_extend(dc->imm16, 16);
334 break;
335 default:
336 i = sign_extend(dc->imm16, 16);
337 break;
338 }
339
340 tcg_gen_setcondi_tl(cond, cpu_R[rX], cpu_R[rY], i);
17c0fa3d
MW		 341 } else {
342 tcg_gen_setcond_tl(cond, cpu_R[rX], cpu_R[rY], cpu_R[rZ]);
343 }
344}
345
346static void dec_cmpe(DisasContext *dc)
347{
348 if (dc->format == OP_FMT_RI) {
349 LOG_DIS("cmpei r%d, r%d, %d\n", dc->r0, dc->r1,
350 sign_extend(dc->imm16, 16));
351 } else {
352 LOG_DIS("cmpe r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
353 }
354
355 gen_compare(dc, TCG_COND_EQ);
356}
357
358static void dec_cmpg(DisasContext *dc)
359{
360 if (dc->format == OP_FMT_RI) {
361 LOG_DIS("cmpgi r%d, r%d, %d\n", dc->r0, dc->r1,
362 sign_extend(dc->imm16, 16));
363 } else {
364 LOG_DIS("cmpg r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
365 }
366
367 gen_compare(dc, TCG_COND_GT);
368}
369
370static void dec_cmpge(DisasContext *dc)
371{
372 if (dc->format == OP_FMT_RI) {
373 LOG_DIS("cmpgei r%d, r%d, %d\n", dc->r0, dc->r1,
374 sign_extend(dc->imm16, 16));
375 } else {
376 LOG_DIS("cmpge r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
377 }
378
379 gen_compare(dc, TCG_COND_GE);
380}
381
382static void dec_cmpgeu(DisasContext *dc)
383{
384 if (dc->format == OP_FMT_RI) {
385 LOG_DIS("cmpgeui r%d, r%d, %d\n", dc->r0, dc->r1,
df5eb7d2 386 zero_extend(dc->imm16, 16));
17c0fa3d
MW		 387 } else {
388 LOG_DIS("cmpgeu r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
389 }
390
391 gen_compare(dc, TCG_COND_GEU);
392}
393
394static void dec_cmpgu(DisasContext *dc)
395{
396 if (dc->format == OP_FMT_RI) {
397 LOG_DIS("cmpgui r%d, r%d, %d\n", dc->r0, dc->r1,
df5eb7d2 398 zero_extend(dc->imm16, 16));
17c0fa3d
MW		 399 } else {
400 LOG_DIS("cmpgu r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
401 }
402
403 gen_compare(dc, TCG_COND_GTU);
404}
405
406static void dec_cmpne(DisasContext *dc)
407{
408 if (dc->format == OP_FMT_RI) {
409 LOG_DIS("cmpnei r%d, r%d, %d\n", dc->r0, dc->r1,
410 sign_extend(dc->imm16, 16));
411 } else {
412 LOG_DIS("cmpne r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
413 }
414
415 gen_compare(dc, TCG_COND_NE);
416}
417
418static void dec_divu(DisasContext *dc)
419{
420 int l1;
421
422 LOG_DIS("divu r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
423
424 if (!(dc->env->features & LM32_FEATURE_DIVIDE)) {
425 cpu_abort(dc->env, "hardware divider is not available\n");
426 }
427
428 l1 = gen_new_label();
429 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_R[dc->r1], 0, l1);
430 tcg_gen_movi_tl(cpu_pc, dc->pc);
431 t_gen_raise_exception(dc, EXCP_DIVIDE_BY_ZERO);
432 gen_set_label(l1);
433 tcg_gen_divu_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
434}
435
436static void dec_lb(DisasContext *dc)
437{
438 TCGv t0;
439
440 LOG_DIS("lb r%d, (r%d+%d)\n", dc->r1, dc->r0, dc->imm16);
441
442 t0 = tcg_temp_new();
443 tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
444 tcg_gen_qemu_ld8s(cpu_R[dc->r1], t0, MEM_INDEX);
445 tcg_temp_free(t0);
446}
447
448static void dec_lbu(DisasContext *dc)
449{
450 TCGv t0;
451
452 LOG_DIS("lbu r%d, (r%d+%d)\n", dc->r1, dc->r0, dc->imm16);
453
454 t0 = tcg_temp_new();
455 tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
456 tcg_gen_qemu_ld8u(cpu_R[dc->r1], t0, MEM_INDEX);
457 tcg_temp_free(t0);
458}
459
460static void dec_lh(DisasContext *dc)
461{
462 TCGv t0;
463
464 LOG_DIS("lh r%d, (r%d+%d)\n", dc->r1, dc->r0, dc->imm16);
465
466 t0 = tcg_temp_new();
467 tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
468 tcg_gen_qemu_ld16s(cpu_R[dc->r1], t0, MEM_INDEX);
469 tcg_temp_free(t0);
470}
471
472static void dec_lhu(DisasContext *dc)
473{
474 TCGv t0;
475
476 LOG_DIS("lhu r%d, (r%d+%d)\n", dc->r1, dc->r0, dc->imm16);
477
478 t0 = tcg_temp_new();
479 tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
480 tcg_gen_qemu_ld16u(cpu_R[dc->r1], t0, MEM_INDEX);
481 tcg_temp_free(t0);
482}
483
484static void dec_lw(DisasContext *dc)
485{
486 TCGv t0;
487
488 LOG_DIS("lw r%d, (r%d+%d)\n", dc->r1, dc->r0, sign_extend(dc->imm16, 16));
489
490 t0 = tcg_temp_new();
491 tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
492 tcg_gen_qemu_ld32s(cpu_R[dc->r1], t0, MEM_INDEX);
493 tcg_temp_free(t0);
494}
495
496static void dec_modu(DisasContext *dc)
497{
498 int l1;
499
500 LOG_DIS("modu r%d, r%d, %d\n", dc->r2, dc->r0, dc->r1);
501
502 if (!(dc->env->features & LM32_FEATURE_DIVIDE)) {
503 cpu_abort(dc->env, "hardware divider is not available\n");
504 }
505
506 l1 = gen_new_label();
507 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_R[dc->r1], 0, l1);
508 tcg_gen_movi_tl(cpu_pc, dc->pc);
509 t_gen_raise_exception(dc, EXCP_DIVIDE_BY_ZERO);
510 gen_set_label(l1);
511 tcg_gen_remu_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
512}
513
514static void dec_mul(DisasContext *dc)
515{
516 if (dc->format == OP_FMT_RI) {
517 LOG_DIS("muli r%d, r%d, %d\n", dc->r0, dc->r1,
518 sign_extend(dc->imm16, 16));
519 } else {
520 LOG_DIS("mul r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
521 }
522
523 if (!(dc->env->features & LM32_FEATURE_MULTIPLY)) {
524 cpu_abort(dc->env, "hardware multiplier is not available\n");
525 }
526
527 if (dc->format == OP_FMT_RI) {
528 tcg_gen_muli_tl(cpu_R[dc->r1], cpu_R[dc->r0],
529 sign_extend(dc->imm16, 16));
530 } else {
531 tcg_gen_mul_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
532 }
533}
534
535static void dec_nor(DisasContext *dc)
536{
537 if (dc->format == OP_FMT_RI) {
538 LOG_DIS("nori r%d, r%d, %d\n", dc->r0, dc->r1,
539 zero_extend(dc->imm16, 16));
540 } else {
541 LOG_DIS("nor r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
542 }
543
544 if (dc->format == OP_FMT_RI) {
545 TCGv t0 = tcg_temp_new();
546 tcg_gen_movi_tl(t0, zero_extend(dc->imm16, 16));
547 tcg_gen_nor_tl(cpu_R[dc->r1], cpu_R[dc->r0], t0);
548 tcg_temp_free(t0);
549 } else {
550 tcg_gen_nor_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
551 }
552}
553
554static void dec_or(DisasContext *dc)
555{
556 if (dc->format == OP_FMT_RI) {
557 LOG_DIS("ori r%d, r%d, %d\n", dc->r1, dc->r0,
558 zero_extend(dc->imm16, 16));
559 } else {
560 if (dc->r1 == R_R0) {
561 LOG_DIS("mv r%d, r%d\n", dc->r2, dc->r0);
562 } else {
563 LOG_DIS("or r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
564 }
565 }
566
567 if (dc->format == OP_FMT_RI) {
568 tcg_gen_ori_tl(cpu_R[dc->r1], cpu_R[dc->r0],
569 zero_extend(dc->imm16, 16));
570 } else {
571 tcg_gen_or_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
572 }
573}
574
575static void dec_orhi(DisasContext *dc)
576{
577 if (dc->r0 == R_R0) {
578 LOG_DIS("mvhi r%d, %d\n", dc->r1, dc->imm16);
579 } else {
580 LOG_DIS("orhi r%d, r%d, %d\n", dc->r1, dc->r0, dc->imm16);
581 }
582
583 tcg_gen_ori_tl(cpu_R[dc->r1], cpu_R[dc->r0], (dc->imm16 << 16));
584}
585
fcda9863 586static void dec_scall(DisasContext *dc)
17c0fa3d 587{
17c0fa3d
MW		 588 if (dc->imm5 == 7) {
589 LOG_DIS("scall\n");
590 } else if (dc->imm5 == 2) {
591 LOG_DIS("break\n");
592 } else {
593 cpu_abort(dc->env, "invalid opcode\n");
594 }
595
17c0fa3d 596 if (dc->imm5 == 7) {
17c0fa3d
MW		 597 tcg_gen_movi_tl(cpu_pc, dc->pc);
598 t_gen_raise_exception(dc, EXCP_SYSTEMCALL);
599 } else {
17c0fa3d
MW		 600 tcg_gen_movi_tl(cpu_pc, dc->pc);
601 t_gen_raise_exception(dc, EXCP_BREAKPOINT);
602 }
603}
604
605static void dec_rcsr(DisasContext *dc)
606{
607 LOG_DIS("rcsr r%d, %d\n", dc->r2, dc->csr);
608
609 switch (dc->csr) {
610 case CSR_IE:
611 tcg_gen_mov_tl(cpu_R[dc->r2], cpu_ie);
612 break;
613 case CSR_IM:
32ac0ca2 614 gen_helper_rcsr_im(cpu_R[dc->r2], cpu_env);
17c0fa3d
MW		 615 break;
616 case CSR_IP:
32ac0ca2 617 gen_helper_rcsr_ip(cpu_R[dc->r2], cpu_env);
17c0fa3d
MW		 618 break;
619 case CSR_CC:
620 tcg_gen_mov_tl(cpu_R[dc->r2], cpu_cc);
621 break;
622 case CSR_CFG:
623 tcg_gen_mov_tl(cpu_R[dc->r2], cpu_cfg);
624 break;
625 case CSR_EBA:
626 tcg_gen_mov_tl(cpu_R[dc->r2], cpu_eba);
627 break;
628 case CSR_DC:
629 tcg_gen_mov_tl(cpu_R[dc->r2], cpu_dc);
630 break;
631 case CSR_DEBA:
632 tcg_gen_mov_tl(cpu_R[dc->r2], cpu_deba);
633 break;
634 case CSR_JTX:
32ac0ca2 635 gen_helper_rcsr_jtx(cpu_R[dc->r2], cpu_env);
17c0fa3d
MW		 636 break;
637 case CSR_JRX:
32ac0ca2 638 gen_helper_rcsr_jrx(cpu_R[dc->r2], cpu_env);
17c0fa3d
MW		 639 break;
640 case CSR_ICC:
641 case CSR_DCC:
642 case CSR_BP0:
643 case CSR_BP1:
644 case CSR_BP2:
645 case CSR_BP3:
646 case CSR_WP0:
647 case CSR_WP1:
648 case CSR_WP2:
649 case CSR_WP3:
650 cpu_abort(dc->env, "invalid read access csr=%x\n", dc->csr);
651 break;
652 default:
653 cpu_abort(dc->env, "read_csr: unknown csr=%x\n", dc->csr);
654 break;
655 }
656}
657
658static void dec_sb(DisasContext *dc)
659{
660 TCGv t0;
661
662 LOG_DIS("sb (r%d+%d), r%d\n", dc->r0, dc->imm16, dc->r1);
663
664 t0 = tcg_temp_new();
665 tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
666 tcg_gen_qemu_st8(cpu_R[dc->r1], t0, MEM_INDEX);
667 tcg_temp_free(t0);
668}
669
670static void dec_sextb(DisasContext *dc)
671{
672 LOG_DIS("sextb r%d, r%d\n", dc->r2, dc->r0);
673
674 if (!(dc->env->features & LM32_FEATURE_SIGN_EXTEND)) {
675 cpu_abort(dc->env, "hardware sign extender is not available\n");
676 }
677
678 tcg_gen_ext8s_tl(cpu_R[dc->r2], cpu_R[dc->r0]);
679}
680
681static void dec_sexth(DisasContext *dc)
682{
683 LOG_DIS("sexth r%d, r%d\n", dc->r2, dc->r0);
684
685 if (!(dc->env->features & LM32_FEATURE_SIGN_EXTEND)) {
686 cpu_abort(dc->env, "hardware sign extender is not available\n");
687 }
688
689 tcg_gen_ext16s_tl(cpu_R[dc->r2], cpu_R[dc->r0]);
690}
691
692static void dec_sh(DisasContext *dc)
693{
694 TCGv t0;
695
696 LOG_DIS("sh (r%d+%d), r%d\n", dc->r0, dc->imm16, dc->r1);
697
698 t0 = tcg_temp_new();
699 tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
700 tcg_gen_qemu_st16(cpu_R[dc->r1], t0, MEM_INDEX);
701 tcg_temp_free(t0);
702}
703
704static void dec_sl(DisasContext *dc)
705{
706 if (dc->format == OP_FMT_RI) {
707 LOG_DIS("sli r%d, r%d, %d\n", dc->r1, dc->r0, dc->imm5);
708 } else {
709 LOG_DIS("sl r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
710 }
711
712 if (!(dc->env->features & LM32_FEATURE_SHIFT)) {
713 cpu_abort(dc->env, "hardware shifter is not available\n");
714 }
715
716 if (dc->format == OP_FMT_RI) {
717 tcg_gen_shli_tl(cpu_R[dc->r1], cpu_R[dc->r0], dc->imm5);
718 } else {
719 TCGv t0 = tcg_temp_new();
720 tcg_gen_andi_tl(t0, cpu_R[dc->r1], 0x1f);
721 tcg_gen_shl_tl(cpu_R[dc->r2], cpu_R[dc->r0], t0);
722 tcg_temp_free(t0);
723 }
724}
725
726static void dec_sr(DisasContext *dc)
727{
728 if (dc->format == OP_FMT_RI) {
729 LOG_DIS("sri r%d, r%d, %d\n", dc->r1, dc->r0, dc->imm5);
730 } else {
731 LOG_DIS("sr r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
732 }
733
734 if (!(dc->env->features & LM32_FEATURE_SHIFT)) {
735 if (dc->format == OP_FMT_RI) {
736 /* TODO: check r1 == 1 during runtime */
737 } else {
738 if (dc->imm5 != 1) {
739 cpu_abort(dc->env, "hardware shifter is not available\n");
740 }
741 }
742 }
743
744 if (dc->format == OP_FMT_RI) {
745 tcg_gen_sari_tl(cpu_R[dc->r1], cpu_R[dc->r0], dc->imm5);
746 } else {
747 TCGv t0 = tcg_temp_new();
748 tcg_gen_andi_tl(t0, cpu_R[dc->r1], 0x1f);
749 tcg_gen_sar_tl(cpu_R[dc->r2], cpu_R[dc->r0], t0);
750 tcg_temp_free(t0);
751 }
752}
753
754static void dec_sru(DisasContext *dc)
755{
756 if (dc->format == OP_FMT_RI) {
757 LOG_DIS("srui r%d, r%d, %d\n", dc->r1, dc->r0, dc->imm5);
758 } else {
759 LOG_DIS("sru r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
760 }
761
762 if (!(dc->env->features & LM32_FEATURE_SHIFT)) {
763 if (dc->format == OP_FMT_RI) {
764 /* TODO: check r1 == 1 during runtime */
765 } else {
766 if (dc->imm5 != 1) {
767 cpu_abort(dc->env, "hardware shifter is not available\n");
768 }
769 }
770 }
771
772 if (dc->format == OP_FMT_RI) {
773 tcg_gen_shri_tl(cpu_R[dc->r1], cpu_R[dc->r0], dc->imm5);
774 } else {
775 TCGv t0 = tcg_temp_new();
776 tcg_gen_andi_tl(t0, cpu_R[dc->r1], 0x1f);
777 tcg_gen_shr_tl(cpu_R[dc->r2], cpu_R[dc->r0], t0);
778 tcg_temp_free(t0);
779 }
780}
781
782static void dec_sub(DisasContext *dc)
783{
784 LOG_DIS("sub r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
785
786 tcg_gen_sub_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
787}
788
789static void dec_sw(DisasContext *dc)
790{
791 TCGv t0;
792
793 LOG_DIS("sw (r%d+%d), r%d\n", dc->r0, sign_extend(dc->imm16, 16), dc->r1);
794
795 t0 = tcg_temp_new();
796 tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
797 tcg_gen_qemu_st32(cpu_R[dc->r1], t0, MEM_INDEX);
798 tcg_temp_free(t0);
799}
800
801static void dec_user(DisasContext *dc)
802{
803 LOG_DIS("user");
804
805 cpu_abort(dc->env, "user insn undefined\n");
806}
807
808static void dec_wcsr(DisasContext *dc)
809{
810 int no;
811
812 LOG_DIS("wcsr r%d, %d\n", dc->r1, dc->csr);
813
814 switch (dc->csr) {
815 case CSR_IE:
816 tcg_gen_mov_tl(cpu_ie, cpu_R[dc->r1]);
817 tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
818 dc->is_jmp = DISAS_UPDATE;
819 break;
820 case CSR_IM:
821 /* mark as an io operation because it could cause an interrupt */
822 if (use_icount) {
823 gen_io_start();
824 }
32ac0ca2 825 gen_helper_wcsr_im(cpu_env, cpu_R[dc->r1]);
17c0fa3d
MW		 826 tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
827 if (use_icount) {
828 gen_io_end();
829 }
830 dc->is_jmp = DISAS_UPDATE;
831 break;
832 case CSR_IP:
833 /* mark as an io operation because it could cause an interrupt */
834 if (use_icount) {
835 gen_io_start();
836 }
32ac0ca2 837 gen_helper_wcsr_ip(cpu_env, cpu_R[dc->r1]);
17c0fa3d
MW		 838 tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
839 if (use_icount) {
840 gen_io_end();
841 }
842 dc->is_jmp = DISAS_UPDATE;
843 break;
844 case CSR_ICC:
845 /* TODO */
846 break;
847 case CSR_DCC:
848 /* TODO */
849 break;
850 case CSR_EBA:
851 tcg_gen_mov_tl(cpu_eba, cpu_R[dc->r1]);
852 break;
853 case CSR_DEBA:
854 tcg_gen_mov_tl(cpu_deba, cpu_R[dc->r1]);
855 break;
856 case CSR_JTX:
32ac0ca2 857 gen_helper_wcsr_jtx(cpu_env, cpu_R[dc->r1]);
17c0fa3d
MW		 858 break;
859 case CSR_JRX:
32ac0ca2 860 gen_helper_wcsr_jrx(cpu_env, cpu_R[dc->r1]);
17c0fa3d
MW		 861 break;
862 case CSR_DC:
863 tcg_gen_mov_tl(cpu_dc, cpu_R[dc->r1]);
864 break;
865 case CSR_BP0:
866 case CSR_BP1:
867 case CSR_BP2:
868 case CSR_BP3:
869 no = dc->csr - CSR_BP0;
870 if (dc->env->num_bps <= no) {
871 cpu_abort(dc->env, "breakpoint #%i is not available\n", no);
872 }
873 tcg_gen_mov_tl(cpu_bp[no], cpu_R[dc->r1]);
874 break;
875 case CSR_WP0:
876 case CSR_WP1:
877 case CSR_WP2:
878 case CSR_WP3:
879 no = dc->csr - CSR_WP0;
880 if (dc->env->num_wps <= no) {
881 cpu_abort(dc->env, "watchpoint #%i is not available\n", no);
882 }
883 tcg_gen_mov_tl(cpu_wp[no], cpu_R[dc->r1]);
884 break;
885 case CSR_CC:
886 case CSR_CFG:
887 cpu_abort(dc->env, "invalid write access csr=%x\n", dc->csr);
888 break;
889 default:
890 cpu_abort(dc->env, "write_csr unknown csr=%x\n", dc->csr);
891 break;
892 }
893}
894
895static void dec_xnor(DisasContext *dc)
896{
897 if (dc->format == OP_FMT_RI) {
898 LOG_DIS("xnori r%d, r%d, %d\n", dc->r0, dc->r1,
899 zero_extend(dc->imm16, 16));
900 } else {
901 if (dc->r1 == R_R0) {
902 LOG_DIS("not r%d, r%d\n", dc->r2, dc->r0);
903 } else {
904 LOG_DIS("xnor r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
905 }
906 }
907
908 if (dc->format == OP_FMT_RI) {
909 tcg_gen_xori_tl(cpu_R[dc->r1], cpu_R[dc->r0],
910 zero_extend(dc->imm16, 16));
911 tcg_gen_not_tl(cpu_R[dc->r1], cpu_R[dc->r1]);
912 } else {
913 tcg_gen_eqv_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
914 }
915}
916
917static void dec_xor(DisasContext *dc)
918{
919 if (dc->format == OP_FMT_RI) {
920 LOG_DIS("xori r%d, r%d, %d\n", dc->r0, dc->r1,
921 zero_extend(dc->imm16, 16));
922 } else {
923 LOG_DIS("xor r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
924 }
925
926 if (dc->format == OP_FMT_RI) {
927 tcg_gen_xori_tl(cpu_R[dc->r1], cpu_R[dc->r0],
928 zero_extend(dc->imm16, 16));
929 } else {
930 tcg_gen_xor_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
931 }
932}
933
a5086f95
MW		 934static void dec_ill(DisasContext *dc)
935{
936 cpu_abort(dc->env, "unknown opcode 0x%02x\n", dc->opcode);
937}
17c0fa3d 938
a5086f95 939typedef void (*DecoderInfo)(DisasContext *dc);
17c0fa3d 940static const DecoderInfo decinfo[] = {
a5086f95
MW		 941 dec_sru, dec_nor, dec_mul, dec_sh, dec_lb, dec_sr, dec_xor, dec_lh,
942 dec_and, dec_xnor, dec_lw, dec_lhu, dec_sb, dec_add, dec_or, dec_sl,
943 dec_lbu, dec_be, dec_bg, dec_bge, dec_bgeu, dec_bgu, dec_sw, dec_bne,
944 dec_andhi, dec_cmpe, dec_cmpg, dec_cmpge, dec_cmpgeu, dec_cmpgu, dec_orhi,
945 dec_cmpne,
946 dec_sru, dec_nor, dec_mul, dec_divu, dec_rcsr, dec_sr, dec_xor, dec_ill,
947 dec_and, dec_xnor, dec_ill, dec_scall, dec_sextb, dec_add, dec_or, dec_sl,
948 dec_b, dec_modu, dec_sub, dec_user, dec_wcsr, dec_ill, dec_call, dec_sexth,
949 dec_bi, dec_cmpe, dec_cmpg, dec_cmpge, dec_cmpgeu, dec_cmpgu, dec_calli,
950 dec_cmpne
17c0fa3d
MW		 951};
952
32ac0ca2 953static inline void decode(DisasContext *dc, uint32_t ir)
17c0fa3d 954{
fdefe51c 955 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
17c0fa3d
MW		 956 tcg_gen_debug_insn_start(dc->pc);
957 }
958
32ac0ca2 959 dc->ir = ir;
17c0fa3d
MW		 960 LOG_DIS("%8.8x\t", dc->ir);
961
962 /* try guessing 'empty' instruction memory, although it may be a valid
963 * instruction sequence (eg. srui r0, r0, 0) */
964 if (dc->ir) {
965 dc->nr_nops = 0;
966 } else {
967 LOG_DIS("nr_nops=%d\t", dc->nr_nops);
968 dc->nr_nops++;
969 if (dc->nr_nops > 4) {
970 cpu_abort(dc->env, "fetching nop sequence\n");
971 }
972 }
973
974 dc->opcode = EXTRACT_FIELD(ir, 26, 31);
975
976 dc->imm5 = EXTRACT_FIELD(ir, 0, 4);
977 dc->imm16 = EXTRACT_FIELD(ir, 0, 15);
978 dc->imm26 = EXTRACT_FIELD(ir, 0, 25);
979
980 dc->csr = EXTRACT_FIELD(ir, 21, 25);
981 dc->r0 = EXTRACT_FIELD(ir, 21, 25);
982 dc->r1 = EXTRACT_FIELD(ir, 16, 20);
983 dc->r2 = EXTRACT_FIELD(ir, 11, 15);
984
985 /* bit 31 seems to indicate insn type. */
986 if (ir & (1 << 31)) {
987 dc->format = OP_FMT_RR;
988 } else {
989 dc->format = OP_FMT_RI;
990 }
991
a5086f95
MW		 992 assert(ARRAY_SIZE(decinfo) == 64);
993 assert(dc->opcode < 64);
17c0fa3d 994
a5086f95 995 decinfo[dc->opcode](dc);
17c0fa3d
MW		 996}
997
6393c08d 998static void check_breakpoint(CPULM32State *env, DisasContext *dc)
17c0fa3d
MW		 999{
1000 CPUBreakpoint *bp;
1001
1002 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
1003 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
1004 if (bp->pc == dc->pc) {
1005 tcg_gen_movi_tl(cpu_pc, dc->pc);
1006 t_gen_raise_exception(dc, EXCP_DEBUG);
1007 dc->is_jmp = DISAS_UPDATE;
1008 }
1009 }
1010 }
1011}
1012
1013/* generate intermediate code for basic block 'tb'. */
28014bca 1014static inline
cd0db97e
AF		 1015void gen_intermediate_code_internal(LM32CPU *cpu,
1016 TranslationBlock *tb, bool search_pc)
17c0fa3d 1017{
ed2803da 1018 CPUState *cs = CPU(cpu);
cd0db97e 1019 CPULM32State *env = &cpu->env;
17c0fa3d
MW		 1020 struct DisasContext ctx, *dc = &ctx;
1021 uint16_t *gen_opc_end;
1022 uint32_t pc_start;
1023 int j, lj;
1024 uint32_t next_page_start;
1025 int num_insns;
1026 int max_insns;
1027
17c0fa3d
MW		 1028 pc_start = tb->pc;
1029 dc->env = env;
1030 dc->tb = tb;
1031
92414b31 1032 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
17c0fa3d
MW		 1033
1034 dc->is_jmp = DISAS_NEXT;
1035 dc->pc = pc_start;
ed2803da 1036 dc->singlestep_enabled = cs->singlestep_enabled;
17c0fa3d
MW		 1037 dc->nr_nops = 0;
1038
1039 if (pc_start & 3) {
1040 cpu_abort(env, "LM32: unaligned PC=%x\n", pc_start);
1041 }
1042
17c0fa3d
MW		 1043 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
1044 lj = -1;
1045 num_insns = 0;
1046 max_insns = tb->cflags & CF_COUNT_MASK;
1047 if (max_insns == 0) {
1048 max_insns = CF_COUNT_MASK;
1049 }
1050
806f352d 1051 gen_tb_start();
17c0fa3d
MW		 1052 do {
1053 check_breakpoint(env, dc);
1054
1055 if (search_pc) {
92414b31 1056 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
17c0fa3d
MW		 1057 if (lj < j) {
1058 lj++;
1059 while (lj < j) {
ab1103de 1060 tcg_ctx.gen_opc_instr_start[lj++] = 0;
17c0fa3d
MW		 1061 }
1062 }
25983cad 1063 tcg_ctx.gen_opc_pc[lj] = dc->pc;
ab1103de 1064 tcg_ctx.gen_opc_instr_start[lj] = 1;
c9c99c22 1065 tcg_ctx.gen_opc_icount[lj] = num_insns;
17c0fa3d
MW		 1066 }
1067
1068 /* Pretty disas. */
1069 LOG_DIS("%8.8x:\t", dc->pc);
1070
1071 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
1072 gen_io_start();
1073 }
1074
32ac0ca2 1075 decode(dc, cpu_ldl_code(env, dc->pc));
17c0fa3d
MW		 1076 dc->pc += 4;
1077 num_insns++;
1078
1079 } while (!dc->is_jmp
efd7f486 1080 && tcg_ctx.gen_opc_ptr < gen_opc_end
ed2803da 1081 && !cs->singlestep_enabled
17c0fa3d
MW		 1082 && !singlestep
1083 && (dc->pc < next_page_start)
1084 && num_insns < max_insns);
1085
1086 if (tb->cflags & CF_LAST_IO) {
1087 gen_io_end();
1088 }
1089
ed2803da 1090 if (unlikely(cs->singlestep_enabled)) {
17c0fa3d
MW		 1091 if (dc->is_jmp == DISAS_NEXT) {
1092 tcg_gen_movi_tl(cpu_pc, dc->pc);
1093 }
1094 t_gen_raise_exception(dc, EXCP_DEBUG);
1095 } else {
1096 switch (dc->is_jmp) {
1097 case DISAS_NEXT:
1098 gen_goto_tb(dc, 1, dc->pc);
1099 break;
1100 default:
1101 case DISAS_JUMP:
1102 case DISAS_UPDATE:
1103 /* indicate that the hash table must be used
1104 to find the next TB */
1105 tcg_gen_exit_tb(0);
1106 break;
1107 case DISAS_TB_JUMP:
1108 /* nothing more to generate */
1109 break;
1110 }
1111 }
1112
806f352d 1113 gen_tb_end(tb, num_insns);
efd7f486 1114 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
17c0fa3d 1115 if (search_pc) {
92414b31 1116 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
17c0fa3d
MW		 1117 lj++;
1118 while (lj <= j) {
ab1103de 1119 tcg_ctx.gen_opc_instr_start[lj++] = 0;
17c0fa3d
MW		 1120 }
1121 } else {
1122 tb->size = dc->pc - pc_start;
1123 tb->icount = num_insns;
1124 }
1125
1126#ifdef DEBUG_DISAS
1127 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1128 qemu_log("\n");
f4359b9f 1129 log_target_disas(env, pc_start, dc->pc - pc_start, 0);
dfa5294f 1130 qemu_log("\nisize=%d osize=%td\n",
92414b31
EV		 1131 dc->pc - pc_start, tcg_ctx.gen_opc_ptr -
1132 tcg_ctx.gen_opc_buf);
17c0fa3d
MW		 1133 }
1134#endif
1135}
1136
6393c08d 1137void gen_intermediate_code(CPULM32State *env, struct TranslationBlock *tb)
17c0fa3d 1138{
cd0db97e 1139 gen_intermediate_code_internal(lm32_env_get_cpu(env), tb, false);
17c0fa3d
MW		 1140}
1141
6393c08d 1142void gen_intermediate_code_pc(CPULM32State *env, struct TranslationBlock *tb)
17c0fa3d 1143{
cd0db97e 1144 gen_intermediate_code_internal(lm32_env_get_cpu(env), tb, true);
17c0fa3d
MW		 1145}
1146
878096ee
AF		 1147void lm32_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
1148 int flags)
17c0fa3d 1149{
878096ee
AF		 1150 LM32CPU *cpu = LM32_CPU(cs);
1151 CPULM32State *env = &cpu->env;
17c0fa3d
MW		 1152 int i;
1153
1154 if (!env || !f) {
1155 return;
1156 }
1157
1158 cpu_fprintf(f, "IN: PC=%x %s\n",
1159 env->pc, lookup_symbol(env->pc));
1160
1161 cpu_fprintf(f, "ie=%8.8x (IE=%x EIE=%x BIE=%x) im=%8.8x ip=%8.8x\n",
1162 env->ie,
1163 (env->ie & IE_IE) ? 1 : 0,
1164 (env->ie & IE_EIE) ? 1 : 0,
1165 (env->ie & IE_BIE) ? 1 : 0,
1166 lm32_pic_get_im(env->pic_state),
1167 lm32_pic_get_ip(env->pic_state));
1168 cpu_fprintf(f, "eba=%8.8x deba=%8.8x\n",
1169 env->eba,
1170 env->deba);
1171
1172 for (i = 0; i < 32; i++) {
1173 cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
1174 if ((i + 1) % 4 == 0) {
1175 cpu_fprintf(f, "\n");
1176 }
1177 }
1178 cpu_fprintf(f, "\n\n");
1179}
1180
6393c08d 1181void restore_state_to_opc(CPULM32State *env, TranslationBlock *tb, int pc_pos)
17c0fa3d 1182{
25983cad 1183 env->pc = tcg_ctx.gen_opc_pc[pc_pos];
17c0fa3d
MW		 1184}
1185
1186void lm32_translate_init(void)
1187{
1188 int i;
1189
1190 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
1191
1192 for (i = 0; i < ARRAY_SIZE(cpu_R); i++) {
1193 cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
6393c08d 1194 offsetof(CPULM32State, regs[i]),
17c0fa3d
MW		 1195 regnames[i]);
1196 }
1197
1198 for (i = 0; i < ARRAY_SIZE(cpu_bp); i++) {
1199 cpu_bp[i] = tcg_global_mem_new(TCG_AREG0,
6393c08d 1200 offsetof(CPULM32State, bp[i]),
17c0fa3d
MW		 1201 regnames[32+i]);
1202 }
1203
1204 for (i = 0; i < ARRAY_SIZE(cpu_wp); i++) {
1205 cpu_wp[i] = tcg_global_mem_new(TCG_AREG0,
6393c08d 1206 offsetof(CPULM32State, wp[i]),
17c0fa3d
MW		 1207 regnames[36+i]);
1208 }
1209
1210 cpu_pc = tcg_global_mem_new(TCG_AREG0,
6393c08d 1211 offsetof(CPULM32State, pc),
17c0fa3d
MW		 1212 "pc");
1213 cpu_ie = tcg_global_mem_new(TCG_AREG0,
6393c08d 1214 offsetof(CPULM32State, ie),
17c0fa3d
MW		 1215 "ie");
1216 cpu_icc = tcg_global_mem_new(TCG_AREG0,
6393c08d 1217 offsetof(CPULM32State, icc),
17c0fa3d
MW		 1218 "icc");
1219 cpu_dcc = tcg_global_mem_new(TCG_AREG0,
6393c08d 1220 offsetof(CPULM32State, dcc),
17c0fa3d
MW		 1221 "dcc");
1222 cpu_cc = tcg_global_mem_new(TCG_AREG0,
6393c08d 1223 offsetof(CPULM32State, cc),
17c0fa3d
MW		 1224 "cc");
1225 cpu_cfg = tcg_global_mem_new(TCG_AREG0,
6393c08d 1226 offsetof(CPULM32State, cfg),
17c0fa3d
MW		 1227 "cfg");
1228 cpu_eba = tcg_global_mem_new(TCG_AREG0,
6393c08d 1229 offsetof(CPULM32State, eba),
17c0fa3d
MW		 1230 "eba");
1231 cpu_dc = tcg_global_mem_new(TCG_AREG0,
6393c08d 1232 offsetof(CPULM32State, dc),
17c0fa3d
MW		 1233 "dc");
1234 cpu_deba = tcg_global_mem_new(TCG_AREG0,
6393c08d 1235 offsetof(CPULM32State, deba),
17c0fa3d
MW		 1236 "deba");
1237}
1238
Qemu copy for testing