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[qemu.git] / cpu-exec.c
1 /*
2 * i386 emulator main execution loop
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include "config.h"
21 #include "exec.h"
22 #include "disas.h"
23
24 #if !defined(CONFIG_SOFTMMU)
25 #undef EAX
26 #undef ECX
27 #undef EDX
28 #undef EBX
29 #undef ESP
30 #undef EBP
31 #undef ESI
32 #undef EDI
33 #undef EIP
34 #include <signal.h>
35 #include <sys/ucontext.h>
36 #endif
37
38 int tb_invalidated_flag;
39
40 //#define DEBUG_EXEC
41 //#define DEBUG_SIGNAL
42
43 #if defined(TARGET_ARM) || defined(TARGET_SPARC)
44 /* XXX: unify with i386 target */
45 void cpu_loop_exit(void)
46 {
47 longjmp(env->jmp_env, 1);
48 }
49 #endif
50 #if !(defined(TARGET_SPARC) || defined(TARGET_SH4))
51 #define reg_T2
52 #endif
53
54 /* exit the current TB from a signal handler. The host registers are
55 restored in a state compatible with the CPU emulator
56 */
57 void cpu_resume_from_signal(CPUState *env1, void *puc)
58 {
59 #if !defined(CONFIG_SOFTMMU)
60 struct ucontext *uc = puc;
61 #endif
62
63 env = env1;
64
65 /* XXX: restore cpu registers saved in host registers */
66
67 #if !defined(CONFIG_SOFTMMU)
68 if (puc) {
69 /* XXX: use siglongjmp ? */
70 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
71 }
72 #endif
73 longjmp(env->jmp_env, 1);
74 }
75
76
77 static TranslationBlock *tb_find_slow(target_ulong pc,
78 target_ulong cs_base,
79 unsigned int flags)
80 {
81 TranslationBlock *tb, **ptb1;
82 int code_gen_size;
83 unsigned int h;
84 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
85 uint8_t *tc_ptr;
86
87 spin_lock(&tb_lock);
88
89 tb_invalidated_flag = 0;
90
91 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
92
93 /* find translated block using physical mappings */
94 phys_pc = get_phys_addr_code(env, pc);
95 phys_page1 = phys_pc & TARGET_PAGE_MASK;
96 phys_page2 = -1;
97 h = tb_phys_hash_func(phys_pc);
98 ptb1 = &tb_phys_hash[h];
99 for(;;) {
100 tb = *ptb1;
101 if (!tb)
102 goto not_found;
103 if (tb->pc == pc &&
104 tb->page_addr[0] == phys_page1 &&
105 tb->cs_base == cs_base &&
106 tb->flags == flags) {
107 /* check next page if needed */
108 if (tb->page_addr[1] != -1) {
109 virt_page2 = (pc & TARGET_PAGE_MASK) +
110 TARGET_PAGE_SIZE;
111 phys_page2 = get_phys_addr_code(env, virt_page2);
112 if (tb->page_addr[1] == phys_page2)
113 goto found;
114 } else {
115 goto found;
116 }
117 }
118 ptb1 = &tb->phys_hash_next;
119 }
120 not_found:
121 /* if no translated code available, then translate it now */
122 tb = tb_alloc(pc);
123 if (!tb) {
124 /* flush must be done */
125 tb_flush(env);
126 /* cannot fail at this point */
127 tb = tb_alloc(pc);
128 /* don't forget to invalidate previous TB info */
129 tb_invalidated_flag = 1;
130 }
131 tc_ptr = code_gen_ptr;
132 tb->tc_ptr = tc_ptr;
133 tb->cs_base = cs_base;
134 tb->flags = flags;
135 cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
136 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
137
138 /* check next page if needed */
139 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
140 phys_page2 = -1;
141 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
142 phys_page2 = get_phys_addr_code(env, virt_page2);
143 }
144 tb_link_phys(tb, phys_pc, phys_page2);
145
146 found:
147 /* we add the TB in the virtual pc hash table */
148 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
149 spin_unlock(&tb_lock);
150 return tb;
151 }
152
153 static inline TranslationBlock *tb_find_fast(void)
154 {
155 TranslationBlock *tb;
156 target_ulong cs_base, pc;
157 unsigned int flags;
158
159 /* we record a subset of the CPU state. It will
160 always be the same before a given translated block
161 is executed. */
162 #if defined(TARGET_I386)
163 flags = env->hflags;
164 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
165 cs_base = env->segs[R_CS].base;
166 pc = cs_base + env->eip;
167 #elif defined(TARGET_ARM)
168 flags = env->thumb | (env->vfp.vec_len << 1)
169 | (env->vfp.vec_stride << 4);
170 if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR)
171 flags |= (1 << 6);
172 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30))
173 flags |= (1 << 7);
174 cs_base = 0;
175 pc = env->regs[15];
176 #elif defined(TARGET_SPARC)
177 #ifdef TARGET_SPARC64
178 flags = (env->pstate << 2) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
179 #else
180 flags = env->psrs | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1);
181 #endif
182 cs_base = env->npc;
183 pc = env->pc;
184 #elif defined(TARGET_PPC)
185 flags = (msr_pr << MSR_PR) | (msr_fp << MSR_FP) |
186 (msr_se << MSR_SE) | (msr_le << MSR_LE);
187 cs_base = 0;
188 pc = env->nip;
189 #elif defined(TARGET_MIPS)
190 flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
191 cs_base = 0;
192 pc = env->PC;
193 #elif defined(TARGET_SH4)
194 flags = env->sr & (SR_MD | SR_RB);
195 cs_base = 0; /* XXXXX */
196 pc = env->pc;
197 #else
198 #error unsupported CPU
199 #endif
200 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
201 if (__builtin_expect(!tb || tb->pc != pc || tb->cs_base != cs_base ||
202 tb->flags != flags, 0)) {
203 tb = tb_find_slow(pc, cs_base, flags);
204 /* Note: we do it here to avoid a gcc bug on Mac OS X when
205 doing it in tb_find_slow */
206 if (tb_invalidated_flag) {
207 /* as some TB could have been invalidated because
208 of memory exceptions while generating the code, we
209 must recompute the hash index here */
210 T0 = 0;
211 }
212 }
213 return tb;
214 }
215
216
217 /* main execution loop */
218
219 int cpu_exec(CPUState *env1)
220 {
221 int saved_T0, saved_T1;
222 #if defined(reg_T2)
223 int saved_T2;
224 #endif
225 CPUState *saved_env;
226 #if defined(TARGET_I386)
227 #ifdef reg_EAX
228 int saved_EAX;
229 #endif
230 #ifdef reg_ECX
231 int saved_ECX;
232 #endif
233 #ifdef reg_EDX
234 int saved_EDX;
235 #endif
236 #ifdef reg_EBX
237 int saved_EBX;
238 #endif
239 #ifdef reg_ESP
240 int saved_ESP;
241 #endif
242 #ifdef reg_EBP
243 int saved_EBP;
244 #endif
245 #ifdef reg_ESI
246 int saved_ESI;
247 #endif
248 #ifdef reg_EDI
249 int saved_EDI;
250 #endif
251 #elif defined(TARGET_SPARC)
252 #if defined(reg_REGWPTR)
253 uint32_t *saved_regwptr;
254 #endif
255 #endif
256 #if defined(__sparc__) && !defined(HOST_SOLARIS)
257 int saved_i7, tmp_T0;
258 #endif
259 int ret, interrupt_request;
260 void (*gen_func)(void);
261 TranslationBlock *tb;
262 uint8_t *tc_ptr;
263
264 #if defined(TARGET_I386)
265 /* handle exit of HALTED state */
266 if (env1->hflags & HF_HALTED_MASK) {
267 /* disable halt condition */
268 if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
269 (env1->eflags & IF_MASK)) {
270 env1->hflags &= ~HF_HALTED_MASK;
271 } else {
272 return EXCP_HALTED;
273 }
274 }
275 #elif defined(TARGET_PPC)
276 if (env1->halted) {
277 if (env1->msr[MSR_EE] &&
278 (env1->interrupt_request &
279 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER))) {
280 env1->halted = 0;
281 } else {
282 return EXCP_HALTED;
283 }
284 }
285 #elif defined(TARGET_SPARC)
286 if (env1->halted) {
287 if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
288 (env1->psret != 0)) {
289 env1->halted = 0;
290 } else {
291 return EXCP_HALTED;
292 }
293 }
294 #elif defined(TARGET_ARM)
295 if (env1->halted) {
296 /* An interrupt wakes the CPU even if the I and F CPSR bits are
297 set. */
298 if (env1->interrupt_request
299 & (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD)) {
300 env1->halted = 0;
301 } else {
302 return EXCP_HALTED;
303 }
304 }
305 #elif defined(TARGET_MIPS)
306 if (env1->halted) {
307 if (env1->interrupt_request &
308 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) {
309 env1->halted = 0;
310 } else {
311 return EXCP_HALTED;
312 }
313 }
314 #endif
315
316 cpu_single_env = env1;
317
318 /* first we save global registers */
319 saved_env = env;
320 env = env1;
321 saved_T0 = T0;
322 saved_T1 = T1;
323 #if defined(reg_T2)
324 saved_T2 = T2;
325 #endif
326 #if defined(__sparc__) && !defined(HOST_SOLARIS)
327 /* we also save i7 because longjmp may not restore it */
328 asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
329 #endif
330
331 #if defined(TARGET_I386)
332 #ifdef reg_EAX
333 saved_EAX = EAX;
334 #endif
335 #ifdef reg_ECX
336 saved_ECX = ECX;
337 #endif
338 #ifdef reg_EDX
339 saved_EDX = EDX;
340 #endif
341 #ifdef reg_EBX
342 saved_EBX = EBX;
343 #endif
344 #ifdef reg_ESP
345 saved_ESP = ESP;
346 #endif
347 #ifdef reg_EBP
348 saved_EBP = EBP;
349 #endif
350 #ifdef reg_ESI
351 saved_ESI = ESI;
352 #endif
353 #ifdef reg_EDI
354 saved_EDI = EDI;
355 #endif
356
357 env_to_regs();
358 /* put eflags in CPU temporary format */
359 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
360 DF = 1 - (2 * ((env->eflags >> 10) & 1));
361 CC_OP = CC_OP_EFLAGS;
362 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
363 #elif defined(TARGET_ARM)
364 #elif defined(TARGET_SPARC)
365 #if defined(reg_REGWPTR)
366 saved_regwptr = REGWPTR;
367 #endif
368 #elif defined(TARGET_PPC)
369 #elif defined(TARGET_MIPS)
370 #elif defined(TARGET_SH4)
371 /* XXXXX */
372 #else
373 #error unsupported target CPU
374 #endif
375 env->exception_index = -1;
376
377 /* prepare setjmp context for exception handling */
378 for(;;) {
379 if (setjmp(env->jmp_env) == 0) {
380 env->current_tb = NULL;
381 /* if an exception is pending, we execute it here */
382 if (env->exception_index >= 0) {
383 if (env->exception_index >= EXCP_INTERRUPT) {
384 /* exit request from the cpu execution loop */
385 ret = env->exception_index;
386 break;
387 } else if (env->user_mode_only) {
388 /* if user mode only, we simulate a fake exception
389 which will be hanlded outside the cpu execution
390 loop */
391 #if defined(TARGET_I386)
392 do_interrupt_user(env->exception_index,
393 env->exception_is_int,
394 env->error_code,
395 env->exception_next_eip);
396 #endif
397 ret = env->exception_index;
398 break;
399 } else {
400 #if defined(TARGET_I386)
401 /* simulate a real cpu exception. On i386, it can
402 trigger new exceptions, but we do not handle
403 double or triple faults yet. */
404 do_interrupt(env->exception_index,
405 env->exception_is_int,
406 env->error_code,
407 env->exception_next_eip, 0);
408 #elif defined(TARGET_PPC)
409 do_interrupt(env);
410 #elif defined(TARGET_MIPS)
411 do_interrupt(env);
412 #elif defined(TARGET_SPARC)
413 do_interrupt(env->exception_index);
414 #elif defined(TARGET_ARM)
415 do_interrupt(env);
416 #elif defined(TARGET_SH4)
417 do_interrupt(env);
418 #endif
419 }
420 env->exception_index = -1;
421 }
422 #ifdef USE_KQEMU
423 if (kqemu_is_ok(env) && env->interrupt_request == 0) {
424 int ret;
425 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
426 ret = kqemu_cpu_exec(env);
427 /* put eflags in CPU temporary format */
428 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
429 DF = 1 - (2 * ((env->eflags >> 10) & 1));
430 CC_OP = CC_OP_EFLAGS;
431 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
432 if (ret == 1) {
433 /* exception */
434 longjmp(env->jmp_env, 1);
435 } else if (ret == 2) {
436 /* softmmu execution needed */
437 } else {
438 if (env->interrupt_request != 0) {
439 /* hardware interrupt will be executed just after */
440 } else {
441 /* otherwise, we restart */
442 longjmp(env->jmp_env, 1);
443 }
444 }
445 }
446 #endif
447
448 T0 = 0; /* force lookup of first TB */
449 for(;;) {
450 #if defined(__sparc__) && !defined(HOST_SOLARIS)
451 /* g1 can be modified by some libc? functions */
452 tmp_T0 = T0;
453 #endif
454 interrupt_request = env->interrupt_request;
455 if (__builtin_expect(interrupt_request, 0)) {
456 #if defined(TARGET_I386)
457 /* if hardware interrupt pending, we execute it */
458 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
459 (env->eflags & IF_MASK) &&
460 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
461 int intno;
462 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
463 intno = cpu_get_pic_interrupt(env);
464 if (loglevel & CPU_LOG_TB_IN_ASM) {
465 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
466 }
467 do_interrupt(intno, 0, 0, 0, 1);
468 /* ensure that no TB jump will be modified as
469 the program flow was changed */
470 #if defined(__sparc__) && !defined(HOST_SOLARIS)
471 tmp_T0 = 0;
472 #else
473 T0 = 0;
474 #endif
475 }
476 #elif defined(TARGET_PPC)
477 #if 0
478 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
479 cpu_ppc_reset(env);
480 }
481 #endif
482 if (msr_ee != 0) {
483 if ((interrupt_request & CPU_INTERRUPT_HARD)) {
484 /* Raise it */
485 env->exception_index = EXCP_EXTERNAL;
486 env->error_code = 0;
487 do_interrupt(env);
488 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
489 #if defined(__sparc__) && !defined(HOST_SOLARIS)
490 tmp_T0 = 0;
491 #else
492 T0 = 0;
493 #endif
494 } else if ((interrupt_request & CPU_INTERRUPT_TIMER)) {
495 /* Raise it */
496 env->exception_index = EXCP_DECR;
497 env->error_code = 0;
498 do_interrupt(env);
499 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
500 #if defined(__sparc__) && !defined(HOST_SOLARIS)
501 tmp_T0 = 0;
502 #else
503 T0 = 0;
504 #endif
505 }
506 }
507 #elif defined(TARGET_MIPS)
508 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
509 (env->CP0_Status & (1 << CP0St_IE)) &&
510 (env->CP0_Status & env->CP0_Cause & 0x0000FF00) &&
511 !(env->hflags & MIPS_HFLAG_EXL) &&
512 !(env->hflags & MIPS_HFLAG_ERL) &&
513 !(env->hflags & MIPS_HFLAG_DM)) {
514 /* Raise it */
515 env->exception_index = EXCP_EXT_INTERRUPT;
516 env->error_code = 0;
517 do_interrupt(env);
518 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
519 #if defined(__sparc__) && !defined(HOST_SOLARIS)
520 tmp_T0 = 0;
521 #else
522 T0 = 0;
523 #endif
524 }
525 #elif defined(TARGET_SPARC)
526 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
527 (env->psret != 0)) {
528 int pil = env->interrupt_index & 15;
529 int type = env->interrupt_index & 0xf0;
530
531 if (((type == TT_EXTINT) &&
532 (pil == 15 || pil > env->psrpil)) ||
533 type != TT_EXTINT) {
534 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
535 do_interrupt(env->interrupt_index);
536 env->interrupt_index = 0;
537 #if defined(__sparc__) && !defined(HOST_SOLARIS)
538 tmp_T0 = 0;
539 #else
540 T0 = 0;
541 #endif
542 }
543 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
544 //do_interrupt(0, 0, 0, 0, 0);
545 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
546 } else if (interrupt_request & CPU_INTERRUPT_HALT) {
547 env1->halted = 1;
548 return EXCP_HALTED;
549 }
550 #elif defined(TARGET_ARM)
551 if (interrupt_request & CPU_INTERRUPT_FIQ
552 && !(env->uncached_cpsr & CPSR_F)) {
553 env->exception_index = EXCP_FIQ;
554 do_interrupt(env);
555 }
556 if (interrupt_request & CPU_INTERRUPT_HARD
557 && !(env->uncached_cpsr & CPSR_I)) {
558 env->exception_index = EXCP_IRQ;
559 do_interrupt(env);
560 }
561 #elif defined(TARGET_SH4)
562 /* XXXXX */
563 #endif
564 /* Don't use the cached interupt_request value,
565 do_interrupt may have updated the EXITTB flag. */
566 if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
567 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
568 /* ensure that no TB jump will be modified as
569 the program flow was changed */
570 #if defined(__sparc__) && !defined(HOST_SOLARIS)
571 tmp_T0 = 0;
572 #else
573 T0 = 0;
574 #endif
575 }
576 if (interrupt_request & CPU_INTERRUPT_EXIT) {
577 env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
578 env->exception_index = EXCP_INTERRUPT;
579 cpu_loop_exit();
580 }
581 }
582 #ifdef DEBUG_EXEC
583 if ((loglevel & CPU_LOG_TB_CPU)) {
584 #if defined(TARGET_I386)
585 /* restore flags in standard format */
586 #ifdef reg_EAX
587 env->regs[R_EAX] = EAX;
588 #endif
589 #ifdef reg_EBX
590 env->regs[R_EBX] = EBX;
591 #endif
592 #ifdef reg_ECX
593 env->regs[R_ECX] = ECX;
594 #endif
595 #ifdef reg_EDX
596 env->regs[R_EDX] = EDX;
597 #endif
598 #ifdef reg_ESI
599 env->regs[R_ESI] = ESI;
600 #endif
601 #ifdef reg_EDI
602 env->regs[R_EDI] = EDI;
603 #endif
604 #ifdef reg_EBP
605 env->regs[R_EBP] = EBP;
606 #endif
607 #ifdef reg_ESP
608 env->regs[R_ESP] = ESP;
609 #endif
610 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
611 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
612 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
613 #elif defined(TARGET_ARM)
614 cpu_dump_state(env, logfile, fprintf, 0);
615 #elif defined(TARGET_SPARC)
616 REGWPTR = env->regbase + (env->cwp * 16);
617 env->regwptr = REGWPTR;
618 cpu_dump_state(env, logfile, fprintf, 0);
619 #elif defined(TARGET_PPC)
620 cpu_dump_state(env, logfile, fprintf, 0);
621 #elif defined(TARGET_MIPS)
622 cpu_dump_state(env, logfile, fprintf, 0);
623 #elif defined(TARGET_SH4)
624 cpu_dump_state(env, logfile, fprintf, 0);
625 #else
626 #error unsupported target CPU
627 #endif
628 }
629 #endif
630 tb = tb_find_fast();
631 #ifdef DEBUG_EXEC
632 if ((loglevel & CPU_LOG_EXEC)) {
633 fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
634 (long)tb->tc_ptr, tb->pc,
635 lookup_symbol(tb->pc));
636 }
637 #endif
638 #if defined(__sparc__) && !defined(HOST_SOLARIS)
639 T0 = tmp_T0;
640 #endif
641 /* see if we can patch the calling TB. When the TB
642 spans two pages, we cannot safely do a direct
643 jump. */
644 {
645 if (T0 != 0 &&
646 #if USE_KQEMU
647 (env->kqemu_enabled != 2) &&
648 #endif
649 tb->page_addr[1] == -1
650 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
651 && (tb->cflags & CF_CODE_COPY) ==
652 (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
653 #endif
654 ) {
655 spin_lock(&tb_lock);
656 tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb);
657 #if defined(USE_CODE_COPY)
658 /* propagates the FP use info */
659 ((TranslationBlock *)(T0 & ~3))->cflags |=
660 (tb->cflags & CF_FP_USED);
661 #endif
662 spin_unlock(&tb_lock);
663 }
664 }
665 tc_ptr = tb->tc_ptr;
666 env->current_tb = tb;
667 /* execute the generated code */
668 gen_func = (void *)tc_ptr;
669 #if defined(__sparc__)
670 __asm__ __volatile__("call %0\n\t"
671 "mov %%o7,%%i0"
672 : /* no outputs */
673 : "r" (gen_func)
674 : "i0", "i1", "i2", "i3", "i4", "i5",
675 "l0", "l1", "l2", "l3", "l4", "l5",
676 "l6", "l7");
677 #elif defined(__arm__)
678 asm volatile ("mov pc, %0\n\t"
679 ".global exec_loop\n\t"
680 "exec_loop:\n\t"
681 : /* no outputs */
682 : "r" (gen_func)
683 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
684 #elif defined(TARGET_I386) && defined(USE_CODE_COPY)
685 {
686 if (!(tb->cflags & CF_CODE_COPY)) {
687 if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
688 save_native_fp_state(env);
689 }
690 gen_func();
691 } else {
692 if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
693 restore_native_fp_state(env);
694 }
695 /* we work with native eflags */
696 CC_SRC = cc_table[CC_OP].compute_all();
697 CC_OP = CC_OP_EFLAGS;
698 asm(".globl exec_loop\n"
699 "\n"
700 "debug1:\n"
701 " pushl %%ebp\n"
702 " fs movl %10, %9\n"
703 " fs movl %11, %%eax\n"
704 " andl $0x400, %%eax\n"
705 " fs orl %8, %%eax\n"
706 " pushl %%eax\n"
707 " popf\n"
708 " fs movl %%esp, %12\n"
709 " fs movl %0, %%eax\n"
710 " fs movl %1, %%ecx\n"
711 " fs movl %2, %%edx\n"
712 " fs movl %3, %%ebx\n"
713 " fs movl %4, %%esp\n"
714 " fs movl %5, %%ebp\n"
715 " fs movl %6, %%esi\n"
716 " fs movl %7, %%edi\n"
717 " fs jmp *%9\n"
718 "exec_loop:\n"
719 " fs movl %%esp, %4\n"
720 " fs movl %12, %%esp\n"
721 " fs movl %%eax, %0\n"
722 " fs movl %%ecx, %1\n"
723 " fs movl %%edx, %2\n"
724 " fs movl %%ebx, %3\n"
725 " fs movl %%ebp, %5\n"
726 " fs movl %%esi, %6\n"
727 " fs movl %%edi, %7\n"
728 " pushf\n"
729 " popl %%eax\n"
730 " movl %%eax, %%ecx\n"
731 " andl $0x400, %%ecx\n"
732 " shrl $9, %%ecx\n"
733 " andl $0x8d5, %%eax\n"
734 " fs movl %%eax, %8\n"
735 " movl $1, %%eax\n"
736 " subl %%ecx, %%eax\n"
737 " fs movl %%eax, %11\n"
738 " fs movl %9, %%ebx\n" /* get T0 value */
739 " popl %%ebp\n"
740 :
741 : "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
742 "m" (*(uint8_t *)offsetof(CPUState, regs[1])),
743 "m" (*(uint8_t *)offsetof(CPUState, regs[2])),
744 "m" (*(uint8_t *)offsetof(CPUState, regs[3])),
745 "m" (*(uint8_t *)offsetof(CPUState, regs[4])),
746 "m" (*(uint8_t *)offsetof(CPUState, regs[5])),
747 "m" (*(uint8_t *)offsetof(CPUState, regs[6])),
748 "m" (*(uint8_t *)offsetof(CPUState, regs[7])),
749 "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
750 "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
751 "a" (gen_func),
752 "m" (*(uint8_t *)offsetof(CPUState, df)),
753 "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
754 : "%ecx", "%edx"
755 );
756 }
757 }
758 #elif defined(__ia64)
759 struct fptr {
760 void *ip;
761 void *gp;
762 } fp;
763
764 fp.ip = tc_ptr;
765 fp.gp = code_gen_buffer + 2 * (1 << 20);
766 (*(void (*)(void)) &fp)();
767 #else
768 gen_func();
769 #endif
770 env->current_tb = NULL;
771 /* reset soft MMU for next block (it can currently
772 only be set by a memory fault) */
773 #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
774 if (env->hflags & HF_SOFTMMU_MASK) {
775 env->hflags &= ~HF_SOFTMMU_MASK;
776 /* do not allow linking to another block */
777 T0 = 0;
778 }
779 #endif
780 #if defined(USE_KQEMU)
781 #define MIN_CYCLE_BEFORE_SWITCH (100 * 1000)
782 if (kqemu_is_ok(env) &&
783 (cpu_get_time_fast() - env->last_io_time) >= MIN_CYCLE_BEFORE_SWITCH) {
784 cpu_loop_exit();
785 }
786 #endif
787 }
788 } else {
789 env_to_regs();
790 }
791 } /* for(;;) */
792
793
794 #if defined(TARGET_I386)
795 #if defined(USE_CODE_COPY)
796 if (env->native_fp_regs) {
797 save_native_fp_state(env);
798 }
799 #endif
800 /* restore flags in standard format */
801 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
802
803 /* restore global registers */
804 #ifdef reg_EAX
805 EAX = saved_EAX;
806 #endif
807 #ifdef reg_ECX
808 ECX = saved_ECX;
809 #endif
810 #ifdef reg_EDX
811 EDX = saved_EDX;
812 #endif
813 #ifdef reg_EBX
814 EBX = saved_EBX;
815 #endif
816 #ifdef reg_ESP
817 ESP = saved_ESP;
818 #endif
819 #ifdef reg_EBP
820 EBP = saved_EBP;
821 #endif
822 #ifdef reg_ESI
823 ESI = saved_ESI;
824 #endif
825 #ifdef reg_EDI
826 EDI = saved_EDI;
827 #endif
828 #elif defined(TARGET_ARM)
829 /* XXX: Save/restore host fpu exception state?. */
830 #elif defined(TARGET_SPARC)
831 #if defined(reg_REGWPTR)
832 REGWPTR = saved_regwptr;
833 #endif
834 #elif defined(TARGET_PPC)
835 #elif defined(TARGET_MIPS)
836 #elif defined(TARGET_SH4)
837 /* XXXXX */
838 #else
839 #error unsupported target CPU
840 #endif
841 #if defined(__sparc__) && !defined(HOST_SOLARIS)
842 asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
843 #endif
844 T0 = saved_T0;
845 T1 = saved_T1;
846 #if defined(reg_T2)
847 T2 = saved_T2;
848 #endif
849 env = saved_env;
850 /* fail safe : never use cpu_single_env outside cpu_exec() */
851 cpu_single_env = NULL;
852 return ret;
853 }
854
855 /* must only be called from the generated code as an exception can be
856 generated */
857 void tb_invalidate_page_range(target_ulong start, target_ulong end)
858 {
859 /* XXX: cannot enable it yet because it yields to MMU exception
860 where NIP != read address on PowerPC */
861 #if 0
862 target_ulong phys_addr;
863 phys_addr = get_phys_addr_code(env, start);
864 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
865 #endif
866 }
867
868 #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
869
870 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
871 {
872 CPUX86State *saved_env;
873
874 saved_env = env;
875 env = s;
876 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
877 selector &= 0xffff;
878 cpu_x86_load_seg_cache(env, seg_reg, selector,
879 (selector << 4), 0xffff, 0);
880 } else {
881 load_seg(seg_reg, selector);
882 }
883 env = saved_env;
884 }
885
886 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
887 {
888 CPUX86State *saved_env;
889
890 saved_env = env;
891 env = s;
892
893 helper_fsave((target_ulong)ptr, data32);
894
895 env = saved_env;
896 }
897
898 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
899 {
900 CPUX86State *saved_env;
901
902 saved_env = env;
903 env = s;
904
905 helper_frstor((target_ulong)ptr, data32);
906
907 env = saved_env;
908 }
909
910 #endif /* TARGET_I386 */
911
912 #if !defined(CONFIG_SOFTMMU)
913
914 #if defined(TARGET_I386)
915
916 /* 'pc' is the host PC at which the exception was raised. 'address' is
917 the effective address of the memory exception. 'is_write' is 1 if a
918 write caused the exception and otherwise 0'. 'old_set' is the
919 signal set which should be restored */
920 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
921 int is_write, sigset_t *old_set,
922 void *puc)
923 {
924 TranslationBlock *tb;
925 int ret;
926
927 if (cpu_single_env)
928 env = cpu_single_env; /* XXX: find a correct solution for multithread */
929 #if defined(DEBUG_SIGNAL)
930 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
931 pc, address, is_write, *(unsigned long *)old_set);
932 #endif
933 /* XXX: locking issue */
934 if (is_write && page_unprotect(h2g(address), pc, puc)) {
935 return 1;
936 }
937
938 /* see if it is an MMU fault */
939 ret = cpu_x86_handle_mmu_fault(env, address, is_write,
940 ((env->hflags & HF_CPL_MASK) == 3), 0);
941 if (ret < 0)
942 return 0; /* not an MMU fault */
943 if (ret == 0)
944 return 1; /* the MMU fault was handled without causing real CPU fault */
945 /* now we have a real cpu fault */
946 tb = tb_find_pc(pc);
947 if (tb) {
948 /* the PC is inside the translated code. It means that we have
949 a virtual CPU fault */
950 cpu_restore_state(tb, env, pc, puc);
951 }
952 if (ret == 1) {
953 #if 0
954 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
955 env->eip, env->cr[2], env->error_code);
956 #endif
957 /* we restore the process signal mask as the sigreturn should
958 do it (XXX: use sigsetjmp) */
959 sigprocmask(SIG_SETMASK, old_set, NULL);
960 raise_exception_err(env->exception_index, env->error_code);
961 } else {
962 /* activate soft MMU for this block */
963 env->hflags |= HF_SOFTMMU_MASK;
964 cpu_resume_from_signal(env, puc);
965 }
966 /* never comes here */
967 return 1;
968 }
969
970 #elif defined(TARGET_ARM)
971 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
972 int is_write, sigset_t *old_set,
973 void *puc)
974 {
975 TranslationBlock *tb;
976 int ret;
977
978 if (cpu_single_env)
979 env = cpu_single_env; /* XXX: find a correct solution for multithread */
980 #if defined(DEBUG_SIGNAL)
981 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
982 pc, address, is_write, *(unsigned long *)old_set);
983 #endif
984 /* XXX: locking issue */
985 if (is_write && page_unprotect(h2g(address), pc, puc)) {
986 return 1;
987 }
988 /* see if it is an MMU fault */
989 ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0);
990 if (ret < 0)
991 return 0; /* not an MMU fault */
992 if (ret == 0)
993 return 1; /* the MMU fault was handled without causing real CPU fault */
994 /* now we have a real cpu fault */
995 tb = tb_find_pc(pc);
996 if (tb) {
997 /* the PC is inside the translated code. It means that we have
998 a virtual CPU fault */
999 cpu_restore_state(tb, env, pc, puc);
1000 }
1001 /* we restore the process signal mask as the sigreturn should
1002 do it (XXX: use sigsetjmp) */
1003 sigprocmask(SIG_SETMASK, old_set, NULL);
1004 cpu_loop_exit();
1005 }
1006 #elif defined(TARGET_SPARC)
1007 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1008 int is_write, sigset_t *old_set,
1009 void *puc)
1010 {
1011 TranslationBlock *tb;
1012 int ret;
1013
1014 if (cpu_single_env)
1015 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1016 #if defined(DEBUG_SIGNAL)
1017 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1018 pc, address, is_write, *(unsigned long *)old_set);
1019 #endif
1020 /* XXX: locking issue */
1021 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1022 return 1;
1023 }
1024 /* see if it is an MMU fault */
1025 ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0);
1026 if (ret < 0)
1027 return 0; /* not an MMU fault */
1028 if (ret == 0)
1029 return 1; /* the MMU fault was handled without causing real CPU fault */
1030 /* now we have a real cpu fault */
1031 tb = tb_find_pc(pc);
1032 if (tb) {
1033 /* the PC is inside the translated code. It means that we have
1034 a virtual CPU fault */
1035 cpu_restore_state(tb, env, pc, puc);
1036 }
1037 /* we restore the process signal mask as the sigreturn should
1038 do it (XXX: use sigsetjmp) */
1039 sigprocmask(SIG_SETMASK, old_set, NULL);
1040 cpu_loop_exit();
1041 }
1042 #elif defined (TARGET_PPC)
1043 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1044 int is_write, sigset_t *old_set,
1045 void *puc)
1046 {
1047 TranslationBlock *tb;
1048 int ret;
1049
1050 if (cpu_single_env)
1051 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1052 #if defined(DEBUG_SIGNAL)
1053 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1054 pc, address, is_write, *(unsigned long *)old_set);
1055 #endif
1056 /* XXX: locking issue */
1057 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1058 return 1;
1059 }
1060
1061 /* see if it is an MMU fault */
1062 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
1063 if (ret < 0)
1064 return 0; /* not an MMU fault */
1065 if (ret == 0)
1066 return 1; /* the MMU fault was handled without causing real CPU fault */
1067
1068 /* now we have a real cpu fault */
1069 tb = tb_find_pc(pc);
1070 if (tb) {
1071 /* the PC is inside the translated code. It means that we have
1072 a virtual CPU fault */
1073 cpu_restore_state(tb, env, pc, puc);
1074 }
1075 if (ret == 1) {
1076 #if 0
1077 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1078 env->nip, env->error_code, tb);
1079 #endif
1080 /* we restore the process signal mask as the sigreturn should
1081 do it (XXX: use sigsetjmp) */
1082 sigprocmask(SIG_SETMASK, old_set, NULL);
1083 do_raise_exception_err(env->exception_index, env->error_code);
1084 } else {
1085 /* activate soft MMU for this block */
1086 cpu_resume_from_signal(env, puc);
1087 }
1088 /* never comes here */
1089 return 1;
1090 }
1091
1092 #elif defined (TARGET_MIPS)
1093 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1094 int is_write, sigset_t *old_set,
1095 void *puc)
1096 {
1097 TranslationBlock *tb;
1098 int ret;
1099
1100 if (cpu_single_env)
1101 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1102 #if defined(DEBUG_SIGNAL)
1103 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1104 pc, address, is_write, *(unsigned long *)old_set);
1105 #endif
1106 /* XXX: locking issue */
1107 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1108 return 1;
1109 }
1110
1111 /* see if it is an MMU fault */
1112 ret = cpu_mips_handle_mmu_fault(env, address, is_write, 1, 0);
1113 if (ret < 0)
1114 return 0; /* not an MMU fault */
1115 if (ret == 0)
1116 return 1; /* the MMU fault was handled without causing real CPU fault */
1117
1118 /* now we have a real cpu fault */
1119 tb = tb_find_pc(pc);
1120 if (tb) {
1121 /* the PC is inside the translated code. It means that we have
1122 a virtual CPU fault */
1123 cpu_restore_state(tb, env, pc, puc);
1124 }
1125 if (ret == 1) {
1126 #if 0
1127 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1128 env->nip, env->error_code, tb);
1129 #endif
1130 /* we restore the process signal mask as the sigreturn should
1131 do it (XXX: use sigsetjmp) */
1132 sigprocmask(SIG_SETMASK, old_set, NULL);
1133 do_raise_exception_err(env->exception_index, env->error_code);
1134 } else {
1135 /* activate soft MMU for this block */
1136 cpu_resume_from_signal(env, puc);
1137 }
1138 /* never comes here */
1139 return 1;
1140 }
1141
1142 #elif defined (TARGET_SH4)
1143 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1144 int is_write, sigset_t *old_set,
1145 void *puc)
1146 {
1147 TranslationBlock *tb;
1148 int ret;
1149
1150 if (cpu_single_env)
1151 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1152 #if defined(DEBUG_SIGNAL)
1153 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1154 pc, address, is_write, *(unsigned long *)old_set);
1155 #endif
1156 /* XXX: locking issue */
1157 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1158 return 1;
1159 }
1160
1161 /* see if it is an MMU fault */
1162 ret = cpu_sh4_handle_mmu_fault(env, address, is_write, 1, 0);
1163 if (ret < 0)
1164 return 0; /* not an MMU fault */
1165 if (ret == 0)
1166 return 1; /* the MMU fault was handled without causing real CPU fault */
1167
1168 /* now we have a real cpu fault */
1169 tb = tb_find_pc(pc);
1170 if (tb) {
1171 /* the PC is inside the translated code. It means that we have
1172 a virtual CPU fault */
1173 cpu_restore_state(tb, env, pc, puc);
1174 }
1175 #if 0
1176 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1177 env->nip, env->error_code, tb);
1178 #endif
1179 /* we restore the process signal mask as the sigreturn should
1180 do it (XXX: use sigsetjmp) */
1181 sigprocmask(SIG_SETMASK, old_set, NULL);
1182 cpu_loop_exit();
1183 /* never comes here */
1184 return 1;
1185 }
1186 #else
1187 #error unsupported target CPU
1188 #endif
1189
1190 #if defined(__i386__)
1191
1192 #if defined(USE_CODE_COPY)
1193 static void cpu_send_trap(unsigned long pc, int trap,
1194 struct ucontext *uc)
1195 {
1196 TranslationBlock *tb;
1197
1198 if (cpu_single_env)
1199 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1200 /* now we have a real cpu fault */
1201 tb = tb_find_pc(pc);
1202 if (tb) {
1203 /* the PC is inside the translated code. It means that we have
1204 a virtual CPU fault */
1205 cpu_restore_state(tb, env, pc, uc);
1206 }
1207 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
1208 raise_exception_err(trap, env->error_code);
1209 }
1210 #endif
1211
1212 int cpu_signal_handler(int host_signum, struct siginfo *info,
1213 void *puc)
1214 {
1215 struct ucontext *uc = puc;
1216 unsigned long pc;
1217 int trapno;
1218
1219 #ifndef REG_EIP
1220 /* for glibc 2.1 */
1221 #define REG_EIP EIP
1222 #define REG_ERR ERR
1223 #define REG_TRAPNO TRAPNO
1224 #endif
1225 pc = uc->uc_mcontext.gregs[REG_EIP];
1226 trapno = uc->uc_mcontext.gregs[REG_TRAPNO];
1227 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
1228 if (trapno == 0x00 || trapno == 0x05) {
1229 /* send division by zero or bound exception */
1230 cpu_send_trap(pc, trapno, uc);
1231 return 1;
1232 } else
1233 #endif
1234 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1235 trapno == 0xe ?
1236 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1237 &uc->uc_sigmask, puc);
1238 }
1239
1240 #elif defined(__x86_64__)
1241
1242 int cpu_signal_handler(int host_signum, struct siginfo *info,
1243 void *puc)
1244 {
1245 struct ucontext *uc = puc;
1246 unsigned long pc;
1247
1248 pc = uc->uc_mcontext.gregs[REG_RIP];
1249 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1250 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
1251 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1252 &uc->uc_sigmask, puc);
1253 }
1254
1255 #elif defined(__powerpc__)
1256
1257 /***********************************************************************
1258 * signal context platform-specific definitions
1259 * From Wine
1260 */
1261 #ifdef linux
1262 /* All Registers access - only for local access */
1263 # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
1264 /* Gpr Registers access */
1265 # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
1266 # define IAR_sig(context) REG_sig(nip, context) /* Program counter */
1267 # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
1268 # define CTR_sig(context) REG_sig(ctr, context) /* Count register */
1269 # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
1270 # define LR_sig(context) REG_sig(link, context) /* Link register */
1271 # define CR_sig(context) REG_sig(ccr, context) /* Condition register */
1272 /* Float Registers access */
1273 # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
1274 # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1275 /* Exception Registers access */
1276 # define DAR_sig(context) REG_sig(dar, context)
1277 # define DSISR_sig(context) REG_sig(dsisr, context)
1278 # define TRAP_sig(context) REG_sig(trap, context)
1279 #endif /* linux */
1280
1281 #ifdef __APPLE__
1282 # include <sys/ucontext.h>
1283 typedef struct ucontext SIGCONTEXT;
1284 /* All Registers access - only for local access */
1285 # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
1286 # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
1287 # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
1288 # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
1289 /* Gpr Registers access */
1290 # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
1291 # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
1292 # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
1293 # define CTR_sig(context) REG_sig(ctr, context)
1294 # define XER_sig(context) REG_sig(xer, context) /* Link register */
1295 # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
1296 # define CR_sig(context) REG_sig(cr, context) /* Condition register */
1297 /* Float Registers access */
1298 # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
1299 # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
1300 /* Exception Registers access */
1301 # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
1302 # define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
1303 # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1304 #endif /* __APPLE__ */
1305
1306 int cpu_signal_handler(int host_signum, struct siginfo *info,
1307 void *puc)
1308 {
1309 struct ucontext *uc = puc;
1310 unsigned long pc;
1311 int is_write;
1312
1313 pc = IAR_sig(uc);
1314 is_write = 0;
1315 #if 0
1316 /* ppc 4xx case */
1317 if (DSISR_sig(uc) & 0x00800000)
1318 is_write = 1;
1319 #else
1320 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
1321 is_write = 1;
1322 #endif
1323 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1324 is_write, &uc->uc_sigmask, puc);
1325 }
1326
1327 #elif defined(__alpha__)
1328
1329 int cpu_signal_handler(int host_signum, struct siginfo *info,
1330 void *puc)
1331 {
1332 struct ucontext *uc = puc;
1333 uint32_t *pc = uc->uc_mcontext.sc_pc;
1334 uint32_t insn = *pc;
1335 int is_write = 0;
1336
1337 /* XXX: need kernel patch to get write flag faster */
1338 switch (insn >> 26) {
1339 case 0x0d: // stw
1340 case 0x0e: // stb
1341 case 0x0f: // stq_u
1342 case 0x24: // stf
1343 case 0x25: // stg
1344 case 0x26: // sts
1345 case 0x27: // stt
1346 case 0x2c: // stl
1347 case 0x2d: // stq
1348 case 0x2e: // stl_c
1349 case 0x2f: // stq_c
1350 is_write = 1;
1351 }
1352
1353 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1354 is_write, &uc->uc_sigmask, puc);
1355 }
1356 #elif defined(__sparc__)
1357
1358 int cpu_signal_handler(int host_signum, struct siginfo *info,
1359 void *puc)
1360 {
1361 uint32_t *regs = (uint32_t *)(info + 1);
1362 void *sigmask = (regs + 20);
1363 unsigned long pc;
1364 int is_write;
1365 uint32_t insn;
1366
1367 /* XXX: is there a standard glibc define ? */
1368 pc = regs[1];
1369 /* XXX: need kernel patch to get write flag faster */
1370 is_write = 0;
1371 insn = *(uint32_t *)pc;
1372 if ((insn >> 30) == 3) {
1373 switch((insn >> 19) & 0x3f) {
1374 case 0x05: // stb
1375 case 0x06: // sth
1376 case 0x04: // st
1377 case 0x07: // std
1378 case 0x24: // stf
1379 case 0x27: // stdf
1380 case 0x25: // stfsr
1381 is_write = 1;
1382 break;
1383 }
1384 }
1385 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1386 is_write, sigmask, NULL);
1387 }
1388
1389 #elif defined(__arm__)
1390
1391 int cpu_signal_handler(int host_signum, struct siginfo *info,
1392 void *puc)
1393 {
1394 struct ucontext *uc = puc;
1395 unsigned long pc;
1396 int is_write;
1397
1398 pc = uc->uc_mcontext.gregs[R15];
1399 /* XXX: compute is_write */
1400 is_write = 0;
1401 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1402 is_write,
1403 &uc->uc_sigmask);
1404 }
1405
1406 #elif defined(__mc68000)
1407
1408 int cpu_signal_handler(int host_signum, struct siginfo *info,
1409 void *puc)
1410 {
1411 struct ucontext *uc = puc;
1412 unsigned long pc;
1413 int is_write;
1414
1415 pc = uc->uc_mcontext.gregs[16];
1416 /* XXX: compute is_write */
1417 is_write = 0;
1418 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1419 is_write,
1420 &uc->uc_sigmask, puc);
1421 }
1422
1423 #elif defined(__ia64)
1424
1425 #ifndef __ISR_VALID
1426 /* This ought to be in <bits/siginfo.h>... */
1427 # define __ISR_VALID 1
1428 #endif
1429
1430 int cpu_signal_handler(int host_signum, struct siginfo *info, void *puc)
1431 {
1432 struct ucontext *uc = puc;
1433 unsigned long ip;
1434 int is_write = 0;
1435
1436 ip = uc->uc_mcontext.sc_ip;
1437 switch (host_signum) {
1438 case SIGILL:
1439 case SIGFPE:
1440 case SIGSEGV:
1441 case SIGBUS:
1442 case SIGTRAP:
1443 if (info->si_code && (info->si_segvflags & __ISR_VALID))
1444 /* ISR.W (write-access) is bit 33: */
1445 is_write = (info->si_isr >> 33) & 1;
1446 break;
1447
1448 default:
1449 break;
1450 }
1451 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1452 is_write,
1453 &uc->uc_sigmask, puc);
1454 }
1455
1456 #elif defined(__s390__)
1457
1458 int cpu_signal_handler(int host_signum, struct siginfo *info,
1459 void *puc)
1460 {
1461 struct ucontext *uc = puc;
1462 unsigned long pc;
1463 int is_write;
1464
1465 pc = uc->uc_mcontext.psw.addr;
1466 /* XXX: compute is_write */
1467 is_write = 0;
1468 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1469 is_write,
1470 &uc->uc_sigmask, puc);
1471 }
1472
1473 #else
1474
1475 #error host CPU specific signal handler needed
1476
1477 #endif
1478
1479 #endif /* !defined(CONFIG_SOFTMMU) */
Qemu copy for testing