cputlb.c

   1 /*
   2  *  Common CPU TLB handling
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "config.h"
  21 #include "cpu.h"
  22 #include "exec-all.h"
  23 #include "memory.h"
  24
  25 #include "cputlb.h"
  26
  27 #include "memory-internal.h"
  28
  29 //#define DEBUG_TLB
  30 //#define DEBUG_TLB_CHECK
  31
  32 /* statistics */
  33 int tlb_flush_count;
  34
  35 static const CPUTLBEntry s_cputlb_empty_entry = {
  36     .addr_read  = -1,
  37     .addr_write = -1,
  38     .addr_code  = -1,
  39     .addend     = -1,
  40 };
  41
  42 /* NOTE:
  43  * If flush_global is true (the usual case), flush all tlb entries.
  44  * If flush_global is false, flush (at least) all tlb entries not
  45  * marked global.
  46  *
  47  * Since QEMU doesn't currently implement a global/not-global flag
  48  * for tlb entries, at the moment tlb_flush() will also flush all
  49  * tlb entries in the flush_global == false case. This is OK because
  50  * CPU architectures generally permit an implementation to drop
  51  * entries from the TLB at any time, so flushing more entries than
  52  * required is only an efficiency issue, not a correctness issue.
  53  */
  54 void tlb_flush(CPUArchState *env, int flush_global)
  55 {
  56     int i;
  57
  58 #if defined(DEBUG_TLB)
  59     printf("tlb_flush:\n");
  60 #endif
  61     /* must reset current TB so that interrupts cannot modify the
  62        links while we are modifying them */
  63     env->current_tb = NULL;
  64
  65     for (i = 0; i < CPU_TLB_SIZE; i++) {
  66         int mmu_idx;
  67
  68         for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
  69             env->tlb_table[mmu_idx][i] = s_cputlb_empty_entry;
  70         }
  71     }
  72
  73     memset(env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *));
  74
  75     env->tlb_flush_addr = -1;
  76     env->tlb_flush_mask = 0;
  77     tlb_flush_count++;
  78 }
  79
  80 static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr)
  81 {
  82     if (addr == (tlb_entry->addr_read &
  83                  (TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
  84         addr == (tlb_entry->addr_write &
  85                  (TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
  86         addr == (tlb_entry->addr_code &
  87                  (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
  88         *tlb_entry = s_cputlb_empty_entry;
  89     }
  90 }
  91
  92 void tlb_flush_page(CPUArchState *env, target_ulong addr)
  93 {
  94     int i;
  95     int mmu_idx;
  96
  97 #if defined(DEBUG_TLB)
  98     printf("tlb_flush_page: " TARGET_FMT_lx "\n", addr);
  99 #endif
 100     /* Check if we need to flush due to large pages.  */
 101     if ((addr & env->tlb_flush_mask) == env->tlb_flush_addr) {
 102 #if defined(DEBUG_TLB)
 103         printf("tlb_flush_page: forced full flush ("
 104                TARGET_FMT_lx "/" TARGET_FMT_lx ")\n",
 105                env->tlb_flush_addr, env->tlb_flush_mask);
 106 #endif
 107         tlb_flush(env, 1);
 108         return;
 109     }
 110     /* must reset current TB so that interrupts cannot modify the
 111        links while we are modifying them */
 112     env->current_tb = NULL;
 113
 114     addr &= TARGET_PAGE_MASK;
 115     i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 116     for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
 117         tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr);
 118     }
 119
 120     tb_flush_jmp_cache(env, addr);
 121 }
 122
 123 /* update the TLBs so that writes to code in the virtual page 'addr'
 124    can be detected */
 125 void tlb_protect_code(ram_addr_t ram_addr)
 126 {
 127     cpu_physical_memory_reset_dirty(ram_addr,
 128                                     ram_addr + TARGET_PAGE_SIZE,
 129                                     CODE_DIRTY_FLAG);
 130 }
 131
 132 /* update the TLB so that writes in physical page 'phys_addr' are no longer
 133    tested for self modifying code */
 134 void tlb_unprotect_code_phys(CPUArchState *env, ram_addr_t ram_addr,
 135                              target_ulong vaddr)
 136 {
 137     cpu_physical_memory_set_dirty_flags(ram_addr, CODE_DIRTY_FLAG);
 138 }
 139
 140 static bool tlb_is_dirty_ram(CPUTLBEntry *tlbe)
 141 {
 142     return (tlbe->addr_write & (TLB_INVALID_MASK|TLB_MMIO|TLB_NOTDIRTY)) == 0;
 143 }
 144
 145 void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, uintptr_t start,
 146                            uintptr_t length)
 147 {
 148     uintptr_t addr;
 149
 150     if (tlb_is_dirty_ram(tlb_entry)) {
 151         addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend;
 152         if ((addr - start) < length) {
 153             tlb_entry->addr_write |= TLB_NOTDIRTY;
 154         }
 155     }
 156 }
 157
 158 static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry)
 159 {
 160     ram_addr_t ram_addr;
 161     void *p;
 162
 163     if (tlb_is_dirty_ram(tlb_entry)) {
 164         p = (void *)(uintptr_t)((tlb_entry->addr_write & TARGET_PAGE_MASK)
 165             + tlb_entry->addend);
 166         ram_addr = qemu_ram_addr_from_host_nofail(p);
 167         if (!cpu_physical_memory_is_dirty(ram_addr)) {
 168             tlb_entry->addr_write |= TLB_NOTDIRTY;
 169         }
 170     }
 171 }
 172
 173 void cpu_tlb_reset_dirty_all(ram_addr_t start1, ram_addr_t length)
 174 {
 175     CPUArchState *env;
 176
 177     for (env = first_cpu; env != NULL; env = env->next_cpu) {
 178         int mmu_idx;
 179
 180         for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
 181             unsigned int i;
 182
 183             for (i = 0; i < CPU_TLB_SIZE; i++) {
 184                 tlb_reset_dirty_range(&env->tlb_table[mmu_idx][i],
 185                                       start1, length);
 186             }
 187         }
 188     }
 189 }
 190
 191 static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr)
 192 {
 193     if (tlb_entry->addr_write == (vaddr | TLB_NOTDIRTY)) {
 194         tlb_entry->addr_write = vaddr;
 195     }
 196 }
 197
 198 /* update the TLB corresponding to virtual page vaddr
 199    so that it is no longer dirty */
 200 void tlb_set_dirty(CPUArchState *env, target_ulong vaddr)
 201 {
 202     int i;
 203     int mmu_idx;
 204
 205     vaddr &= TARGET_PAGE_MASK;
 206     i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 207     for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
 208         tlb_set_dirty1(&env->tlb_table[mmu_idx][i], vaddr);
 209     }
 210 }
 211
 212 /* Our TLB does not support large pages, so remember the area covered by
 213    large pages and trigger a full TLB flush if these are invalidated.  */
 214 static void tlb_add_large_page(CPUArchState *env, target_ulong vaddr,
 215                                target_ulong size)
 216 {
 217     target_ulong mask = ~(size - 1);
 218
 219     if (env->tlb_flush_addr == (target_ulong)-1) {
 220         env->tlb_flush_addr = vaddr & mask;
 221         env->tlb_flush_mask = mask;
 222         return;
 223     }
 224     /* Extend the existing region to include the new page.
 225        This is a compromise between unnecessary flushes and the cost
 226        of maintaining a full variable size TLB.  */
 227     mask &= env->tlb_flush_mask;
 228     while (((env->tlb_flush_addr ^ vaddr) & mask) != 0) {
 229         mask <<= 1;
 230     }
 231     env->tlb_flush_addr &= mask;
 232     env->tlb_flush_mask = mask;
 233 }
 234
 235 /* Add a new TLB entry. At most one entry for a given virtual address
 236    is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the
 237    supplied size is only used by tlb_flush_page.  */
 238 void tlb_set_page(CPUArchState *env, target_ulong vaddr,
 239                   target_phys_addr_t paddr, int prot,
 240                   int mmu_idx, target_ulong size)
 241 {
 242     MemoryRegionSection *section;
 243     unsigned int index;
 244     target_ulong address;
 245     target_ulong code_address;
 246     uintptr_t addend;
 247     CPUTLBEntry *te;
 248     target_phys_addr_t iotlb;
 249
 250     assert(size >= TARGET_PAGE_SIZE);
 251     if (size != TARGET_PAGE_SIZE) {
 252         tlb_add_large_page(env, vaddr, size);
 253     }
 254     section = phys_page_find(paddr >> TARGET_PAGE_BITS);
 255 #if defined(DEBUG_TLB)
 256     printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx
 257            " prot=%x idx=%d pd=0x%08lx\n",
 258            vaddr, paddr, prot, mmu_idx, pd);
 259 #endif
 260
 261     address = vaddr;
 262     if (!(memory_region_is_ram(section->mr) ||
 263           memory_region_is_romd(section->mr))) {
 264         /* IO memory case (romd handled later) */
 265         address |= TLB_MMIO;
 266     }
 267     if (memory_region_is_ram(section->mr) ||
 268         memory_region_is_romd(section->mr)) {
 269         addend = (uintptr_t)memory_region_get_ram_ptr(section->mr)
 270         + memory_region_section_addr(section, paddr);
 271     } else {
 272         addend = 0;
 273     }
 274
 275     code_address = address;
 276     iotlb = memory_region_section_get_iotlb(env, section, vaddr, paddr, prot,
 277                                             &address);
 278
 279     index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 280     env->iotlb[mmu_idx][index] = iotlb - vaddr;
 281     te = &env->tlb_table[mmu_idx][index];
 282     te->addend = addend - vaddr;
 283     if (prot & PAGE_READ) {
 284         te->addr_read = address;
 285     } else {
 286         te->addr_read = -1;
 287     }
 288
 289     if (prot & PAGE_EXEC) {
 290         te->addr_code = code_address;
 291     } else {
 292         te->addr_code = -1;
 293     }
 294     if (prot & PAGE_WRITE) {
 295         if ((memory_region_is_ram(section->mr) && section->readonly)
 296             || memory_region_is_romd(section->mr)) {
 297             /* Write access calls the I/O callback.  */
 298             te->addr_write = address | TLB_MMIO;
 299         } else if (memory_region_is_ram(section->mr)
 300                    && !cpu_physical_memory_is_dirty(
 301                            section->mr->ram_addr
 302                            + memory_region_section_addr(section, paddr))) {
 303             te->addr_write = address | TLB_NOTDIRTY;
 304         } else {
 305             te->addr_write = address;
 306         }
 307     } else {
 308         te->addr_write = -1;
 309     }
 310 }
 311
 312 /* NOTE: this function can trigger an exception */
 313 /* NOTE2: the returned address is not exactly the physical address: it
 314  * is actually a ram_addr_t (in system mode; the user mode emulation
 315  * version of this function returns a guest virtual address).
 316  */
 317 tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
 318 {
 319     int mmu_idx, page_index, pd;
 320     void *p;
 321     MemoryRegion *mr;
 322
 323     page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 324     mmu_idx = cpu_mmu_index(env1);
 325     if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
 326                  (addr & TARGET_PAGE_MASK))) {
 327         cpu_ldub_code(env1, addr);
 328     }
 329     pd = env1->iotlb[mmu_idx][page_index] & ~TARGET_PAGE_MASK;
 330     mr = iotlb_to_region(pd);
 331     if (memory_region_is_unassigned(mr)) {
 332 #if defined(TARGET_ALPHA) || defined(TARGET_MIPS) || defined(TARGET_SPARC)
 333         cpu_unassigned_access(env1, addr, 0, 1, 0, 4);
 334 #else
 335         cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x"
 336                   TARGET_FMT_lx "\n", addr);
 337 #endif
 338     }
 339     p = (void *)((uintptr_t)addr + env1->tlb_table[mmu_idx][page_index].addend);
 340     return qemu_ram_addr_from_host_nofail(p);
 341 }
 342
 343 #define MMUSUFFIX _cmmu
 344 #undef GETPC
 345 #define GETPC() ((uintptr_t)0)
 346 #define SOFTMMU_CODE_ACCESS
 347
 348 #define SHIFT 0
 349 #include "softmmu_template.h"
 350
 351 #define SHIFT 1
 352 #include "softmmu_template.h"
 353
 354 #define SHIFT 2
 355 #include "softmmu_template.h"
 356
 357 #define SHIFT 3
 358 #include "softmmu_template.h"
 359
 360 #undef env