docs/memory.txt

   1 The memory API
   2 ==============
   3
   4 The memory API models the memory and I/O buses and controllers of a QEMU
   5 machine.  It attempts to allow modelling of:
   6
   7  - ordinary RAM
   8  - memory-mapped I/O (MMIO)
   9  - memory controllers that can dynamically reroute physical memory regions
  10    to different destinations
  11
  12 The memory model provides support for
  13
  14  - tracking RAM changes by the guest
  15  - setting up coalesced memory for kvm
  16  - setting up ioeventfd regions for kvm
  17
  18 Memory is modelled as an acyclic graph of MemoryRegion objects.  Sinks
  19 (leaves) are RAM and MMIO regions, while other nodes represent
  20 buses, memory controllers, and memory regions that have been rerouted.
  21
  22 In addition to MemoryRegion objects, the memory API provides AddressSpace
  23 objects for every root and possibly for intermediate MemoryRegions too.
  24 These represent memory as seen from the CPU or a device's viewpoint.
  25
  26 Types of regions
  27 ----------------
  28
  29 There are four types of memory regions (all represented by a single C type
  30 MemoryRegion):
  31
  32 - RAM: a RAM region is simply a range of host memory that can be made available
  33   to the guest.
  34
  35 - MMIO: a range of guest memory that is implemented by host callbacks;
  36   each read or write causes a callback to be called on the host.
  37
  38 - container: a container simply includes other memory regions, each at
  39   a different offset.  Containers are useful for grouping several regions
  40   into one unit.  For example, a PCI BAR may be composed of a RAM region
  41   and an MMIO region.
  42
  43   A container's subregions are usually non-overlapping.  In some cases it is
  44   useful to have overlapping regions; for example a memory controller that
  45   can overlay a subregion of RAM with MMIO or ROM, or a PCI controller
  46   that does not prevent card from claiming overlapping BARs.
  47
  48 - alias: a subsection of another region.  Aliases allow a region to be
  49   split apart into discontiguous regions.  Examples of uses are memory banks
  50   used when the guest address space is smaller than the amount of RAM
  51   addressed, or a memory controller that splits main memory to expose a "PCI
  52   hole".  Aliases may point to any type of region, including other aliases,
  53   but an alias may not point back to itself, directly or indirectly.
  54
  55 It is valid to add subregions to a region which is not a pure container
  56 (that is, to an MMIO, RAM or ROM region). This means that the region
  57 will act like a container, except that any addresses within the container's
  58 region which are not claimed by any subregion are handled by the
  59 container itself (ie by its MMIO callbacks or RAM backing). However
  60 it is generally possible to achieve the same effect with a pure container
  61 one of whose subregions is a low priority "background" region covering
  62 the whole address range; this is often clearer and is preferred.
  63 Subregions cannot be added to an alias region.
  64
  65 Region names
  66 ------------
  67
  68 Regions are assigned names by the constructor.  For most regions these are
  69 only used for debugging purposes, but RAM regions also use the name to identify
  70 live migration sections.  This means that RAM region names need to have ABI
  71 stability.
  72
  73 Region lifecycle
  74 ----------------
  75
  76 A region is created by one of the constructor functions (memory_region_init*())
  77 and destroyed by the destructor (memory_region_destroy()).  In between,
  78 a region can be added to an address space by using memory_region_add_subregion()
  79 and removed using memory_region_del_subregion().  Region attributes may be
  80 changed at any point; they take effect once the region becomes exposed to the
  81 guest.
  82
  83 Overlapping regions and priority
  84 --------------------------------
  85 Usually, regions may not overlap each other; a memory address decodes into
  86 exactly one target.  In some cases it is useful to allow regions to overlap,
  87 and sometimes to control which of an overlapping regions is visible to the
  88 guest.  This is done with memory_region_add_subregion_overlap(), which
  89 allows the region to overlap any other region in the same container, and
  90 specifies a priority that allows the core to decide which of two regions at
  91 the same address are visible (highest wins).
  92 Priority values are signed, and the default value is zero. This means that
  93 you can use memory_region_add_subregion_overlap() both to specify a region
  94 that must sit 'above' any others (with a positive priority) and also a
  95 background region that sits 'below' others (with a negative priority).
  96
  97 If the higher priority region in an overlap is a container or alias, then
  98 the lower priority region will appear in any "holes" that the higher priority
  99 region has left by not mapping subregions to that area of its address range.
 100 (This applies recursively -- if the subregions are themselves containers or
 101 aliases that leave holes then the lower priority region will appear in these
 102 holes too.)
 103
 104 For example, suppose we have a container A of size 0x8000 with two subregions
 105 B and C. B is a container mapped at 0x2000, size 0x4000, priority 1; C is
 106 an MMIO region mapped at 0x0, size 0x6000, priority 2. B currently has two
 107 of its own subregions: D of size 0x1000 at offset 0 and E of size 0x1000 at
 108 offset 0x2000. As a diagram:
 109
 110         0      1000   2000   3000   4000   5000   6000   7000    8000
 111         |------|------|------|------|------|------|------|-------|
 112   A:    [                                                       ]
 113   C:    [CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC]
 114   B:                  [                          ]
 115   D:                  [DDDDD]
 116   E:                                [EEEEE]
 117
 118 The regions that will be seen within this address range then are:
 119         [CCCCCCCCCCCC][DDDDD][CCCCC][EEEEE][CCCCC]
 120
 121 Since B has higher priority than C, its subregions appear in the flat map
 122 even where they overlap with C. In ranges where B has not mapped anything
 123 C's region appears.
 124
 125 If B had provided its own MMIO operations (ie it was not a pure container)
 126 then these would be used for any addresses in its range not handled by
 127 D or E, and the result would be:
 128         [CCCCCCCCCCCC][DDDDD][BBBBB][EEEEE][BBBBB]
 129
 130 Priority values are local to a container, because the priorities of two
 131 regions are only compared when they are both children of the same container.
 132 This means that the device in charge of the container (typically modelling
 133 a bus or a memory controller) can use them to manage the interaction of
 134 its child regions without any side effects on other parts of the system.
 135 In the example above, the priorities of D and E are unimportant because
 136 they do not overlap each other. It is the relative priority of B and C
 137 that causes D and E to appear on top of C: D and E's priorities are never
 138 compared against the priority of C.
 139
 140 Visibility
 141 ----------
 142 The memory core uses the following rules to select a memory region when the
 143 guest accesses an address:
 144
 145 - all direct subregions of the root region are matched against the address, in
 146   descending priority order
 147   - if the address lies outside the region offset/size, the subregion is
 148     discarded
 149   - if the subregion is a leaf (RAM or MMIO), the search terminates, returning
 150     this leaf region
 151   - if the subregion is a container, the same algorithm is used within the
 152     subregion (after the address is adjusted by the subregion offset)
 153   - if the subregion is an alias, the search is continued at the alias target
 154     (after the address is adjusted by the subregion offset and alias offset)
 155   - if a recursive search within a container or alias subregion does not
 156     find a match (because of a "hole" in the container's coverage of its
 157     address range), then if this is a container with its own MMIO or RAM
 158     backing the search terminates, returning the container itself. Otherwise
 159     we continue with the next subregion in priority order
 160 - if none of the subregions match the address then the search terminates
 161   with no match found
 162
 163 Example memory map
 164 ------------------
 165
 166 system_memory: container@0-2^48-1
 167  |
 168  +---- lomem: alias@0-0xdfffffff ---> #ram (0-0xdfffffff)
 169  |
 170  +---- himem: alias@0x100000000-0x11fffffff ---> #ram (0xe0000000-0xffffffff)
 171  |
 172  +---- vga-window: alias@0xa0000-0xbfffff ---> #pci (0xa0000-0xbffff)
 173  |      (prio 1)
 174  |
 175  +---- pci-hole: alias@0xe0000000-0xffffffff ---> #pci (0xe0000000-0xffffffff)
 176
 177 pci (0-2^32-1)
 178  |
 179  +--- vga-area: container@0xa0000-0xbffff
 180  |      |
 181  |      +--- alias@0x00000-0x7fff  ---> #vram (0x010000-0x017fff)
 182  |      |
 183  |      +--- alias@0x08000-0xffff  ---> #vram (0x020000-0x027fff)
 184  |
 185  +---- vram: ram@0xe1000000-0xe1ffffff
 186  |
 187  +---- vga-mmio: mmio@0xe2000000-0xe200ffff
 188
 189 ram: ram@0x00000000-0xffffffff
 190
 191 This is a (simplified) PC memory map. The 4GB RAM block is mapped into the
 192 system address space via two aliases: "lomem" is a 1:1 mapping of the first
 193 3.5GB; "himem" maps the last 0.5GB at address 4GB.  This leaves 0.5GB for the
 194 so-called PCI hole, that allows a 32-bit PCI bus to exist in a system with
 195 4GB of memory.
 196
 197 The memory controller diverts addresses in the range 640K-768K to the PCI
 198 address space.  This is modelled using the "vga-window" alias, mapped at a
 199 higher priority so it obscures the RAM at the same addresses.  The vga window
 200 can be removed by programming the memory controller; this is modelled by
 201 removing the alias and exposing the RAM underneath.
 202
 203 The pci address space is not a direct child of the system address space, since
 204 we only want parts of it to be visible (we accomplish this using aliases).
 205 It has two subregions: vga-area models the legacy vga window and is occupied
 206 by two 32K memory banks pointing at two sections of the framebuffer.
 207 In addition the vram is mapped as a BAR at address e1000000, and an additional
 208 BAR containing MMIO registers is mapped after it.
 209
 210 Note that if the guest maps a BAR outside the PCI hole, it would not be
 211 visible as the pci-hole alias clips it to a 0.5GB range.
 212
 213 Attributes
 214 ----------
 215
 216 Various region attributes (read-only, dirty logging, coalesced mmio, ioeventfd)
 217 can be changed during the region lifecycle.  They take effect once the region
 218 is made visible (which can be immediately, later, or never).
 219
 220 MMIO Operations
 221 ---------------
 222
 223 MMIO regions are provided with ->read() and ->write() callbacks; in addition
 224 various constraints can be supplied to control how these callbacks are called:
 225
 226  - .valid.min_access_size, .valid.max_access_size define the access sizes
 227    (in bytes) which the device accepts; accesses outside this range will
 228    have device and bus specific behaviour (ignored, or machine check)
 229  - .valid.aligned specifies that the device only accepts naturally aligned
 230    accesses.  Unaligned accesses invoke device and bus specific behaviour.
 231  - .impl.min_access_size, .impl.max_access_size define the access sizes
 232    (in bytes) supported by the *implementation*; other access sizes will be
 233    emulated using the ones available.  For example a 4-byte write will be
 234    emulated using four 1-byte writes, if .impl.max_access_size = 1.
 235  - .impl.valid specifies that the *implementation* only supports unaligned
 236    accesses; unaligned accesses will be emulated by two aligned accesses.
 237  - .old_portio and .old_mmio can be used to ease porting from code using
 238    cpu_register_io_memory() and register_ioport().  They should not be used
 239    in new code.