exec-all.h

   1 /*
   2  * internal execution defines for qemu
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20
  21 /* allow to see translation results - the slowdown should be negligible, so we leave it */
  22 #define DEBUG_DISAS
  23
  24 #ifndef glue
  25 #define xglue(x, y) x ## y
  26 #define glue(x, y) xglue(x, y)
  27 #define stringify(s)    tostring(s)
  28 #define tostring(s)     #s
  29 #endif
  30
  31 #if GCC_MAJOR < 3
  32 #define __builtin_expect(x, n) (x)
  33 #endif
  34
  35 #ifdef __i386__
  36 #define REGPARM(n) __attribute((regparm(n)))
  37 #else
  38 #define REGPARM(n)
  39 #endif
  40
  41 /* is_jmp field values */
  42 #define DISAS_NEXT    0 /* next instruction can be analyzed */
  43 #define DISAS_JUMP    1 /* only pc was modified dynamically */
  44 #define DISAS_UPDATE  2 /* cpu state was modified dynamically */
  45 #define DISAS_TB_JUMP 3 /* only pc was modified statically */
  46
  47 struct TranslationBlock;
  48
  49 /* XXX: make safe guess about sizes */
  50 #define MAX_OP_PER_INSTR 32
  51 #define OPC_BUF_SIZE 512
  52 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
  53
  54 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3)
  55
  56 extern uint16_t gen_opc_buf[OPC_BUF_SIZE];
  57 extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
  58 extern long gen_labels[OPC_BUF_SIZE];
  59 extern int nb_gen_labels;
  60 extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
  61 extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
  62 extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
  63 extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
  64 extern target_ulong gen_opc_jump_pc[2];
  65
  66 typedef void (GenOpFunc)(void);
  67 typedef void (GenOpFunc1)(long);
  68 typedef void (GenOpFunc2)(long, long);
  69 typedef void (GenOpFunc3)(long, long, long);
  70
  71 #if defined(TARGET_I386)
  72
  73 void optimize_flags_init(void);
  74
  75 #endif
  76
  77 extern FILE *logfile;
  78 extern int loglevel;
  79
  80 int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
  81 int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
  82 void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf);
  83 int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
  84                  int max_code_size, int *gen_code_size_ptr);
  85 int cpu_restore_state(struct TranslationBlock *tb,
  86                       CPUState *env, unsigned long searched_pc,
  87                       void *puc);
  88 int cpu_gen_code_copy(CPUState *env, struct TranslationBlock *tb,
  89                       int max_code_size, int *gen_code_size_ptr);
  90 int cpu_restore_state_copy(struct TranslationBlock *tb,
  91                            CPUState *env, unsigned long searched_pc,
  92                            void *puc);
  93 void cpu_resume_from_signal(CPUState *env1, void *puc);
  94 void cpu_exec_init(void);
  95 int page_unprotect(unsigned long address, unsigned long pc, void *puc);
  96 void tb_invalidate_phys_page_range(target_ulong start, target_ulong end,
  97                                    int is_cpu_write_access);
  98 void tb_invalidate_page_range(target_ulong start, target_ulong end);
  99 void tlb_flush_page(CPUState *env, target_ulong addr);
 100 void tlb_flush(CPUState *env, int flush_global);
 101 int tlb_set_page(CPUState *env, target_ulong vaddr,
 102                  target_phys_addr_t paddr, int prot,
 103                  int is_user, int is_softmmu);
 104
 105 #define CODE_GEN_MAX_SIZE        65536
 106 #define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */
 107
 108 #define CODE_GEN_HASH_BITS     15
 109 #define CODE_GEN_HASH_SIZE     (1 << CODE_GEN_HASH_BITS)
 110
 111 #define CODE_GEN_PHYS_HASH_BITS     15
 112 #define CODE_GEN_PHYS_HASH_SIZE     (1 << CODE_GEN_PHYS_HASH_BITS)
 113
 114 /* maximum total translate dcode allocated */
 115
 116 /* NOTE: the translated code area cannot be too big because on some
 117    archs the range of "fast" function calls is limited. Here is a
 118    summary of the ranges:
 119
 120    i386  : signed 32 bits
 121    arm   : signed 26 bits
 122    ppc   : signed 24 bits
 123    sparc : signed 32 bits
 124    alpha : signed 23 bits
 125 */
 126
 127 #if defined(__alpha__)
 128 #define CODE_GEN_BUFFER_SIZE     (2 * 1024 * 1024)
 129 #elif defined(__powerpc__)
 130 #define CODE_GEN_BUFFER_SIZE     (6 * 1024 * 1024)
 131 #else
 132 #define CODE_GEN_BUFFER_SIZE     (8 * 1024 * 1024)
 133 #endif
 134
 135 //#define CODE_GEN_BUFFER_SIZE     (128 * 1024)
 136
 137 /* estimated block size for TB allocation */
 138 /* XXX: use a per code average code fragment size and modulate it
 139    according to the host CPU */
 140 #if defined(CONFIG_SOFTMMU)
 141 #define CODE_GEN_AVG_BLOCK_SIZE 128
 142 #else
 143 #define CODE_GEN_AVG_BLOCK_SIZE 64
 144 #endif
 145
 146 #define CODE_GEN_MAX_BLOCKS    (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)
 147
 148 #if defined(__powerpc__)
 149 #define USE_DIRECT_JUMP
 150 #endif
 151 #if defined(__i386__) && !defined(_WIN32)
 152 #define USE_DIRECT_JUMP
 153 #endif
 154
 155 typedef struct TranslationBlock {
 156     target_ulong pc;   /* simulated PC corresponding to this block (EIP + CS base) */
 157     target_ulong cs_base; /* CS base for this block */
 158     unsigned int flags; /* flags defining in which context the code was generated */
 159     uint16_t size;      /* size of target code for this block (1 <=
 160                            size <= TARGET_PAGE_SIZE) */
 161     uint16_t cflags;    /* compile flags */
 162 #define CF_CODE_COPY   0x0001 /* block was generated in code copy mode */
 163 #define CF_TB_FP_USED  0x0002 /* fp ops are used in the TB */
 164 #define CF_FP_USED     0x0004 /* fp ops are used in the TB or in a chained TB */
 165 #define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */
 166
 167     uint8_t *tc_ptr;    /* pointer to the translated code */
 168     struct TranslationBlock *hash_next; /* next matching tb for virtual address */
 169     /* next matching tb for physical address. */
 170     struct TranslationBlock *phys_hash_next;
 171     /* first and second physical page containing code. The lower bit
 172        of the pointer tells the index in page_next[] */
 173     struct TranslationBlock *page_next[2];
 174     target_ulong page_addr[2];
 175
 176     /* the following data are used to directly call another TB from
 177        the code of this one. */
 178     uint16_t tb_next_offset[2]; /* offset of original jump target */
 179 #ifdef USE_DIRECT_JUMP
 180     uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
 181 #else
 182     uint32_t tb_next[2]; /* address of jump generated code */
 183 #endif
 184     /* list of TBs jumping to this one. This is a circular list using
 185        the two least significant bits of the pointers to tell what is
 186        the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
 187        jmp_first */
 188     struct TranslationBlock *jmp_next[2];
 189     struct TranslationBlock *jmp_first;
 190 } TranslationBlock;
 191
 192 static inline unsigned int tb_hash_func(target_ulong pc)
 193 {
 194     return pc & (CODE_GEN_HASH_SIZE - 1);
 195 }
 196
 197 static inline unsigned int tb_phys_hash_func(unsigned long pc)
 198 {
 199     return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
 200 }
 201
 202 TranslationBlock *tb_alloc(target_ulong pc);
 203 void tb_flush(CPUState *env);
 204 void tb_link(TranslationBlock *tb);
 205 void tb_link_phys(TranslationBlock *tb,
 206                   target_ulong phys_pc, target_ulong phys_page2);
 207
 208 extern TranslationBlock *tb_hash[CODE_GEN_HASH_SIZE];
 209 extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
 210
 211 extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
 212 extern uint8_t *code_gen_ptr;
 213
 214 /* find a translation block in the translation cache. If not found,
 215    return NULL and the pointer to the last element of the list in pptb */
 216 static inline TranslationBlock *tb_find(TranslationBlock ***pptb,
 217                                         target_ulong pc,
 218                                         target_ulong cs_base,
 219                                         unsigned int flags)
 220 {
 221     TranslationBlock **ptb, *tb;
 222     unsigned int h;
 223
 224     h = tb_hash_func(pc);
 225     ptb = &tb_hash[h];
 226     for(;;) {
 227         tb = *ptb;
 228         if (!tb)
 229             break;
 230         if (tb->pc == pc && tb->cs_base == cs_base && tb->flags == flags)
 231             return tb;
 232         ptb = &tb->hash_next;
 233     }
 234     *pptb = ptb;
 235     return NULL;
 236 }
 237
 238
 239 #if defined(USE_DIRECT_JUMP)
 240
 241 #if defined(__powerpc__)
 242 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
 243 {
 244     uint32_t val, *ptr;
 245
 246     /* patch the branch destination */
 247     ptr = (uint32_t *)jmp_addr;
 248     val = *ptr;
 249     val = (val & ~0x03fffffc) | ((addr - jmp_addr) & 0x03fffffc);
 250     *ptr = val;
 251     /* flush icache */
 252     asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
 253     asm volatile ("sync" : : : "memory");
 254     asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
 255     asm volatile ("sync" : : : "memory");
 256     asm volatile ("isync" : : : "memory");
 257 }
 258 #elif defined(__i386__)
 259 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
 260 {
 261     /* patch the branch destination */
 262     *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
 263     /* no need to flush icache explicitely */
 264 }
 265 #endif
 266
 267 static inline void tb_set_jmp_target(TranslationBlock *tb,
 268                                      int n, unsigned long addr)
 269 {
 270     unsigned long offset;
 271
 272     offset = tb->tb_jmp_offset[n];
 273     tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
 274     offset = tb->tb_jmp_offset[n + 2];
 275     if (offset != 0xffff)
 276         tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
 277 }
 278
 279 #else
 280
 281 /* set the jump target */
 282 static inline void tb_set_jmp_target(TranslationBlock *tb,
 283                                      int n, unsigned long addr)
 284 {
 285     tb->tb_next[n] = addr;
 286 }
 287
 288 #endif
 289
 290 static inline void tb_add_jump(TranslationBlock *tb, int n,
 291                                TranslationBlock *tb_next)
 292 {
 293     /* NOTE: this test is only needed for thread safety */
 294     if (!tb->jmp_next[n]) {
 295         /* patch the native jump address */
 296         tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
 297
 298         /* add in TB jmp circular list */
 299         tb->jmp_next[n] = tb_next->jmp_first;
 300         tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
 301     }
 302 }
 303
 304 TranslationBlock *tb_find_pc(unsigned long pc_ptr);
 305
 306 #ifndef offsetof
 307 #define offsetof(type, field) ((size_t) &((type *)0)->field)
 308 #endif
 309
 310 #if defined(_WIN32)
 311 #define ASM_DATA_SECTION ".section \".data\"\n"
 312 #define ASM_PREVIOUS_SECTION ".section .text\n"
 313 #elif defined(__APPLE__)
 314 #define ASM_DATA_SECTION ".data\n"
 315 #define ASM_PREVIOUS_SECTION ".text\n"
 316 #else
 317 #define ASM_DATA_SECTION ".section \".data\"\n"
 318 #define ASM_PREVIOUS_SECTION ".previous\n"
 319 #endif
 320
 321 #if defined(__powerpc__)
 322
 323 /* we patch the jump instruction directly */
 324 #define GOTO_TB(opname, tbparam, n)\
 325 do {\
 326     asm volatile (ASM_DATA_SECTION\
 327                   ASM_NAME(__op_label) #n "." ASM_NAME(opname) ":\n"\
 328                   ".long 1f\n"\
 329                   ASM_PREVIOUS_SECTION \
 330                   "b " ASM_NAME(__op_jmp) #n "\n"\
 331                   "1:\n");\
 332 } while (0)
 333
 334 #elif defined(__i386__) && defined(USE_DIRECT_JUMP)
 335
 336 /* we patch the jump instruction directly */
 337 #define GOTO_TB(opname, tbparam, n)\
 338 do {\
 339     asm volatile (".section .data\n"\
 340                   ASM_NAME(__op_label) #n "." ASM_NAME(opname) ":\n"\
 341                   ".long 1f\n"\
 342                   ASM_PREVIOUS_SECTION \
 343                   "jmp " ASM_NAME(__op_jmp) #n "\n"\
 344                   "1:\n");\
 345 } while (0)
 346
 347 #else
 348
 349 /* jump to next block operations (more portable code, does not need
 350    cache flushing, but slower because of indirect jump) */
 351 #define GOTO_TB(opname, tbparam, n)\
 352 do {\
 353     static void __attribute__((unused)) *dummy ## n = &&dummy_label ## n;\
 354     static void __attribute__((unused)) *__op_label ## n = &&label ## n;\
 355     goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n]);\
 356 label ## n: ;\
 357 dummy_label ## n: ;\
 358 } while (0)
 359
 360 #endif
 361
 362 /* XXX: will be suppressed */
 363 #define JUMP_TB(opname, tbparam, n, eip)\
 364 do {\
 365     GOTO_TB(opname, tbparam, n);\
 366     T0 = (long)(tbparam) + (n);\
 367     EIP = (int32_t)eip;\
 368     EXIT_TB();\
 369 } while (0)
 370
 371 extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
 372 extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
 373 extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
 374
 375 #ifdef __powerpc__
 376 static inline int testandset (int *p)
 377 {
 378     int ret;
 379     __asm__ __volatile__ (
 380                           "0:    lwarx %0,0,%1\n"
 381                           "      xor. %0,%3,%0\n"
 382                           "      bne 1f\n"
 383                           "      stwcx. %2,0,%1\n"
 384                           "      bne- 0b\n"
 385                           "1:    "
 386                           : "=&r" (ret)
 387                           : "r" (p), "r" (1), "r" (0)
 388                           : "cr0", "memory");
 389     return ret;
 390 }
 391 #endif
 392
 393 #ifdef __i386__
 394 static inline int testandset (int *p)
 395 {
 396     long int readval = 0;
 397
 398     __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
 399                           : "+m" (*p), "+a" (readval)
 400                           : "r" (1)
 401                           : "cc");
 402     return readval;
 403 }
 404 #endif
 405
 406 #ifdef __x86_64__
 407 static inline int testandset (int *p)
 408 {
 409     long int readval = 0;
 410
 411     __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
 412                           : "+m" (*p), "+a" (readval)
 413                           : "r" (1)
 414                           : "cc");
 415     return readval;
 416 }
 417 #endif
 418
 419 #ifdef __s390__
 420 static inline int testandset (int *p)
 421 {
 422     int ret;
 423
 424     __asm__ __volatile__ ("0: cs    %0,%1,0(%2)\n"
 425                           "   jl    0b"
 426                           : "=&d" (ret)
 427                           : "r" (1), "a" (p), "0" (*p)
 428                           : "cc", "memory" );
 429     return ret;
 430 }
 431 #endif
 432
 433 #ifdef __alpha__
 434 static inline int testandset (int *p)
 435 {
 436     int ret;
 437     unsigned long one;
 438
 439     __asm__ __volatile__ ("0:   mov 1,%2\n"
 440                           "     ldl_l %0,%1\n"
 441                           "     stl_c %2,%1\n"
 442                           "     beq %2,1f\n"
 443                           ".subsection 2\n"
 444                           "1:   br 0b\n"
 445                           ".previous"
 446                           : "=r" (ret), "=m" (*p), "=r" (one)
 447                           : "m" (*p));
 448     return ret;
 449 }
 450 #endif
 451
 452 #ifdef __sparc__
 453 static inline int testandset (int *p)
 454 {
 455         int ret;
 456
 457         __asm__ __volatile__("ldstub    [%1], %0"
 458                              : "=r" (ret)
 459                              : "r" (p)
 460                              : "memory");
 461
 462         return (ret ? 1 : 0);
 463 }
 464 #endif
 465
 466 #ifdef __arm__
 467 static inline int testandset (int *spinlock)
 468 {
 469     register unsigned int ret;
 470     __asm__ __volatile__("swp %0, %1, [%2]"
 471                          : "=r"(ret)
 472                          : "0"(1), "r"(spinlock));
 473
 474     return ret;
 475 }
 476 #endif
 477
 478 #ifdef __mc68000
 479 static inline int testandset (int *p)
 480 {
 481     char ret;
 482     __asm__ __volatile__("tas %1; sne %0"
 483                          : "=r" (ret)
 484                          : "m" (p)
 485                          : "cc","memory");
 486     return ret;
 487 }
 488 #endif
 489
 490 typedef int spinlock_t;
 491
 492 #define SPIN_LOCK_UNLOCKED 0
 493
 494 #if defined(CONFIG_USER_ONLY)
 495 static inline void spin_lock(spinlock_t *lock)
 496 {
 497     while (testandset(lock));
 498 }
 499
 500 static inline void spin_unlock(spinlock_t *lock)
 501 {
 502     *lock = 0;
 503 }
 504
 505 static inline int spin_trylock(spinlock_t *lock)
 506 {
 507     return !testandset(lock);
 508 }
 509 #else
 510 static inline void spin_lock(spinlock_t *lock)
 511 {
 512 }
 513
 514 static inline void spin_unlock(spinlock_t *lock)
 515 {
 516 }
 517
 518 static inline int spin_trylock(spinlock_t *lock)
 519 {
 520     return 1;
 521 }
 522 #endif
 523
 524 extern spinlock_t tb_lock;
 525
 526 extern int tb_invalidated_flag;
 527
 528 #if !defined(CONFIG_USER_ONLY)
 529
 530 void tlb_fill(target_ulong addr, int is_write, int is_user,
 531               void *retaddr);
 532
 533 #define ACCESS_TYPE 3
 534 #define MEMSUFFIX _code
 535 #define env cpu_single_env
 536
 537 #define DATA_SIZE 1
 538 #include "softmmu_header.h"
 539
 540 #define DATA_SIZE 2
 541 #include "softmmu_header.h"
 542
 543 #define DATA_SIZE 4
 544 #include "softmmu_header.h"
 545
 546 #define DATA_SIZE 8
 547 #include "softmmu_header.h"
 548
 549 #undef ACCESS_TYPE
 550 #undef MEMSUFFIX
 551 #undef env
 552
 553 #endif
 554
 555 #if defined(CONFIG_USER_ONLY)
 556 static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
 557 {
 558     return addr;
 559 }
 560 #else
 561 /* NOTE: this function can trigger an exception */
 562 /* NOTE2: the returned address is not exactly the physical address: it
 563    is the offset relative to phys_ram_base */
 564 /* XXX: i386 target specific */
 565 static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
 566 {
 567     int is_user, index, pd;
 568
 569     index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 570 #if defined(TARGET_I386)
 571     is_user = ((env->hflags & HF_CPL_MASK) == 3);
 572 #elif defined (TARGET_PPC)
 573     is_user = msr_pr;
 574 #elif defined (TARGET_SPARC)
 575     is_user = (env->psrs == 0);
 576 #else
 577 #error "Unimplemented !"
 578 #endif
 579     if (__builtin_expect(env->tlb_read[is_user][index].address !=
 580                          (addr & TARGET_PAGE_MASK), 0)) {
 581         ldub_code(addr);
 582     }
 583     pd = env->tlb_read[is_user][index].address & ~TARGET_PAGE_MASK;
 584     if (pd > IO_MEM_ROM) {
 585         cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x%08lx\n", addr);
 586     }
 587     return addr + env->tlb_read[is_user][index].addend - (unsigned long)phys_ram_base;
 588 }
 589 #endif
 590
 591
 592 #ifdef USE_KQEMU
 593 extern int kqemu_fd;
 594 extern int kqemu_flushed;
 595
 596 int kqemu_init(CPUState *env);
 597 int kqemu_cpu_exec(CPUState *env);
 598 void kqemu_flush_page(CPUState *env, target_ulong addr);
 599 void kqemu_flush(CPUState *env, int global);
 600
 601 static inline int kqemu_is_ok(CPUState *env)
 602 {
 603     return(env->kqemu_enabled &&
 604            (env->hflags & HF_CPL_MASK) == 3 &&
 605            (env->eflags & IOPL_MASK) != IOPL_MASK &&
 606            (env->cr[0] & CR0_PE_MASK) &&
 607            (env->eflags & IF_MASK) &&
 608            !(env->eflags & VM_MASK));
 609 }
 610
 611 #endif