hw/acpi_piix4.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  17  *
  18  * Contributions after 2012-01-13 are licensed under the terms of the
  19  * GNU GPL, version 2 or (at your option) any later version.
  20  */
  21 #include "hw.h"
  22 #include "pc.h"
  23 #include "apm.h"
  24 #include "pm_smbus.h"
  25 #include "pci.h"
  26 #include "acpi.h"
  27 #include "sysemu.h"
  28 #include "range.h"
  29 #include "ioport.h"
  30
  31 //#define DEBUG
  32
  33 #ifdef DEBUG
  34 # define PIIX4_DPRINTF(format, ...)     printf(format, ## __VA_ARGS__)
  35 #else
  36 # define PIIX4_DPRINTF(format, ...)     do { } while (0)
  37 #endif
  38
  39 #define ACPI_DBG_IO_ADDR  0xb044
  40
  41 #define GPE_BASE 0xafe0
  42 #define GPE_LEN 4
  43 #define PCI_BASE 0xae00
  44 #define PCI_EJ_BASE 0xae08
  45 #define PCI_RMV_BASE 0xae0c
  46
  47 #define PIIX4_PCI_HOTPLUG_STATUS 2
  48
  49 struct pci_status {
  50     uint32_t up;
  51     uint32_t down;
  52 };
  53
  54 typedef struct PIIX4PMState {
  55     PCIDevice dev;
  56     IORange ioport;
  57     ACPIPM1EVT pm1a;
  58     ACPIPM1CNT pm1_cnt;
  59
  60     APMState apm;
  61
  62     ACPIPMTimer tmr;
  63
  64     PMSMBus smb;
  65     uint32_t smb_io_base;
  66
  67     qemu_irq irq;
  68     qemu_irq smi_irq;
  69     int kvm_enabled;
  70     Notifier machine_ready;
  71
  72     /* for pci hotplug */
  73     ACPIGPE gpe;
  74     struct pci_status pci0_status;
  75     uint32_t pci0_hotplug_enable;
  76 } PIIX4PMState;
  77
  78 static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s);
  79
  80 #define ACPI_ENABLE 0xf1
  81 #define ACPI_DISABLE 0xf0
  82
  83 static void pm_update_sci(PIIX4PMState *s)
  84 {
  85     int sci_level, pmsts;
  86
  87     pmsts = acpi_pm1_evt_get_sts(&s->pm1a, s->tmr.overflow_time);
  88     sci_level = (((pmsts & s->pm1a.en) &
  89                   (ACPI_BITMASK_RT_CLOCK_ENABLE |
  90                    ACPI_BITMASK_POWER_BUTTON_ENABLE |
  91                    ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
  92                    ACPI_BITMASK_TIMER_ENABLE)) != 0) ||
  93         (((s->gpe.sts[0] & s->gpe.en[0]) & PIIX4_PCI_HOTPLUG_STATUS) != 0);
  94
  95     qemu_set_irq(s->irq, sci_level);
  96     /* schedule a timer interruption if needed */
  97     acpi_pm_tmr_update(&s->tmr, (s->pm1a.en & ACPI_BITMASK_TIMER_ENABLE) &&
  98                        !(pmsts & ACPI_BITMASK_TIMER_STATUS));
  99 }
 100
 101 static void pm_tmr_timer(ACPIPMTimer *tmr)
 102 {
 103     PIIX4PMState *s = container_of(tmr, PIIX4PMState, tmr);
 104     pm_update_sci(s);
 105 }
 106
 107 static void pm_ioport_write(IORange *ioport, uint64_t addr, unsigned width,
 108                             uint64_t val)
 109 {
 110     PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport);
 111
 112     if (width != 2) {
 113         PIIX4_DPRINTF("PM write port=0x%04x width=%d val=0x%08x\n",
 114                       (unsigned)addr, width, (unsigned)val);
 115     }
 116
 117     switch(addr) {
 118     case 0x00:
 119         acpi_pm1_evt_write_sts(&s->pm1a, &s->tmr, val);
 120         pm_update_sci(s);
 121         break;
 122     case 0x02:
 123         s->pm1a.en = val;
 124         pm_update_sci(s);
 125         break;
 126     case 0x04:
 127         acpi_pm1_cnt_write(&s->pm1a, &s->pm1_cnt, val);
 128         break;
 129     default:
 130         break;
 131     }
 132     PIIX4_DPRINTF("PM writew port=0x%04x val=0x%04x\n", (unsigned int)addr,
 133                   (unsigned int)val);
 134 }
 135
 136 static void pm_ioport_read(IORange *ioport, uint64_t addr, unsigned width,
 137                             uint64_t *data)
 138 {
 139     PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport);
 140     uint32_t val;
 141
 142     switch(addr) {
 143     case 0x00:
 144         val = acpi_pm1_evt_get_sts(&s->pm1a, s->tmr.overflow_time);
 145         break;
 146     case 0x02:
 147         val = s->pm1a.en;
 148         break;
 149     case 0x04:
 150         val = s->pm1_cnt.cnt;
 151         break;
 152     case 0x08:
 153         val = acpi_pm_tmr_get(&s->tmr);
 154         break;
 155     default:
 156         val = 0;
 157         break;
 158     }
 159     PIIX4_DPRINTF("PM readw port=0x%04x val=0x%04x\n", (unsigned int)addr, val);
 160     *data = val;
 161 }
 162
 163 static const IORangeOps pm_iorange_ops = {
 164     .read = pm_ioport_read,
 165     .write = pm_ioport_write,
 166 };
 167
 168 static void apm_ctrl_changed(uint32_t val, void *arg)
 169 {
 170     PIIX4PMState *s = arg;
 171
 172     /* ACPI specs 3.0, 4.7.2.5 */
 173     acpi_pm1_cnt_update(&s->pm1_cnt, val == ACPI_ENABLE, val == ACPI_DISABLE);
 174
 175     if (s->dev.config[0x5b] & (1 << 1)) {
 176         if (s->smi_irq) {
 177             qemu_irq_raise(s->smi_irq);
 178         }
 179     }
 180 }
 181
 182 static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
 183 {
 184     PIIX4_DPRINTF("ACPI: DBG: 0x%08x\n", val);
 185 }
 186
 187 static void pm_io_space_update(PIIX4PMState *s)
 188 {
 189     uint32_t pm_io_base;
 190
 191     if (s->dev.config[0x80] & 1) {
 192         pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
 193         pm_io_base &= 0xffc0;
 194
 195         /* XXX: need to improve memory and ioport allocation */
 196         PIIX4_DPRINTF("PM: mapping to 0x%x\n", pm_io_base);
 197         iorange_init(&s->ioport, &pm_iorange_ops, pm_io_base, 64);
 198         ioport_register(&s->ioport);
 199     }
 200 }
 201
 202 static void pm_write_config(PCIDevice *d,
 203                             uint32_t address, uint32_t val, int len)
 204 {
 205     pci_default_write_config(d, address, val, len);
 206     if (range_covers_byte(address, len, 0x80))
 207         pm_io_space_update((PIIX4PMState *)d);
 208 }
 209
 210 static int vmstate_acpi_post_load(void *opaque, int version_id)
 211 {
 212     PIIX4PMState *s = opaque;
 213
 214     pm_io_space_update(s);
 215     return 0;
 216 }
 217
 218 #define VMSTATE_GPE_ARRAY(_field, _state)                            \
 219  {                                                                   \
 220      .name       = (stringify(_field)),                              \
 221      .version_id = 0,                                                \
 222      .num        = GPE_LEN,                                          \
 223      .info       = &vmstate_info_uint16,                             \
 224      .size       = sizeof(uint16_t),                                 \
 225      .flags      = VMS_ARRAY | VMS_POINTER,                          \
 226      .offset     = vmstate_offset_pointer(_state, _field, uint8_t),  \
 227  }
 228
 229 static const VMStateDescription vmstate_gpe = {
 230     .name = "gpe",
 231     .version_id = 1,
 232     .minimum_version_id = 1,
 233     .minimum_version_id_old = 1,
 234     .fields      = (VMStateField []) {
 235         VMSTATE_GPE_ARRAY(sts, ACPIGPE),
 236         VMSTATE_GPE_ARRAY(en, ACPIGPE),
 237         VMSTATE_END_OF_LIST()
 238     }
 239 };
 240
 241 static const VMStateDescription vmstate_pci_status = {
 242     .name = "pci_status",
 243     .version_id = 1,
 244     .minimum_version_id = 1,
 245     .minimum_version_id_old = 1,
 246     .fields      = (VMStateField []) {
 247         VMSTATE_UINT32(up, struct pci_status),
 248         VMSTATE_UINT32(down, struct pci_status),
 249         VMSTATE_END_OF_LIST()
 250     }
 251 };
 252
 253 static const VMStateDescription vmstate_acpi = {
 254     .name = "piix4_pm",
 255     .version_id = 2,
 256     .minimum_version_id = 1,
 257     .minimum_version_id_old = 1,
 258     .post_load = vmstate_acpi_post_load,
 259     .fields      = (VMStateField []) {
 260         VMSTATE_PCI_DEVICE(dev, PIIX4PMState),
 261         VMSTATE_UINT16(pm1a.sts, PIIX4PMState),
 262         VMSTATE_UINT16(pm1a.en, PIIX4PMState),
 263         VMSTATE_UINT16(pm1_cnt.cnt, PIIX4PMState),
 264         VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
 265         VMSTATE_TIMER(tmr.timer, PIIX4PMState),
 266         VMSTATE_INT64(tmr.overflow_time, PIIX4PMState),
 267         VMSTATE_STRUCT(gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE),
 268         VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status,
 269                        struct pci_status),
 270         VMSTATE_END_OF_LIST()
 271     }
 272 };
 273
 274 static void piix4_update_hotplug(PIIX4PMState *s)
 275 {
 276     PCIDevice *dev = &s->dev;
 277     BusState *bus = qdev_get_parent_bus(&dev->qdev);
 278     DeviceState *qdev, *next;
 279
 280     s->pci0_hotplug_enable = ~0;
 281
 282     QTAILQ_FOREACH_SAFE(qdev, &bus->children, sibling, next) {
 283         PCIDeviceInfo *info = container_of(qdev->info, PCIDeviceInfo, qdev);
 284         PCIDevice *pdev = DO_UPCAST(PCIDevice, qdev, qdev);
 285         int slot = PCI_SLOT(pdev->devfn);
 286
 287         if (info->no_hotplug) {
 288             s->pci0_hotplug_enable &= ~(1 << slot);
 289         }
 290     }
 291 }
 292
 293 static void piix4_reset(void *opaque)
 294 {
 295     PIIX4PMState *s = opaque;
 296     uint8_t *pci_conf = s->dev.config;
 297
 298     pci_conf[0x58] = 0;
 299     pci_conf[0x59] = 0;
 300     pci_conf[0x5a] = 0;
 301     pci_conf[0x5b] = 0;
 302
 303     if (s->kvm_enabled) {
 304         /* Mark SMM as already inited (until KVM supports SMM). */
 305         pci_conf[0x5B] = 0x02;
 306     }
 307     piix4_update_hotplug(s);
 308 }
 309
 310 static void piix4_powerdown(void *opaque, int irq, int power_failing)
 311 {
 312     PIIX4PMState *s = opaque;
 313     ACPIPM1EVT *pm1a = s? &s->pm1a: NULL;
 314     ACPIPMTimer *tmr = s? &s->tmr: NULL;
 315
 316     acpi_pm1_evt_power_down(pm1a, tmr);
 317 }
 318
 319 static void piix4_pm_machine_ready(Notifier *n, void *opaque)
 320 {
 321     PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready);
 322     uint8_t *pci_conf;
 323
 324     pci_conf = s->dev.config;
 325     pci_conf[0x5f] = (isa_is_ioport_assigned(0x378) ? 0x80 : 0) | 0x10;
 326     pci_conf[0x63] = 0x60;
 327     pci_conf[0x67] = (isa_is_ioport_assigned(0x3f8) ? 0x08 : 0) |
 328         (isa_is_ioport_assigned(0x2f8) ? 0x90 : 0);
 329
 330 }
 331
 332 static int piix4_pm_initfn(PCIDevice *dev)
 333 {
 334     PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev);
 335     uint8_t *pci_conf;
 336
 337     pci_conf = s->dev.config;
 338     pci_conf[0x06] = 0x80;
 339     pci_conf[0x07] = 0x02;
 340     pci_conf[0x09] = 0x00;
 341     pci_conf[0x3d] = 0x01; // interrupt pin 1
 342
 343     pci_conf[0x40] = 0x01; /* PM io base read only bit */
 344
 345     /* APM */
 346     apm_init(&s->apm, apm_ctrl_changed, s);
 347
 348     register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
 349
 350     if (s->kvm_enabled) {
 351         /* Mark SMM as already inited to prevent SMM from running.  KVM does not
 352          * support SMM mode. */
 353         pci_conf[0x5B] = 0x02;
 354     }
 355
 356     /* XXX: which specification is used ? The i82731AB has different
 357        mappings */
 358     pci_conf[0x90] = s->smb_io_base | 1;
 359     pci_conf[0x91] = s->smb_io_base >> 8;
 360     pci_conf[0xd2] = 0x09;
 361     register_ioport_write(s->smb_io_base, 64, 1, smb_ioport_writeb, &s->smb);
 362     register_ioport_read(s->smb_io_base, 64, 1, smb_ioport_readb, &s->smb);
 363
 364     acpi_pm_tmr_init(&s->tmr, pm_tmr_timer);
 365     acpi_gpe_init(&s->gpe, GPE_LEN);
 366
 367     qemu_system_powerdown = *qemu_allocate_irqs(piix4_powerdown, s, 1);
 368
 369     pm_smbus_init(&s->dev.qdev, &s->smb);
 370     s->machine_ready.notify = piix4_pm_machine_ready;
 371     qemu_add_machine_init_done_notifier(&s->machine_ready);
 372     qemu_register_reset(piix4_reset, s);
 373     piix4_acpi_system_hot_add_init(dev->bus, s);
 374
 375     return 0;
 376 }
 377
 378 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 379                        qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq,
 380                        int kvm_enabled)
 381 {
 382     PCIDevice *dev;
 383     PIIX4PMState *s;
 384
 385     dev = pci_create(bus, devfn, "PIIX4_PM");
 386     qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
 387
 388     s = DO_UPCAST(PIIX4PMState, dev, dev);
 389     s->irq = sci_irq;
 390     acpi_pm1_cnt_init(&s->pm1_cnt, cmos_s3);
 391     s->smi_irq = smi_irq;
 392     s->kvm_enabled = kvm_enabled;
 393
 394     qdev_init_nofail(&dev->qdev);
 395
 396     return s->smb.smbus;
 397 }
 398
 399 static PCIDeviceInfo piix4_pm_info = {
 400     .qdev.name          = "PIIX4_PM",
 401     .qdev.desc          = "PM",
 402     .qdev.size          = sizeof(PIIX4PMState),
 403     .qdev.vmsd          = &vmstate_acpi,
 404     .qdev.no_user       = 1,
 405     .no_hotplug         = 1,
 406     .init               = piix4_pm_initfn,
 407     .config_write       = pm_write_config,
 408     .vendor_id          = PCI_VENDOR_ID_INTEL,
 409     .device_id          = PCI_DEVICE_ID_INTEL_82371AB_3,
 410     .revision           = 0x03,
 411     .class_id           = PCI_CLASS_BRIDGE_OTHER,
 412     .qdev.props         = (Property[]) {
 413         DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
 414         DEFINE_PROP_END_OF_LIST(),
 415     }
 416 };
 417
 418 static void piix4_pm_register(void)
 419 {
 420     pci_qdev_register(&piix4_pm_info);
 421 }
 422
 423 device_init(piix4_pm_register);
 424
 425 static uint32_t gpe_readb(void *opaque, uint32_t addr)
 426 {
 427     PIIX4PMState *s = opaque;
 428     uint32_t val = acpi_gpe_ioport_readb(&s->gpe, addr);
 429
 430     PIIX4_DPRINTF("gpe read %x == %x\n", addr, val);
 431     return val;
 432 }
 433
 434 static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
 435 {
 436     PIIX4PMState *s = opaque;
 437
 438     acpi_gpe_ioport_writeb(&s->gpe, addr, val);
 439     pm_update_sci(s);
 440
 441     PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val);
 442 }
 443
 444 static uint32_t pcihotplug_read(void *opaque, uint32_t addr)
 445 {
 446     uint32_t val = 0;
 447     struct pci_status *g = opaque;
 448     switch (addr) {
 449         case PCI_BASE:
 450             val = g->up;
 451             break;
 452         case PCI_BASE + 4:
 453             val = g->down;
 454             break;
 455         default:
 456             break;
 457     }
 458
 459     PIIX4_DPRINTF("pcihotplug read %x == %x\n", addr, val);
 460     return val;
 461 }
 462
 463 static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val)
 464 {
 465     struct pci_status *g = opaque;
 466     switch (addr) {
 467         case PCI_BASE:
 468             g->up = val;
 469             break;
 470         case PCI_BASE + 4:
 471             g->down = val;
 472             break;
 473    }
 474
 475     PIIX4_DPRINTF("pcihotplug write %x <== %d\n", addr, val);
 476 }
 477
 478 static uint32_t pciej_read(void *opaque, uint32_t addr)
 479 {
 480     PIIX4_DPRINTF("pciej read %x\n", addr);
 481     return 0;
 482 }
 483
 484 static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
 485 {
 486     BusState *bus = opaque;
 487     DeviceState *qdev, *next;
 488     PCIDevice *dev;
 489     PCIDeviceInfo *info;
 490     int slot = ffs(val) - 1;
 491
 492     QTAILQ_FOREACH_SAFE(qdev, &bus->children, sibling, next) {
 493         dev = DO_UPCAST(PCIDevice, qdev, qdev);
 494         info = container_of(qdev->info, PCIDeviceInfo, qdev);
 495         if (PCI_SLOT(dev->devfn) == slot && !info->no_hotplug) {
 496             qdev_free(qdev);
 497         }
 498     }
 499
 500
 501     PIIX4_DPRINTF("pciej write %x <== %d\n", addr, val);
 502 }
 503
 504 static uint32_t pcirmv_read(void *opaque, uint32_t addr)
 505 {
 506     PIIX4PMState *s = opaque;
 507
 508     return s->pci0_hotplug_enable;
 509 }
 510
 511 static void pcirmv_write(void *opaque, uint32_t addr, uint32_t val)
 512 {
 513     return;
 514 }
 515
 516 static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,
 517                                 PCIHotplugState state);
 518
 519 static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s)
 520 {
 521     struct pci_status *pci0_status = &s->pci0_status;
 522
 523     register_ioport_write(GPE_BASE, GPE_LEN, 1, gpe_writeb, s);
 524     register_ioport_read(GPE_BASE, GPE_LEN, 1,  gpe_readb, s);
 525     acpi_gpe_blk(&s->gpe, GPE_BASE);
 526
 527     register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, pci0_status);
 528     register_ioport_read(PCI_BASE, 8, 4,  pcihotplug_read, pci0_status);
 529
 530     register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, bus);
 531     register_ioport_read(PCI_EJ_BASE, 4, 4,  pciej_read, bus);
 532
 533     register_ioport_write(PCI_RMV_BASE, 4, 4, pcirmv_write, s);
 534     register_ioport_read(PCI_RMV_BASE, 4, 4,  pcirmv_read, s);
 535
 536     pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev);
 537 }
 538
 539 static void enable_device(PIIX4PMState *s, int slot)
 540 {
 541     s->gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS;
 542     s->pci0_status.up |= (1 << slot);
 543 }
 544
 545 static void disable_device(PIIX4PMState *s, int slot)
 546 {
 547     s->gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS;
 548     s->pci0_status.down |= (1 << slot);
 549 }
 550
 551 static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,
 552                                 PCIHotplugState state)
 553 {
 554     int slot = PCI_SLOT(dev->devfn);
 555     PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev,
 556                                 DO_UPCAST(PCIDevice, qdev, qdev));
 557
 558     /* Don't send event when device is enabled during qemu machine creation:
 559      * it is present on boot, no hotplug event is necessary. We do send an
 560      * event when the device is disabled later. */
 561     if (state == PCI_COLDPLUG_ENABLED) {
 562         return 0;
 563     }
 564
 565     s->pci0_status.up = 0;
 566     s->pci0_status.down = 0;
 567     if (state == PCI_HOTPLUG_ENABLED) {
 568         enable_device(s, slot);
 569     } else {
 570         disable_device(s, slot);
 571     }
 572
 573     pm_update_sci(s);
 574
 575     return 0;
 576 }