hw/char/etraxfs_ser.c

   1 /*
   2  * QEMU ETRAX System Emulator
   3  *
   4  * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw/sysbus.h"
  26 #include "sysemu/char.h"
  27 #include "qemu/log.h"
  28
  29 #define D(x)
  30
  31 #define RW_TR_CTRL     (0x00 / 4)
  32 #define RW_TR_DMA_EN   (0x04 / 4)
  33 #define RW_REC_CTRL    (0x08 / 4)
  34 #define RW_DOUT        (0x1c / 4)
  35 #define RS_STAT_DIN    (0x20 / 4)
  36 #define R_STAT_DIN     (0x24 / 4)
  37 #define RW_INTR_MASK   (0x2c / 4)
  38 #define RW_ACK_INTR    (0x30 / 4)
  39 #define R_INTR         (0x34 / 4)
  40 #define R_MASKED_INTR  (0x38 / 4)
  41 #define R_MAX          (0x3c / 4)
  42
  43 #define STAT_DAV     16
  44 #define STAT_TR_IDLE 22
  45 #define STAT_TR_RDY  24
  46
  47 struct etrax_serial
  48 {
  49     SysBusDevice busdev;
  50     MemoryRegion mmio;
  51     CharDriverState *chr;
  52     qemu_irq irq;
  53
  54     int pending_tx;
  55
  56     uint8_t rx_fifo[16];
  57     unsigned int rx_fifo_pos;
  58     unsigned int rx_fifo_len;
  59
  60     /* Control registers.  */
  61     uint32_t regs[R_MAX];
  62 };
  63
  64 static void ser_update_irq(struct etrax_serial *s)
  65 {
  66
  67     if (s->rx_fifo_len) {
  68         s->regs[R_INTR] |= 8;
  69     } else {
  70         s->regs[R_INTR] &= ~8;
  71     }
  72
  73     s->regs[R_MASKED_INTR] = s->regs[R_INTR] & s->regs[RW_INTR_MASK];
  74     qemu_set_irq(s->irq, !!s->regs[R_MASKED_INTR]);
  75 }
  76
  77 static uint64_t
  78 ser_read(void *opaque, hwaddr addr, unsigned int size)
  79 {
  80     struct etrax_serial *s = opaque;
  81     uint32_t r = 0;
  82
  83     addr >>= 2;
  84     switch (addr)
  85     {
  86         case R_STAT_DIN:
  87             r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 15];
  88             if (s->rx_fifo_len) {
  89                 r |= 1 << STAT_DAV;
  90             }
  91             r |= 1 << STAT_TR_RDY;
  92             r |= 1 << STAT_TR_IDLE;
  93             break;
  94         case RS_STAT_DIN:
  95             r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 15];
  96             if (s->rx_fifo_len) {
  97                 r |= 1 << STAT_DAV;
  98                 s->rx_fifo_len--;
  99             }
 100             r |= 1 << STAT_TR_RDY;
 101             r |= 1 << STAT_TR_IDLE;
 102             break;
 103         default:
 104             r = s->regs[addr];
 105             D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr, r));
 106             break;
 107     }
 108     return r;
 109 }
 110
 111 static void
 112 ser_write(void *opaque, hwaddr addr,
 113           uint64_t val64, unsigned int size)
 114 {
 115     struct etrax_serial *s = opaque;
 116     uint32_t value = val64;
 117     unsigned char ch = val64;
 118
 119     D(qemu_log("%s " TARGET_FMT_plx "=%x\n",  __func__, addr, value));
 120     addr >>= 2;
 121     switch (addr)
 122     {
 123         case RW_DOUT:
 124             qemu_chr_fe_write(s->chr, &ch, 1);
 125             s->regs[R_INTR] |= 3;
 126             s->pending_tx = 1;
 127             s->regs[addr] = value;
 128             break;
 129         case RW_ACK_INTR:
 130             if (s->pending_tx) {
 131                 value &= ~1;
 132                 s->pending_tx = 0;
 133                 D(qemu_log("fixedup value=%x r_intr=%x\n",
 134                            value, s->regs[R_INTR]));
 135             }
 136             s->regs[addr] = value;
 137             s->regs[R_INTR] &= ~value;
 138             D(printf("r_intr=%x\n", s->regs[R_INTR]));
 139             break;
 140         default:
 141             s->regs[addr] = value;
 142             break;
 143     }
 144     ser_update_irq(s);
 145 }
 146
 147 static const MemoryRegionOps ser_ops = {
 148     .read = ser_read,
 149     .write = ser_write,
 150     .endianness = DEVICE_NATIVE_ENDIAN,
 151     .valid = {
 152         .min_access_size = 4,
 153         .max_access_size = 4
 154     }
 155 };
 156
 157 static void serial_receive(void *opaque, const uint8_t *buf, int size)
 158 {
 159     struct etrax_serial *s = opaque;
 160     int i;
 161
 162     /* Got a byte.  */
 163     if (s->rx_fifo_len >= 16) {
 164         qemu_log("WARNING: UART dropped char.\n");
 165         return;
 166     }
 167
 168     for (i = 0; i < size; i++) {
 169         s->rx_fifo[s->rx_fifo_pos] = buf[i];
 170         s->rx_fifo_pos++;
 171         s->rx_fifo_pos &= 15;
 172         s->rx_fifo_len++;
 173     }
 174
 175     ser_update_irq(s);
 176 }
 177
 178 static int serial_can_receive(void *opaque)
 179 {
 180     struct etrax_serial *s = opaque;
 181     int r;
 182
 183     /* Is the receiver enabled?  */
 184     if (!(s->regs[RW_REC_CTRL] & (1 << 3))) {
 185         return 0;
 186     }
 187
 188     r = sizeof(s->rx_fifo) - s->rx_fifo_len;
 189     return r;
 190 }
 191
 192 static void serial_event(void *opaque, int event)
 193 {
 194
 195 }
 196
 197 static void etraxfs_ser_reset(DeviceState *d)
 198 {
 199     struct etrax_serial *s = container_of(d, typeof(*s), busdev.qdev);
 200
 201     /* transmitter begins ready and idle.  */
 202     s->regs[RS_STAT_DIN] |= (1 << STAT_TR_RDY);
 203     s->regs[RS_STAT_DIN] |= (1 << STAT_TR_IDLE);
 204
 205     s->regs[RW_REC_CTRL] = 0x10000;
 206
 207 }
 208
 209 static int etraxfs_ser_init(SysBusDevice *dev)
 210 {
 211     struct etrax_serial *s = FROM_SYSBUS(typeof (*s), dev);
 212
 213     sysbus_init_irq(dev, &s->irq);
 214     memory_region_init_io(&s->mmio, &ser_ops, s, "etraxfs-serial", R_MAX * 4);
 215     sysbus_init_mmio(dev, &s->mmio);
 216
 217     s->chr = qemu_char_get_next_serial();
 218     if (s->chr)
 219         qemu_chr_add_handlers(s->chr,
 220                       serial_can_receive, serial_receive,
 221                       serial_event, s);
 222     return 0;
 223 }
 224
 225 static void etraxfs_ser_class_init(ObjectClass *klass, void *data)
 226 {
 227     DeviceClass *dc = DEVICE_CLASS(klass);
 228     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 229
 230     k->init = etraxfs_ser_init;
 231     dc->reset = etraxfs_ser_reset;
 232 }
 233
 234 static const TypeInfo etraxfs_ser_info = {
 235     .name          = "etraxfs,serial",
 236     .parent        = TYPE_SYS_BUS_DEVICE,
 237     .instance_size = sizeof(struct etrax_serial),
 238     .class_init    = etraxfs_ser_class_init,
 239 };
 240
 241 static void etraxfs_serial_register_types(void)
 242 {
 243     type_register_static(&etraxfs_ser_info);
 244 }
 245
 246 type_init(etraxfs_serial_register_types)