hw/cpu/a9mpcore.c

   1 /*
   2  * Cortex-A9MPCore internal peripheral emulation.
   3  *
   4  * Copyright (c) 2009 CodeSourcery.
   5  * Copyright (c) 2011 Linaro Limited.
   6  * Written by Paul Brook, Peter Maydell.
   7  *
   8  * This code is licensed under the GPL.
   9  */
  10
  11 #include "hw/sysbus.h"
  12 #include "hw/intc/arm_gic.h"
  13 #include "hw/misc/a9scu.h"
  14 #include "hw/timer/arm_mptimer.h"
  15
  16 #define TYPE_A9MPCORE_PRIV "a9mpcore_priv"
  17 #define A9MPCORE_PRIV(obj) \
  18     OBJECT_CHECK(A9MPPrivState, (obj), TYPE_A9MPCORE_PRIV)
  19
  20 typedef struct A9MPPrivState {
  21     /*< private >*/
  22     SysBusDevice parent_obj;
  23     /*< public >*/
  24
  25     uint32_t num_cpu;
  26     MemoryRegion container;
  27     uint32_t num_irq;
  28
  29     GICState gic;
  30     A9SCUState scu;
  31     ARMMPTimerState mptimer;
  32     ARMMPTimerState wdt;
  33 } A9MPPrivState;
  34
  35 static void a9mp_priv_set_irq(void *opaque, int irq, int level)
  36 {
  37     A9MPPrivState *s = (A9MPPrivState *)opaque;
  38
  39     qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level);
  40 }
  41
  42 static void a9mp_priv_initfn(Object *obj)
  43 {
  44     A9MPPrivState *s = A9MPCORE_PRIV(obj);
  45
  46     memory_region_init(&s->container, obj, "a9mp-priv-container", 0x2000);
  47     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->container);
  48
  49     object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC);
  50     qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());
  51
  52     object_initialize(&s->scu, sizeof(s->scu), TYPE_A9_SCU);
  53     qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default());
  54
  55     object_initialize(&s->mptimer, sizeof(s->mptimer), TYPE_ARM_MPTIMER);
  56     qdev_set_parent_bus(DEVICE(&s->mptimer), sysbus_get_default());
  57
  58     object_initialize(&s->wdt, sizeof(s->wdt), TYPE_ARM_MPTIMER);
  59     qdev_set_parent_bus(DEVICE(&s->wdt), sysbus_get_default());
  60 }
  61
  62 static void a9mp_priv_realize(DeviceState *dev, Error **errp)
  63 {
  64     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
  65     A9MPPrivState *s = A9MPCORE_PRIV(dev);
  66     DeviceState *gicdev, *scudev, *mptimerdev, *wdtdev;
  67     SysBusDevice *timerbusdev, *wdtbusdev, *gicbusdev, *scubusdev;
  68     Error *err = NULL;
  69     int i;
  70
  71     gicdev = DEVICE(&s->gic);
  72     qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu);
  73     qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq);
  74     object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
  75     if (err != NULL) {
  76         error_propagate(errp, err);
  77         return;
  78     }
  79     gicbusdev = SYS_BUS_DEVICE(&s->gic);
  80
  81     /* Pass through outbound IRQ lines from the GIC */
  82     sysbus_pass_irq(sbd, gicbusdev);
  83
  84     /* Pass through inbound GPIO lines to the GIC */
  85     qdev_init_gpio_in(dev, a9mp_priv_set_irq, s->num_irq - 32);
  86
  87     scudev = DEVICE(&s->scu);
  88     qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu);
  89     object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
  90     if (err != NULL) {
  91         error_propagate(errp, err);
  92         return;
  93     }
  94     scubusdev = SYS_BUS_DEVICE(&s->scu);
  95
  96     mptimerdev = DEVICE(&s->mptimer);
  97     qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu);
  98     object_property_set_bool(OBJECT(&s->mptimer), true, "realized", &err);
  99     if (err != NULL) {
 100         error_propagate(errp, err);
 101         return;
 102     }
 103     timerbusdev = SYS_BUS_DEVICE(&s->mptimer);
 104
 105     wdtdev = DEVICE(&s->wdt);
 106     qdev_prop_set_uint32(wdtdev, "num-cpu", s->num_cpu);
 107     object_property_set_bool(OBJECT(&s->wdt), true, "realized", &err);
 108     if (err != NULL) {
 109         error_propagate(errp, err);
 110         return;
 111     }
 112     wdtbusdev = SYS_BUS_DEVICE(&s->wdt);
 113
 114     /* Memory map (addresses are offsets from PERIPHBASE):
 115      *  0x0000-0x00ff -- Snoop Control Unit
 116      *  0x0100-0x01ff -- GIC CPU interface
 117      *  0x0200-0x02ff -- Global Timer
 118      *  0x0300-0x05ff -- nothing
 119      *  0x0600-0x06ff -- private timers and watchdogs
 120      *  0x0700-0x0fff -- nothing
 121      *  0x1000-0x1fff -- GIC Distributor
 122      *
 123      * We should implement the global timer but don't currently do so.
 124      */
 125     memory_region_add_subregion(&s->container, 0,
 126                                 sysbus_mmio_get_region(scubusdev, 0));
 127     /* GIC CPU interface */
 128     memory_region_add_subregion(&s->container, 0x100,
 129                                 sysbus_mmio_get_region(gicbusdev, 1));
 130     /* Note that the A9 exposes only the "timer/watchdog for this core"
 131      * memory region, not the "timer/watchdog for core X" ones 11MPcore has.
 132      */
 133     memory_region_add_subregion(&s->container, 0x600,
 134                                 sysbus_mmio_get_region(timerbusdev, 0));
 135     memory_region_add_subregion(&s->container, 0x620,
 136                                 sysbus_mmio_get_region(wdtbusdev, 0));
 137     memory_region_add_subregion(&s->container, 0x1000,
 138                                 sysbus_mmio_get_region(gicbusdev, 0));
 139
 140     /* Wire up the interrupt from each watchdog and timer.
 141      * For each core the timer is PPI 29 and the watchdog PPI 30.
 142      */
 143     for (i = 0; i < s->num_cpu; i++) {
 144         int ppibase = (s->num_irq - 32) + i * 32;
 145         sysbus_connect_irq(timerbusdev, i,
 146                            qdev_get_gpio_in(gicdev, ppibase + 29));
 147         sysbus_connect_irq(wdtbusdev, i,
 148                            qdev_get_gpio_in(gicdev, ppibase + 30));
 149     }
 150 }
 151
 152 static Property a9mp_priv_properties[] = {
 153     DEFINE_PROP_UINT32("num-cpu", A9MPPrivState, num_cpu, 1),
 154     /* The Cortex-A9MP may have anything from 0 to 224 external interrupt
 155      * IRQ lines (with another 32 internal). We default to 64+32, which
 156      * is the number provided by the Cortex-A9MP test chip in the
 157      * Realview PBX-A9 and Versatile Express A9 development boards.
 158      * Other boards may differ and should set this property appropriately.
 159      */
 160     DEFINE_PROP_UINT32("num-irq", A9MPPrivState, num_irq, 96),
 161     DEFINE_PROP_END_OF_LIST(),
 162 };
 163
 164 static void a9mp_priv_class_init(ObjectClass *klass, void *data)
 165 {
 166     DeviceClass *dc = DEVICE_CLASS(klass);
 167
 168     dc->realize = a9mp_priv_realize;
 169     dc->props = a9mp_priv_properties;
 170 }
 171
 172 static const TypeInfo a9mp_priv_info = {
 173     .name          = TYPE_A9MPCORE_PRIV,
 174     .parent        = TYPE_SYS_BUS_DEVICE,
 175     .instance_size = sizeof(A9MPPrivState),
 176     .instance_init = a9mp_priv_initfn,
 177     .class_init    = a9mp_priv_class_init,
 178 };
 179
 180 static void a9mp_register_types(void)
 181 {
 182     type_register_static(&a9mp_priv_info);
 183 }
 184
 185 type_init(a9mp_register_types)