hw/display/vmware_vga.c

   1 /*
   2  * QEMU VMware-SVGA "chipset".
   3  *
   4  * Copyright (c) 2007 Andrzej Zaborowski  <balrog@zabor.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw/hw.h"
  25 #include "hw/loader.h"
  26 #include "ui/console.h"
  27 #include "hw/pci/pci.h"
  28
  29 #undef VERBOSE
  30 #define HW_RECT_ACCEL
  31 #define HW_FILL_ACCEL
  32 #define HW_MOUSE_ACCEL
  33
  34 #include "hw/vga_int.h"
  35
  36 /* See http://vmware-svga.sf.net/ for some documentation on VMWare SVGA */
  37
  38 struct vmsvga_state_s {
  39     VGACommonState vga;
  40
  41     int invalidated;
  42     int depth;
  43     int bypp;
  44     int enable;
  45     int config;
  46     struct {
  47         int id;
  48         int x;
  49         int y;
  50         int on;
  51     } cursor;
  52
  53     int index;
  54     int scratch_size;
  55     uint32_t *scratch;
  56     int new_width;
  57     int new_height;
  58     uint32_t guest;
  59     uint32_t svgaid;
  60     int syncing;
  61
  62     MemoryRegion fifo_ram;
  63     uint8_t *fifo_ptr;
  64     unsigned int fifo_size;
  65
  66     union {
  67         uint32_t *fifo;
  68         struct QEMU_PACKED {
  69             uint32_t min;
  70             uint32_t max;
  71             uint32_t next_cmd;
  72             uint32_t stop;
  73             /* Add registers here when adding capabilities.  */
  74             uint32_t fifo[0];
  75         } *cmd;
  76     };
  77
  78 #define REDRAW_FIFO_LEN  512
  79     struct vmsvga_rect_s {
  80         int x, y, w, h;
  81     } redraw_fifo[REDRAW_FIFO_LEN];
  82     int redraw_fifo_first, redraw_fifo_last;
  83 };
  84
  85 struct pci_vmsvga_state_s {
  86     PCIDevice card;
  87     struct vmsvga_state_s chip;
  88     MemoryRegion io_bar;
  89 };
  90
  91 #define SVGA_MAGIC              0x900000UL
  92 #define SVGA_MAKE_ID(ver)       (SVGA_MAGIC << 8 | (ver))
  93 #define SVGA_ID_0               SVGA_MAKE_ID(0)
  94 #define SVGA_ID_1               SVGA_MAKE_ID(1)
  95 #define SVGA_ID_2               SVGA_MAKE_ID(2)
  96
  97 #define SVGA_LEGACY_BASE_PORT   0x4560
  98 #define SVGA_INDEX_PORT         0x0
  99 #define SVGA_VALUE_PORT         0x1
 100 #define SVGA_BIOS_PORT          0x2
 101
 102 #define SVGA_VERSION_2
 103
 104 #ifdef SVGA_VERSION_2
 105 # define SVGA_ID                SVGA_ID_2
 106 # define SVGA_IO_BASE           SVGA_LEGACY_BASE_PORT
 107 # define SVGA_IO_MUL            1
 108 # define SVGA_FIFO_SIZE         0x10000
 109 # define SVGA_PCI_DEVICE_ID     PCI_DEVICE_ID_VMWARE_SVGA2
 110 #else
 111 # define SVGA_ID                SVGA_ID_1
 112 # define SVGA_IO_BASE           SVGA_LEGACY_BASE_PORT
 113 # define SVGA_IO_MUL            4
 114 # define SVGA_FIFO_SIZE         0x10000
 115 # define SVGA_PCI_DEVICE_ID     PCI_DEVICE_ID_VMWARE_SVGA
 116 #endif
 117
 118 enum {
 119     /* ID 0, 1 and 2 registers */
 120     SVGA_REG_ID = 0,
 121     SVGA_REG_ENABLE = 1,
 122     SVGA_REG_WIDTH = 2,
 123     SVGA_REG_HEIGHT = 3,
 124     SVGA_REG_MAX_WIDTH = 4,
 125     SVGA_REG_MAX_HEIGHT = 5,
 126     SVGA_REG_DEPTH = 6,
 127     SVGA_REG_BITS_PER_PIXEL = 7,        /* Current bpp in the guest */
 128     SVGA_REG_PSEUDOCOLOR = 8,
 129     SVGA_REG_RED_MASK = 9,
 130     SVGA_REG_GREEN_MASK = 10,
 131     SVGA_REG_BLUE_MASK = 11,
 132     SVGA_REG_BYTES_PER_LINE = 12,
 133     SVGA_REG_FB_START = 13,
 134     SVGA_REG_FB_OFFSET = 14,
 135     SVGA_REG_VRAM_SIZE = 15,
 136     SVGA_REG_FB_SIZE = 16,
 137
 138     /* ID 1 and 2 registers */
 139     SVGA_REG_CAPABILITIES = 17,
 140     SVGA_REG_MEM_START = 18,            /* Memory for command FIFO */
 141     SVGA_REG_MEM_SIZE = 19,
 142     SVGA_REG_CONFIG_DONE = 20,          /* Set when memory area configured */
 143     SVGA_REG_SYNC = 21,                 /* Write to force synchronization */
 144     SVGA_REG_BUSY = 22,                 /* Read to check if sync is done */
 145     SVGA_REG_GUEST_ID = 23,             /* Set guest OS identifier */
 146     SVGA_REG_CURSOR_ID = 24,            /* ID of cursor */
 147     SVGA_REG_CURSOR_X = 25,             /* Set cursor X position */
 148     SVGA_REG_CURSOR_Y = 26,             /* Set cursor Y position */
 149     SVGA_REG_CURSOR_ON = 27,            /* Turn cursor on/off */
 150     SVGA_REG_HOST_BITS_PER_PIXEL = 28,  /* Current bpp in the host */
 151     SVGA_REG_SCRATCH_SIZE = 29,         /* Number of scratch registers */
 152     SVGA_REG_MEM_REGS = 30,             /* Number of FIFO registers */
 153     SVGA_REG_NUM_DISPLAYS = 31,         /* Number of guest displays */
 154     SVGA_REG_PITCHLOCK = 32,            /* Fixed pitch for all modes */
 155
 156     SVGA_PALETTE_BASE = 1024,           /* Base of SVGA color map */
 157     SVGA_PALETTE_END  = SVGA_PALETTE_BASE + 767,
 158     SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768,
 159 };
 160
 161 #define SVGA_CAP_NONE                   0
 162 #define SVGA_CAP_RECT_FILL              (1 << 0)
 163 #define SVGA_CAP_RECT_COPY              (1 << 1)
 164 #define SVGA_CAP_RECT_PAT_FILL          (1 << 2)
 165 #define SVGA_CAP_LEGACY_OFFSCREEN       (1 << 3)
 166 #define SVGA_CAP_RASTER_OP              (1 << 4)
 167 #define SVGA_CAP_CURSOR                 (1 << 5)
 168 #define SVGA_CAP_CURSOR_BYPASS          (1 << 6)
 169 #define SVGA_CAP_CURSOR_BYPASS_2        (1 << 7)
 170 #define SVGA_CAP_8BIT_EMULATION         (1 << 8)
 171 #define SVGA_CAP_ALPHA_CURSOR           (1 << 9)
 172 #define SVGA_CAP_GLYPH                  (1 << 10)
 173 #define SVGA_CAP_GLYPH_CLIPPING         (1 << 11)
 174 #define SVGA_CAP_OFFSCREEN_1            (1 << 12)
 175 #define SVGA_CAP_ALPHA_BLEND            (1 << 13)
 176 #define SVGA_CAP_3D                     (1 << 14)
 177 #define SVGA_CAP_EXTENDED_FIFO          (1 << 15)
 178 #define SVGA_CAP_MULTIMON               (1 << 16)
 179 #define SVGA_CAP_PITCHLOCK              (1 << 17)
 180
 181 /*
 182  * FIFO offsets (seen as an array of 32-bit words)
 183  */
 184 enum {
 185     /*
 186      * The original defined FIFO offsets
 187      */
 188     SVGA_FIFO_MIN = 0,
 189     SVGA_FIFO_MAX,      /* The distance from MIN to MAX must be at least 10K */
 190     SVGA_FIFO_NEXT_CMD,
 191     SVGA_FIFO_STOP,
 192
 193     /*
 194      * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO
 195      */
 196     SVGA_FIFO_CAPABILITIES = 4,
 197     SVGA_FIFO_FLAGS,
 198     SVGA_FIFO_FENCE,
 199     SVGA_FIFO_3D_HWVERSION,
 200     SVGA_FIFO_PITCHLOCK,
 201 };
 202
 203 #define SVGA_FIFO_CAP_NONE              0
 204 #define SVGA_FIFO_CAP_FENCE             (1 << 0)
 205 #define SVGA_FIFO_CAP_ACCELFRONT        (1 << 1)
 206 #define SVGA_FIFO_CAP_PITCHLOCK         (1 << 2)
 207
 208 #define SVGA_FIFO_FLAG_NONE             0
 209 #define SVGA_FIFO_FLAG_ACCELFRONT       (1 << 0)
 210
 211 /* These values can probably be changed arbitrarily.  */
 212 #define SVGA_SCRATCH_SIZE               0x8000
 213 #define SVGA_MAX_WIDTH                  2360
 214 #define SVGA_MAX_HEIGHT                 1770
 215
 216 #ifdef VERBOSE
 217 # define GUEST_OS_BASE          0x5001
 218 static const char *vmsvga_guest_id[] = {
 219     [0x00] = "Dos",
 220     [0x01] = "Windows 3.1",
 221     [0x02] = "Windows 95",
 222     [0x03] = "Windows 98",
 223     [0x04] = "Windows ME",
 224     [0x05] = "Windows NT",
 225     [0x06] = "Windows 2000",
 226     [0x07] = "Linux",
 227     [0x08] = "OS/2",
 228     [0x09] = "an unknown OS",
 229     [0x0a] = "BSD",
 230     [0x0b] = "Whistler",
 231     [0x0c] = "an unknown OS",
 232     [0x0d] = "an unknown OS",
 233     [0x0e] = "an unknown OS",
 234     [0x0f] = "an unknown OS",
 235     [0x10] = "an unknown OS",
 236     [0x11] = "an unknown OS",
 237     [0x12] = "an unknown OS",
 238     [0x13] = "an unknown OS",
 239     [0x14] = "an unknown OS",
 240     [0x15] = "Windows 2003",
 241 };
 242 #endif
 243
 244 enum {
 245     SVGA_CMD_INVALID_CMD = 0,
 246     SVGA_CMD_UPDATE = 1,
 247     SVGA_CMD_RECT_FILL = 2,
 248     SVGA_CMD_RECT_COPY = 3,
 249     SVGA_CMD_DEFINE_BITMAP = 4,
 250     SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5,
 251     SVGA_CMD_DEFINE_PIXMAP = 6,
 252     SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7,
 253     SVGA_CMD_RECT_BITMAP_FILL = 8,
 254     SVGA_CMD_RECT_PIXMAP_FILL = 9,
 255     SVGA_CMD_RECT_BITMAP_COPY = 10,
 256     SVGA_CMD_RECT_PIXMAP_COPY = 11,
 257     SVGA_CMD_FREE_OBJECT = 12,
 258     SVGA_CMD_RECT_ROP_FILL = 13,
 259     SVGA_CMD_RECT_ROP_COPY = 14,
 260     SVGA_CMD_RECT_ROP_BITMAP_FILL = 15,
 261     SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16,
 262     SVGA_CMD_RECT_ROP_BITMAP_COPY = 17,
 263     SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18,
 264     SVGA_CMD_DEFINE_CURSOR = 19,
 265     SVGA_CMD_DISPLAY_CURSOR = 20,
 266     SVGA_CMD_MOVE_CURSOR = 21,
 267     SVGA_CMD_DEFINE_ALPHA_CURSOR = 22,
 268     SVGA_CMD_DRAW_GLYPH = 23,
 269     SVGA_CMD_DRAW_GLYPH_CLIPPED = 24,
 270     SVGA_CMD_UPDATE_VERBOSE = 25,
 271     SVGA_CMD_SURFACE_FILL = 26,
 272     SVGA_CMD_SURFACE_COPY = 27,
 273     SVGA_CMD_SURFACE_ALPHA_BLEND = 28,
 274     SVGA_CMD_FRONT_ROP_FILL = 29,
 275     SVGA_CMD_FENCE = 30,
 276 };
 277
 278 /* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */
 279 enum {
 280     SVGA_CURSOR_ON_HIDE = 0,
 281     SVGA_CURSOR_ON_SHOW = 1,
 282     SVGA_CURSOR_ON_REMOVE_FROM_FB = 2,
 283     SVGA_CURSOR_ON_RESTORE_TO_FB = 3,
 284 };
 285
 286 static inline void vmsvga_update_rect(struct vmsvga_state_s *s,
 287                 int x, int y, int w, int h)
 288 {
 289     DisplaySurface *surface = qemu_console_surface(s->vga.con);
 290     int line;
 291     int bypl;
 292     int width;
 293     int start;
 294     uint8_t *src;
 295     uint8_t *dst;
 296
 297     if (x < 0) {
 298         fprintf(stderr, "%s: update x was < 0 (%d)\n", __func__, x);
 299         w += x;
 300         x = 0;
 301     }
 302     if (w < 0) {
 303         fprintf(stderr, "%s: update w was < 0 (%d)\n", __func__, w);
 304         w = 0;
 305     }
 306     if (x + w > surface_width(surface)) {
 307         fprintf(stderr, "%s: update width too large x: %d, w: %d\n",
 308                 __func__, x, w);
 309         x = MIN(x, surface_width(surface));
 310         w = surface_width(surface) - x;
 311     }
 312
 313     if (y < 0) {
 314         fprintf(stderr, "%s: update y was < 0 (%d)\n",  __func__, y);
 315         h += y;
 316         y = 0;
 317     }
 318     if (h < 0) {
 319         fprintf(stderr, "%s: update h was < 0 (%d)\n",  __func__, h);
 320         h = 0;
 321     }
 322     if (y + h > surface_height(surface)) {
 323         fprintf(stderr, "%s: update height too large y: %d, h: %d\n",
 324                 __func__, y, h);
 325         y = MIN(y, surface_height(surface));
 326         h = surface_height(surface) - y;
 327     }
 328
 329     bypl = surface_stride(surface);
 330     width = surface_bytes_per_pixel(surface) * w;
 331     start = surface_bytes_per_pixel(surface) * x + bypl * y;
 332     src = s->vga.vram_ptr + start;
 333     dst = surface_data(surface) + start;
 334
 335     for (line = h; line > 0; line--, src += bypl, dst += bypl) {
 336         memcpy(dst, src, width);
 337     }
 338     dpy_gfx_update(s->vga.con, x, y, w, h);
 339 }
 340
 341 static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s,
 342                 int x, int y, int w, int h)
 343 {
 344     struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last++];
 345
 346     s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1;
 347     rect->x = x;
 348     rect->y = y;
 349     rect->w = w;
 350     rect->h = h;
 351 }
 352
 353 static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s)
 354 {
 355     struct vmsvga_rect_s *rect;
 356
 357     if (s->invalidated) {
 358         s->redraw_fifo_first = s->redraw_fifo_last;
 359         return;
 360     }
 361     /* Overlapping region updates can be optimised out here - if someone
 362      * knows a smart algorithm to do that, please share.  */
 363     while (s->redraw_fifo_first != s->redraw_fifo_last) {
 364         rect = &s->redraw_fifo[s->redraw_fifo_first++];
 365         s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1;
 366         vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h);
 367     }
 368 }
 369
 370 #ifdef HW_RECT_ACCEL
 371 static inline void vmsvga_copy_rect(struct vmsvga_state_s *s,
 372                 int x0, int y0, int x1, int y1, int w, int h)
 373 {
 374     DisplaySurface *surface = qemu_console_surface(s->vga.con);
 375     uint8_t *vram = s->vga.vram_ptr;
 376     int bypl = surface_stride(surface);
 377     int bypp = surface_bytes_per_pixel(surface);
 378     int width = bypp * w;
 379     int line = h;
 380     uint8_t *ptr[2];
 381
 382     if (y1 > y0) {
 383         ptr[0] = vram + bypp * x0 + bypl * (y0 + h - 1);
 384         ptr[1] = vram + bypp * x1 + bypl * (y1 + h - 1);
 385         for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl) {
 386             memmove(ptr[1], ptr[0], width);
 387         }
 388     } else {
 389         ptr[0] = vram + bypp * x0 + bypl * y0;
 390         ptr[1] = vram + bypp * x1 + bypl * y1;
 391         for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl) {
 392             memmove(ptr[1], ptr[0], width);
 393         }
 394     }
 395
 396     vmsvga_update_rect_delayed(s, x1, y1, w, h);
 397 }
 398 #endif
 399
 400 #ifdef HW_FILL_ACCEL
 401 static inline void vmsvga_fill_rect(struct vmsvga_state_s *s,
 402                 uint32_t c, int x, int y, int w, int h)
 403 {
 404     DisplaySurface *surface = qemu_console_surface(s->vga.con);
 405     int bypl = surface_stride(surface);
 406     int width = surface_bytes_per_pixel(surface) * w;
 407     int line = h;
 408     int column;
 409     uint8_t *fst;
 410     uint8_t *dst;
 411     uint8_t *src;
 412     uint8_t col[4];
 413
 414     col[0] = c;
 415     col[1] = c >> 8;
 416     col[2] = c >> 16;
 417     col[3] = c >> 24;
 418
 419     fst = s->vga.vram_ptr + surface_bytes_per_pixel(surface) * x + bypl * y;
 420
 421     if (line--) {
 422         dst = fst;
 423         src = col;
 424         for (column = width; column > 0; column--) {
 425             *(dst++) = *(src++);
 426             if (src - col == surface_bytes_per_pixel(surface)) {
 427                 src = col;
 428             }
 429         }
 430         dst = fst;
 431         for (; line > 0; line--) {
 432             dst += bypl;
 433             memcpy(dst, fst, width);
 434         }
 435     }
 436
 437     vmsvga_update_rect_delayed(s, x, y, w, h);
 438 }
 439 #endif
 440
 441 struct vmsvga_cursor_definition_s {
 442     int width;
 443     int height;
 444     int id;
 445     int bpp;
 446     int hot_x;
 447     int hot_y;
 448     uint32_t mask[1024];
 449     uint32_t image[4096];
 450 };
 451
 452 #define SVGA_BITMAP_SIZE(w, h)          ((((w) + 31) >> 5) * (h))
 453 #define SVGA_PIXMAP_SIZE(w, h, bpp)     (((((w) * (bpp)) + 31) >> 5) * (h))
 454
 455 #ifdef HW_MOUSE_ACCEL
 456 static inline void vmsvga_cursor_define(struct vmsvga_state_s *s,
 457                 struct vmsvga_cursor_definition_s *c)
 458 {
 459     QEMUCursor *qc;
 460     int i, pixels;
 461
 462     qc = cursor_alloc(c->width, c->height);
 463     qc->hot_x = c->hot_x;
 464     qc->hot_y = c->hot_y;
 465     switch (c->bpp) {
 466     case 1:
 467         cursor_set_mono(qc, 0xffffff, 0x000000, (void *)c->image,
 468                         1, (void *)c->mask);
 469 #ifdef DEBUG
 470         cursor_print_ascii_art(qc, "vmware/mono");
 471 #endif
 472         break;
 473     case 32:
 474         /* fill alpha channel from mask, set color to zero */
 475         cursor_set_mono(qc, 0x000000, 0x000000, (void *)c->mask,
 476                         1, (void *)c->mask);
 477         /* add in rgb values */
 478         pixels = c->width * c->height;
 479         for (i = 0; i < pixels; i++) {
 480             qc->data[i] |= c->image[i] & 0xffffff;
 481         }
 482 #ifdef DEBUG
 483         cursor_print_ascii_art(qc, "vmware/32bit");
 484 #endif
 485         break;
 486     default:
 487         fprintf(stderr, "%s: unhandled bpp %d, using fallback cursor\n",
 488                 __func__, c->bpp);
 489         cursor_put(qc);
 490         qc = cursor_builtin_left_ptr();
 491     }
 492
 493     dpy_cursor_define(s->vga.con, qc);
 494     cursor_put(qc);
 495 }
 496 #endif
 497
 498 #define CMD(f)  le32_to_cpu(s->cmd->f)
 499
 500 static inline int vmsvga_fifo_length(struct vmsvga_state_s *s)
 501 {
 502     int num;
 503
 504     if (!s->config || !s->enable) {
 505         return 0;
 506     }
 507     num = CMD(next_cmd) - CMD(stop);
 508     if (num < 0) {
 509         num += CMD(max) - CMD(min);
 510     }
 511     return num >> 2;
 512 }
 513
 514 static inline uint32_t vmsvga_fifo_read_raw(struct vmsvga_state_s *s)
 515 {
 516     uint32_t cmd = s->fifo[CMD(stop) >> 2];
 517
 518     s->cmd->stop = cpu_to_le32(CMD(stop) + 4);
 519     if (CMD(stop) >= CMD(max)) {
 520         s->cmd->stop = s->cmd->min;
 521     }
 522     return cmd;
 523 }
 524
 525 static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s)
 526 {
 527     return le32_to_cpu(vmsvga_fifo_read_raw(s));
 528 }
 529
 530 static void vmsvga_fifo_run(struct vmsvga_state_s *s)
 531 {
 532     uint32_t cmd, colour;
 533     int args, len;
 534     int x, y, dx, dy, width, height;
 535     struct vmsvga_cursor_definition_s cursor;
 536     uint32_t cmd_start;
 537
 538     len = vmsvga_fifo_length(s);
 539     while (len > 0) {
 540         /* May need to go back to the start of the command if incomplete */
 541         cmd_start = s->cmd->stop;
 542
 543         switch (cmd = vmsvga_fifo_read(s)) {
 544         case SVGA_CMD_UPDATE:
 545         case SVGA_CMD_UPDATE_VERBOSE:
 546             len -= 5;
 547             if (len < 0) {
 548                 goto rewind;
 549             }
 550
 551             x = vmsvga_fifo_read(s);
 552             y = vmsvga_fifo_read(s);
 553             width = vmsvga_fifo_read(s);
 554             height = vmsvga_fifo_read(s);
 555             vmsvga_update_rect_delayed(s, x, y, width, height);
 556             break;
 557
 558         case SVGA_CMD_RECT_FILL:
 559             len -= 6;
 560             if (len < 0) {
 561                 goto rewind;
 562             }
 563
 564             colour = vmsvga_fifo_read(s);
 565             x = vmsvga_fifo_read(s);
 566             y = vmsvga_fifo_read(s);
 567             width = vmsvga_fifo_read(s);
 568             height = vmsvga_fifo_read(s);
 569 #ifdef HW_FILL_ACCEL
 570             vmsvga_fill_rect(s, colour, x, y, width, height);
 571             break;
 572 #else
 573             args = 0;
 574             goto badcmd;
 575 #endif
 576
 577         case SVGA_CMD_RECT_COPY:
 578             len -= 7;
 579             if (len < 0) {
 580                 goto rewind;
 581             }
 582
 583             x = vmsvga_fifo_read(s);
 584             y = vmsvga_fifo_read(s);
 585             dx = vmsvga_fifo_read(s);
 586             dy = vmsvga_fifo_read(s);
 587             width = vmsvga_fifo_read(s);
 588             height = vmsvga_fifo_read(s);
 589 #ifdef HW_RECT_ACCEL
 590             vmsvga_copy_rect(s, x, y, dx, dy, width, height);
 591             break;
 592 #else
 593             args = 0;
 594             goto badcmd;
 595 #endif
 596
 597         case SVGA_CMD_DEFINE_CURSOR:
 598             len -= 8;
 599             if (len < 0) {
 600                 goto rewind;
 601             }
 602
 603             cursor.id = vmsvga_fifo_read(s);
 604             cursor.hot_x = vmsvga_fifo_read(s);
 605             cursor.hot_y = vmsvga_fifo_read(s);
 606             cursor.width = x = vmsvga_fifo_read(s);
 607             cursor.height = y = vmsvga_fifo_read(s);
 608             vmsvga_fifo_read(s);
 609             cursor.bpp = vmsvga_fifo_read(s);
 610
 611             args = SVGA_BITMAP_SIZE(x, y) + SVGA_PIXMAP_SIZE(x, y, cursor.bpp);
 612             if (SVGA_BITMAP_SIZE(x, y) > sizeof cursor.mask ||
 613                 SVGA_PIXMAP_SIZE(x, y, cursor.bpp) > sizeof cursor.image) {
 614                     goto badcmd;
 615             }
 616
 617             len -= args;
 618             if (len < 0) {
 619                 goto rewind;
 620             }
 621
 622             for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args++) {
 623                 cursor.mask[args] = vmsvga_fifo_read_raw(s);
 624             }
 625             for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args++) {
 626                 cursor.image[args] = vmsvga_fifo_read_raw(s);
 627             }
 628 #ifdef HW_MOUSE_ACCEL
 629             vmsvga_cursor_define(s, &cursor);
 630             break;
 631 #else
 632             args = 0;
 633             goto badcmd;
 634 #endif
 635
 636         /*
 637          * Other commands that we at least know the number of arguments
 638          * for so we can avoid FIFO desync if driver uses them illegally.
 639          */
 640         case SVGA_CMD_DEFINE_ALPHA_CURSOR:
 641             len -= 6;
 642             if (len < 0) {
 643                 goto rewind;
 644             }
 645             vmsvga_fifo_read(s);
 646             vmsvga_fifo_read(s);
 647             vmsvga_fifo_read(s);
 648             x = vmsvga_fifo_read(s);
 649             y = vmsvga_fifo_read(s);
 650             args = x * y;
 651             goto badcmd;
 652         case SVGA_CMD_RECT_ROP_FILL:
 653             args = 6;
 654             goto badcmd;
 655         case SVGA_CMD_RECT_ROP_COPY:
 656             args = 7;
 657             goto badcmd;
 658         case SVGA_CMD_DRAW_GLYPH_CLIPPED:
 659             len -= 4;
 660             if (len < 0) {
 661                 goto rewind;
 662             }
 663             vmsvga_fifo_read(s);
 664             vmsvga_fifo_read(s);
 665             args = 7 + (vmsvga_fifo_read(s) >> 2);
 666             goto badcmd;
 667         case SVGA_CMD_SURFACE_ALPHA_BLEND:
 668             args = 12;
 669             goto badcmd;
 670
 671         /*
 672          * Other commands that are not listed as depending on any
 673          * CAPABILITIES bits, but are not described in the README either.
 674          */
 675         case SVGA_CMD_SURFACE_FILL:
 676         case SVGA_CMD_SURFACE_COPY:
 677         case SVGA_CMD_FRONT_ROP_FILL:
 678         case SVGA_CMD_FENCE:
 679         case SVGA_CMD_INVALID_CMD:
 680             break; /* Nop */
 681
 682         default:
 683             args = 0;
 684         badcmd:
 685             len -= args;
 686             if (len < 0) {
 687                 goto rewind;
 688             }
 689             while (args--) {
 690                 vmsvga_fifo_read(s);
 691             }
 692             printf("%s: Unknown command 0x%02x in SVGA command FIFO\n",
 693                    __func__, cmd);
 694             break;
 695
 696         rewind:
 697             s->cmd->stop = cmd_start;
 698             break;
 699         }
 700     }
 701
 702     s->syncing = 0;
 703 }
 704
 705 static uint32_t vmsvga_index_read(void *opaque, uint32_t address)
 706 {
 707     struct vmsvga_state_s *s = opaque;
 708
 709     return s->index;
 710 }
 711
 712 static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index)
 713 {
 714     struct vmsvga_state_s *s = opaque;
 715
 716     s->index = index;
 717 }
 718
 719 static uint32_t vmsvga_value_read(void *opaque, uint32_t address)
 720 {
 721     uint32_t caps;
 722     struct vmsvga_state_s *s = opaque;
 723     DisplaySurface *surface = qemu_console_surface(s->vga.con);
 724
 725     switch (s->index) {
 726     case SVGA_REG_ID:
 727         return s->svgaid;
 728
 729     case SVGA_REG_ENABLE:
 730         return s->enable;
 731
 732     case SVGA_REG_WIDTH:
 733         return surface_width(surface);
 734
 735     case SVGA_REG_HEIGHT:
 736         return surface_height(surface);
 737
 738     case SVGA_REG_MAX_WIDTH:
 739         return SVGA_MAX_WIDTH;
 740
 741     case SVGA_REG_MAX_HEIGHT:
 742         return SVGA_MAX_HEIGHT;
 743
 744     case SVGA_REG_DEPTH:
 745         return s->depth;
 746
 747     case SVGA_REG_BITS_PER_PIXEL:
 748         return (s->depth + 7) & ~7;
 749
 750     case SVGA_REG_PSEUDOCOLOR:
 751         return 0x0;
 752
 753     case SVGA_REG_RED_MASK:
 754         return surface->pf.rmask;
 755
 756     case SVGA_REG_GREEN_MASK:
 757         return surface->pf.gmask;
 758
 759     case SVGA_REG_BLUE_MASK:
 760         return surface->pf.bmask;
 761
 762     case SVGA_REG_BYTES_PER_LINE:
 763         return s->bypp * s->new_width;
 764
 765     case SVGA_REG_FB_START: {
 766         struct pci_vmsvga_state_s *pci_vmsvga
 767             = container_of(s, struct pci_vmsvga_state_s, chip);
 768         return pci_get_bar_addr(&pci_vmsvga->card, 1);
 769     }
 770
 771     case SVGA_REG_FB_OFFSET:
 772         return 0x0;
 773
 774     case SVGA_REG_VRAM_SIZE:
 775         return s->vga.vram_size; /* No physical VRAM besides the framebuffer */
 776
 777     case SVGA_REG_FB_SIZE:
 778         return s->vga.vram_size;
 779
 780     case SVGA_REG_CAPABILITIES:
 781         caps = SVGA_CAP_NONE;
 782 #ifdef HW_RECT_ACCEL
 783         caps |= SVGA_CAP_RECT_COPY;
 784 #endif
 785 #ifdef HW_FILL_ACCEL
 786         caps |= SVGA_CAP_RECT_FILL;
 787 #endif
 788 #ifdef HW_MOUSE_ACCEL
 789         if (dpy_cursor_define_supported(s->vga.con)) {
 790             caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 |
 791                     SVGA_CAP_CURSOR_BYPASS;
 792         }
 793 #endif
 794         return caps;
 795
 796     case SVGA_REG_MEM_START: {
 797         struct pci_vmsvga_state_s *pci_vmsvga
 798             = container_of(s, struct pci_vmsvga_state_s, chip);
 799         return pci_get_bar_addr(&pci_vmsvga->card, 2);
 800     }
 801
 802     case SVGA_REG_MEM_SIZE:
 803         return s->fifo_size;
 804
 805     case SVGA_REG_CONFIG_DONE:
 806         return s->config;
 807
 808     case SVGA_REG_SYNC:
 809     case SVGA_REG_BUSY:
 810         return s->syncing;
 811
 812     case SVGA_REG_GUEST_ID:
 813         return s->guest;
 814
 815     case SVGA_REG_CURSOR_ID:
 816         return s->cursor.id;
 817
 818     case SVGA_REG_CURSOR_X:
 819         return s->cursor.x;
 820
 821     case SVGA_REG_CURSOR_Y:
 822         return s->cursor.x;
 823
 824     case SVGA_REG_CURSOR_ON:
 825         return s->cursor.on;
 826
 827     case SVGA_REG_HOST_BITS_PER_PIXEL:
 828         return (s->depth + 7) & ~7;
 829
 830     case SVGA_REG_SCRATCH_SIZE:
 831         return s->scratch_size;
 832
 833     case SVGA_REG_MEM_REGS:
 834     case SVGA_REG_NUM_DISPLAYS:
 835     case SVGA_REG_PITCHLOCK:
 836     case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
 837         return 0;
 838
 839     default:
 840         if (s->index >= SVGA_SCRATCH_BASE &&
 841             s->index < SVGA_SCRATCH_BASE + s->scratch_size) {
 842             return s->scratch[s->index - SVGA_SCRATCH_BASE];
 843         }
 844         printf("%s: Bad register %02x\n", __func__, s->index);
 845     }
 846
 847     return 0;
 848 }
 849
 850 static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value)
 851 {
 852     struct vmsvga_state_s *s = opaque;
 853
 854     switch (s->index) {
 855     case SVGA_REG_ID:
 856         if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0) {
 857             s->svgaid = value;
 858         }
 859         break;
 860
 861     case SVGA_REG_ENABLE:
 862         s->enable = !!value;
 863         s->invalidated = 1;
 864         s->vga.invalidate(&s->vga);
 865         if (s->enable && s->config) {
 866             vga_dirty_log_stop(&s->vga);
 867         } else {
 868             vga_dirty_log_start(&s->vga);
 869         }
 870         break;
 871
 872     case SVGA_REG_WIDTH:
 873         if (value <= SVGA_MAX_WIDTH) {
 874             s->new_width = value;
 875             s->invalidated = 1;
 876         } else {
 877             printf("%s: Bad width: %i\n", __func__, value);
 878         }
 879         break;
 880
 881     case SVGA_REG_HEIGHT:
 882         if (value <= SVGA_MAX_HEIGHT) {
 883             s->new_height = value;
 884             s->invalidated = 1;
 885         } else {
 886             printf("%s: Bad height: %i\n", __func__, value);
 887         }
 888         break;
 889
 890     case SVGA_REG_BITS_PER_PIXEL:
 891         if (value != s->depth) {
 892             printf("%s: Bad bits per pixel: %i bits\n", __func__, value);
 893             s->config = 0;
 894         }
 895         break;
 896
 897     case SVGA_REG_CONFIG_DONE:
 898         if (value) {
 899             s->fifo = (uint32_t *) s->fifo_ptr;
 900             /* Check range and alignment.  */
 901             if ((CMD(min) | CMD(max) | CMD(next_cmd) | CMD(stop)) & 3) {
 902                 break;
 903             }
 904             if (CMD(min) < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo) {
 905                 break;
 906             }
 907             if (CMD(max) > SVGA_FIFO_SIZE) {
 908                 break;
 909             }
 910             if (CMD(max) < CMD(min) + 10 * 1024) {
 911                 break;
 912             }
 913             vga_dirty_log_stop(&s->vga);
 914         }
 915         s->config = !!value;
 916         break;
 917
 918     case SVGA_REG_SYNC:
 919         s->syncing = 1;
 920         vmsvga_fifo_run(s); /* Or should we just wait for update_display? */
 921         break;
 922
 923     case SVGA_REG_GUEST_ID:
 924         s->guest = value;
 925 #ifdef VERBOSE
 926         if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE +
 927             ARRAY_SIZE(vmsvga_guest_id)) {
 928             printf("%s: guest runs %s.\n", __func__,
 929                    vmsvga_guest_id[value - GUEST_OS_BASE]);
 930         }
 931 #endif
 932         break;
 933
 934     case SVGA_REG_CURSOR_ID:
 935         s->cursor.id = value;
 936         break;
 937
 938     case SVGA_REG_CURSOR_X:
 939         s->cursor.x = value;
 940         break;
 941
 942     case SVGA_REG_CURSOR_Y:
 943         s->cursor.y = value;
 944         break;
 945
 946     case SVGA_REG_CURSOR_ON:
 947         s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW);
 948         s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE);
 949 #ifdef HW_MOUSE_ACCEL
 950         if (value <= SVGA_CURSOR_ON_SHOW) {
 951             dpy_mouse_set(s->vga.con, s->cursor.x, s->cursor.y, s->cursor.on);
 952         }
 953 #endif
 954         break;
 955
 956     case SVGA_REG_DEPTH:
 957     case SVGA_REG_MEM_REGS:
 958     case SVGA_REG_NUM_DISPLAYS:
 959     case SVGA_REG_PITCHLOCK:
 960     case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
 961         break;
 962
 963     default:
 964         if (s->index >= SVGA_SCRATCH_BASE &&
 965                 s->index < SVGA_SCRATCH_BASE + s->scratch_size) {
 966             s->scratch[s->index - SVGA_SCRATCH_BASE] = value;
 967             break;
 968         }
 969         printf("%s: Bad register %02x\n", __func__, s->index);
 970     }
 971 }
 972
 973 static uint32_t vmsvga_bios_read(void *opaque, uint32_t address)
 974 {
 975     printf("%s: what are we supposed to return?\n", __func__);
 976     return 0xcafe;
 977 }
 978
 979 static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data)
 980 {
 981     printf("%s: what are we supposed to do with (%08x)?\n", __func__, data);
 982 }
 983
 984 static inline void vmsvga_check_size(struct vmsvga_state_s *s)
 985 {
 986     DisplaySurface *surface = qemu_console_surface(s->vga.con);
 987
 988     if (s->new_width != surface_width(surface) ||
 989         s->new_height != surface_height(surface)) {
 990         qemu_console_resize(s->vga.con, s->new_width, s->new_height);
 991         s->invalidated = 1;
 992     }
 993 }
 994
 995 static void vmsvga_update_display(void *opaque)
 996 {
 997     struct vmsvga_state_s *s = opaque;
 998     DisplaySurface *surface = qemu_console_surface(s->vga.con);
 999     bool dirty = false;
1000
1001     if (!s->enable) {
1002         s->vga.update(&s->vga);
1003         return;
1004     }
1005
1006     vmsvga_check_size(s);
1007
1008     vmsvga_fifo_run(s);
1009     vmsvga_update_rect_flush(s);
1010
1011     /*
1012      * Is it more efficient to look at vram VGA-dirty bits or wait
1013      * for the driver to issue SVGA_CMD_UPDATE?
1014      */
1015     if (memory_region_is_logging(&s->vga.vram)) {
1016         vga_sync_dirty_bitmap(&s->vga);
1017         dirty = memory_region_get_dirty(&s->vga.vram, 0,
1018             surface_stride(surface) * surface_height(surface),
1019             DIRTY_MEMORY_VGA);
1020     }
1021     if (s->invalidated || dirty) {
1022         s->invalidated = 0;
1023         memcpy(surface_data(surface), s->vga.vram_ptr,
1024                surface_stride(surface) * surface_height(surface));
1025         dpy_gfx_update(s->vga.con, 0, 0,
1026                    surface_width(surface), surface_height(surface));
1027     }
1028     if (dirty) {
1029         memory_region_reset_dirty(&s->vga.vram, 0,
1030             surface_stride(surface) * surface_height(surface),
1031             DIRTY_MEMORY_VGA);
1032     }
1033 }
1034
1035 static void vmsvga_reset(DeviceState *dev)
1036 {
1037     struct pci_vmsvga_state_s *pci =
1038         DO_UPCAST(struct pci_vmsvga_state_s, card.qdev, dev);
1039     struct vmsvga_state_s *s = &pci->chip;
1040
1041     s->index = 0;
1042     s->enable = 0;
1043     s->config = 0;
1044     s->svgaid = SVGA_ID;
1045     s->cursor.on = 0;
1046     s->redraw_fifo_first = 0;
1047     s->redraw_fifo_last = 0;
1048     s->syncing = 0;
1049
1050     vga_dirty_log_start(&s->vga);
1051 }
1052
1053 static void vmsvga_invalidate_display(void *opaque)
1054 {
1055     struct vmsvga_state_s *s = opaque;
1056     if (!s->enable) {
1057         s->vga.invalidate(&s->vga);
1058         return;
1059     }
1060
1061     s->invalidated = 1;
1062 }
1063
1064 /* save the vga display in a PPM image even if no display is
1065    available */
1066 static void vmsvga_screen_dump(void *opaque, const char *filename, bool cswitch,
1067                                Error **errp)
1068 {
1069     struct vmsvga_state_s *s = opaque;
1070     DisplaySurface *surface = qemu_console_surface(s->vga.con);
1071
1072     if (!s->enable) {
1073         s->vga.screen_dump(&s->vga, filename, cswitch, errp);
1074         return;
1075     }
1076
1077     if (surface_bits_per_pixel(surface) == 32) {
1078         DisplaySurface *ds = qemu_create_displaysurface_from(
1079                                  surface_width(surface),
1080                                  surface_height(surface),
1081                                  32,
1082                                  surface_stride(surface),
1083                                  s->vga.vram_ptr, false);
1084         ppm_save(filename, ds, errp);
1085         g_free(ds);
1086     }
1087 }
1088
1089 static void vmsvga_text_update(void *opaque, console_ch_t *chardata)
1090 {
1091     struct vmsvga_state_s *s = opaque;
1092
1093     if (s->vga.text_update) {
1094         s->vga.text_update(&s->vga, chardata);
1095     }
1096 }
1097
1098 static int vmsvga_post_load(void *opaque, int version_id)
1099 {
1100     struct vmsvga_state_s *s = opaque;
1101
1102     s->invalidated = 1;
1103     if (s->config) {
1104         s->fifo = (uint32_t *) s->fifo_ptr;
1105     }
1106     return 0;
1107 }
1108
1109 static const VMStateDescription vmstate_vmware_vga_internal = {
1110     .name = "vmware_vga_internal",
1111     .version_id = 0,
1112     .minimum_version_id = 0,
1113     .minimum_version_id_old = 0,
1114     .post_load = vmsvga_post_load,
1115     .fields      = (VMStateField[]) {
1116         VMSTATE_INT32_EQUAL(depth, struct vmsvga_state_s),
1117         VMSTATE_INT32(enable, struct vmsvga_state_s),
1118         VMSTATE_INT32(config, struct vmsvga_state_s),
1119         VMSTATE_INT32(cursor.id, struct vmsvga_state_s),
1120         VMSTATE_INT32(cursor.x, struct vmsvga_state_s),
1121         VMSTATE_INT32(cursor.y, struct vmsvga_state_s),
1122         VMSTATE_INT32(cursor.on, struct vmsvga_state_s),
1123         VMSTATE_INT32(index, struct vmsvga_state_s),
1124         VMSTATE_VARRAY_INT32(scratch, struct vmsvga_state_s,
1125                              scratch_size, 0, vmstate_info_uint32, uint32_t),
1126         VMSTATE_INT32(new_width, struct vmsvga_state_s),
1127         VMSTATE_INT32(new_height, struct vmsvga_state_s),
1128         VMSTATE_UINT32(guest, struct vmsvga_state_s),
1129         VMSTATE_UINT32(svgaid, struct vmsvga_state_s),
1130         VMSTATE_INT32(syncing, struct vmsvga_state_s),
1131         VMSTATE_UNUSED(4), /* was fb_size */
1132         VMSTATE_END_OF_LIST()
1133     }
1134 };
1135
1136 static const VMStateDescription vmstate_vmware_vga = {
1137     .name = "vmware_vga",
1138     .version_id = 0,
1139     .minimum_version_id = 0,
1140     .minimum_version_id_old = 0,
1141     .fields      = (VMStateField[]) {
1142         VMSTATE_PCI_DEVICE(card, struct pci_vmsvga_state_s),
1143         VMSTATE_STRUCT(chip, struct pci_vmsvga_state_s, 0,
1144                        vmstate_vmware_vga_internal, struct vmsvga_state_s),
1145         VMSTATE_END_OF_LIST()
1146     }
1147 };
1148
1149 static void vmsvga_init(struct vmsvga_state_s *s,
1150                         MemoryRegion *address_space, MemoryRegion *io)
1151 {
1152     DisplaySurface *surface;
1153
1154     s->scratch_size = SVGA_SCRATCH_SIZE;
1155     s->scratch = g_malloc(s->scratch_size * 4);
1156
1157     s->vga.con = graphic_console_init(vmsvga_update_display,
1158                                       vmsvga_invalidate_display,
1159                                       vmsvga_screen_dump,
1160                                       vmsvga_text_update, s);
1161     surface = qemu_console_surface(s->vga.con);
1162
1163     s->fifo_size = SVGA_FIFO_SIZE;
1164     memory_region_init_ram(&s->fifo_ram, "vmsvga.fifo", s->fifo_size);
1165     vmstate_register_ram_global(&s->fifo_ram);
1166     s->fifo_ptr = memory_region_get_ram_ptr(&s->fifo_ram);
1167
1168     vga_common_init(&s->vga);
1169     vga_init(&s->vga, address_space, io, true);
1170     vmstate_register(NULL, 0, &vmstate_vga_common, &s->vga);
1171     /* Save some values here in case they are changed later.
1172      * This is suspicious and needs more though why it is needed. */
1173     s->depth = surface_bits_per_pixel(surface);
1174     s->bypp = surface_bytes_per_pixel(surface);
1175 }
1176
1177 static uint64_t vmsvga_io_read(void *opaque, hwaddr addr, unsigned size)
1178 {
1179     struct vmsvga_state_s *s = opaque;
1180
1181     switch (addr) {
1182     case SVGA_IO_MUL * SVGA_INDEX_PORT: return vmsvga_index_read(s, addr);
1183     case SVGA_IO_MUL * SVGA_VALUE_PORT: return vmsvga_value_read(s, addr);
1184     case SVGA_IO_MUL * SVGA_BIOS_PORT: return vmsvga_bios_read(s, addr);
1185     default: return -1u;
1186     }
1187 }
1188
1189 static void vmsvga_io_write(void *opaque, hwaddr addr,
1190                             uint64_t data, unsigned size)
1191 {
1192     struct vmsvga_state_s *s = opaque;
1193
1194     switch (addr) {
1195     case SVGA_IO_MUL * SVGA_INDEX_PORT:
1196         vmsvga_index_write(s, addr, data);
1197         break;
1198     case SVGA_IO_MUL * SVGA_VALUE_PORT:
1199         vmsvga_value_write(s, addr, data);
1200         break;
1201     case SVGA_IO_MUL * SVGA_BIOS_PORT:
1202         vmsvga_bios_write(s, addr, data);
1203         break;
1204     }
1205 }
1206
1207 static const MemoryRegionOps vmsvga_io_ops = {
1208     .read = vmsvga_io_read,
1209     .write = vmsvga_io_write,
1210     .endianness = DEVICE_LITTLE_ENDIAN,
1211     .valid = {
1212         .min_access_size = 4,
1213         .max_access_size = 4,
1214     },
1215 };
1216
1217 static int pci_vmsvga_initfn(PCIDevice *dev)
1218 {
1219     struct pci_vmsvga_state_s *s =
1220         DO_UPCAST(struct pci_vmsvga_state_s, card, dev);
1221
1222     s->card.config[PCI_CACHE_LINE_SIZE] = 0x08;         /* Cache line size */
1223     s->card.config[PCI_LATENCY_TIMER] = 0x40;           /* Latency timer */
1224     s->card.config[PCI_INTERRUPT_LINE] = 0xff;          /* End */
1225
1226     memory_region_init_io(&s->io_bar, &vmsvga_io_ops, &s->chip,
1227                           "vmsvga-io", 0x10);
1228     memory_region_set_flush_coalesced(&s->io_bar);
1229     pci_register_bar(&s->card, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
1230
1231     vmsvga_init(&s->chip, pci_address_space(dev), pci_address_space_io(dev));
1232
1233     pci_register_bar(&s->card, 1, PCI_BASE_ADDRESS_MEM_PREFETCH,
1234                      &s->chip.vga.vram);
1235     pci_register_bar(&s->card, 2, PCI_BASE_ADDRESS_MEM_PREFETCH,
1236                      &s->chip.fifo_ram);
1237
1238     if (!dev->rom_bar) {
1239         /* compatibility with pc-0.13 and older */
1240         vga_init_vbe(&s->chip.vga, pci_address_space(dev));
1241     }
1242
1243     return 0;
1244 }
1245
1246 static Property vga_vmware_properties[] = {
1247     DEFINE_PROP_UINT32("vgamem_mb", struct pci_vmsvga_state_s,
1248                        chip.vga.vram_size_mb, 16),
1249     DEFINE_PROP_END_OF_LIST(),
1250 };
1251
1252 static void vmsvga_class_init(ObjectClass *klass, void *data)
1253 {
1254     DeviceClass *dc = DEVICE_CLASS(klass);
1255     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1256
1257     k->no_hotplug = 1;
1258     k->init = pci_vmsvga_initfn;
1259     k->romfile = "vgabios-vmware.bin";
1260     k->vendor_id = PCI_VENDOR_ID_VMWARE;
1261     k->device_id = SVGA_PCI_DEVICE_ID;
1262     k->class_id = PCI_CLASS_DISPLAY_VGA;
1263     k->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE;
1264     k->subsystem_id = SVGA_PCI_DEVICE_ID;
1265     dc->reset = vmsvga_reset;
1266     dc->vmsd = &vmstate_vmware_vga;
1267     dc->props = vga_vmware_properties;
1268 }
1269
1270 static const TypeInfo vmsvga_info = {
1271     .name          = "vmware-svga",
1272     .parent        = TYPE_PCI_DEVICE,
1273     .instance_size = sizeof(struct pci_vmsvga_state_s),
1274     .class_init    = vmsvga_class_init,
1275 };
1276
1277 static void vmsvga_register_types(void)
1278 {
1279     type_register_static(&vmsvga_info);
1280 }
1281
1282 type_init(vmsvga_register_types)