hw/pci.c

   1 /*
   2  * QEMU PCI bus manager
   3  *
   4  * Copyright (c) 2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "monitor.h"
  27 #include "net.h"
  28 #include "sysemu.h"
  29
  30 //#define DEBUG_PCI
  31 #ifdef DEBUG_PCI
  32 # define PCI_DPRINTF(format, ...)       printf(format, ## __VA_ARGS__)
  33 #else
  34 # define PCI_DPRINTF(format, ...)       do { } while (0)
  35 #endif
  36
  37 struct PCIBus {
  38     BusState qbus;
  39     int devfn_min;
  40     pci_set_irq_fn set_irq;
  41     pci_map_irq_fn map_irq;
  42     pci_hotplug_fn hotplug;
  43     uint32_t config_reg; /* XXX: suppress */
  44     void *irq_opaque;
  45     PCIDevice *devices[256];
  46     PCIDevice *parent_dev;
  47
  48     QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */
  49     QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */
  50
  51     /* The bus IRQ state is the logical OR of the connected devices.
  52        Keep a count of the number of devices with raised IRQs.  */
  53     int nirq;
  54     int *irq_count;
  55 };
  56
  57 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
  58
  59 static struct BusInfo pci_bus_info = {
  60     .name       = "PCI",
  61     .size       = sizeof(PCIBus),
  62     .print_dev  = pcibus_dev_print,
  63     .props      = (Property[]) {
  64         DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
  65         DEFINE_PROP_END_OF_LIST()
  66     }
  67 };
  68
  69 static void pci_update_mappings(PCIDevice *d);
  70 static void pci_set_irq(void *opaque, int irq_num, int level);
  71
  72 target_phys_addr_t pci_mem_base;
  73 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
  74 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
  75
  76 struct PCIHostBus {
  77     int domain;
  78     struct PCIBus *bus;
  79     QLIST_ENTRY(PCIHostBus) next;
  80 };
  81 static QLIST_HEAD(, PCIHostBus) host_buses;
  82
  83 static const VMStateDescription vmstate_pcibus = {
  84     .name = "PCIBUS",
  85     .version_id = 1,
  86     .minimum_version_id = 1,
  87     .minimum_version_id_old = 1,
  88     .fields      = (VMStateField []) {
  89         VMSTATE_INT32_EQUAL(nirq, PCIBus),
  90         VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
  91         VMSTATE_END_OF_LIST()
  92     }
  93 };
  94
  95 static int pci_bar(PCIDevice *d, int reg)
  96 {
  97     uint8_t type;
  98
  99     if (reg != PCI_ROM_SLOT)
 100         return PCI_BASE_ADDRESS_0 + reg * 4;
 101
 102     type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
 103     return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
 104 }
 105
 106 static void pci_device_reset(PCIDevice *dev)
 107 {
 108     int r;
 109
 110     memset(dev->irq_state, 0, sizeof dev->irq_state);
 111     dev->config[PCI_COMMAND] &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
 112                                   PCI_COMMAND_MASTER);
 113     dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
 114     dev->config[PCI_INTERRUPT_LINE] = 0x0;
 115     for (r = 0; r < PCI_NUM_REGIONS; ++r) {
 116         if (!dev->io_regions[r].size) {
 117             continue;
 118         }
 119         pci_set_long(dev->config + pci_bar(dev, r), dev->io_regions[r].type);
 120     }
 121     pci_update_mappings(dev);
 122 }
 123
 124 static void pci_bus_reset(void *opaque)
 125 {
 126     PCIBus *bus = opaque;
 127     int i;
 128
 129     for (i = 0; i < bus->nirq; i++) {
 130         bus->irq_count[i] = 0;
 131     }
 132     for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
 133         if (bus->devices[i]) {
 134             pci_device_reset(bus->devices[i]);
 135         }
 136     }
 137 }
 138
 139 static void pci_host_bus_register(int domain, PCIBus *bus)
 140 {
 141     struct PCIHostBus *host;
 142     host = qemu_mallocz(sizeof(*host));
 143     host->domain = domain;
 144     host->bus = bus;
 145     QLIST_INSERT_HEAD(&host_buses, host, next);
 146 }
 147
 148 PCIBus *pci_find_root_bus(int domain)
 149 {
 150     struct PCIHostBus *host;
 151
 152     QLIST_FOREACH(host, &host_buses, next) {
 153         if (host->domain == domain) {
 154             return host->bus;
 155         }
 156     }
 157
 158     return NULL;
 159 }
 160
 161 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 162                          const char *name, int devfn_min)
 163 {
 164     qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name);
 165     bus->devfn_min = devfn_min;
 166
 167     /* host bridge */
 168     QLIST_INIT(&bus->child);
 169     pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */
 170
 171     vmstate_register(-1, &vmstate_pcibus, bus);
 172     qemu_register_reset(pci_bus_reset, bus);
 173 }
 174
 175 PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min)
 176 {
 177     PCIBus *bus;
 178
 179     bus = qemu_mallocz(sizeof(*bus));
 180     bus->qbus.qdev_allocated = 1;
 181     pci_bus_new_inplace(bus, parent, name, devfn_min);
 182     return bus;
 183 }
 184
 185 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 186                   void *irq_opaque, int nirq)
 187 {
 188     bus->set_irq = set_irq;
 189     bus->map_irq = map_irq;
 190     bus->irq_opaque = irq_opaque;
 191     bus->nirq = nirq;
 192     bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0]));
 193 }
 194
 195 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug)
 196 {
 197     bus->qbus.allow_hotplug = 1;
 198     bus->hotplug = hotplug;
 199 }
 200
 201 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 202                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 203                          void *irq_opaque, int devfn_min, int nirq)
 204 {
 205     PCIBus *bus;
 206
 207     bus = pci_bus_new(parent, name, devfn_min);
 208     pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
 209     return bus;
 210 }
 211
 212 static void pci_register_secondary_bus(PCIBus *parent,
 213                                        PCIBus *bus,
 214                                        PCIDevice *dev,
 215                                        pci_map_irq_fn map_irq,
 216                                        const char *name)
 217 {
 218     qbus_create_inplace(&bus->qbus, &pci_bus_info, &dev->qdev, name);
 219     bus->map_irq = map_irq;
 220     bus->parent_dev = dev;
 221
 222     QLIST_INIT(&bus->child);
 223     QLIST_INSERT_HEAD(&parent->child, bus, sibling);
 224 }
 225
 226 static void pci_unregister_secondary_bus(PCIBus *bus)
 227 {
 228     assert(QLIST_EMPTY(&bus->child));
 229     QLIST_REMOVE(bus, sibling);
 230 }
 231
 232 int pci_bus_num(PCIBus *s)
 233 {
 234     if (!s->parent_dev)
 235         return 0;       /* pci host bridge */
 236     return s->parent_dev->config[PCI_SECONDARY_BUS];
 237 }
 238
 239 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
 240 {
 241     PCIDevice *s = container_of(pv, PCIDevice, config);
 242     uint8_t *config;
 243     int i;
 244
 245     assert(size == pci_config_size(s));
 246     config = qemu_malloc(size);
 247
 248     qemu_get_buffer(f, config, size);
 249     for (i = 0; i < size; ++i) {
 250         if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i]) {
 251             qemu_free(config);
 252             return -EINVAL;
 253         }
 254     }
 255     memcpy(s->config, config, size);
 256
 257     pci_update_mappings(s);
 258
 259     qemu_free(config);
 260     return 0;
 261 }
 262
 263 /* just put buffer */
 264 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
 265 {
 266     const uint8_t **v = pv;
 267     assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
 268     qemu_put_buffer(f, *v, size);
 269 }
 270
 271 static VMStateInfo vmstate_info_pci_config = {
 272     .name = "pci config",
 273     .get  = get_pci_config_device,
 274     .put  = put_pci_config_device,
 275 };
 276
 277 const VMStateDescription vmstate_pci_device = {
 278     .name = "PCIDevice",
 279     .version_id = 2,
 280     .minimum_version_id = 1,
 281     .minimum_version_id_old = 1,
 282     .fields      = (VMStateField []) {
 283         VMSTATE_INT32_LE(version_id, PCIDevice),
 284         VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
 285                                    vmstate_info_pci_config,
 286                                    PCI_CONFIG_SPACE_SIZE),
 287         VMSTATE_INT32_ARRAY_V(irq_state, PCIDevice, PCI_NUM_PINS, 2),
 288         VMSTATE_END_OF_LIST()
 289     }
 290 };
 291
 292 const VMStateDescription vmstate_pcie_device = {
 293     .name = "PCIDevice",
 294     .version_id = 2,
 295     .minimum_version_id = 1,
 296     .minimum_version_id_old = 1,
 297     .fields      = (VMStateField []) {
 298         VMSTATE_INT32_LE(version_id, PCIDevice),
 299         VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
 300                                    vmstate_info_pci_config,
 301                                    PCIE_CONFIG_SPACE_SIZE),
 302         VMSTATE_INT32_ARRAY_V(irq_state, PCIDevice, PCI_NUM_PINS, 2),
 303         VMSTATE_END_OF_LIST()
 304     }
 305 };
 306
 307 static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
 308 {
 309     return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
 310 }
 311
 312 void pci_device_save(PCIDevice *s, QEMUFile *f)
 313 {
 314     vmstate_save_state(f, pci_get_vmstate(s), s);
 315 }
 316
 317 int pci_device_load(PCIDevice *s, QEMUFile *f)
 318 {
 319     return vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
 320 }
 321
 322 static int pci_set_default_subsystem_id(PCIDevice *pci_dev)
 323 {
 324     uint16_t *id;
 325
 326     id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]);
 327     id[0] = cpu_to_le16(pci_default_sub_vendor_id);
 328     id[1] = cpu_to_le16(pci_default_sub_device_id);
 329     return 0;
 330 }
 331
 332 /*
 333  * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
 334  */
 335 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
 336 {
 337     const char *p;
 338     char *e;
 339     unsigned long val;
 340     unsigned long dom = 0, bus = 0;
 341     unsigned slot = 0;
 342
 343     p = addr;
 344     val = strtoul(p, &e, 16);
 345     if (e == p)
 346         return -1;
 347     if (*e == ':') {
 348         bus = val;
 349         p = e + 1;
 350         val = strtoul(p, &e, 16);
 351         if (e == p)
 352             return -1;
 353         if (*e == ':') {
 354             dom = bus;
 355             bus = val;
 356             p = e + 1;
 357             val = strtoul(p, &e, 16);
 358             if (e == p)
 359                 return -1;
 360         }
 361     }
 362
 363     if (dom > 0xffff || bus > 0xff || val > 0x1f)
 364         return -1;
 365
 366     slot = val;
 367
 368     if (*e)
 369         return -1;
 370
 371     /* Note: QEMU doesn't implement domains other than 0 */
 372     if (!pci_find_bus(pci_find_root_bus(dom), bus))
 373         return -1;
 374
 375     *domp = dom;
 376     *busp = bus;
 377     *slotp = slot;
 378     return 0;
 379 }
 380
 381 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 382                      unsigned *slotp)
 383 {
 384     /* strip legacy tag */
 385     if (!strncmp(addr, "pci_addr=", 9)) {
 386         addr += 9;
 387     }
 388     if (pci_parse_devaddr(addr, domp, busp, slotp)) {
 389         monitor_printf(mon, "Invalid pci address\n");
 390         return -1;
 391     }
 392     return 0;
 393 }
 394
 395 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
 396 {
 397     int dom, bus;
 398     unsigned slot;
 399
 400     if (!devaddr) {
 401         *devfnp = -1;
 402         return pci_find_bus(pci_find_root_bus(0), 0);
 403     }
 404
 405     if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) {
 406         return NULL;
 407     }
 408
 409     *devfnp = slot << 3;
 410     return pci_find_bus(pci_find_root_bus(0), bus);
 411 }
 412
 413 static void pci_init_cmask(PCIDevice *dev)
 414 {
 415     pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
 416     pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
 417     dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
 418     dev->cmask[PCI_REVISION_ID] = 0xff;
 419     dev->cmask[PCI_CLASS_PROG] = 0xff;
 420     pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
 421     dev->cmask[PCI_HEADER_TYPE] = 0xff;
 422     dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
 423 }
 424
 425 static void pci_init_wmask(PCIDevice *dev)
 426 {
 427     int config_size = pci_config_size(dev);
 428
 429     dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
 430     dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
 431     pci_set_word(dev->wmask + PCI_COMMAND,
 432                  PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 433
 434     memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
 435            config_size - PCI_CONFIG_HEADER_SIZE);
 436 }
 437
 438 static void pci_init_wmask_bridge(PCIDevice *d)
 439 {
 440     /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
 441        PCI_SEC_LETENCY_TIMER */
 442     memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
 443
 444     /* base and limit */
 445     d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
 446     d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
 447     pci_set_word(d->wmask + PCI_MEMORY_BASE,
 448                  PCI_MEMORY_RANGE_MASK & 0xffff);
 449     pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
 450                  PCI_MEMORY_RANGE_MASK & 0xffff);
 451     pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
 452                  PCI_PREF_RANGE_MASK & 0xffff);
 453     pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
 454                  PCI_PREF_RANGE_MASK & 0xffff);
 455
 456     /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
 457     memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
 458
 459     pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 0xffff);
 460 }
 461
 462 static void pci_config_alloc(PCIDevice *pci_dev)
 463 {
 464     int config_size = pci_config_size(pci_dev);
 465
 466     pci_dev->config = qemu_mallocz(config_size);
 467     pci_dev->cmask = qemu_mallocz(config_size);
 468     pci_dev->wmask = qemu_mallocz(config_size);
 469     pci_dev->used = qemu_mallocz(config_size);
 470 }
 471
 472 static void pci_config_free(PCIDevice *pci_dev)
 473 {
 474     qemu_free(pci_dev->config);
 475     qemu_free(pci_dev->cmask);
 476     qemu_free(pci_dev->wmask);
 477     qemu_free(pci_dev->used);
 478 }
 479
 480 /* -1 for devfn means auto assign */
 481 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
 482                                          const char *name, int devfn,
 483                                          PCIConfigReadFunc *config_read,
 484                                          PCIConfigWriteFunc *config_write,
 485                                          uint8_t header_type)
 486 {
 487     if (devfn < 0) {
 488         for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
 489             devfn += 8) {
 490             if (!bus->devices[devfn])
 491                 goto found;
 492         }
 493         hw_error("PCI: no devfn available for %s, all in use\n", name);
 494     found: ;
 495     } else if (bus->devices[devfn]) {
 496         hw_error("PCI: devfn %d not available for %s, in use by %s\n", devfn,
 497                  name, bus->devices[devfn]->name);
 498     }
 499     pci_dev->bus = bus;
 500     pci_dev->devfn = devfn;
 501     pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
 502     memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state));
 503     pci_config_alloc(pci_dev);
 504
 505     header_type &= ~PCI_HEADER_TYPE_MULTI_FUNCTION;
 506     if (header_type == PCI_HEADER_TYPE_NORMAL) {
 507         pci_set_default_subsystem_id(pci_dev);
 508     }
 509     pci_init_cmask(pci_dev);
 510     pci_init_wmask(pci_dev);
 511     if (header_type == PCI_HEADER_TYPE_BRIDGE) {
 512         pci_init_wmask_bridge(pci_dev);
 513     }
 514
 515     if (!config_read)
 516         config_read = pci_default_read_config;
 517     if (!config_write)
 518         config_write = pci_default_write_config;
 519     pci_dev->config_read = config_read;
 520     pci_dev->config_write = config_write;
 521     bus->devices[devfn] = pci_dev;
 522     pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS);
 523     pci_dev->version_id = 2; /* Current pci device vmstate version */
 524     return pci_dev;
 525 }
 526
 527 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 528                                int instance_size, int devfn,
 529                                PCIConfigReadFunc *config_read,
 530                                PCIConfigWriteFunc *config_write)
 531 {
 532     PCIDevice *pci_dev;
 533
 534     pci_dev = qemu_mallocz(instance_size);
 535     pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
 536                                      config_read, config_write,
 537                                      PCI_HEADER_TYPE_NORMAL);
 538     return pci_dev;
 539 }
 540 static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
 541 {
 542     return addr + pci_mem_base;
 543 }
 544
 545 static void pci_unregister_io_regions(PCIDevice *pci_dev)
 546 {
 547     PCIIORegion *r;
 548     int i;
 549
 550     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 551         r = &pci_dev->io_regions[i];
 552         if (!r->size || r->addr == PCI_BAR_UNMAPPED)
 553             continue;
 554         if (r->type == PCI_BASE_ADDRESS_SPACE_IO) {
 555             isa_unassign_ioport(r->addr, r->filtered_size);
 556         } else {
 557             cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 558                                                      r->filtered_size,
 559                                                      IO_MEM_UNASSIGNED);
 560         }
 561     }
 562 }
 563
 564 static int pci_unregister_device(DeviceState *dev)
 565 {
 566     PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
 567     PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info);
 568     int ret = 0;
 569
 570     if (info->exit)
 571         ret = info->exit(pci_dev);
 572     if (ret)
 573         return ret;
 574
 575     pci_unregister_io_regions(pci_dev);
 576
 577     qemu_free_irqs(pci_dev->irq);
 578     pci_dev->bus->devices[pci_dev->devfn] = NULL;
 579     pci_config_free(pci_dev);
 580     return 0;
 581 }
 582
 583 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 584                             pcibus_t size, int type,
 585                             PCIMapIORegionFunc *map_func)
 586 {
 587     PCIIORegion *r;
 588     uint32_t addr;
 589     pcibus_t wmask;
 590
 591     if ((unsigned int)region_num >= PCI_NUM_REGIONS)
 592         return;
 593
 594     if (size & (size-1)) {
 595         fprintf(stderr, "ERROR: PCI region size must be pow2 "
 596                     "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
 597         exit(1);
 598     }
 599
 600     r = &pci_dev->io_regions[region_num];
 601     r->addr = PCI_BAR_UNMAPPED;
 602     r->size = size;
 603     r->filtered_size = size;
 604     r->type = type;
 605     r->map_func = map_func;
 606
 607     wmask = ~(size - 1);
 608     addr = pci_bar(pci_dev, region_num);
 609     if (region_num == PCI_ROM_SLOT) {
 610         /* ROM enable bit is writeable */
 611         wmask |= PCI_ROM_ADDRESS_ENABLE;
 612     }
 613     pci_set_long(pci_dev->config + addr, type);
 614     if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
 615         r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
 616         pci_set_quad(pci_dev->wmask + addr, wmask);
 617         pci_set_quad(pci_dev->cmask + addr, ~0ULL);
 618     } else {
 619         pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
 620         pci_set_long(pci_dev->cmask + addr, 0xffffffff);
 621     }
 622 }
 623
 624 static uint32_t pci_config_get_io_base(PCIDevice *d,
 625                                        uint32_t base, uint32_t base_upper16)
 626 {
 627     uint32_t val;
 628
 629     val = ((uint32_t)d->config[base] & PCI_IO_RANGE_MASK) << 8;
 630     if (d->config[base] & PCI_IO_RANGE_TYPE_32) {
 631         val |= (uint32_t)pci_get_word(d->config + base_upper16) << 16;
 632     }
 633     return val;
 634 }
 635
 636 static pcibus_t pci_config_get_memory_base(PCIDevice *d, uint32_t base)
 637 {
 638     return ((pcibus_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK)
 639         << 16;
 640 }
 641
 642 static pcibus_t pci_config_get_pref_base(PCIDevice *d,
 643                                          uint32_t base, uint32_t upper)
 644 {
 645     pcibus_t tmp;
 646     pcibus_t val;
 647
 648     tmp = (pcibus_t)pci_get_word(d->config + base);
 649     val = (tmp & PCI_PREF_RANGE_MASK) << 16;
 650     if (tmp & PCI_PREF_RANGE_TYPE_64) {
 651         val |= (pcibus_t)pci_get_long(d->config + upper) << 32;
 652     }
 653     return val;
 654 }
 655
 656 static pcibus_t pci_bridge_get_base(PCIDevice *bridge, uint8_t type)
 657 {
 658     pcibus_t base;
 659     if (type & PCI_BASE_ADDRESS_SPACE_IO) {
 660         base = pci_config_get_io_base(bridge,
 661                                       PCI_IO_BASE, PCI_IO_BASE_UPPER16);
 662     } else {
 663         if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
 664             base = pci_config_get_pref_base(
 665                 bridge, PCI_PREF_MEMORY_BASE, PCI_PREF_BASE_UPPER32);
 666         } else {
 667             base = pci_config_get_memory_base(bridge, PCI_MEMORY_BASE);
 668         }
 669     }
 670
 671     return base;
 672 }
 673
 674 static pcibus_t pci_bridge_get_limit(PCIDevice *bridge, uint8_t type)
 675 {
 676     pcibus_t limit;
 677     if (type & PCI_BASE_ADDRESS_SPACE_IO) {
 678         limit = pci_config_get_io_base(bridge,
 679                                       PCI_IO_LIMIT, PCI_IO_LIMIT_UPPER16);
 680         limit |= 0xfff;         /* PCI bridge spec 3.2.5.6. */
 681     } else {
 682         if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
 683             limit = pci_config_get_pref_base(
 684                 bridge, PCI_PREF_MEMORY_LIMIT, PCI_PREF_LIMIT_UPPER32);
 685         } else {
 686             limit = pci_config_get_memory_base(bridge, PCI_MEMORY_LIMIT);
 687         }
 688         limit |= 0xfffff;       /* PCI bridge spec 3.2.5.{1, 8}. */
 689     }
 690     return limit;
 691 }
 692
 693 static void pci_bridge_filter(PCIDevice *d, pcibus_t *addr, pcibus_t *size,
 694                               uint8_t type)
 695 {
 696     pcibus_t base = *addr;
 697     pcibus_t limit = *addr + *size - 1;
 698     PCIDevice *br;
 699
 700     for (br = d->bus->parent_dev; br; br = br->bus->parent_dev) {
 701         uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
 702
 703         if (type & PCI_BASE_ADDRESS_SPACE_IO) {
 704             if (!(cmd & PCI_COMMAND_IO)) {
 705                 goto no_map;
 706             }
 707         } else {
 708             if (!(cmd & PCI_COMMAND_MEMORY)) {
 709                 goto no_map;
 710             }
 711         }
 712
 713         base = MAX(base, pci_bridge_get_base(br, type));
 714         limit = MIN(limit, pci_bridge_get_limit(br, type));
 715     }
 716
 717     if (base > limit) {
 718         goto no_map;
 719     }
 720     *addr = base;
 721     *size = limit - base + 1;
 722     return;
 723 no_map:
 724     *addr = PCI_BAR_UNMAPPED;
 725     *size = 0;
 726 }
 727
 728 static pcibus_t pci_bar_address(PCIDevice *d,
 729                                 int reg, uint8_t type, pcibus_t size)
 730 {
 731     pcibus_t new_addr, last_addr;
 732     int bar = pci_bar(d, reg);
 733     uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
 734
 735     if (type & PCI_BASE_ADDRESS_SPACE_IO) {
 736         if (!(cmd & PCI_COMMAND_IO)) {
 737             return PCI_BAR_UNMAPPED;
 738         }
 739         new_addr = pci_get_long(d->config + bar) & ~(size - 1);
 740         last_addr = new_addr + size - 1;
 741         /* NOTE: we have only 64K ioports on PC */
 742         if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) {
 743             return PCI_BAR_UNMAPPED;
 744         }
 745         return new_addr;
 746     }
 747
 748     if (!(cmd & PCI_COMMAND_MEMORY)) {
 749         return PCI_BAR_UNMAPPED;
 750     }
 751     if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
 752         new_addr = pci_get_quad(d->config + bar);
 753     } else {
 754         new_addr = pci_get_long(d->config + bar);
 755     }
 756     /* the ROM slot has a specific enable bit */
 757     if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
 758         return PCI_BAR_UNMAPPED;
 759     }
 760     new_addr &= ~(size - 1);
 761     last_addr = new_addr + size - 1;
 762     /* NOTE: we do not support wrapping */
 763     /* XXX: as we cannot support really dynamic
 764        mappings, we handle specific values as invalid
 765        mappings. */
 766     if (last_addr <= new_addr || new_addr == 0 ||
 767         last_addr == PCI_BAR_UNMAPPED) {
 768         return PCI_BAR_UNMAPPED;
 769     }
 770
 771     /* Now pcibus_t is 64bit.
 772      * Check if 32 bit BAR wraps around explicitly.
 773      * Without this, PC ide doesn't work well.
 774      * TODO: remove this work around.
 775      */
 776     if  (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
 777         return PCI_BAR_UNMAPPED;
 778     }
 779
 780     /*
 781      * OS is allowed to set BAR beyond its addressable
 782      * bits. For example, 32 bit OS can set 64bit bar
 783      * to >4G. Check it. TODO: we might need to support
 784      * it in the future for e.g. PAE.
 785      */
 786     if (last_addr >= TARGET_PHYS_ADDR_MAX) {
 787         return PCI_BAR_UNMAPPED;
 788     }
 789
 790     return new_addr;
 791 }
 792
 793 static void pci_update_mappings(PCIDevice *d)
 794 {
 795     PCIIORegion *r;
 796     int i;
 797     pcibus_t new_addr, filtered_size;
 798
 799     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 800         r = &d->io_regions[i];
 801
 802         /* this region isn't registered */
 803         if (!r->size)
 804             continue;
 805
 806         new_addr = pci_bar_address(d, i, r->type, r->size);
 807
 808         /* bridge filtering */
 809         filtered_size = r->size;
 810         if (new_addr != PCI_BAR_UNMAPPED) {
 811             pci_bridge_filter(d, &new_addr, &filtered_size, r->type);
 812         }
 813
 814         /* This bar isn't changed */
 815         if (new_addr == r->addr && filtered_size == r->filtered_size)
 816             continue;
 817
 818         /* now do the real mapping */
 819         if (r->addr != PCI_BAR_UNMAPPED) {
 820             if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
 821                 int class;
 822                 /* NOTE: specific hack for IDE in PC case:
 823                    only one byte must be mapped. */
 824                 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
 825                 if (class == 0x0101 && r->size == 4) {
 826                     isa_unassign_ioport(r->addr + 2, 1);
 827                 } else {
 828                     isa_unassign_ioport(r->addr, r->filtered_size);
 829                 }
 830             } else {
 831                 cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 832                                              r->filtered_size,
 833                                              IO_MEM_UNASSIGNED);
 834                 qemu_unregister_coalesced_mmio(r->addr, r->filtered_size);
 835             }
 836         }
 837         r->addr = new_addr;
 838         r->filtered_size = filtered_size;
 839         if (r->addr != PCI_BAR_UNMAPPED) {
 840             /*
 841              * TODO: currently almost all the map funcions assumes
 842              * filtered_size == size and addr & ~(size - 1) == addr.
 843              * However with bridge filtering, they aren't always true.
 844              * Teach them such cases, such that filtered_size < size and
 845              * addr & (size - 1) != 0.
 846              */
 847             r->map_func(d, i, r->addr, r->filtered_size, r->type);
 848         }
 849     }
 850 }
 851
 852 uint32_t pci_default_read_config(PCIDevice *d,
 853                                  uint32_t address, int len)
 854 {
 855     uint32_t val = 0;
 856     assert(len == 1 || len == 2 || len == 4);
 857     len = MIN(len, pci_config_size(d) - address);
 858     memcpy(&val, d->config + address, len);
 859     return le32_to_cpu(val);
 860 }
 861
 862 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
 863 {
 864     int i;
 865     uint32_t config_size = pci_config_size(d);
 866
 867     for (i = 0; i < l && addr + i < config_size; val >>= 8, ++i) {
 868         uint8_t wmask = d->wmask[addr + i];
 869         d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
 870     }
 871     if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
 872         ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
 873         ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
 874         range_covers_byte(addr, l, PCI_COMMAND))
 875         pci_update_mappings(d);
 876 }
 877
 878 /***********************************************************/
 879 /* generic PCI irq support */
 880
 881 /* 0 <= irq_num <= 3. level must be 0 or 1 */
 882 static void pci_set_irq(void *opaque, int irq_num, int level)
 883 {
 884     PCIDevice *pci_dev = opaque;
 885     PCIBus *bus;
 886     int change;
 887
 888     change = level - pci_dev->irq_state[irq_num];
 889     if (!change)
 890         return;
 891
 892     pci_dev->irq_state[irq_num] = level;
 893     for (;;) {
 894         bus = pci_dev->bus;
 895         irq_num = bus->map_irq(pci_dev, irq_num);
 896         if (bus->set_irq)
 897             break;
 898         pci_dev = bus->parent_dev;
 899     }
 900     bus->irq_count[irq_num] += change;
 901     bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
 902 }
 903
 904 /***********************************************************/
 905 /* monitor info on PCI */
 906
 907 typedef struct {
 908     uint16_t class;
 909     const char *desc;
 910 } pci_class_desc;
 911
 912 static const pci_class_desc pci_class_descriptions[] =
 913 {
 914     { 0x0100, "SCSI controller"},
 915     { 0x0101, "IDE controller"},
 916     { 0x0102, "Floppy controller"},
 917     { 0x0103, "IPI controller"},
 918     { 0x0104, "RAID controller"},
 919     { 0x0106, "SATA controller"},
 920     { 0x0107, "SAS controller"},
 921     { 0x0180, "Storage controller"},
 922     { 0x0200, "Ethernet controller"},
 923     { 0x0201, "Token Ring controller"},
 924     { 0x0202, "FDDI controller"},
 925     { 0x0203, "ATM controller"},
 926     { 0x0280, "Network controller"},
 927     { 0x0300, "VGA controller"},
 928     { 0x0301, "XGA controller"},
 929     { 0x0302, "3D controller"},
 930     { 0x0380, "Display controller"},
 931     { 0x0400, "Video controller"},
 932     { 0x0401, "Audio controller"},
 933     { 0x0402, "Phone"},
 934     { 0x0480, "Multimedia controller"},
 935     { 0x0500, "RAM controller"},
 936     { 0x0501, "Flash controller"},
 937     { 0x0580, "Memory controller"},
 938     { 0x0600, "Host bridge"},
 939     { 0x0601, "ISA bridge"},
 940     { 0x0602, "EISA bridge"},
 941     { 0x0603, "MC bridge"},
 942     { 0x0604, "PCI bridge"},
 943     { 0x0605, "PCMCIA bridge"},
 944     { 0x0606, "NUBUS bridge"},
 945     { 0x0607, "CARDBUS bridge"},
 946     { 0x0608, "RACEWAY bridge"},
 947     { 0x0680, "Bridge"},
 948     { 0x0c03, "USB controller"},
 949     { 0, NULL}
 950 };
 951
 952 static void pci_info_device(PCIBus *bus, PCIDevice *d)
 953 {
 954     Monitor *mon = cur_mon;
 955     int i, class;
 956     PCIIORegion *r;
 957     const pci_class_desc *desc;
 958
 959     monitor_printf(mon, "  Bus %2d, device %3d, function %d:\n",
 960                    pci_bus_num(d->bus),
 961                    PCI_SLOT(d->devfn), PCI_FUNC(d->devfn));
 962     class = pci_get_word(d->config + PCI_CLASS_DEVICE);
 963     monitor_printf(mon, "    ");
 964     desc = pci_class_descriptions;
 965     while (desc->desc && class != desc->class)
 966         desc++;
 967     if (desc->desc) {
 968         monitor_printf(mon, "%s", desc->desc);
 969     } else {
 970         monitor_printf(mon, "Class %04x", class);
 971     }
 972     monitor_printf(mon, ": PCI device %04x:%04x\n",
 973            pci_get_word(d->config + PCI_VENDOR_ID),
 974            pci_get_word(d->config + PCI_DEVICE_ID));
 975
 976     if (d->config[PCI_INTERRUPT_PIN] != 0) {
 977         monitor_printf(mon, "      IRQ %d.\n",
 978                        d->config[PCI_INTERRUPT_LINE]);
 979     }
 980     if (class == 0x0604) {
 981         uint64_t base;
 982         uint64_t limit;
 983
 984         monitor_printf(mon, "      BUS %d.\n", d->config[0x19]);
 985         monitor_printf(mon, "      secondary bus %d.\n",
 986                        d->config[PCI_SECONDARY_BUS]);
 987         monitor_printf(mon, "      subordinate bus %d.\n",
 988                        d->config[PCI_SUBORDINATE_BUS]);
 989
 990         base = pci_bridge_get_base(d, PCI_BASE_ADDRESS_SPACE_IO);
 991         limit = pci_bridge_get_limit(d, PCI_BASE_ADDRESS_SPACE_IO);
 992         monitor_printf(mon, "      IO range [0x%04"PRIx64", 0x%04"PRIx64"]\n",
 993                        base, limit);
 994
 995         base = pci_bridge_get_base(d, PCI_BASE_ADDRESS_SPACE_MEMORY);
 996         limit= pci_bridge_get_limit(d, PCI_BASE_ADDRESS_SPACE_MEMORY);
 997         monitor_printf(mon,
 998                        "      memory range [0x%08"PRIx64", 0x%08"PRIx64"]\n",
 999                        base, limit);
1000
1001         base = pci_bridge_get_base(d, PCI_BASE_ADDRESS_SPACE_MEMORY |
1002                                    PCI_BASE_ADDRESS_MEM_PREFETCH);
1003         limit = pci_bridge_get_limit(d, PCI_BASE_ADDRESS_SPACE_MEMORY |
1004                                      PCI_BASE_ADDRESS_MEM_PREFETCH);
1005         monitor_printf(mon, "      prefetchable memory range "
1006                        "[0x%08"PRIx64", 0x%08"PRIx64"]\n", base, limit);
1007     }
1008     for(i = 0;i < PCI_NUM_REGIONS; i++) {
1009         r = &d->io_regions[i];
1010         if (r->size != 0) {
1011             monitor_printf(mon, "      BAR%d: ", i);
1012             if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1013                 monitor_printf(mon, "I/O at 0x%04"FMT_PCIBUS
1014                                " [0x%04"FMT_PCIBUS"].\n",
1015                                r->addr, r->addr + r->size - 1);
1016             } else {
1017                 const char *type = r->type & PCI_BASE_ADDRESS_MEM_TYPE_64 ?
1018                     "64 bit" : "32 bit";
1019                 const char *prefetch =
1020                     r->type & PCI_BASE_ADDRESS_MEM_PREFETCH ?
1021                     " prefetchable" : "";
1022
1023                 monitor_printf(mon, "%s%s memory at 0x%08"FMT_PCIBUS
1024                                " [0x%08"FMT_PCIBUS"].\n",
1025                                type, prefetch,
1026                                r->addr, r->addr + r->size - 1);
1027             }
1028         }
1029     }
1030     monitor_printf(mon, "      id \"%s\"\n", d->qdev.id ? d->qdev.id : "");
1031     if (class == 0x0604 && d->config[0x19] != 0) {
1032         pci_for_each_device(bus, d->config[0x19], pci_info_device);
1033     }
1034 }
1035
1036 static void pci_for_each_device_under_bus(PCIBus *bus,
1037                                           void (*fn)(PCIBus *b, PCIDevice *d))
1038 {
1039     PCIDevice *d;
1040     int devfn;
1041
1042     for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1043         d = bus->devices[devfn];
1044         if (d)
1045             fn(bus, d);
1046     }
1047 }
1048
1049 void pci_for_each_device(PCIBus *bus, int bus_num,
1050                          void (*fn)(PCIBus *b, PCIDevice *d))
1051 {
1052     bus = pci_find_bus(bus, bus_num);
1053
1054     if (bus) {
1055         pci_for_each_device_under_bus(bus, fn);
1056     }
1057 }
1058
1059 void pci_info(Monitor *mon)
1060 {
1061     struct PCIHostBus *host;
1062     QLIST_FOREACH(host, &host_buses, next) {
1063         pci_for_each_device(host->bus, 0, pci_info_device);
1064     }
1065 }
1066
1067 static const char * const pci_nic_models[] = {
1068     "ne2k_pci",
1069     "i82551",
1070     "i82557b",
1071     "i82559er",
1072     "rtl8139",
1073     "e1000",
1074     "pcnet",
1075     "virtio",
1076     NULL
1077 };
1078
1079 static const char * const pci_nic_names[] = {
1080     "ne2k_pci",
1081     "i82551",
1082     "i82557b",
1083     "i82559er",
1084     "rtl8139",
1085     "e1000",
1086     "pcnet",
1087     "virtio-net-pci",
1088     NULL
1089 };
1090
1091 /* Initialize a PCI NIC.  */
1092 /* FIXME callers should check for failure, but don't */
1093 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
1094                         const char *default_devaddr)
1095 {
1096     const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1097     PCIBus *bus;
1098     int devfn;
1099     PCIDevice *pci_dev;
1100     DeviceState *dev;
1101     int i;
1102
1103     i = qemu_find_nic_model(nd, pci_nic_models, default_model);
1104     if (i < 0)
1105         return NULL;
1106
1107     bus = pci_get_bus_devfn(&devfn, devaddr);
1108     if (!bus) {
1109         qemu_error("Invalid PCI device address %s for device %s\n",
1110                    devaddr, pci_nic_names[i]);
1111         return NULL;
1112     }
1113
1114     pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
1115     dev = &pci_dev->qdev;
1116     if (nd->name)
1117         dev->id = qemu_strdup(nd->name);
1118     qdev_set_nic_properties(dev, nd);
1119     if (qdev_init(dev) < 0)
1120         return NULL;
1121     return pci_dev;
1122 }
1123
1124 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
1125                                const char *default_devaddr)
1126 {
1127     PCIDevice *res;
1128
1129     if (qemu_show_nic_models(nd->model, pci_nic_models))
1130         exit(0);
1131
1132     res = pci_nic_init(nd, default_model, default_devaddr);
1133     if (!res)
1134         exit(1);
1135     return res;
1136 }
1137
1138 typedef struct {
1139     PCIDevice dev;
1140     PCIBus bus;
1141     uint32_t vid;
1142     uint32_t did;
1143 } PCIBridge;
1144
1145
1146 static void pci_bridge_update_mappings_fn(PCIBus *b, PCIDevice *d)
1147 {
1148     pci_update_mappings(d);
1149 }
1150
1151 static void pci_bridge_update_mappings(PCIBus *b)
1152 {
1153     PCIBus *child;
1154
1155     pci_for_each_device_under_bus(b, pci_bridge_update_mappings_fn);
1156
1157     QLIST_FOREACH(child, &b->child, sibling) {
1158         pci_bridge_update_mappings(child);
1159     }
1160 }
1161
1162 static void pci_bridge_write_config(PCIDevice *d,
1163                              uint32_t address, uint32_t val, int len)
1164 {
1165     pci_default_write_config(d, address, val, len);
1166
1167     if (/* io base/limit */
1168         ranges_overlap(address, len, PCI_IO_BASE, 2) ||
1169
1170         /* memory base/limit, prefetchable base/limit and
1171            io base/limit upper 16 */
1172         ranges_overlap(address, len, PCI_MEMORY_BASE, 20)) {
1173         pci_bridge_update_mappings(d->bus);
1174     }
1175 }
1176
1177 PCIBus *pci_find_bus(PCIBus *bus, int bus_num)
1178 {
1179     PCIBus *sec;
1180
1181     if (!bus)
1182         return NULL;
1183
1184     if (pci_bus_num(bus) == bus_num) {
1185         return bus;
1186     }
1187
1188     /* try child bus */
1189     QLIST_FOREACH(sec, &bus->child, sibling) {
1190
1191         if (!bus->parent_dev /* pci host bridge */
1192             || (pci_bus_num(sec) <= bus_num &&
1193                 bus->parent_dev->config[PCI_SUBORDINATE_BUS])) {
1194             return pci_find_bus(sec, bus_num);
1195         }
1196     }
1197
1198     return NULL;
1199 }
1200
1201 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function)
1202 {
1203     bus = pci_find_bus(bus, bus_num);
1204
1205     if (!bus)
1206         return NULL;
1207
1208     return bus->devices[PCI_DEVFN(slot, function)];
1209 }
1210
1211 static int pci_bridge_initfn(PCIDevice *dev)
1212 {
1213     PCIBridge *s = DO_UPCAST(PCIBridge, dev, dev);
1214
1215     pci_config_set_vendor_id(s->dev.config, s->vid);
1216     pci_config_set_device_id(s->dev.config, s->did);
1217
1218     pci_set_word(dev->config + PCI_STATUS,
1219                  PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
1220     pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_PCI);
1221     dev->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_BRIDGE;
1222     pci_set_word(dev->config + PCI_SEC_STATUS,
1223                  PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
1224     return 0;
1225 }
1226
1227 static int pci_bridge_exitfn(PCIDevice *pci_dev)
1228 {
1229     PCIBridge *s = DO_UPCAST(PCIBridge, dev, pci_dev);
1230     PCIBus *bus = &s->bus;
1231     pci_unregister_secondary_bus(bus);
1232     return 0;
1233 }
1234
1235 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
1236                         pci_map_irq_fn map_irq, const char *name)
1237 {
1238     PCIDevice *dev;
1239     PCIBridge *s;
1240
1241     dev = pci_create(bus, devfn, "pci-bridge");
1242     qdev_prop_set_uint32(&dev->qdev, "vendorid", vid);
1243     qdev_prop_set_uint32(&dev->qdev, "deviceid", did);
1244     qdev_init_nofail(&dev->qdev);
1245
1246     s = DO_UPCAST(PCIBridge, dev, dev);
1247     pci_register_secondary_bus(bus, &s->bus, &s->dev, map_irq, name);
1248     return &s->bus;
1249 }
1250
1251 PCIDevice *pci_bridge_get_device(PCIBus *bus)
1252 {
1253     return bus->parent_dev;
1254 }
1255
1256 static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
1257 {
1258     PCIDevice *pci_dev = (PCIDevice *)qdev;
1259     PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
1260     PCIBus *bus;
1261     int devfn, rc;
1262
1263     /* initialize cap_present for pci_is_express() and pci_config_size() */
1264     if (info->is_express) {
1265         pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1266     }
1267
1268     bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
1269     devfn = pci_dev->devfn;
1270     pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn,
1271                                      info->config_read, info->config_write,
1272                                      info->header_type);
1273     rc = info->init(pci_dev);
1274     if (rc != 0)
1275         return rc;
1276     if (qdev->hotplugged)
1277         bus->hotplug(pci_dev, 1);
1278     return 0;
1279 }
1280
1281 static int pci_unplug_device(DeviceState *qdev)
1282 {
1283     PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
1284
1285     dev->bus->hotplug(dev, 0);
1286     return 0;
1287 }
1288
1289 void pci_qdev_register(PCIDeviceInfo *info)
1290 {
1291     info->qdev.init = pci_qdev_init;
1292     info->qdev.unplug = pci_unplug_device;
1293     info->qdev.exit = pci_unregister_device;
1294     info->qdev.bus_info = &pci_bus_info;
1295     qdev_register(&info->qdev);
1296 }
1297
1298 void pci_qdev_register_many(PCIDeviceInfo *info)
1299 {
1300     while (info->qdev.name) {
1301         pci_qdev_register(info);
1302         info++;
1303     }
1304 }
1305
1306 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
1307 {
1308     DeviceState *dev;
1309
1310     dev = qdev_create(&bus->qbus, name);
1311     qdev_prop_set_uint32(dev, "addr", devfn);
1312     return DO_UPCAST(PCIDevice, qdev, dev);
1313 }
1314
1315 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1316 {
1317     PCIDevice *dev = pci_create(bus, devfn, name);
1318     qdev_init_nofail(&dev->qdev);
1319     return dev;
1320 }
1321
1322 static int pci_find_space(PCIDevice *pdev, uint8_t size)
1323 {
1324     int config_size = pci_config_size(pdev);
1325     int offset = PCI_CONFIG_HEADER_SIZE;
1326     int i;
1327     for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
1328         if (pdev->used[i])
1329             offset = i + 1;
1330         else if (i - offset + 1 == size)
1331             return offset;
1332     return 0;
1333 }
1334
1335 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1336                                         uint8_t *prev_p)
1337 {
1338     uint8_t next, prev;
1339
1340     if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1341         return 0;
1342
1343     for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1344          prev = next + PCI_CAP_LIST_NEXT)
1345         if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1346             break;
1347
1348     if (prev_p)
1349         *prev_p = prev;
1350     return next;
1351 }
1352
1353 /* Reserve space and add capability to the linked list in pci config space */
1354 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1355 {
1356     uint8_t offset = pci_find_space(pdev, size);
1357     uint8_t *config = pdev->config + offset;
1358     if (!offset)
1359         return -ENOSPC;
1360     config[PCI_CAP_LIST_ID] = cap_id;
1361     config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
1362     pdev->config[PCI_CAPABILITY_LIST] = offset;
1363     pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
1364     memset(pdev->used + offset, 0xFF, size);
1365     /* Make capability read-only by default */
1366     memset(pdev->wmask + offset, 0, size);
1367     /* Check capability by default */
1368     memset(pdev->cmask + offset, 0xFF, size);
1369     return offset;
1370 }
1371
1372 /* Unlink capability from the pci config space. */
1373 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1374 {
1375     uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
1376     if (!offset)
1377         return;
1378     pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
1379     /* Make capability writeable again */
1380     memset(pdev->wmask + offset, 0xff, size);
1381     /* Clear cmask as device-specific registers can't be checked */
1382     memset(pdev->cmask + offset, 0, size);
1383     memset(pdev->used + offset, 0, size);
1384
1385     if (!pdev->config[PCI_CAPABILITY_LIST])
1386         pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
1387 }
1388
1389 /* Reserve space for capability at a known offset (to call after load). */
1390 void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
1391 {
1392     memset(pdev->used + offset, 0xff, size);
1393 }
1394
1395 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
1396 {
1397     return pci_find_capability_list(pdev, cap_id, NULL);
1398 }
1399
1400 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
1401 {
1402     PCIDevice *d = (PCIDevice *)dev;
1403     const pci_class_desc *desc;
1404     char ctxt[64];
1405     PCIIORegion *r;
1406     int i, class;
1407
1408     class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1409     desc = pci_class_descriptions;
1410     while (desc->desc && class != desc->class)
1411         desc++;
1412     if (desc->desc) {
1413         snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
1414     } else {
1415         snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
1416     }
1417
1418     monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
1419                    "pci id %04x:%04x (sub %04x:%04x)\n",
1420                    indent, "", ctxt,
1421                    d->config[PCI_SECONDARY_BUS],
1422                    PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
1423                    pci_get_word(d->config + PCI_VENDOR_ID),
1424                    pci_get_word(d->config + PCI_DEVICE_ID),
1425                    pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
1426                    pci_get_word(d->config + PCI_SUBSYSTEM_ID));
1427     for (i = 0; i < PCI_NUM_REGIONS; i++) {
1428         r = &d->io_regions[i];
1429         if (!r->size)
1430             continue;
1431         monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
1432                        " [0x%"FMT_PCIBUS"]\n",
1433                        indent, "",
1434                        i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
1435                        r->addr, r->addr + r->size - 1);
1436     }
1437 }
1438
1439 static PCIDeviceInfo bridge_info = {
1440     .qdev.name    = "pci-bridge",
1441     .qdev.size    = sizeof(PCIBridge),
1442     .init         = pci_bridge_initfn,
1443     .exit         = pci_bridge_exitfn,
1444     .config_write = pci_bridge_write_config,
1445     .qdev.props   = (Property[]) {
1446         DEFINE_PROP_HEX32("vendorid", PCIBridge, vid, 0),
1447         DEFINE_PROP_HEX32("deviceid", PCIBridge, did, 0),
1448         DEFINE_PROP_END_OF_LIST(),
1449     }
1450 };
1451
1452 static void pci_register_devices(void)
1453 {
1454     pci_qdev_register(&bridge_info);
1455 }
1456
1457 device_init(pci_register_devices)