hw/pci/host/prep.c

   1 /*
   2  * QEMU PREP PCI host
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  * Copyright (c) 2011-2013 Andreas Färber
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "hw/hw.h"
  27 #include "hw/pci/pci.h"
  28 #include "hw/pci/pci_bus.h"
  29 #include "hw/pci/pci_host.h"
  30 #include "hw/i386/pc.h"
  31 #include "exec/address-spaces.h"
  32
  33 #define TYPE_RAVEN_PCI_DEVICE "raven"
  34 #define TYPE_RAVEN_PCI_HOST_BRIDGE "raven-pcihost"
  35
  36 #define RAVEN_PCI_DEVICE(obj) \
  37     OBJECT_CHECK(RavenPCIState, (obj), TYPE_RAVEN_PCI_DEVICE)
  38
  39 typedef struct RavenPCIState {
  40     PCIDevice dev;
  41 } RavenPCIState;
  42
  43 #define RAVEN_PCI_HOST_BRIDGE(obj) \
  44     OBJECT_CHECK(PREPPCIState, (obj), TYPE_RAVEN_PCI_HOST_BRIDGE)
  45
  46 typedef struct PRePPCIState {
  47     PCIHostState parent_obj;
  48
  49     MemoryRegion intack;
  50     qemu_irq irq[4];
  51     PCIBus pci_bus;
  52     RavenPCIState pci_dev;
  53 } PREPPCIState;
  54
  55 static inline uint32_t PPC_PCIIO_config(hwaddr addr)
  56 {
  57     int i;
  58
  59     for (i = 0; i < 11; i++) {
  60         if ((addr & (1 << (11 + i))) != 0) {
  61             break;
  62         }
  63     }
  64     return (addr & 0x7ff) |  (i << 11);
  65 }
  66
  67 static void ppc_pci_io_write(void *opaque, hwaddr addr,
  68                              uint64_t val, unsigned int size)
  69 {
  70     PREPPCIState *s = opaque;
  71     PCIHostState *phb = PCI_HOST_BRIDGE(s);
  72     pci_data_write(phb->bus, PPC_PCIIO_config(addr), val, size);
  73 }
  74
  75 static uint64_t ppc_pci_io_read(void *opaque, hwaddr addr,
  76                                 unsigned int size)
  77 {
  78     PREPPCIState *s = opaque;
  79     PCIHostState *phb = PCI_HOST_BRIDGE(s);
  80     return pci_data_read(phb->bus, PPC_PCIIO_config(addr), size);
  81 }
  82
  83 static const MemoryRegionOps PPC_PCIIO_ops = {
  84     .read = ppc_pci_io_read,
  85     .write = ppc_pci_io_write,
  86     .endianness = DEVICE_LITTLE_ENDIAN,
  87 };
  88
  89 static uint64_t ppc_intack_read(void *opaque, hwaddr addr,
  90                                 unsigned int size)
  91 {
  92     return pic_read_irq(isa_pic);
  93 }
  94
  95 static const MemoryRegionOps PPC_intack_ops = {
  96     .read = ppc_intack_read,
  97     .valid = {
  98         .max_access_size = 1,
  99     },
 100 };
 101
 102 static int prep_map_irq(PCIDevice *pci_dev, int irq_num)
 103 {
 104     return (irq_num + (pci_dev->devfn >> 3)) & 1;
 105 }
 106
 107 static void prep_set_irq(void *opaque, int irq_num, int level)
 108 {
 109     qemu_irq *pic = opaque;
 110
 111     qemu_set_irq(pic[irq_num] , level);
 112 }
 113
 114 static void raven_pcihost_realizefn(DeviceState *d, Error **errp)
 115 {
 116     SysBusDevice *dev = SYS_BUS_DEVICE(d);
 117     PCIHostState *h = PCI_HOST_BRIDGE(dev);
 118     PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(dev);
 119     MemoryRegion *address_space_mem = get_system_memory();
 120     int i;
 121
 122     for (i = 0; i < 4; i++) {
 123         sysbus_init_irq(dev, &s->irq[i]);
 124     }
 125
 126     pci_bus_irqs(&s->pci_bus, prep_set_irq, prep_map_irq, s->irq, 4);
 127
 128     memory_region_init_io(&h->conf_mem, &pci_host_conf_be_ops, s,
 129                           "pci-conf-idx", 1);
 130     sysbus_add_io(dev, 0xcf8, &h->conf_mem);
 131     sysbus_init_ioports(&h->busdev, 0xcf8, 1);
 132
 133     memory_region_init_io(&h->data_mem, &pci_host_data_be_ops, s,
 134                           "pci-conf-data", 1);
 135     sysbus_add_io(dev, 0xcfc, &h->data_mem);
 136     sysbus_init_ioports(&h->busdev, 0xcfc, 1);
 137
 138     memory_region_init_io(&h->mmcfg, &PPC_PCIIO_ops, s, "pciio", 0x00400000);
 139     memory_region_add_subregion(address_space_mem, 0x80800000, &h->mmcfg);
 140
 141     memory_region_init_io(&s->intack, &PPC_intack_ops, s, "pci-intack", 1);
 142     memory_region_add_subregion(address_space_mem, 0xbffffff0, &s->intack);
 143
 144     /* TODO Remove once realize propagates to child devices. */
 145     object_property_set_bool(OBJECT(&s->pci_dev), true, "realized", errp);
 146 }
 147
 148 static void raven_pcihost_initfn(Object *obj)
 149 {
 150     PCIHostState *h = PCI_HOST_BRIDGE(obj);
 151     PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(obj);
 152     MemoryRegion *address_space_mem = get_system_memory();
 153     MemoryRegion *address_space_io = get_system_io();
 154     DeviceState *pci_dev;
 155
 156     pci_bus_new_inplace(&s->pci_bus, DEVICE(obj), NULL,
 157                         address_space_mem, address_space_io, 0, TYPE_PCI_BUS);
 158     h->bus = &s->pci_bus;
 159
 160     object_initialize(&s->pci_dev, TYPE_RAVEN_PCI_DEVICE);
 161     pci_dev = DEVICE(&s->pci_dev);
 162     qdev_set_parent_bus(pci_dev, BUS(&s->pci_bus));
 163     object_property_set_int(OBJECT(&s->pci_dev), PCI_DEVFN(0, 0), "addr",
 164                             NULL);
 165     qdev_prop_set_bit(pci_dev, "multifunction", false);
 166 }
 167
 168 static int raven_init(PCIDevice *d)
 169 {
 170     d->config[0x0C] = 0x08; // cache_line_size
 171     d->config[0x0D] = 0x10; // latency_timer
 172     d->config[0x34] = 0x00; // capabilities_pointer
 173
 174     return 0;
 175 }
 176
 177 static const VMStateDescription vmstate_raven = {
 178     .name = "raven",
 179     .version_id = 0,
 180     .minimum_version_id = 0,
 181     .fields = (VMStateField[]) {
 182         VMSTATE_PCI_DEVICE(dev, RavenPCIState),
 183         VMSTATE_END_OF_LIST()
 184     },
 185 };
 186
 187 static void raven_class_init(ObjectClass *klass, void *data)
 188 {
 189     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 190     DeviceClass *dc = DEVICE_CLASS(klass);
 191
 192     k->init = raven_init;
 193     k->vendor_id = PCI_VENDOR_ID_MOTOROLA;
 194     k->device_id = PCI_DEVICE_ID_MOTOROLA_RAVEN;
 195     k->revision = 0x00;
 196     k->class_id = PCI_CLASS_BRIDGE_HOST;
 197     dc->desc = "PReP Host Bridge - Motorola Raven";
 198     dc->vmsd = &vmstate_raven;
 199     dc->no_user = 1;
 200 }
 201
 202 static const TypeInfo raven_info = {
 203     .name = TYPE_RAVEN_PCI_DEVICE,
 204     .parent = TYPE_PCI_DEVICE,
 205     .instance_size = sizeof(RavenPCIState),
 206     .class_init = raven_class_init,
 207 };
 208
 209 static void raven_pcihost_class_init(ObjectClass *klass, void *data)
 210 {
 211     DeviceClass *dc = DEVICE_CLASS(klass);
 212
 213     dc->realize = raven_pcihost_realizefn;
 214     dc->fw_name = "pci";
 215     dc->no_user = 1;
 216 }
 217
 218 static const TypeInfo raven_pcihost_info = {
 219     .name = TYPE_RAVEN_PCI_HOST_BRIDGE,
 220     .parent = TYPE_PCI_HOST_BRIDGE,
 221     .instance_size = sizeof(PREPPCIState),
 222     .instance_init = raven_pcihost_initfn,
 223     .class_init = raven_pcihost_class_init,
 224 };
 225
 226 static void raven_register_types(void)
 227 {
 228     type_register_static(&raven_pcihost_info);
 229     type_register_static(&raven_info);
 230 }
 231
 232 type_init(raven_register_types)