hw/ppc_prep.c

   1 /*
   2  * QEMU PPC PREP hardware System Emulator
   3  *
   4  * Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "nvram.h"
  26 #include "pc.h"
  27 #include "fdc.h"
  28 #include "net.h"
  29 #include "sysemu.h"
  30 #include "isa.h"
  31 #include "pci.h"
  32 #include "pci_host.h"
  33 #include "ppc.h"
  34 #include "boards.h"
  35 #include "qemu-log.h"
  36 #include "ide.h"
  37 #include "loader.h"
  38 #include "mc146818rtc.h"
  39 #include "pc87312.h"
  40 #include "blockdev.h"
  41 #include "arch_init.h"
  42 #include "exec-memory.h"
  43
  44 //#define HARD_DEBUG_PPC_IO
  45 //#define DEBUG_PPC_IO
  46
  47 /* SMP is not enabled, for now */
  48 #define MAX_CPUS 1
  49
  50 #define MAX_IDE_BUS 2
  51
  52 #define BIOS_SIZE (1024 * 1024)
  53 #define BIOS_FILENAME "ppc_rom.bin"
  54 #define KERNEL_LOAD_ADDR 0x01000000
  55 #define INITRD_LOAD_ADDR 0x01800000
  56
  57 #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
  58 #define DEBUG_PPC_IO
  59 #endif
  60
  61 #if defined (HARD_DEBUG_PPC_IO)
  62 #define PPC_IO_DPRINTF(fmt, ...)                         \
  63 do {                                                     \
  64     if (qemu_loglevel_mask(CPU_LOG_IOPORT)) {            \
  65         qemu_log("%s: " fmt, __func__ , ## __VA_ARGS__); \
  66     } else {                                             \
  67         printf("%s : " fmt, __func__ , ## __VA_ARGS__);  \
  68     }                                                    \
  69 } while (0)
  70 #elif defined (DEBUG_PPC_IO)
  71 #define PPC_IO_DPRINTF(fmt, ...) \
  72 qemu_log_mask(CPU_LOG_IOPORT, fmt, ## __VA_ARGS__)
  73 #else
  74 #define PPC_IO_DPRINTF(fmt, ...) do { } while (0)
  75 #endif
  76
  77 /* Constants for devices init */
  78 static const int ide_iobase[2] = { 0x1f0, 0x170 };
  79 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
  80 static const int ide_irq[2] = { 13, 13 };
  81
  82 #define NE2000_NB_MAX 6
  83
  84 static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
  85 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
  86
  87 /* ISA IO ports bridge */
  88 #define PPC_IO_BASE 0x80000000
  89
  90 /* PowerPC control and status registers */
  91 #if 0 // Not used
  92 static struct {
  93     /* IDs */
  94     uint32_t veni_devi;
  95     uint32_t revi;
  96     /* Control and status */
  97     uint32_t gcsr;
  98     uint32_t xcfr;
  99     uint32_t ct32;
 100     uint32_t mcsr;
 101     /* General purpose registers */
 102     uint32_t gprg[6];
 103     /* Exceptions */
 104     uint32_t feen;
 105     uint32_t fest;
 106     uint32_t fema;
 107     uint32_t fecl;
 108     uint32_t eeen;
 109     uint32_t eest;
 110     uint32_t eecl;
 111     uint32_t eeint;
 112     uint32_t eemck0;
 113     uint32_t eemck1;
 114     /* Error diagnostic */
 115 } XCSR;
 116
 117 static void PPC_XCSR_writeb (void *opaque,
 118                              target_phys_addr_t addr, uint32_t value)
 119 {
 120     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
 121            value);
 122 }
 123
 124 static void PPC_XCSR_writew (void *opaque,
 125                              target_phys_addr_t addr, uint32_t value)
 126 {
 127     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
 128            value);
 129 }
 130
 131 static void PPC_XCSR_writel (void *opaque,
 132                              target_phys_addr_t addr, uint32_t value)
 133 {
 134     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
 135            value);
 136 }
 137
 138 static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr)
 139 {
 140     uint32_t retval = 0;
 141
 142     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 143            retval);
 144
 145     return retval;
 146 }
 147
 148 static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr)
 149 {
 150     uint32_t retval = 0;
 151
 152     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 153            retval);
 154
 155     return retval;
 156 }
 157
 158 static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr)
 159 {
 160     uint32_t retval = 0;
 161
 162     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 163            retval);
 164
 165     return retval;
 166 }
 167
 168 static const MemoryRegionOps PPC_XCSR_ops = {
 169     .old_mmio = {
 170         .read = { PPC_XCSR_readb, PPC_XCSR_readw, PPC_XCSR_readl, },
 171         .write = { PPC_XCSR_writeb, PPC_XCSR_writew, PPC_XCSR_writel, },
 172     },
 173     .endianness = DEVICE_LITTLE_ENDIAN,
 174 };
 175
 176 #endif
 177
 178 /* Fake super-io ports for PREP platform (Intel 82378ZB) */
 179 typedef struct sysctrl_t {
 180     qemu_irq reset_irq;
 181     M48t59State *nvram;
 182     uint8_t state;
 183     uint8_t syscontrol;
 184     int contiguous_map;
 185     int endian;
 186 } sysctrl_t;
 187
 188 enum {
 189     STATE_HARDFILE = 0x01,
 190 };
 191
 192 static sysctrl_t *sysctrl;
 193
 194 static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
 195 {
 196     sysctrl_t *sysctrl = opaque;
 197
 198     PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n",
 199                    addr - PPC_IO_BASE, val);
 200     switch (addr) {
 201     case 0x0092:
 202         /* Special port 92 */
 203         /* Check soft reset asked */
 204         if (val & 0x01) {
 205             qemu_irq_raise(sysctrl->reset_irq);
 206         } else {
 207             qemu_irq_lower(sysctrl->reset_irq);
 208         }
 209         /* Check LE mode */
 210         if (val & 0x02) {
 211             sysctrl->endian = 1;
 212         } else {
 213             sysctrl->endian = 0;
 214         }
 215         break;
 216     case 0x0800:
 217         /* Motorola CPU configuration register : read-only */
 218         break;
 219     case 0x0802:
 220         /* Motorola base module feature register : read-only */
 221         break;
 222     case 0x0803:
 223         /* Motorola base module status register : read-only */
 224         break;
 225     case 0x0808:
 226         /* Hardfile light register */
 227         if (val & 1)
 228             sysctrl->state |= STATE_HARDFILE;
 229         else
 230             sysctrl->state &= ~STATE_HARDFILE;
 231         break;
 232     case 0x0810:
 233         /* Password protect 1 register */
 234         if (sysctrl->nvram != NULL)
 235             m48t59_toggle_lock(sysctrl->nvram, 1);
 236         break;
 237     case 0x0812:
 238         /* Password protect 2 register */
 239         if (sysctrl->nvram != NULL)
 240             m48t59_toggle_lock(sysctrl->nvram, 2);
 241         break;
 242     case 0x0814:
 243         /* L2 invalidate register */
 244         //        tlb_flush(first_cpu, 1);
 245         break;
 246     case 0x081C:
 247         /* system control register */
 248         sysctrl->syscontrol = val & 0x0F;
 249         break;
 250     case 0x0850:
 251         /* I/O map type register */
 252         sysctrl->contiguous_map = val & 0x01;
 253         break;
 254     default:
 255         printf("ERROR: unaffected IO port write: %04" PRIx32
 256                " => %02" PRIx32"\n", addr, val);
 257         break;
 258     }
 259 }
 260
 261 static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
 262 {
 263     sysctrl_t *sysctrl = opaque;
 264     uint32_t retval = 0xFF;
 265
 266     switch (addr) {
 267     case 0x0092:
 268         /* Special port 92 */
 269         retval = 0x00;
 270         break;
 271     case 0x0800:
 272         /* Motorola CPU configuration register */
 273         retval = 0xEF; /* MPC750 */
 274         break;
 275     case 0x0802:
 276         /* Motorola Base module feature register */
 277         retval = 0xAD; /* No ESCC, PMC slot neither ethernet */
 278         break;
 279     case 0x0803:
 280         /* Motorola base module status register */
 281         retval = 0xE0; /* Standard MPC750 */
 282         break;
 283     case 0x080C:
 284         /* Equipment present register:
 285          *  no L2 cache
 286          *  no upgrade processor
 287          *  no cards in PCI slots
 288          *  SCSI fuse is bad
 289          */
 290         retval = 0x3C;
 291         break;
 292     case 0x0810:
 293         /* Motorola base module extended feature register */
 294         retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */
 295         break;
 296     case 0x0814:
 297         /* L2 invalidate: don't care */
 298         break;
 299     case 0x0818:
 300         /* Keylock */
 301         retval = 0x00;
 302         break;
 303     case 0x081C:
 304         /* system control register
 305          * 7 - 6 / 1 - 0: L2 cache enable
 306          */
 307         retval = sysctrl->syscontrol;
 308         break;
 309     case 0x0823:
 310         /* */
 311         retval = 0x03; /* no L2 cache */
 312         break;
 313     case 0x0850:
 314         /* I/O map type register */
 315         retval = sysctrl->contiguous_map;
 316         break;
 317     default:
 318         printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr);
 319         break;
 320     }
 321     PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n",
 322                    addr - PPC_IO_BASE, retval);
 323
 324     return retval;
 325 }
 326
 327 static inline target_phys_addr_t prep_IO_address(sysctrl_t *sysctrl,
 328                                                  target_phys_addr_t addr)
 329 {
 330     if (sysctrl->contiguous_map == 0) {
 331         /* 64 KB contiguous space for IOs */
 332         addr &= 0xFFFF;
 333     } else {
 334         /* 8 MB non-contiguous space for IOs */
 335         addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
 336     }
 337
 338     return addr;
 339 }
 340
 341 static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr,
 342                                 uint32_t value)
 343 {
 344     sysctrl_t *sysctrl = opaque;
 345
 346     addr = prep_IO_address(sysctrl, addr);
 347     cpu_outb(addr, value);
 348 }
 349
 350 static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr)
 351 {
 352     sysctrl_t *sysctrl = opaque;
 353     uint32_t ret;
 354
 355     addr = prep_IO_address(sysctrl, addr);
 356     ret = cpu_inb(addr);
 357
 358     return ret;
 359 }
 360
 361 static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr,
 362                                 uint32_t value)
 363 {
 364     sysctrl_t *sysctrl = opaque;
 365
 366     addr = prep_IO_address(sysctrl, addr);
 367     PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);
 368     cpu_outw(addr, value);
 369 }
 370
 371 static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr)
 372 {
 373     sysctrl_t *sysctrl = opaque;
 374     uint32_t ret;
 375
 376     addr = prep_IO_address(sysctrl, addr);
 377     ret = cpu_inw(addr);
 378     PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);
 379
 380     return ret;
 381 }
 382
 383 static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr,
 384                                 uint32_t value)
 385 {
 386     sysctrl_t *sysctrl = opaque;
 387
 388     addr = prep_IO_address(sysctrl, addr);
 389     PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);
 390     cpu_outl(addr, value);
 391 }
 392
 393 static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr)
 394 {
 395     sysctrl_t *sysctrl = opaque;
 396     uint32_t ret;
 397
 398     addr = prep_IO_address(sysctrl, addr);
 399     ret = cpu_inl(addr);
 400     PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);
 401
 402     return ret;
 403 }
 404
 405 static const MemoryRegionOps PPC_prep_io_ops = {
 406     .old_mmio = {
 407         .read = { PPC_prep_io_readb, PPC_prep_io_readw, PPC_prep_io_readl },
 408         .write = { PPC_prep_io_writeb, PPC_prep_io_writew, PPC_prep_io_writel },
 409     },
 410     .endianness = DEVICE_LITTLE_ENDIAN,
 411 };
 412
 413 #define NVRAM_SIZE        0x2000
 414
 415 static void cpu_request_exit(void *opaque, int irq, int level)
 416 {
 417     CPUPPCState *env = cpu_single_env;
 418
 419     if (env && level) {
 420         cpu_exit(env);
 421     }
 422 }
 423
 424 static void ppc_prep_reset(void *opaque)
 425 {
 426     PowerPCCPU *cpu = opaque;
 427
 428     cpu_reset(CPU(cpu));
 429 }
 430
 431 /* PowerPC PREP hardware initialisation */
 432 static void ppc_prep_init (ram_addr_t ram_size,
 433                            const char *boot_device,
 434                            const char *kernel_filename,
 435                            const char *kernel_cmdline,
 436                            const char *initrd_filename,
 437                            const char *cpu_model)
 438 {
 439     MemoryRegion *sysmem = get_system_memory();
 440     PowerPCCPU *cpu = NULL;
 441     CPUPPCState *env = NULL;
 442     char *filename;
 443     nvram_t nvram;
 444     M48t59State *m48t59;
 445     MemoryRegion *PPC_io_memory = g_new(MemoryRegion, 1);
 446 #if 0
 447     MemoryRegion *xcsr = g_new(MemoryRegion, 1);
 448 #endif
 449     int linux_boot, i, nb_nics1, bios_size;
 450     MemoryRegion *ram = g_new(MemoryRegion, 1);
 451     MemoryRegion *bios = g_new(MemoryRegion, 1);
 452     uint32_t kernel_base, initrd_base;
 453     long kernel_size, initrd_size;
 454     DeviceState *dev;
 455     SysBusDevice *sys;
 456     PCIHostState *pcihost;
 457     PCIBus *pci_bus;
 458     PCIDevice *pci;
 459     ISABus *isa_bus;
 460     ISADevice *isa;
 461     qemu_irq *cpu_exit_irq;
 462     int ppc_boot_device;
 463     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 464
 465     sysctrl = g_malloc0(sizeof(sysctrl_t));
 466
 467     linux_boot = (kernel_filename != NULL);
 468
 469     /* init CPUs */
 470     if (cpu_model == NULL)
 471         cpu_model = "602";
 472     for (i = 0; i < smp_cpus; i++) {
 473         cpu = cpu_ppc_init(cpu_model);
 474         if (cpu == NULL) {
 475             fprintf(stderr, "Unable to find PowerPC CPU definition\n");
 476             exit(1);
 477         }
 478         env = &cpu->env;
 479
 480         if (env->flags & POWERPC_FLAG_RTC_CLK) {
 481             /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
 482             cpu_ppc_tb_init(env, 7812500UL);
 483         } else {
 484             /* Set time-base frequency to 100 Mhz */
 485             cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
 486         }
 487         qemu_register_reset(ppc_prep_reset, cpu);
 488     }
 489
 490     /* allocate RAM */
 491     memory_region_init_ram(ram, "ppc_prep.ram", ram_size);
 492     vmstate_register_ram_global(ram);
 493     memory_region_add_subregion(sysmem, 0, ram);
 494
 495     /* allocate and load BIOS */
 496     memory_region_init_ram(bios, "ppc_prep.bios", BIOS_SIZE);
 497     memory_region_set_readonly(bios, true);
 498     memory_region_add_subregion(sysmem, (uint32_t)(-BIOS_SIZE), bios);
 499     vmstate_register_ram_global(bios);
 500     if (bios_name == NULL)
 501         bios_name = BIOS_FILENAME;
 502     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 503     if (filename) {
 504         bios_size = get_image_size(filename);
 505     } else {
 506         bios_size = -1;
 507     }
 508     if (bios_size > 0 && bios_size <= BIOS_SIZE) {
 509         target_phys_addr_t bios_addr;
 510         bios_size = (bios_size + 0xfff) & ~0xfff;
 511         bios_addr = (uint32_t)(-bios_size);
 512         bios_size = load_image_targphys(filename, bios_addr, bios_size);
 513     }
 514     if (bios_size < 0 || bios_size > BIOS_SIZE) {
 515         hw_error("qemu: could not load PPC PREP bios '%s'\n", bios_name);
 516     }
 517     if (filename) {
 518         g_free(filename);
 519     }
 520
 521     if (linux_boot) {
 522         kernel_base = KERNEL_LOAD_ADDR;
 523         /* now we can load the kernel */
 524         kernel_size = load_image_targphys(kernel_filename, kernel_base,
 525                                           ram_size - kernel_base);
 526         if (kernel_size < 0) {
 527             hw_error("qemu: could not load kernel '%s'\n", kernel_filename);
 528             exit(1);
 529         }
 530         /* load initrd */
 531         if (initrd_filename) {
 532             initrd_base = INITRD_LOAD_ADDR;
 533             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 534                                               ram_size - initrd_base);
 535             if (initrd_size < 0) {
 536                 hw_error("qemu: could not load initial ram disk '%s'\n",
 537                           initrd_filename);
 538             }
 539         } else {
 540             initrd_base = 0;
 541             initrd_size = 0;
 542         }
 543         ppc_boot_device = 'm';
 544     } else {
 545         kernel_base = 0;
 546         kernel_size = 0;
 547         initrd_base = 0;
 548         initrd_size = 0;
 549         ppc_boot_device = '\0';
 550         /* For now, OHW cannot boot from the network. */
 551         for (i = 0; boot_device[i] != '\0'; i++) {
 552             if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
 553                 ppc_boot_device = boot_device[i];
 554                 break;
 555             }
 556         }
 557         if (ppc_boot_device == '\0') {
 558             fprintf(stderr, "No valid boot device for Mac99 machine\n");
 559             exit(1);
 560         }
 561     }
 562
 563     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
 564         hw_error("Only 6xx bus is supported on PREP machine\n");
 565     }
 566
 567     dev = qdev_create(NULL, "raven-pcihost");
 568     sys = sysbus_from_qdev(dev);
 569     pcihost = DO_UPCAST(PCIHostState, busdev, sys);
 570     pcihost->address_space = get_system_memory();
 571     object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL);
 572     qdev_init_nofail(dev);
 573     pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
 574     if (pci_bus == NULL) {
 575         fprintf(stderr, "Couldn't create PCI host controller.\n");
 576         exit(1);
 577     }
 578
 579     /* PCI -> ISA bridge */
 580     pci = pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378");
 581     cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
 582     qdev_connect_gpio_out(&pci->qdev, 0,
 583                           first_cpu->irq_inputs[PPC6xx_INPUT_INT]);
 584     qdev_connect_gpio_out(&pci->qdev, 1, *cpu_exit_irq);
 585     sysbus_connect_irq(&pcihost->busdev, 0, qdev_get_gpio_in(&pci->qdev, 9));
 586     sysbus_connect_irq(&pcihost->busdev, 1, qdev_get_gpio_in(&pci->qdev, 11));
 587     sysbus_connect_irq(&pcihost->busdev, 2, qdev_get_gpio_in(&pci->qdev, 9));
 588     sysbus_connect_irq(&pcihost->busdev, 3, qdev_get_gpio_in(&pci->qdev, 11));
 589     isa_bus = DO_UPCAST(ISABus, qbus, qdev_get_child_bus(&pci->qdev, "isa.0"));
 590
 591     /* Super I/O (parallel + serial ports) */
 592     isa = isa_create(isa_bus, TYPE_PC87312);
 593     qdev_prop_set_uint8(&isa->qdev, "config", 13); /* fdc, ser0, ser1, par0 */
 594     qdev_init_nofail(&isa->qdev);
 595
 596     /* Register 8 MB of ISA IO space (needed for non-contiguous map) */
 597     memory_region_init_io(PPC_io_memory, &PPC_prep_io_ops, sysctrl,
 598                           "ppc-io", 0x00800000);
 599     memory_region_add_subregion(sysmem, 0x80000000, PPC_io_memory);
 600
 601     /* init basic PC hardware */
 602     pci_vga_init(pci_bus);
 603
 604     nb_nics1 = nb_nics;
 605     if (nb_nics1 > NE2000_NB_MAX)
 606         nb_nics1 = NE2000_NB_MAX;
 607     for(i = 0; i < nb_nics1; i++) {
 608         if (nd_table[i].model == NULL) {
 609             nd_table[i].model = g_strdup("ne2k_isa");
 610         }
 611         if (strcmp(nd_table[i].model, "ne2k_isa") == 0) {
 612             isa_ne2000_init(isa_bus, ne2000_io[i], ne2000_irq[i],
 613                             &nd_table[i]);
 614         } else {
 615             pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
 616         }
 617     }
 618
 619     ide_drive_get(hd, MAX_IDE_BUS);
 620     for(i = 0; i < MAX_IDE_BUS; i++) {
 621         isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i],
 622                      hd[2 * i],
 623                      hd[2 * i + 1]);
 624     }
 625     isa_create_simple(isa_bus, "i8042");
 626
 627     sysctrl->reset_irq = first_cpu->irq_inputs[PPC6xx_INPUT_HRESET];
 628     /* System control ports */
 629     register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl);
 630     register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl);
 631     register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl);
 632     register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl);
 633     /* PowerPC control and status register group */
 634 #if 0
 635     memory_region_init_io(xcsr, &PPC_XCSR_ops, NULL, "ppc-xcsr", 0x1000);
 636     memory_region_add_subregion(sysmem, 0xFEFF0000, xcsr);
 637 #endif
 638
 639     if (usb_enabled) {
 640         pci_create_simple(pci_bus, -1, "pci-ohci");
 641     }
 642
 643     m48t59 = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 59);
 644     if (m48t59 == NULL)
 645         return;
 646     sysctrl->nvram = m48t59;
 647
 648     /* Initialise NVRAM */
 649     nvram.opaque = m48t59;
 650     nvram.read_fn = &m48t59_read;
 651     nvram.write_fn = &m48t59_write;
 652     PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "PREP", ram_size, ppc_boot_device,
 653                          kernel_base, kernel_size,
 654                          kernel_cmdline,
 655                          initrd_base, initrd_size,
 656                          /* XXX: need an option to load a NVRAM image */
 657                          0,
 658                          graphic_width, graphic_height, graphic_depth);
 659
 660     /* Special port to get debug messages from Open-Firmware */
 661     register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
 662
 663     /* Initialize audio subsystem */
 664     audio_init(isa_bus, pci_bus);
 665 }
 666
 667 static QEMUMachine prep_machine = {
 668     .name = "prep",
 669     .desc = "PowerPC PREP platform",
 670     .init = ppc_prep_init,
 671     .max_cpus = MAX_CPUS,
 672 };
 673
 674 static void prep_machine_init(void)
 675 {
 676     qemu_register_machine(&prep_machine);
 677 }
 678
 679 machine_init(prep_machine_init);