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1 /*
2 * Intel XScale PXA255/270 processor support.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
6 *
7 * This code is licensed under the GPL.
8 */
9
10 #include "sysbus.h"
11 #include "pxa.h"
12 #include "sysemu.h"
13 #include "pc.h"
14 #include "i2c.h"
15 #include "ssi.h"
16 #include "qemu-char.h"
17 #include "blockdev.h"
18
19 static struct {
20 target_phys_addr_t io_base;
21 int irqn;
22 } pxa255_serial[] = {
23 { 0x40100000, PXA2XX_PIC_FFUART },
24 { 0x40200000, PXA2XX_PIC_BTUART },
25 { 0x40700000, PXA2XX_PIC_STUART },
26 { 0x41600000, PXA25X_PIC_HWUART },
27 { 0, 0 }
28 }, pxa270_serial[] = {
29 { 0x40100000, PXA2XX_PIC_FFUART },
30 { 0x40200000, PXA2XX_PIC_BTUART },
31 { 0x40700000, PXA2XX_PIC_STUART },
32 { 0, 0 }
33 };
34
35 typedef struct PXASSPDef {
36 target_phys_addr_t io_base;
37 int irqn;
38 } PXASSPDef;
39
40 #if 0
41 static PXASSPDef pxa250_ssp[] = {
42 { 0x41000000, PXA2XX_PIC_SSP },
43 { 0, 0 }
44 };
45 #endif
46
47 static PXASSPDef pxa255_ssp[] = {
48 { 0x41000000, PXA2XX_PIC_SSP },
49 { 0x41400000, PXA25X_PIC_NSSP },
50 { 0, 0 }
51 };
52
53 #if 0
54 static PXASSPDef pxa26x_ssp[] = {
55 { 0x41000000, PXA2XX_PIC_SSP },
56 { 0x41400000, PXA25X_PIC_NSSP },
57 { 0x41500000, PXA26X_PIC_ASSP },
58 { 0, 0 }
59 };
60 #endif
61
62 static PXASSPDef pxa27x_ssp[] = {
63 { 0x41000000, PXA2XX_PIC_SSP },
64 { 0x41700000, PXA27X_PIC_SSP2 },
65 { 0x41900000, PXA2XX_PIC_SSP3 },
66 { 0, 0 }
67 };
68
69 #define PMCR 0x00 /* Power Manager Control register */
70 #define PSSR 0x04 /* Power Manager Sleep Status register */
71 #define PSPR 0x08 /* Power Manager Scratch-Pad register */
72 #define PWER 0x0c /* Power Manager Wake-Up Enable register */
73 #define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */
74 #define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */
75 #define PEDR 0x18 /* Power Manager Edge-Detect Status register */
76 #define PCFR 0x1c /* Power Manager General Configuration register */
77 #define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */
78 #define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */
79 #define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */
80 #define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */
81 #define RCSR 0x30 /* Reset Controller Status register */
82 #define PSLR 0x34 /* Power Manager Sleep Configuration register */
83 #define PTSR 0x38 /* Power Manager Standby Configuration register */
84 #define PVCR 0x40 /* Power Manager Voltage Change Control register */
85 #define PUCR 0x4c /* Power Manager USIM Card Control/Status register */
86 #define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */
87 #define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */
88 #define PCMD0 0x80 /* Power Manager I2C Command register File 0 */
89 #define PCMD31 0xfc /* Power Manager I2C Command register File 31 */
90
91 static uint64_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr,
92 unsigned size)
93 {
94 PXA2xxState *s = (PXA2xxState *) opaque;
95
96 switch (addr) {
97 case PMCR ... PCMD31:
98 if (addr & 3)
99 goto fail;
100
101 return s->pm_regs[addr >> 2];
102 default:
103 fail:
104 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
105 break;
106 }
107 return 0;
108 }
109
110 static void pxa2xx_pm_write(void *opaque, target_phys_addr_t addr,
111 uint64_t value, unsigned size)
112 {
113 PXA2xxState *s = (PXA2xxState *) opaque;
114
115 switch (addr) {
116 case PMCR:
117 /* Clear the write-one-to-clear bits... */
118 s->pm_regs[addr >> 2] &= ~(value & 0x2a);
119 /* ...and set the plain r/w bits */
120 s->pm_regs[addr >> 2] &= ~0x15;
121 s->pm_regs[addr >> 2] |= value & 0x15;
122 break;
123
124 case PSSR: /* Read-clean registers */
125 case RCSR:
126 case PKSR:
127 s->pm_regs[addr >> 2] &= ~value;
128 break;
129
130 default: /* Read-write registers */
131 if (!(addr & 3)) {
132 s->pm_regs[addr >> 2] = value;
133 break;
134 }
135
136 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
137 break;
138 }
139 }
140
141 static const MemoryRegionOps pxa2xx_pm_ops = {
142 .read = pxa2xx_pm_read,
143 .write = pxa2xx_pm_write,
144 .endianness = DEVICE_NATIVE_ENDIAN,
145 };
146
147 static const VMStateDescription vmstate_pxa2xx_pm = {
148 .name = "pxa2xx_pm",
149 .version_id = 0,
150 .minimum_version_id = 0,
151 .minimum_version_id_old = 0,
152 .fields = (VMStateField[]) {
153 VMSTATE_UINT32_ARRAY(pm_regs, PXA2xxState, 0x40),
154 VMSTATE_END_OF_LIST()
155 }
156 };
157
158 #define CCCR 0x00 /* Core Clock Configuration register */
159 #define CKEN 0x04 /* Clock Enable register */
160 #define OSCC 0x08 /* Oscillator Configuration register */
161 #define CCSR 0x0c /* Core Clock Status register */
162
163 static uint64_t pxa2xx_cm_read(void *opaque, target_phys_addr_t addr,
164 unsigned size)
165 {
166 PXA2xxState *s = (PXA2xxState *) opaque;
167
168 switch (addr) {
169 case CCCR:
170 case CKEN:
171 case OSCC:
172 return s->cm_regs[addr >> 2];
173
174 case CCSR:
175 return s->cm_regs[CCCR >> 2] | (3 << 28);
176
177 default:
178 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
179 break;
180 }
181 return 0;
182 }
183
184 static void pxa2xx_cm_write(void *opaque, target_phys_addr_t addr,
185 uint64_t value, unsigned size)
186 {
187 PXA2xxState *s = (PXA2xxState *) opaque;
188
189 switch (addr) {
190 case CCCR:
191 case CKEN:
192 s->cm_regs[addr >> 2] = value;
193 break;
194
195 case OSCC:
196 s->cm_regs[addr >> 2] &= ~0x6c;
197 s->cm_regs[addr >> 2] |= value & 0x6e;
198 if ((value >> 1) & 1) /* OON */
199 s->cm_regs[addr >> 2] |= 1 << 0; /* Oscillator is now stable */
200 break;
201
202 default:
203 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
204 break;
205 }
206 }
207
208 static const MemoryRegionOps pxa2xx_cm_ops = {
209 .read = pxa2xx_cm_read,
210 .write = pxa2xx_cm_write,
211 .endianness = DEVICE_NATIVE_ENDIAN,
212 };
213
214 static const VMStateDescription vmstate_pxa2xx_cm = {
215 .name = "pxa2xx_cm",
216 .version_id = 0,
217 .minimum_version_id = 0,
218 .minimum_version_id_old = 0,
219 .fields = (VMStateField[]) {
220 VMSTATE_UINT32_ARRAY(cm_regs, PXA2xxState, 4),
221 VMSTATE_UINT32(clkcfg, PXA2xxState),
222 VMSTATE_UINT32(pmnc, PXA2xxState),
223 VMSTATE_END_OF_LIST()
224 }
225 };
226
227 static uint32_t pxa2xx_clkpwr_read(void *opaque, int op2, int reg, int crm)
228 {
229 PXA2xxState *s = (PXA2xxState *) opaque;
230
231 switch (reg) {
232 case 6: /* Clock Configuration register */
233 return s->clkcfg;
234
235 case 7: /* Power Mode register */
236 return 0;
237
238 default:
239 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
240 break;
241 }
242 return 0;
243 }
244
245 static void pxa2xx_clkpwr_write(void *opaque, int op2, int reg, int crm,
246 uint32_t value)
247 {
248 PXA2xxState *s = (PXA2xxState *) opaque;
249 static const char *pwrmode[8] = {
250 "Normal", "Idle", "Deep-idle", "Standby",
251 "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep",
252 };
253
254 switch (reg) {
255 case 6: /* Clock Configuration register */
256 s->clkcfg = value & 0xf;
257 if (value & 2)
258 printf("%s: CPU frequency change attempt\n", __FUNCTION__);
259 break;
260
261 case 7: /* Power Mode register */
262 if (value & 8)
263 printf("%s: CPU voltage change attempt\n", __FUNCTION__);
264 switch (value & 7) {
265 case 0:
266 /* Do nothing */
267 break;
268
269 case 1:
270 /* Idle */
271 if (!(s->cm_regs[CCCR >> 2] & (1 << 31))) { /* CPDIS */
272 cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HALT);
273 break;
274 }
275 /* Fall through. */
276
277 case 2:
278 /* Deep-Idle */
279 cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HALT);
280 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
281 goto message;
282
283 case 3:
284 s->cpu->env.uncached_cpsr =
285 ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
286 s->cpu->env.cp15.c1_sys = 0;
287 s->cpu->env.cp15.c1_coproc = 0;
288 s->cpu->env.cp15.c2_base0 = 0;
289 s->cpu->env.cp15.c3 = 0;
290 s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */
291 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
292
293 /*
294 * The scratch-pad register is almost universally used
295 * for storing the return address on suspend. For the
296 * lack of a resuming bootloader, perform a jump
297 * directly to that address.
298 */
299 memset(s->cpu->env.regs, 0, 4 * 15);
300 s->cpu->env.regs[15] = s->pm_regs[PSPR >> 2];
301
302 #if 0
303 buffer = 0xe59ff000; /* ldr pc, [pc, #0] */
304 cpu_physical_memory_write(0, &buffer, 4);
305 buffer = s->pm_regs[PSPR >> 2];
306 cpu_physical_memory_write(8, &buffer, 4);
307 #endif
308
309 /* Suspend */
310 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
311
312 goto message;
313
314 default:
315 message:
316 printf("%s: machine entered %s mode\n", __FUNCTION__,
317 pwrmode[value & 7]);
318 }
319 break;
320
321 default:
322 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
323 break;
324 }
325 }
326
327 /* Performace Monitoring Registers */
328 #define CPPMNC 0 /* Performance Monitor Control register */
329 #define CPCCNT 1 /* Clock Counter register */
330 #define CPINTEN 4 /* Interrupt Enable register */
331 #define CPFLAG 5 /* Overflow Flag register */
332 #define CPEVTSEL 8 /* Event Selection register */
333
334 #define CPPMN0 0 /* Performance Count register 0 */
335 #define CPPMN1 1 /* Performance Count register 1 */
336 #define CPPMN2 2 /* Performance Count register 2 */
337 #define CPPMN3 3 /* Performance Count register 3 */
338
339 static uint32_t pxa2xx_perf_read(void *opaque, int op2, int reg, int crm)
340 {
341 PXA2xxState *s = (PXA2xxState *) opaque;
342
343 switch (reg) {
344 case CPPMNC:
345 return s->pmnc;
346 case CPCCNT:
347 if (s->pmnc & 1)
348 return qemu_get_clock_ns(vm_clock);
349 else
350 return 0;
351 case CPINTEN:
352 case CPFLAG:
353 case CPEVTSEL:
354 return 0;
355
356 default:
357 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
358 break;
359 }
360 return 0;
361 }
362
363 static void pxa2xx_perf_write(void *opaque, int op2, int reg, int crm,
364 uint32_t value)
365 {
366 PXA2xxState *s = (PXA2xxState *) opaque;
367
368 switch (reg) {
369 case CPPMNC:
370 s->pmnc = value;
371 break;
372
373 case CPCCNT:
374 case CPINTEN:
375 case CPFLAG:
376 case CPEVTSEL:
377 break;
378
379 default:
380 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
381 break;
382 }
383 }
384
385 static uint32_t pxa2xx_cp14_read(void *opaque, int op2, int reg, int crm)
386 {
387 switch (crm) {
388 case 0:
389 return pxa2xx_clkpwr_read(opaque, op2, reg, crm);
390 case 1:
391 return pxa2xx_perf_read(opaque, op2, reg, crm);
392 case 2:
393 switch (reg) {
394 case CPPMN0:
395 case CPPMN1:
396 case CPPMN2:
397 case CPPMN3:
398 return 0;
399 }
400 /* Fall through */
401 default:
402 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
403 break;
404 }
405 return 0;
406 }
407
408 static void pxa2xx_cp14_write(void *opaque, int op2, int reg, int crm,
409 uint32_t value)
410 {
411 switch (crm) {
412 case 0:
413 pxa2xx_clkpwr_write(opaque, op2, reg, crm, value);
414 break;
415 case 1:
416 pxa2xx_perf_write(opaque, op2, reg, crm, value);
417 break;
418 case 2:
419 switch (reg) {
420 case CPPMN0:
421 case CPPMN1:
422 case CPPMN2:
423 case CPPMN3:
424 return;
425 }
426 /* Fall through */
427 default:
428 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
429 break;
430 }
431 }
432
433 #define MDCNFG 0x00 /* SDRAM Configuration register */
434 #define MDREFR 0x04 /* SDRAM Refresh Control register */
435 #define MSC0 0x08 /* Static Memory Control register 0 */
436 #define MSC1 0x0c /* Static Memory Control register 1 */
437 #define MSC2 0x10 /* Static Memory Control register 2 */
438 #define MECR 0x14 /* Expansion Memory Bus Config register */
439 #define SXCNFG 0x1c /* Synchronous Static Memory Config register */
440 #define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */
441 #define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */
442 #define MCATT0 0x30 /* PC Card Attribute Socket 0 register */
443 #define MCATT1 0x34 /* PC Card Attribute Socket 1 register */
444 #define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */
445 #define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */
446 #define MDMRS 0x40 /* SDRAM Mode Register Set Config register */
447 #define BOOT_DEF 0x44 /* Boot-time Default Configuration register */
448 #define ARB_CNTL 0x48 /* Arbiter Control register */
449 #define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */
450 #define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */
451 #define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */
452 #define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */
453 #define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */
454 #define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */
455 #define SA1110 0x64 /* SA-1110 Memory Compatibility register */
456
457 static uint64_t pxa2xx_mm_read(void *opaque, target_phys_addr_t addr,
458 unsigned size)
459 {
460 PXA2xxState *s = (PXA2xxState *) opaque;
461
462 switch (addr) {
463 case MDCNFG ... SA1110:
464 if ((addr & 3) == 0)
465 return s->mm_regs[addr >> 2];
466
467 default:
468 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
469 break;
470 }
471 return 0;
472 }
473
474 static void pxa2xx_mm_write(void *opaque, target_phys_addr_t addr,
475 uint64_t value, unsigned size)
476 {
477 PXA2xxState *s = (PXA2xxState *) opaque;
478
479 switch (addr) {
480 case MDCNFG ... SA1110:
481 if ((addr & 3) == 0) {
482 s->mm_regs[addr >> 2] = value;
483 break;
484 }
485
486 default:
487 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
488 break;
489 }
490 }
491
492 static const MemoryRegionOps pxa2xx_mm_ops = {
493 .read = pxa2xx_mm_read,
494 .write = pxa2xx_mm_write,
495 .endianness = DEVICE_NATIVE_ENDIAN,
496 };
497
498 static const VMStateDescription vmstate_pxa2xx_mm = {
499 .name = "pxa2xx_mm",
500 .version_id = 0,
501 .minimum_version_id = 0,
502 .minimum_version_id_old = 0,
503 .fields = (VMStateField[]) {
504 VMSTATE_UINT32_ARRAY(mm_regs, PXA2xxState, 0x1a),
505 VMSTATE_END_OF_LIST()
506 }
507 };
508
509 /* Synchronous Serial Ports */
510 typedef struct {
511 SysBusDevice busdev;
512 MemoryRegion iomem;
513 qemu_irq irq;
514 int enable;
515 SSIBus *bus;
516
517 uint32_t sscr[2];
518 uint32_t sspsp;
519 uint32_t ssto;
520 uint32_t ssitr;
521 uint32_t sssr;
522 uint8_t sstsa;
523 uint8_t ssrsa;
524 uint8_t ssacd;
525
526 uint32_t rx_fifo[16];
527 int rx_level;
528 int rx_start;
529 } PXA2xxSSPState;
530
531 #define SSCR0 0x00 /* SSP Control register 0 */
532 #define SSCR1 0x04 /* SSP Control register 1 */
533 #define SSSR 0x08 /* SSP Status register */
534 #define SSITR 0x0c /* SSP Interrupt Test register */
535 #define SSDR 0x10 /* SSP Data register */
536 #define SSTO 0x28 /* SSP Time-Out register */
537 #define SSPSP 0x2c /* SSP Programmable Serial Protocol register */
538 #define SSTSA 0x30 /* SSP TX Time Slot Active register */
539 #define SSRSA 0x34 /* SSP RX Time Slot Active register */
540 #define SSTSS 0x38 /* SSP Time Slot Status register */
541 #define SSACD 0x3c /* SSP Audio Clock Divider register */
542
543 /* Bitfields for above registers */
544 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
545 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
546 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
547 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
548 #define SSCR0_SSE (1 << 7)
549 #define SSCR0_RIM (1 << 22)
550 #define SSCR0_TIM (1 << 23)
551 #define SSCR0_MOD (1 << 31)
552 #define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1)
553 #define SSCR1_RIE (1 << 0)
554 #define SSCR1_TIE (1 << 1)
555 #define SSCR1_LBM (1 << 2)
556 #define SSCR1_MWDS (1 << 5)
557 #define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1)
558 #define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1)
559 #define SSCR1_EFWR (1 << 14)
560 #define SSCR1_PINTE (1 << 18)
561 #define SSCR1_TINTE (1 << 19)
562 #define SSCR1_RSRE (1 << 20)
563 #define SSCR1_TSRE (1 << 21)
564 #define SSCR1_EBCEI (1 << 29)
565 #define SSITR_INT (7 << 5)
566 #define SSSR_TNF (1 << 2)
567 #define SSSR_RNE (1 << 3)
568 #define SSSR_TFS (1 << 5)
569 #define SSSR_RFS (1 << 6)
570 #define SSSR_ROR (1 << 7)
571 #define SSSR_PINT (1 << 18)
572 #define SSSR_TINT (1 << 19)
573 #define SSSR_EOC (1 << 20)
574 #define SSSR_TUR (1 << 21)
575 #define SSSR_BCE (1 << 23)
576 #define SSSR_RW 0x00bc0080
577
578 static void pxa2xx_ssp_int_update(PXA2xxSSPState *s)
579 {
580 int level = 0;
581
582 level |= s->ssitr & SSITR_INT;
583 level |= (s->sssr & SSSR_BCE) && (s->sscr[1] & SSCR1_EBCEI);
584 level |= (s->sssr & SSSR_TUR) && !(s->sscr[0] & SSCR0_TIM);
585 level |= (s->sssr & SSSR_EOC) && (s->sssr & (SSSR_TINT | SSSR_PINT));
586 level |= (s->sssr & SSSR_TINT) && (s->sscr[1] & SSCR1_TINTE);
587 level |= (s->sssr & SSSR_PINT) && (s->sscr[1] & SSCR1_PINTE);
588 level |= (s->sssr & SSSR_ROR) && !(s->sscr[0] & SSCR0_RIM);
589 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE);
590 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE);
591 qemu_set_irq(s->irq, !!level);
592 }
593
594 static void pxa2xx_ssp_fifo_update(PXA2xxSSPState *s)
595 {
596 s->sssr &= ~(0xf << 12); /* Clear RFL */
597 s->sssr &= ~(0xf << 8); /* Clear TFL */
598 s->sssr &= ~SSSR_TFS;
599 s->sssr &= ~SSSR_TNF;
600 if (s->enable) {
601 s->sssr |= ((s->rx_level - 1) & 0xf) << 12;
602 if (s->rx_level >= SSCR1_RFT(s->sscr[1]))
603 s->sssr |= SSSR_RFS;
604 else
605 s->sssr &= ~SSSR_RFS;
606 if (s->rx_level)
607 s->sssr |= SSSR_RNE;
608 else
609 s->sssr &= ~SSSR_RNE;
610 /* TX FIFO is never filled, so it is always in underrun
611 condition if SSP is enabled */
612 s->sssr |= SSSR_TFS;
613 s->sssr |= SSSR_TNF;
614 }
615
616 pxa2xx_ssp_int_update(s);
617 }
618
619 static uint64_t pxa2xx_ssp_read(void *opaque, target_phys_addr_t addr,
620 unsigned size)
621 {
622 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
623 uint32_t retval;
624
625 switch (addr) {
626 case SSCR0:
627 return s->sscr[0];
628 case SSCR1:
629 return s->sscr[1];
630 case SSPSP:
631 return s->sspsp;
632 case SSTO:
633 return s->ssto;
634 case SSITR:
635 return s->ssitr;
636 case SSSR:
637 return s->sssr | s->ssitr;
638 case SSDR:
639 if (!s->enable)
640 return 0xffffffff;
641 if (s->rx_level < 1) {
642 printf("%s: SSP Rx Underrun\n", __FUNCTION__);
643 return 0xffffffff;
644 }
645 s->rx_level --;
646 retval = s->rx_fifo[s->rx_start ++];
647 s->rx_start &= 0xf;
648 pxa2xx_ssp_fifo_update(s);
649 return retval;
650 case SSTSA:
651 return s->sstsa;
652 case SSRSA:
653 return s->ssrsa;
654 case SSTSS:
655 return 0;
656 case SSACD:
657 return s->ssacd;
658 default:
659 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
660 break;
661 }
662 return 0;
663 }
664
665 static void pxa2xx_ssp_write(void *opaque, target_phys_addr_t addr,
666 uint64_t value64, unsigned size)
667 {
668 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
669 uint32_t value = value64;
670
671 switch (addr) {
672 case SSCR0:
673 s->sscr[0] = value & 0xc7ffffff;
674 s->enable = value & SSCR0_SSE;
675 if (value & SSCR0_MOD)
676 printf("%s: Attempt to use network mode\n", __FUNCTION__);
677 if (s->enable && SSCR0_DSS(value) < 4)
678 printf("%s: Wrong data size: %i bits\n", __FUNCTION__,
679 SSCR0_DSS(value));
680 if (!(value & SSCR0_SSE)) {
681 s->sssr = 0;
682 s->ssitr = 0;
683 s->rx_level = 0;
684 }
685 pxa2xx_ssp_fifo_update(s);
686 break;
687
688 case SSCR1:
689 s->sscr[1] = value;
690 if (value & (SSCR1_LBM | SSCR1_EFWR))
691 printf("%s: Attempt to use SSP test mode\n", __FUNCTION__);
692 pxa2xx_ssp_fifo_update(s);
693 break;
694
695 case SSPSP:
696 s->sspsp = value;
697 break;
698
699 case SSTO:
700 s->ssto = value;
701 break;
702
703 case SSITR:
704 s->ssitr = value & SSITR_INT;
705 pxa2xx_ssp_int_update(s);
706 break;
707
708 case SSSR:
709 s->sssr &= ~(value & SSSR_RW);
710 pxa2xx_ssp_int_update(s);
711 break;
712
713 case SSDR:
714 if (SSCR0_UWIRE(s->sscr[0])) {
715 if (s->sscr[1] & SSCR1_MWDS)
716 value &= 0xffff;
717 else
718 value &= 0xff;
719 } else
720 /* Note how 32bits overflow does no harm here */
721 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1;
722
723 /* Data goes from here to the Tx FIFO and is shifted out from
724 * there directly to the slave, no need to buffer it.
725 */
726 if (s->enable) {
727 uint32_t readval;
728 readval = ssi_transfer(s->bus, value);
729 if (s->rx_level < 0x10) {
730 s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = readval;
731 } else {
732 s->sssr |= SSSR_ROR;
733 }
734 }
735 pxa2xx_ssp_fifo_update(s);
736 break;
737
738 case SSTSA:
739 s->sstsa = value;
740 break;
741
742 case SSRSA:
743 s->ssrsa = value;
744 break;
745
746 case SSACD:
747 s->ssacd = value;
748 break;
749
750 default:
751 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
752 break;
753 }
754 }
755
756 static const MemoryRegionOps pxa2xx_ssp_ops = {
757 .read = pxa2xx_ssp_read,
758 .write = pxa2xx_ssp_write,
759 .endianness = DEVICE_NATIVE_ENDIAN,
760 };
761
762 static void pxa2xx_ssp_save(QEMUFile *f, void *opaque)
763 {
764 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
765 int i;
766
767 qemu_put_be32(f, s->enable);
768
769 qemu_put_be32s(f, &s->sscr[0]);
770 qemu_put_be32s(f, &s->sscr[1]);
771 qemu_put_be32s(f, &s->sspsp);
772 qemu_put_be32s(f, &s->ssto);
773 qemu_put_be32s(f, &s->ssitr);
774 qemu_put_be32s(f, &s->sssr);
775 qemu_put_8s(f, &s->sstsa);
776 qemu_put_8s(f, &s->ssrsa);
777 qemu_put_8s(f, &s->ssacd);
778
779 qemu_put_byte(f, s->rx_level);
780 for (i = 0; i < s->rx_level; i ++)
781 qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 0xf]);
782 }
783
784 static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)
785 {
786 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
787 int i;
788
789 s->enable = qemu_get_be32(f);
790
791 qemu_get_be32s(f, &s->sscr[0]);
792 qemu_get_be32s(f, &s->sscr[1]);
793 qemu_get_be32s(f, &s->sspsp);
794 qemu_get_be32s(f, &s->ssto);
795 qemu_get_be32s(f, &s->ssitr);
796 qemu_get_be32s(f, &s->sssr);
797 qemu_get_8s(f, &s->sstsa);
798 qemu_get_8s(f, &s->ssrsa);
799 qemu_get_8s(f, &s->ssacd);
800
801 s->rx_level = qemu_get_byte(f);
802 s->rx_start = 0;
803 for (i = 0; i < s->rx_level; i ++)
804 s->rx_fifo[i] = qemu_get_byte(f);
805
806 return 0;
807 }
808
809 static int pxa2xx_ssp_init(SysBusDevice *dev)
810 {
811 PXA2xxSSPState *s = FROM_SYSBUS(PXA2xxSSPState, dev);
812
813 sysbus_init_irq(dev, &s->irq);
814
815 memory_region_init_io(&s->iomem, &pxa2xx_ssp_ops, s, "pxa2xx-ssp", 0x1000);
816 sysbus_init_mmio(dev, &s->iomem);
817 register_savevm(&dev->qdev, "pxa2xx_ssp", -1, 0,
818 pxa2xx_ssp_save, pxa2xx_ssp_load, s);
819
820 s->bus = ssi_create_bus(&dev->qdev, "ssi");
821 return 0;
822 }
823
824 /* Real-Time Clock */
825 #define RCNR 0x00 /* RTC Counter register */
826 #define RTAR 0x04 /* RTC Alarm register */
827 #define RTSR 0x08 /* RTC Status register */
828 #define RTTR 0x0c /* RTC Timer Trim register */
829 #define RDCR 0x10 /* RTC Day Counter register */
830 #define RYCR 0x14 /* RTC Year Counter register */
831 #define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */
832 #define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */
833 #define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */
834 #define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */
835 #define SWCR 0x28 /* RTC Stopwatch Counter register */
836 #define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */
837 #define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */
838 #define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */
839 #define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */
840
841 typedef struct {
842 SysBusDevice busdev;
843 MemoryRegion iomem;
844 uint32_t rttr;
845 uint32_t rtsr;
846 uint32_t rtar;
847 uint32_t rdar1;
848 uint32_t rdar2;
849 uint32_t ryar1;
850 uint32_t ryar2;
851 uint32_t swar1;
852 uint32_t swar2;
853 uint32_t piar;
854 uint32_t last_rcnr;
855 uint32_t last_rdcr;
856 uint32_t last_rycr;
857 uint32_t last_swcr;
858 uint32_t last_rtcpicr;
859 int64_t last_hz;
860 int64_t last_sw;
861 int64_t last_pi;
862 QEMUTimer *rtc_hz;
863 QEMUTimer *rtc_rdal1;
864 QEMUTimer *rtc_rdal2;
865 QEMUTimer *rtc_swal1;
866 QEMUTimer *rtc_swal2;
867 QEMUTimer *rtc_pi;
868 qemu_irq rtc_irq;
869 } PXA2xxRTCState;
870
871 static inline void pxa2xx_rtc_int_update(PXA2xxRTCState *s)
872 {
873 qemu_set_irq(s->rtc_irq, !!(s->rtsr & 0x2553));
874 }
875
876 static void pxa2xx_rtc_hzupdate(PXA2xxRTCState *s)
877 {
878 int64_t rt = qemu_get_clock_ms(rtc_clock);
879 s->last_rcnr += ((rt - s->last_hz) << 15) /
880 (1000 * ((s->rttr & 0xffff) + 1));
881 s->last_rdcr += ((rt - s->last_hz) << 15) /
882 (1000 * ((s->rttr & 0xffff) + 1));
883 s->last_hz = rt;
884 }
885
886 static void pxa2xx_rtc_swupdate(PXA2xxRTCState *s)
887 {
888 int64_t rt = qemu_get_clock_ms(rtc_clock);
889 if (s->rtsr & (1 << 12))
890 s->last_swcr += (rt - s->last_sw) / 10;
891 s->last_sw = rt;
892 }
893
894 static void pxa2xx_rtc_piupdate(PXA2xxRTCState *s)
895 {
896 int64_t rt = qemu_get_clock_ms(rtc_clock);
897 if (s->rtsr & (1 << 15))
898 s->last_swcr += rt - s->last_pi;
899 s->last_pi = rt;
900 }
901
902 static inline void pxa2xx_rtc_alarm_update(PXA2xxRTCState *s,
903 uint32_t rtsr)
904 {
905 if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0)))
906 qemu_mod_timer(s->rtc_hz, s->last_hz +
907 (((s->rtar - s->last_rcnr) * 1000 *
908 ((s->rttr & 0xffff) + 1)) >> 15));
909 else
910 qemu_del_timer(s->rtc_hz);
911
912 if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4)))
913 qemu_mod_timer(s->rtc_rdal1, s->last_hz +
914 (((s->rdar1 - s->last_rdcr) * 1000 *
915 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
916 else
917 qemu_del_timer(s->rtc_rdal1);
918
919 if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6)))
920 qemu_mod_timer(s->rtc_rdal2, s->last_hz +
921 (((s->rdar2 - s->last_rdcr) * 1000 *
922 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
923 else
924 qemu_del_timer(s->rtc_rdal2);
925
926 if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8)))
927 qemu_mod_timer(s->rtc_swal1, s->last_sw +
928 (s->swar1 - s->last_swcr) * 10); /* TODO: fixup */
929 else
930 qemu_del_timer(s->rtc_swal1);
931
932 if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10)))
933 qemu_mod_timer(s->rtc_swal2, s->last_sw +
934 (s->swar2 - s->last_swcr) * 10); /* TODO: fixup */
935 else
936 qemu_del_timer(s->rtc_swal2);
937
938 if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13)))
939 qemu_mod_timer(s->rtc_pi, s->last_pi +
940 (s->piar & 0xffff) - s->last_rtcpicr);
941 else
942 qemu_del_timer(s->rtc_pi);
943 }
944
945 static inline void pxa2xx_rtc_hz_tick(void *opaque)
946 {
947 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
948 s->rtsr |= (1 << 0);
949 pxa2xx_rtc_alarm_update(s, s->rtsr);
950 pxa2xx_rtc_int_update(s);
951 }
952
953 static inline void pxa2xx_rtc_rdal1_tick(void *opaque)
954 {
955 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
956 s->rtsr |= (1 << 4);
957 pxa2xx_rtc_alarm_update(s, s->rtsr);
958 pxa2xx_rtc_int_update(s);
959 }
960
961 static inline void pxa2xx_rtc_rdal2_tick(void *opaque)
962 {
963 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
964 s->rtsr |= (1 << 6);
965 pxa2xx_rtc_alarm_update(s, s->rtsr);
966 pxa2xx_rtc_int_update(s);
967 }
968
969 static inline void pxa2xx_rtc_swal1_tick(void *opaque)
970 {
971 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
972 s->rtsr |= (1 << 8);
973 pxa2xx_rtc_alarm_update(s, s->rtsr);
974 pxa2xx_rtc_int_update(s);
975 }
976
977 static inline void pxa2xx_rtc_swal2_tick(void *opaque)
978 {
979 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
980 s->rtsr |= (1 << 10);
981 pxa2xx_rtc_alarm_update(s, s->rtsr);
982 pxa2xx_rtc_int_update(s);
983 }
984
985 static inline void pxa2xx_rtc_pi_tick(void *opaque)
986 {
987 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
988 s->rtsr |= (1 << 13);
989 pxa2xx_rtc_piupdate(s);
990 s->last_rtcpicr = 0;
991 pxa2xx_rtc_alarm_update(s, s->rtsr);
992 pxa2xx_rtc_int_update(s);
993 }
994
995 static uint64_t pxa2xx_rtc_read(void *opaque, target_phys_addr_t addr,
996 unsigned size)
997 {
998 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
999
1000 switch (addr) {
1001 case RTTR:
1002 return s->rttr;
1003 case RTSR:
1004 return s->rtsr;
1005 case RTAR:
1006 return s->rtar;
1007 case RDAR1:
1008 return s->rdar1;
1009 case RDAR2:
1010 return s->rdar2;
1011 case RYAR1:
1012 return s->ryar1;
1013 case RYAR2:
1014 return s->ryar2;
1015 case SWAR1:
1016 return s->swar1;
1017 case SWAR2:
1018 return s->swar2;
1019 case PIAR:
1020 return s->piar;
1021 case RCNR:
1022 return s->last_rcnr + ((qemu_get_clock_ms(rtc_clock) - s->last_hz) << 15) /
1023 (1000 * ((s->rttr & 0xffff) + 1));
1024 case RDCR:
1025 return s->last_rdcr + ((qemu_get_clock_ms(rtc_clock) - s->last_hz) << 15) /
1026 (1000 * ((s->rttr & 0xffff) + 1));
1027 case RYCR:
1028 return s->last_rycr;
1029 case SWCR:
1030 if (s->rtsr & (1 << 12))
1031 return s->last_swcr + (qemu_get_clock_ms(rtc_clock) - s->last_sw) / 10;
1032 else
1033 return s->last_swcr;
1034 default:
1035 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1036 break;
1037 }
1038 return 0;
1039 }
1040
1041 static void pxa2xx_rtc_write(void *opaque, target_phys_addr_t addr,
1042 uint64_t value64, unsigned size)
1043 {
1044 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1045 uint32_t value = value64;
1046
1047 switch (addr) {
1048 case RTTR:
1049 if (!(s->rttr & (1 << 31))) {
1050 pxa2xx_rtc_hzupdate(s);
1051 s->rttr = value;
1052 pxa2xx_rtc_alarm_update(s, s->rtsr);
1053 }
1054 break;
1055
1056 case RTSR:
1057 if ((s->rtsr ^ value) & (1 << 15))
1058 pxa2xx_rtc_piupdate(s);
1059
1060 if ((s->rtsr ^ value) & (1 << 12))
1061 pxa2xx_rtc_swupdate(s);
1062
1063 if (((s->rtsr ^ value) & 0x4aac) | (value & ~0xdaac))
1064 pxa2xx_rtc_alarm_update(s, value);
1065
1066 s->rtsr = (value & 0xdaac) | (s->rtsr & ~(value & ~0xdaac));
1067 pxa2xx_rtc_int_update(s);
1068 break;
1069
1070 case RTAR:
1071 s->rtar = value;
1072 pxa2xx_rtc_alarm_update(s, s->rtsr);
1073 break;
1074
1075 case RDAR1:
1076 s->rdar1 = value;
1077 pxa2xx_rtc_alarm_update(s, s->rtsr);
1078 break;
1079
1080 case RDAR2:
1081 s->rdar2 = value;
1082 pxa2xx_rtc_alarm_update(s, s->rtsr);
1083 break;
1084
1085 case RYAR1:
1086 s->ryar1 = value;
1087 pxa2xx_rtc_alarm_update(s, s->rtsr);
1088 break;
1089
1090 case RYAR2:
1091 s->ryar2 = value;
1092 pxa2xx_rtc_alarm_update(s, s->rtsr);
1093 break;
1094
1095 case SWAR1:
1096 pxa2xx_rtc_swupdate(s);
1097 s->swar1 = value;
1098 s->last_swcr = 0;
1099 pxa2xx_rtc_alarm_update(s, s->rtsr);
1100 break;
1101
1102 case SWAR2:
1103 s->swar2 = value;
1104 pxa2xx_rtc_alarm_update(s, s->rtsr);
1105 break;
1106
1107 case PIAR:
1108 s->piar = value;
1109 pxa2xx_rtc_alarm_update(s, s->rtsr);
1110 break;
1111
1112 case RCNR:
1113 pxa2xx_rtc_hzupdate(s);
1114 s->last_rcnr = value;
1115 pxa2xx_rtc_alarm_update(s, s->rtsr);
1116 break;
1117
1118 case RDCR:
1119 pxa2xx_rtc_hzupdate(s);
1120 s->last_rdcr = value;
1121 pxa2xx_rtc_alarm_update(s, s->rtsr);
1122 break;
1123
1124 case RYCR:
1125 s->last_rycr = value;
1126 break;
1127
1128 case SWCR:
1129 pxa2xx_rtc_swupdate(s);
1130 s->last_swcr = value;
1131 pxa2xx_rtc_alarm_update(s, s->rtsr);
1132 break;
1133
1134 case RTCPICR:
1135 pxa2xx_rtc_piupdate(s);
1136 s->last_rtcpicr = value & 0xffff;
1137 pxa2xx_rtc_alarm_update(s, s->rtsr);
1138 break;
1139
1140 default:
1141 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1142 }
1143 }
1144
1145 static const MemoryRegionOps pxa2xx_rtc_ops = {
1146 .read = pxa2xx_rtc_read,
1147 .write = pxa2xx_rtc_write,
1148 .endianness = DEVICE_NATIVE_ENDIAN,
1149 };
1150
1151 static int pxa2xx_rtc_init(SysBusDevice *dev)
1152 {
1153 PXA2xxRTCState *s = FROM_SYSBUS(PXA2xxRTCState, dev);
1154 struct tm tm;
1155 int wom;
1156
1157 s->rttr = 0x7fff;
1158 s->rtsr = 0;
1159
1160 qemu_get_timedate(&tm, 0);
1161 wom = ((tm.tm_mday - 1) / 7) + 1;
1162
1163 s->last_rcnr = (uint32_t) mktimegm(&tm);
1164 s->last_rdcr = (wom << 20) | ((tm.tm_wday + 1) << 17) |
1165 (tm.tm_hour << 12) | (tm.tm_min << 6) | tm.tm_sec;
1166 s->last_rycr = ((tm.tm_year + 1900) << 9) |
1167 ((tm.tm_mon + 1) << 5) | tm.tm_mday;
1168 s->last_swcr = (tm.tm_hour << 19) |
1169 (tm.tm_min << 13) | (tm.tm_sec << 7);
1170 s->last_rtcpicr = 0;
1171 s->last_hz = s->last_sw = s->last_pi = qemu_get_clock_ms(rtc_clock);
1172
1173 s->rtc_hz = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_hz_tick, s);
1174 s->rtc_rdal1 = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_rdal1_tick, s);
1175 s->rtc_rdal2 = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_rdal2_tick, s);
1176 s->rtc_swal1 = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_swal1_tick, s);
1177 s->rtc_swal2 = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_swal2_tick, s);
1178 s->rtc_pi = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_pi_tick, s);
1179
1180 sysbus_init_irq(dev, &s->rtc_irq);
1181
1182 memory_region_init_io(&s->iomem, &pxa2xx_rtc_ops, s, "pxa2xx-rtc", 0x10000);
1183 sysbus_init_mmio(dev, &s->iomem);
1184
1185 return 0;
1186 }
1187
1188 static void pxa2xx_rtc_pre_save(void *opaque)
1189 {
1190 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1191
1192 pxa2xx_rtc_hzupdate(s);
1193 pxa2xx_rtc_piupdate(s);
1194 pxa2xx_rtc_swupdate(s);
1195 }
1196
1197 static int pxa2xx_rtc_post_load(void *opaque, int version_id)
1198 {
1199 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1200
1201 pxa2xx_rtc_alarm_update(s, s->rtsr);
1202
1203 return 0;
1204 }
1205
1206 static const VMStateDescription vmstate_pxa2xx_rtc_regs = {
1207 .name = "pxa2xx_rtc",
1208 .version_id = 0,
1209 .minimum_version_id = 0,
1210 .minimum_version_id_old = 0,
1211 .pre_save = pxa2xx_rtc_pre_save,
1212 .post_load = pxa2xx_rtc_post_load,
1213 .fields = (VMStateField[]) {
1214 VMSTATE_UINT32(rttr, PXA2xxRTCState),
1215 VMSTATE_UINT32(rtsr, PXA2xxRTCState),
1216 VMSTATE_UINT32(rtar, PXA2xxRTCState),
1217 VMSTATE_UINT32(rdar1, PXA2xxRTCState),
1218 VMSTATE_UINT32(rdar2, PXA2xxRTCState),
1219 VMSTATE_UINT32(ryar1, PXA2xxRTCState),
1220 VMSTATE_UINT32(ryar2, PXA2xxRTCState),
1221 VMSTATE_UINT32(swar1, PXA2xxRTCState),
1222 VMSTATE_UINT32(swar2, PXA2xxRTCState),
1223 VMSTATE_UINT32(piar, PXA2xxRTCState),
1224 VMSTATE_UINT32(last_rcnr, PXA2xxRTCState),
1225 VMSTATE_UINT32(last_rdcr, PXA2xxRTCState),
1226 VMSTATE_UINT32(last_rycr, PXA2xxRTCState),
1227 VMSTATE_UINT32(last_swcr, PXA2xxRTCState),
1228 VMSTATE_UINT32(last_rtcpicr, PXA2xxRTCState),
1229 VMSTATE_INT64(last_hz, PXA2xxRTCState),
1230 VMSTATE_INT64(last_sw, PXA2xxRTCState),
1231 VMSTATE_INT64(last_pi, PXA2xxRTCState),
1232 VMSTATE_END_OF_LIST(),
1233 },
1234 };
1235
1236 static void pxa2xx_rtc_sysbus_class_init(ObjectClass *klass, void *data)
1237 {
1238 DeviceClass *dc = DEVICE_CLASS(klass);
1239 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1240
1241 k->init = pxa2xx_rtc_init;
1242 dc->desc = "PXA2xx RTC Controller";
1243 dc->vmsd = &vmstate_pxa2xx_rtc_regs;
1244 }
1245
1246 static TypeInfo pxa2xx_rtc_sysbus_info = {
1247 .name = "pxa2xx_rtc",
1248 .parent = TYPE_SYS_BUS_DEVICE,
1249 .instance_size = sizeof(PXA2xxRTCState),
1250 .class_init = pxa2xx_rtc_sysbus_class_init,
1251 };
1252
1253 /* I2C Interface */
1254 typedef struct {
1255 I2CSlave i2c;
1256 PXA2xxI2CState *host;
1257 } PXA2xxI2CSlaveState;
1258
1259 struct PXA2xxI2CState {
1260 SysBusDevice busdev;
1261 MemoryRegion iomem;
1262 PXA2xxI2CSlaveState *slave;
1263 i2c_bus *bus;
1264 qemu_irq irq;
1265 uint32_t offset;
1266 uint32_t region_size;
1267
1268 uint16_t control;
1269 uint16_t status;
1270 uint8_t ibmr;
1271 uint8_t data;
1272 };
1273
1274 #define IBMR 0x80 /* I2C Bus Monitor register */
1275 #define IDBR 0x88 /* I2C Data Buffer register */
1276 #define ICR 0x90 /* I2C Control register */
1277 #define ISR 0x98 /* I2C Status register */
1278 #define ISAR 0xa0 /* I2C Slave Address register */
1279
1280 static void pxa2xx_i2c_update(PXA2xxI2CState *s)
1281 {
1282 uint16_t level = 0;
1283 level |= s->status & s->control & (1 << 10); /* BED */
1284 level |= (s->status & (1 << 7)) && (s->control & (1 << 9)); /* IRF */
1285 level |= (s->status & (1 << 6)) && (s->control & (1 << 8)); /* ITE */
1286 level |= s->status & (1 << 9); /* SAD */
1287 qemu_set_irq(s->irq, !!level);
1288 }
1289
1290 /* These are only stubs now. */
1291 static void pxa2xx_i2c_event(I2CSlave *i2c, enum i2c_event event)
1292 {
1293 PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c);
1294 PXA2xxI2CState *s = slave->host;
1295
1296 switch (event) {
1297 case I2C_START_SEND:
1298 s->status |= (1 << 9); /* set SAD */
1299 s->status &= ~(1 << 0); /* clear RWM */
1300 break;
1301 case I2C_START_RECV:
1302 s->status |= (1 << 9); /* set SAD */
1303 s->status |= 1 << 0; /* set RWM */
1304 break;
1305 case I2C_FINISH:
1306 s->status |= (1 << 4); /* set SSD */
1307 break;
1308 case I2C_NACK:
1309 s->status |= 1 << 1; /* set ACKNAK */
1310 break;
1311 }
1312 pxa2xx_i2c_update(s);
1313 }
1314
1315 static int pxa2xx_i2c_rx(I2CSlave *i2c)
1316 {
1317 PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c);
1318 PXA2xxI2CState *s = slave->host;
1319 if ((s->control & (1 << 14)) || !(s->control & (1 << 6)))
1320 return 0;
1321
1322 if (s->status & (1 << 0)) { /* RWM */
1323 s->status |= 1 << 6; /* set ITE */
1324 }
1325 pxa2xx_i2c_update(s);
1326
1327 return s->data;
1328 }
1329
1330 static int pxa2xx_i2c_tx(I2CSlave *i2c, uint8_t data)
1331 {
1332 PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c);
1333 PXA2xxI2CState *s = slave->host;
1334 if ((s->control & (1 << 14)) || !(s->control & (1 << 6)))
1335 return 1;
1336
1337 if (!(s->status & (1 << 0))) { /* RWM */
1338 s->status |= 1 << 7; /* set IRF */
1339 s->data = data;
1340 }
1341 pxa2xx_i2c_update(s);
1342
1343 return 1;
1344 }
1345
1346 static uint64_t pxa2xx_i2c_read(void *opaque, target_phys_addr_t addr,
1347 unsigned size)
1348 {
1349 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
1350
1351 addr -= s->offset;
1352 switch (addr) {
1353 case ICR:
1354 return s->control;
1355 case ISR:
1356 return s->status | (i2c_bus_busy(s->bus) << 2);
1357 case ISAR:
1358 return s->slave->i2c.address;
1359 case IDBR:
1360 return s->data;
1361 case IBMR:
1362 if (s->status & (1 << 2))
1363 s->ibmr ^= 3; /* Fake SCL and SDA pin changes */
1364 else
1365 s->ibmr = 0;
1366 return s->ibmr;
1367 default:
1368 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1369 break;
1370 }
1371 return 0;
1372 }
1373
1374 static void pxa2xx_i2c_write(void *opaque, target_phys_addr_t addr,
1375 uint64_t value64, unsigned size)
1376 {
1377 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
1378 uint32_t value = value64;
1379 int ack;
1380
1381 addr -= s->offset;
1382 switch (addr) {
1383 case ICR:
1384 s->control = value & 0xfff7;
1385 if ((value & (1 << 3)) && (value & (1 << 6))) { /* TB and IUE */
1386 /* TODO: slave mode */
1387 if (value & (1 << 0)) { /* START condition */
1388 if (s->data & 1)
1389 s->status |= 1 << 0; /* set RWM */
1390 else
1391 s->status &= ~(1 << 0); /* clear RWM */
1392 ack = !i2c_start_transfer(s->bus, s->data >> 1, s->data & 1);
1393 } else {
1394 if (s->status & (1 << 0)) { /* RWM */
1395 s->data = i2c_recv(s->bus);
1396 if (value & (1 << 2)) /* ACKNAK */
1397 i2c_nack(s->bus);
1398 ack = 1;
1399 } else
1400 ack = !i2c_send(s->bus, s->data);
1401 }
1402
1403 if (value & (1 << 1)) /* STOP condition */
1404 i2c_end_transfer(s->bus);
1405
1406 if (ack) {
1407 if (value & (1 << 0)) /* START condition */
1408 s->status |= 1 << 6; /* set ITE */
1409 else
1410 if (s->status & (1 << 0)) /* RWM */
1411 s->status |= 1 << 7; /* set IRF */
1412 else
1413 s->status |= 1 << 6; /* set ITE */
1414 s->status &= ~(1 << 1); /* clear ACKNAK */
1415 } else {
1416 s->status |= 1 << 6; /* set ITE */
1417 s->status |= 1 << 10; /* set BED */
1418 s->status |= 1 << 1; /* set ACKNAK */
1419 }
1420 }
1421 if (!(value & (1 << 3)) && (value & (1 << 6))) /* !TB and IUE */
1422 if (value & (1 << 4)) /* MA */
1423 i2c_end_transfer(s->bus);
1424 pxa2xx_i2c_update(s);
1425 break;
1426
1427 case ISR:
1428 s->status &= ~(value & 0x07f0);
1429 pxa2xx_i2c_update(s);
1430 break;
1431
1432 case ISAR:
1433 i2c_set_slave_address(&s->slave->i2c, value & 0x7f);
1434 break;
1435
1436 case IDBR:
1437 s->data = value & 0xff;
1438 break;
1439
1440 default:
1441 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1442 }
1443 }
1444
1445 static const MemoryRegionOps pxa2xx_i2c_ops = {
1446 .read = pxa2xx_i2c_read,
1447 .write = pxa2xx_i2c_write,
1448 .endianness = DEVICE_NATIVE_ENDIAN,
1449 };
1450
1451 static const VMStateDescription vmstate_pxa2xx_i2c_slave = {
1452 .name = "pxa2xx_i2c_slave",
1453 .version_id = 1,
1454 .minimum_version_id = 1,
1455 .minimum_version_id_old = 1,
1456 .fields = (VMStateField []) {
1457 VMSTATE_I2C_SLAVE(i2c, PXA2xxI2CSlaveState),
1458 VMSTATE_END_OF_LIST()
1459 }
1460 };
1461
1462 static const VMStateDescription vmstate_pxa2xx_i2c = {
1463 .name = "pxa2xx_i2c",
1464 .version_id = 1,
1465 .minimum_version_id = 1,
1466 .minimum_version_id_old = 1,
1467 .fields = (VMStateField []) {
1468 VMSTATE_UINT16(control, PXA2xxI2CState),
1469 VMSTATE_UINT16(status, PXA2xxI2CState),
1470 VMSTATE_UINT8(ibmr, PXA2xxI2CState),
1471 VMSTATE_UINT8(data, PXA2xxI2CState),
1472 VMSTATE_STRUCT_POINTER(slave, PXA2xxI2CState,
1473 vmstate_pxa2xx_i2c_slave, PXA2xxI2CSlaveState *),
1474 VMSTATE_END_OF_LIST()
1475 }
1476 };
1477
1478 static int pxa2xx_i2c_slave_init(I2CSlave *i2c)
1479 {
1480 /* Nothing to do. */
1481 return 0;
1482 }
1483
1484 static void pxa2xx_i2c_slave_class_init(ObjectClass *klass, void *data)
1485 {
1486 I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
1487
1488 k->init = pxa2xx_i2c_slave_init;
1489 k->event = pxa2xx_i2c_event;
1490 k->recv = pxa2xx_i2c_rx;
1491 k->send = pxa2xx_i2c_tx;
1492 }
1493
1494 static TypeInfo pxa2xx_i2c_slave_info = {
1495 .name = "pxa2xx-i2c-slave",
1496 .parent = TYPE_I2C_SLAVE,
1497 .instance_size = sizeof(PXA2xxI2CSlaveState),
1498 .class_init = pxa2xx_i2c_slave_class_init,
1499 };
1500
1501 PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base,
1502 qemu_irq irq, uint32_t region_size)
1503 {
1504 DeviceState *dev;
1505 SysBusDevice *i2c_dev;
1506 PXA2xxI2CState *s;
1507
1508 i2c_dev = sysbus_from_qdev(qdev_create(NULL, "pxa2xx_i2c"));
1509 qdev_prop_set_uint32(&i2c_dev->qdev, "size", region_size + 1);
1510 qdev_prop_set_uint32(&i2c_dev->qdev, "offset", base & region_size);
1511
1512 qdev_init_nofail(&i2c_dev->qdev);
1513
1514 sysbus_mmio_map(i2c_dev, 0, base & ~region_size);
1515 sysbus_connect_irq(i2c_dev, 0, irq);
1516
1517 s = FROM_SYSBUS(PXA2xxI2CState, i2c_dev);
1518 /* FIXME: Should the slave device really be on a separate bus? */
1519 dev = i2c_create_slave(i2c_init_bus(NULL, "dummy"), "pxa2xx-i2c-slave", 0);
1520 s->slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, I2C_SLAVE_FROM_QDEV(dev));
1521 s->slave->host = s;
1522
1523 return s;
1524 }
1525
1526 static int pxa2xx_i2c_initfn(SysBusDevice *dev)
1527 {
1528 PXA2xxI2CState *s = FROM_SYSBUS(PXA2xxI2CState, dev);
1529
1530 s->bus = i2c_init_bus(&dev->qdev, "i2c");
1531
1532 memory_region_init_io(&s->iomem, &pxa2xx_i2c_ops, s,
1533 "pxa2xx-i2x", s->region_size);
1534 sysbus_init_mmio(dev, &s->iomem);
1535 sysbus_init_irq(dev, &s->irq);
1536
1537 return 0;
1538 }
1539
1540 i2c_bus *pxa2xx_i2c_bus(PXA2xxI2CState *s)
1541 {
1542 return s->bus;
1543 }
1544
1545 static Property pxa2xx_i2c_properties[] = {
1546 DEFINE_PROP_UINT32("size", PXA2xxI2CState, region_size, 0x10000),
1547 DEFINE_PROP_UINT32("offset", PXA2xxI2CState, offset, 0),
1548 DEFINE_PROP_END_OF_LIST(),
1549 };
1550
1551 static void pxa2xx_i2c_class_init(ObjectClass *klass, void *data)
1552 {
1553 DeviceClass *dc = DEVICE_CLASS(klass);
1554 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1555
1556 k->init = pxa2xx_i2c_initfn;
1557 dc->desc = "PXA2xx I2C Bus Controller";
1558 dc->vmsd = &vmstate_pxa2xx_i2c;
1559 dc->props = pxa2xx_i2c_properties;
1560 }
1561
1562 static TypeInfo pxa2xx_i2c_info = {
1563 .name = "pxa2xx_i2c",
1564 .parent = TYPE_SYS_BUS_DEVICE,
1565 .instance_size = sizeof(PXA2xxI2CState),
1566 .class_init = pxa2xx_i2c_class_init,
1567 };
1568
1569 /* PXA Inter-IC Sound Controller */
1570 static void pxa2xx_i2s_reset(PXA2xxI2SState *i2s)
1571 {
1572 i2s->rx_len = 0;
1573 i2s->tx_len = 0;
1574 i2s->fifo_len = 0;
1575 i2s->clk = 0x1a;
1576 i2s->control[0] = 0x00;
1577 i2s->control[1] = 0x00;
1578 i2s->status = 0x00;
1579 i2s->mask = 0x00;
1580 }
1581
1582 #define SACR_TFTH(val) ((val >> 8) & 0xf)
1583 #define SACR_RFTH(val) ((val >> 12) & 0xf)
1584 #define SACR_DREC(val) (val & (1 << 3))
1585 #define SACR_DPRL(val) (val & (1 << 4))
1586
1587 static inline void pxa2xx_i2s_update(PXA2xxI2SState *i2s)
1588 {
1589 int rfs, tfs;
1590 rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len &&
1591 !SACR_DREC(i2s->control[1]);
1592 tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) &&
1593 i2s->enable && !SACR_DPRL(i2s->control[1]);
1594
1595 qemu_set_irq(i2s->rx_dma, rfs);
1596 qemu_set_irq(i2s->tx_dma, tfs);
1597
1598 i2s->status &= 0xe0;
1599 if (i2s->fifo_len < 16 || !i2s->enable)
1600 i2s->status |= 1 << 0; /* TNF */
1601 if (i2s->rx_len)
1602 i2s->status |= 1 << 1; /* RNE */
1603 if (i2s->enable)
1604 i2s->status |= 1 << 2; /* BSY */
1605 if (tfs)
1606 i2s->status |= 1 << 3; /* TFS */
1607 if (rfs)
1608 i2s->status |= 1 << 4; /* RFS */
1609 if (!(i2s->tx_len && i2s->enable))
1610 i2s->status |= i2s->fifo_len << 8; /* TFL */
1611 i2s->status |= MAX(i2s->rx_len, 0xf) << 12; /* RFL */
1612
1613 qemu_set_irq(i2s->irq, i2s->status & i2s->mask);
1614 }
1615
1616 #define SACR0 0x00 /* Serial Audio Global Control register */
1617 #define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */
1618 #define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */
1619 #define SAIMR 0x14 /* Serial Audio Interrupt Mask register */
1620 #define SAICR 0x18 /* Serial Audio Interrupt Clear register */
1621 #define SADIV 0x60 /* Serial Audio Clock Divider register */
1622 #define SADR 0x80 /* Serial Audio Data register */
1623
1624 static uint64_t pxa2xx_i2s_read(void *opaque, target_phys_addr_t addr,
1625 unsigned size)
1626 {
1627 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1628
1629 switch (addr) {
1630 case SACR0:
1631 return s->control[0];
1632 case SACR1:
1633 return s->control[1];
1634 case SASR0:
1635 return s->status;
1636 case SAIMR:
1637 return s->mask;
1638 case SAICR:
1639 return 0;
1640 case SADIV:
1641 return s->clk;
1642 case SADR:
1643 if (s->rx_len > 0) {
1644 s->rx_len --;
1645 pxa2xx_i2s_update(s);
1646 return s->codec_in(s->opaque);
1647 }
1648 return 0;
1649 default:
1650 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1651 break;
1652 }
1653 return 0;
1654 }
1655
1656 static void pxa2xx_i2s_write(void *opaque, target_phys_addr_t addr,
1657 uint64_t value, unsigned size)
1658 {
1659 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1660 uint32_t *sample;
1661
1662 switch (addr) {
1663 case SACR0:
1664 if (value & (1 << 3)) /* RST */
1665 pxa2xx_i2s_reset(s);
1666 s->control[0] = value & 0xff3d;
1667 if (!s->enable && (value & 1) && s->tx_len) { /* ENB */
1668 for (sample = s->fifo; s->fifo_len > 0; s->fifo_len --, sample ++)
1669 s->codec_out(s->opaque, *sample);
1670 s->status &= ~(1 << 7); /* I2SOFF */
1671 }
1672 if (value & (1 << 4)) /* EFWR */
1673 printf("%s: Attempt to use special function\n", __FUNCTION__);
1674 s->enable = (value & 9) == 1; /* ENB && !RST*/
1675 pxa2xx_i2s_update(s);
1676 break;
1677 case SACR1:
1678 s->control[1] = value & 0x0039;
1679 if (value & (1 << 5)) /* ENLBF */
1680 printf("%s: Attempt to use loopback function\n", __FUNCTION__);
1681 if (value & (1 << 4)) /* DPRL */
1682 s->fifo_len = 0;
1683 pxa2xx_i2s_update(s);
1684 break;
1685 case SAIMR:
1686 s->mask = value & 0x0078;
1687 pxa2xx_i2s_update(s);
1688 break;
1689 case SAICR:
1690 s->status &= ~(value & (3 << 5));
1691 pxa2xx_i2s_update(s);
1692 break;
1693 case SADIV:
1694 s->clk = value & 0x007f;
1695 break;
1696 case SADR:
1697 if (s->tx_len && s->enable) {
1698 s->tx_len --;
1699 pxa2xx_i2s_update(s);
1700 s->codec_out(s->opaque, value);
1701 } else if (s->fifo_len < 16) {
1702 s->fifo[s->fifo_len ++] = value;
1703 pxa2xx_i2s_update(s);
1704 }
1705 break;
1706 default:
1707 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1708 }
1709 }
1710
1711 static const MemoryRegionOps pxa2xx_i2s_ops = {
1712 .read = pxa2xx_i2s_read,
1713 .write = pxa2xx_i2s_write,
1714 .endianness = DEVICE_NATIVE_ENDIAN,
1715 };
1716
1717 static const VMStateDescription vmstate_pxa2xx_i2s = {
1718 .name = "pxa2xx_i2s",
1719 .version_id = 0,
1720 .minimum_version_id = 0,
1721 .minimum_version_id_old = 0,
1722 .fields = (VMStateField[]) {
1723 VMSTATE_UINT32_ARRAY(control, PXA2xxI2SState, 2),
1724 VMSTATE_UINT32(status, PXA2xxI2SState),
1725 VMSTATE_UINT32(mask, PXA2xxI2SState),
1726 VMSTATE_UINT32(clk, PXA2xxI2SState),
1727 VMSTATE_INT32(enable, PXA2xxI2SState),
1728 VMSTATE_INT32(rx_len, PXA2xxI2SState),
1729 VMSTATE_INT32(tx_len, PXA2xxI2SState),
1730 VMSTATE_INT32(fifo_len, PXA2xxI2SState),
1731 VMSTATE_END_OF_LIST()
1732 }
1733 };
1734
1735 static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx)
1736 {
1737 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1738 uint32_t *sample;
1739
1740 /* Signal FIFO errors */
1741 if (s->enable && s->tx_len)
1742 s->status |= 1 << 5; /* TUR */
1743 if (s->enable && s->rx_len)
1744 s->status |= 1 << 6; /* ROR */
1745
1746 /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to
1747 * handle the cases where it makes a difference. */
1748 s->tx_len = tx - s->fifo_len;
1749 s->rx_len = rx;
1750 /* Note that is s->codec_out wasn't set, we wouldn't get called. */
1751 if (s->enable)
1752 for (sample = s->fifo; s->fifo_len; s->fifo_len --, sample ++)
1753 s->codec_out(s->opaque, *sample);
1754 pxa2xx_i2s_update(s);
1755 }
1756
1757 static PXA2xxI2SState *pxa2xx_i2s_init(MemoryRegion *sysmem,
1758 target_phys_addr_t base,
1759 qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma)
1760 {
1761 PXA2xxI2SState *s = (PXA2xxI2SState *)
1762 g_malloc0(sizeof(PXA2xxI2SState));
1763
1764 s->irq = irq;
1765 s->rx_dma = rx_dma;
1766 s->tx_dma = tx_dma;
1767 s->data_req = pxa2xx_i2s_data_req;
1768
1769 pxa2xx_i2s_reset(s);
1770
1771 memory_region_init_io(&s->iomem, &pxa2xx_i2s_ops, s,
1772 "pxa2xx-i2s", 0x100000);
1773 memory_region_add_subregion(sysmem, base, &s->iomem);
1774
1775 vmstate_register(NULL, base, &vmstate_pxa2xx_i2s, s);
1776
1777 return s;
1778 }
1779
1780 /* PXA Fast Infra-red Communications Port */
1781 struct PXA2xxFIrState {
1782 MemoryRegion iomem;
1783 qemu_irq irq;
1784 qemu_irq rx_dma;
1785 qemu_irq tx_dma;
1786 int enable;
1787 CharDriverState *chr;
1788
1789 uint8_t control[3];
1790 uint8_t status[2];
1791
1792 int rx_len;
1793 int rx_start;
1794 uint8_t rx_fifo[64];
1795 };
1796
1797 static void pxa2xx_fir_reset(PXA2xxFIrState *s)
1798 {
1799 s->control[0] = 0x00;
1800 s->control[1] = 0x00;
1801 s->control[2] = 0x00;
1802 s->status[0] = 0x00;
1803 s->status[1] = 0x00;
1804 s->enable = 0;
1805 }
1806
1807 static inline void pxa2xx_fir_update(PXA2xxFIrState *s)
1808 {
1809 static const int tresh[4] = { 8, 16, 32, 0 };
1810 int intr = 0;
1811 if ((s->control[0] & (1 << 4)) && /* RXE */
1812 s->rx_len >= tresh[s->control[2] & 3]) /* TRIG */
1813 s->status[0] |= 1 << 4; /* RFS */
1814 else
1815 s->status[0] &= ~(1 << 4); /* RFS */
1816 if (s->control[0] & (1 << 3)) /* TXE */
1817 s->status[0] |= 1 << 3; /* TFS */
1818 else
1819 s->status[0] &= ~(1 << 3); /* TFS */
1820 if (s->rx_len)
1821 s->status[1] |= 1 << 2; /* RNE */
1822 else
1823 s->status[1] &= ~(1 << 2); /* RNE */
1824 if (s->control[0] & (1 << 4)) /* RXE */
1825 s->status[1] |= 1 << 0; /* RSY */
1826 else
1827 s->status[1] &= ~(1 << 0); /* RSY */
1828
1829 intr |= (s->control[0] & (1 << 5)) && /* RIE */
1830 (s->status[0] & (1 << 4)); /* RFS */
1831 intr |= (s->control[0] & (1 << 6)) && /* TIE */
1832 (s->status[0] & (1 << 3)); /* TFS */
1833 intr |= (s->control[2] & (1 << 4)) && /* TRAIL */
1834 (s->status[0] & (1 << 6)); /* EOC */
1835 intr |= (s->control[0] & (1 << 2)) && /* TUS */
1836 (s->status[0] & (1 << 1)); /* TUR */
1837 intr |= s->status[0] & 0x25; /* FRE, RAB, EIF */
1838
1839 qemu_set_irq(s->rx_dma, (s->status[0] >> 4) & 1);
1840 qemu_set_irq(s->tx_dma, (s->status[0] >> 3) & 1);
1841
1842 qemu_set_irq(s->irq, intr && s->enable);
1843 }
1844
1845 #define ICCR0 0x00 /* FICP Control register 0 */
1846 #define ICCR1 0x04 /* FICP Control register 1 */
1847 #define ICCR2 0x08 /* FICP Control register 2 */
1848 #define ICDR 0x0c /* FICP Data register */
1849 #define ICSR0 0x14 /* FICP Status register 0 */
1850 #define ICSR1 0x18 /* FICP Status register 1 */
1851 #define ICFOR 0x1c /* FICP FIFO Occupancy Status register */
1852
1853 static uint64_t pxa2xx_fir_read(void *opaque, target_phys_addr_t addr,
1854 unsigned size)
1855 {
1856 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1857 uint8_t ret;
1858
1859 switch (addr) {
1860 case ICCR0:
1861 return s->control[0];
1862 case ICCR1:
1863 return s->control[1];
1864 case ICCR2:
1865 return s->control[2];
1866 case ICDR:
1867 s->status[0] &= ~0x01;
1868 s->status[1] &= ~0x72;
1869 if (s->rx_len) {
1870 s->rx_len --;
1871 ret = s->rx_fifo[s->rx_start ++];
1872 s->rx_start &= 63;
1873 pxa2xx_fir_update(s);
1874 return ret;
1875 }
1876 printf("%s: Rx FIFO underrun.\n", __FUNCTION__);
1877 break;
1878 case ICSR0:
1879 return s->status[0];
1880 case ICSR1:
1881 return s->status[1] | (1 << 3); /* TNF */
1882 case ICFOR:
1883 return s->rx_len;
1884 default:
1885 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1886 break;
1887 }
1888 return 0;
1889 }
1890
1891 static void pxa2xx_fir_write(void *opaque, target_phys_addr_t addr,
1892 uint64_t value64, unsigned size)
1893 {
1894 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1895 uint32_t value = value64;
1896 uint8_t ch;
1897
1898 switch (addr) {
1899 case ICCR0:
1900 s->control[0] = value;
1901 if (!(value & (1 << 4))) /* RXE */
1902 s->rx_len = s->rx_start = 0;
1903 if (!(value & (1 << 3))) { /* TXE */
1904 /* Nop */
1905 }
1906 s->enable = value & 1; /* ITR */
1907 if (!s->enable)
1908 s->status[0] = 0;
1909 pxa2xx_fir_update(s);
1910 break;
1911 case ICCR1:
1912 s->control[1] = value;
1913 break;
1914 case ICCR2:
1915 s->control[2] = value & 0x3f;
1916 pxa2xx_fir_update(s);
1917 break;
1918 case ICDR:
1919 if (s->control[2] & (1 << 2)) /* TXP */
1920 ch = value;
1921 else
1922 ch = ~value;
1923 if (s->chr && s->enable && (s->control[0] & (1 << 3))) /* TXE */
1924 qemu_chr_fe_write(s->chr, &ch, 1);
1925 break;
1926 case ICSR0:
1927 s->status[0] &= ~(value & 0x66);
1928 pxa2xx_fir_update(s);
1929 break;
1930 case ICFOR:
1931 break;
1932 default:
1933 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1934 }
1935 }
1936
1937 static const MemoryRegionOps pxa2xx_fir_ops = {
1938 .read = pxa2xx_fir_read,
1939 .write = pxa2xx_fir_write,
1940 .endianness = DEVICE_NATIVE_ENDIAN,
1941 };
1942
1943 static int pxa2xx_fir_is_empty(void *opaque)
1944 {
1945 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1946 return (s->rx_len < 64);
1947 }
1948
1949 static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size)
1950 {
1951 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1952 if (!(s->control[0] & (1 << 4))) /* RXE */
1953 return;
1954
1955 while (size --) {
1956 s->status[1] |= 1 << 4; /* EOF */
1957 if (s->rx_len >= 64) {
1958 s->status[1] |= 1 << 6; /* ROR */
1959 break;
1960 }
1961
1962 if (s->control[2] & (1 << 3)) /* RXP */
1963 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = *(buf ++);
1964 else
1965 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = ~*(buf ++);
1966 }
1967
1968 pxa2xx_fir_update(s);
1969 }
1970
1971 static void pxa2xx_fir_event(void *opaque, int event)
1972 {
1973 }
1974
1975 static void pxa2xx_fir_save(QEMUFile *f, void *opaque)
1976 {
1977 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1978 int i;
1979
1980 qemu_put_be32(f, s->enable);
1981
1982 qemu_put_8s(f, &s->control[0]);
1983 qemu_put_8s(f, &s->control[1]);
1984 qemu_put_8s(f, &s->control[2]);
1985 qemu_put_8s(f, &s->status[0]);
1986 qemu_put_8s(f, &s->status[1]);
1987
1988 qemu_put_byte(f, s->rx_len);
1989 for (i = 0; i < s->rx_len; i ++)
1990 qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 63]);
1991 }
1992
1993 static int pxa2xx_fir_load(QEMUFile *f, void *opaque, int version_id)
1994 {
1995 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1996 int i;
1997
1998 s->enable = qemu_get_be32(f);
1999
2000 qemu_get_8s(f, &s->control[0]);
2001 qemu_get_8s(f, &s->control[1]);
2002 qemu_get_8s(f, &s->control[2]);
2003 qemu_get_8s(f, &s->status[0]);
2004 qemu_get_8s(f, &s->status[1]);
2005
2006 s->rx_len = qemu_get_byte(f);
2007 s->rx_start = 0;
2008 for (i = 0; i < s->rx_len; i ++)
2009 s->rx_fifo[i] = qemu_get_byte(f);
2010
2011 return 0;
2012 }
2013
2014 static PXA2xxFIrState *pxa2xx_fir_init(MemoryRegion *sysmem,
2015 target_phys_addr_t base,
2016 qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma,
2017 CharDriverState *chr)
2018 {
2019 PXA2xxFIrState *s = (PXA2xxFIrState *)
2020 g_malloc0(sizeof(PXA2xxFIrState));
2021
2022 s->irq = irq;
2023 s->rx_dma = rx_dma;
2024 s->tx_dma = tx_dma;
2025 s->chr = chr;
2026
2027 pxa2xx_fir_reset(s);
2028
2029 memory_region_init_io(&s->iomem, &pxa2xx_fir_ops, s, "pxa2xx-fir", 0x1000);
2030 memory_region_add_subregion(sysmem, base, &s->iomem);
2031
2032 if (chr)
2033 qemu_chr_add_handlers(chr, pxa2xx_fir_is_empty,
2034 pxa2xx_fir_rx, pxa2xx_fir_event, s);
2035
2036 register_savevm(NULL, "pxa2xx_fir", 0, 0, pxa2xx_fir_save,
2037 pxa2xx_fir_load, s);
2038
2039 return s;
2040 }
2041
2042 static void pxa2xx_reset(void *opaque, int line, int level)
2043 {
2044 PXA2xxState *s = (PXA2xxState *) opaque;
2045
2046 if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */
2047 cpu_reset(CPU(s->cpu));
2048 /* TODO: reset peripherals */
2049 }
2050 }
2051
2052 /* Initialise a PXA270 integrated chip (ARM based core). */
2053 PXA2xxState *pxa270_init(MemoryRegion *address_space,
2054 unsigned int sdram_size, const char *revision)
2055 {
2056 PXA2xxState *s;
2057 int i;
2058 DriveInfo *dinfo;
2059 s = (PXA2xxState *) g_malloc0(sizeof(PXA2xxState));
2060
2061 if (revision && strncmp(revision, "pxa27", 5)) {
2062 fprintf(stderr, "Machine requires a PXA27x processor.\n");
2063 exit(1);
2064 }
2065 if (!revision)
2066 revision = "pxa270";
2067
2068 s->cpu = cpu_arm_init(revision);
2069 if (s->cpu == NULL) {
2070 fprintf(stderr, "Unable to find CPU definition\n");
2071 exit(1);
2072 }
2073 s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
2074
2075 /* SDRAM & Internal Memory Storage */
2076 memory_region_init_ram(&s->sdram, "pxa270.sdram", sdram_size);
2077 vmstate_register_ram_global(&s->sdram);
2078 memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram);
2079 memory_region_init_ram(&s->internal, "pxa270.internal", 0x40000);
2080 vmstate_register_ram_global(&s->internal);
2081 memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE,
2082 &s->internal);
2083
2084 s->pic = pxa2xx_pic_init(0x40d00000, s->cpu);
2085
2086 s->dma = pxa27x_dma_init(0x40000000,
2087 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA));
2088
2089 sysbus_create_varargs("pxa27x-timer", 0x40a00000,
2090 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0),
2091 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1),
2092 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2),
2093 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3),
2094 qdev_get_gpio_in(s->pic, PXA27X_PIC_OST_4_11),
2095 NULL);
2096
2097 s->gpio = pxa2xx_gpio_init(0x40e00000, &s->cpu->env, s->pic, 121);
2098
2099 dinfo = drive_get(IF_SD, 0, 0);
2100 if (!dinfo) {
2101 fprintf(stderr, "qemu: missing SecureDigital device\n");
2102 exit(1);
2103 }
2104 s->mmc = pxa2xx_mmci_init(address_space, 0x41100000, dinfo->bdrv,
2105 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC),
2106 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI),
2107 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI));
2108
2109 for (i = 0; pxa270_serial[i].io_base; i++) {
2110 if (serial_hds[i]) {
2111 serial_mm_init(address_space, pxa270_serial[i].io_base, 2,
2112 qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn),
2113 14857000 / 16, serial_hds[i],
2114 DEVICE_NATIVE_ENDIAN);
2115 } else {
2116 break;
2117 }
2118 }
2119 if (serial_hds[i])
2120 s->fir = pxa2xx_fir_init(address_space, 0x40800000,
2121 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP),
2122 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP),
2123 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP),
2124 serial_hds[i]);
2125
2126 s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000,
2127 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD));
2128
2129 s->cm_base = 0x41300000;
2130 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
2131 s->clkcfg = 0x00000009; /* Turbo mode active */
2132 memory_region_init_io(&s->cm_iomem, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000);
2133 memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem);
2134 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s);
2135
2136 cpu_arm_set_cp_io(&s->cpu->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
2137
2138 s->mm_base = 0x48000000;
2139 s->mm_regs[MDMRS >> 2] = 0x00020002;
2140 s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2141 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
2142 memory_region_init_io(&s->mm_iomem, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000);
2143 memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem);
2144 vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s);
2145
2146 s->pm_base = 0x40f00000;
2147 memory_region_init_io(&s->pm_iomem, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100);
2148 memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem);
2149 vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s);
2150
2151 for (i = 0; pxa27x_ssp[i].io_base; i ++);
2152 s->ssp = (SSIBus **)g_malloc0(sizeof(SSIBus *) * i);
2153 for (i = 0; pxa27x_ssp[i].io_base; i ++) {
2154 DeviceState *dev;
2155 dev = sysbus_create_simple("pxa2xx-ssp", pxa27x_ssp[i].io_base,
2156 qdev_get_gpio_in(s->pic, pxa27x_ssp[i].irqn));
2157 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
2158 }
2159
2160 if (usb_enabled) {
2161 sysbus_create_simple("sysbus-ohci", 0x4c000000,
2162 qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
2163 }
2164
2165 s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000);
2166 s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000);
2167
2168 sysbus_create_simple("pxa2xx_rtc", 0x40900000,
2169 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM));
2170
2171 s->i2c[0] = pxa2xx_i2c_init(0x40301600,
2172 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff);
2173 s->i2c[1] = pxa2xx_i2c_init(0x40f00100,
2174 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff);
2175
2176 s->i2s = pxa2xx_i2s_init(address_space, 0x40400000,
2177 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S),
2178 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S),
2179 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S));
2180
2181 s->kp = pxa27x_keypad_init(address_space, 0x41500000,
2182 qdev_get_gpio_in(s->pic, PXA2XX_PIC_KEYPAD));
2183
2184 /* GPIO1 resets the processor */
2185 /* The handler can be overridden by board-specific code */
2186 qdev_connect_gpio_out(s->gpio, 1, s->reset);
2187 return s;
2188 }
2189
2190 /* Initialise a PXA255 integrated chip (ARM based core). */
2191 PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
2192 {
2193 PXA2xxState *s;
2194 int i;
2195 DriveInfo *dinfo;
2196
2197 s = (PXA2xxState *) g_malloc0(sizeof(PXA2xxState));
2198
2199 s->cpu = cpu_arm_init("pxa255");
2200 if (s->cpu == NULL) {
2201 fprintf(stderr, "Unable to find CPU definition\n");
2202 exit(1);
2203 }
2204 s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
2205
2206 /* SDRAM & Internal Memory Storage */
2207 memory_region_init_ram(&s->sdram, "pxa255.sdram", sdram_size);
2208 vmstate_register_ram_global(&s->sdram);
2209 memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram);
2210 memory_region_init_ram(&s->internal, "pxa255.internal",
2211 PXA2XX_INTERNAL_SIZE);
2212 vmstate_register_ram_global(&s->internal);
2213 memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE,
2214 &s->internal);
2215
2216 s->pic = pxa2xx_pic_init(0x40d00000, s->cpu);
2217
2218 s->dma = pxa255_dma_init(0x40000000,
2219 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA));
2220
2221 sysbus_create_varargs("pxa25x-timer", 0x40a00000,
2222 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0),
2223 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1),
2224 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2),
2225 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3),
2226 NULL);
2227
2228 s->gpio = pxa2xx_gpio_init(0x40e00000, &s->cpu->env, s->pic, 85);
2229
2230 dinfo = drive_get(IF_SD, 0, 0);
2231 if (!dinfo) {
2232 fprintf(stderr, "qemu: missing SecureDigital device\n");
2233 exit(1);
2234 }
2235 s->mmc = pxa2xx_mmci_init(address_space, 0x41100000, dinfo->bdrv,
2236 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC),
2237 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI),
2238 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI));
2239
2240 for (i = 0; pxa255_serial[i].io_base; i++) {
2241 if (serial_hds[i]) {
2242 serial_mm_init(address_space, pxa255_serial[i].io_base, 2,
2243 qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn),
2244 14745600 / 16, serial_hds[i],
2245 DEVICE_NATIVE_ENDIAN);
2246 } else {
2247 break;
2248 }
2249 }
2250 if (serial_hds[i])
2251 s->fir = pxa2xx_fir_init(address_space, 0x40800000,
2252 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP),
2253 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP),
2254 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP),
2255 serial_hds[i]);
2256
2257 s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000,
2258 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD));
2259
2260 s->cm_base = 0x41300000;
2261 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
2262 s->clkcfg = 0x00000009; /* Turbo mode active */
2263 memory_region_init_io(&s->cm_iomem, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000);
2264 memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem);
2265 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s);
2266
2267 cpu_arm_set_cp_io(&s->cpu->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
2268
2269 s->mm_base = 0x48000000;
2270 s->mm_regs[MDMRS >> 2] = 0x00020002;
2271 s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2272 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
2273 memory_region_init_io(&s->mm_iomem, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000);
2274 memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem);
2275 vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s);
2276
2277 s->pm_base = 0x40f00000;
2278 memory_region_init_io(&s->pm_iomem, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100);
2279 memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem);
2280 vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s);
2281
2282 for (i = 0; pxa255_ssp[i].io_base; i ++);
2283 s->ssp = (SSIBus **)g_malloc0(sizeof(SSIBus *) * i);
2284 for (i = 0; pxa255_ssp[i].io_base; i ++) {
2285 DeviceState *dev;
2286 dev = sysbus_create_simple("pxa2xx-ssp", pxa255_ssp[i].io_base,
2287 qdev_get_gpio_in(s->pic, pxa255_ssp[i].irqn));
2288 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
2289 }
2290
2291 if (usb_enabled) {
2292 sysbus_create_simple("sysbus-ohci", 0x4c000000,
2293 qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
2294 }
2295
2296 s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000);
2297 s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000);
2298
2299 sysbus_create_simple("pxa2xx_rtc", 0x40900000,
2300 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM));
2301
2302 s->i2c[0] = pxa2xx_i2c_init(0x40301600,
2303 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff);
2304 s->i2c[1] = pxa2xx_i2c_init(0x40f00100,
2305 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff);
2306
2307 s->i2s = pxa2xx_i2s_init(address_space, 0x40400000,
2308 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S),
2309 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S),
2310 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S));
2311
2312 /* GPIO1 resets the processor */
2313 /* The handler can be overridden by board-specific code */
2314 qdev_connect_gpio_out(s->gpio, 1, s->reset);
2315 return s;
2316 }
2317
2318 static void pxa2xx_ssp_class_init(ObjectClass *klass, void *data)
2319 {
2320 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
2321
2322 sdc->init = pxa2xx_ssp_init;
2323 }
2324
2325 static TypeInfo pxa2xx_ssp_info = {
2326 .name = "pxa2xx-ssp",
2327 .parent = TYPE_SYS_BUS_DEVICE,
2328 .instance_size = sizeof(PXA2xxSSPState),
2329 .class_init = pxa2xx_ssp_class_init,
2330 };
2331
2332 static void pxa2xx_register_types(void)
2333 {
2334 type_register_static(&pxa2xx_i2c_slave_info);
2335 type_register_static(&pxa2xx_ssp_info);
2336 type_register_static(&pxa2xx_i2c_info);
2337 type_register_static(&pxa2xx_rtc_sysbus_info);
2338 }
2339
2340 type_init(pxa2xx_register_types)
Qemu copy for testing