hw/timer/mc146818rtc.c

   1 /*
   2  * QEMU MC146818 RTC emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw/hw.h"
  25 #include "qemu/timer.h"
  26 #include "sysemu/sysemu.h"
  27 #include "hw/timer/mc146818rtc.h"
  28 #include "qapi/visitor.h"
  29
  30 #ifdef TARGET_I386
  31 #include "hw/i386/apic.h"
  32 #endif
  33
  34 //#define DEBUG_CMOS
  35 //#define DEBUG_COALESCED
  36
  37 #ifdef DEBUG_CMOS
  38 # define CMOS_DPRINTF(format, ...)      printf(format, ## __VA_ARGS__)
  39 #else
  40 # define CMOS_DPRINTF(format, ...)      do { } while (0)
  41 #endif
  42
  43 #ifdef DEBUG_COALESCED
  44 # define DPRINTF_C(format, ...)      printf(format, ## __VA_ARGS__)
  45 #else
  46 # define DPRINTF_C(format, ...)      do { } while (0)
  47 #endif
  48
  49 #define NSEC_PER_SEC    1000000000LL
  50 #define SEC_PER_MIN     60
  51 #define MIN_PER_HOUR    60
  52 #define SEC_PER_HOUR    3600
  53 #define HOUR_PER_DAY    24
  54 #define SEC_PER_DAY     86400
  55
  56 #define RTC_REINJECT_ON_ACK_COUNT 20
  57 #define RTC_CLOCK_RATE            32768
  58 #define UIP_HOLD_LENGTH           (8 * NSEC_PER_SEC / 32768)
  59
  60 #define MC146818_RTC(obj) OBJECT_CHECK(RTCState, (obj), TYPE_MC146818_RTC)
  61
  62 typedef struct RTCState {
  63     ISADevice parent_obj;
  64
  65     MemoryRegion io;
  66     uint8_t cmos_data[128];
  67     uint8_t cmos_index;
  68     int32_t base_year;
  69     uint64_t base_rtc;
  70     uint64_t last_update;
  71     int64_t offset;
  72     qemu_irq irq;
  73     int it_shift;
  74     /* periodic timer */
  75     QEMUTimer *periodic_timer;
  76     int64_t next_periodic_time;
  77     /* update-ended timer */
  78     QEMUTimer *update_timer;
  79     uint64_t next_alarm_time;
  80     uint16_t irq_reinject_on_ack_count;
  81     uint32_t irq_coalesced;
  82     uint32_t period;
  83     QEMUTimer *coalesced_timer;
  84     Notifier clock_reset_notifier;
  85     LostTickPolicy lost_tick_policy;
  86     Notifier suspend_notifier;
  87 } RTCState;
  88
  89 static void rtc_set_time(RTCState *s);
  90 static void rtc_update_time(RTCState *s);
  91 static void rtc_set_cmos(RTCState *s, const struct tm *tm);
  92 static inline int rtc_from_bcd(RTCState *s, int a);
  93 static uint64_t get_next_alarm(RTCState *s);
  94
  95 static inline bool rtc_running(RTCState *s)
  96 {
  97     return (!(s->cmos_data[RTC_REG_B] & REG_B_SET) &&
  98             (s->cmos_data[RTC_REG_A] & 0x70) <= 0x20);
  99 }
 100
 101 static uint64_t get_guest_rtc_ns(RTCState *s)
 102 {
 103     uint64_t guest_rtc;
 104     uint64_t guest_clock = qemu_clock_get_ns(rtc_clock);
 105
 106     guest_rtc = s->base_rtc * NSEC_PER_SEC
 107                  + guest_clock - s->last_update + s->offset;
 108     return guest_rtc;
 109 }
 110
 111 #ifdef TARGET_I386
 112 static void rtc_coalesced_timer_update(RTCState *s)
 113 {
 114     if (s->irq_coalesced == 0) {
 115         timer_del(s->coalesced_timer);
 116     } else {
 117         /* divide each RTC interval to 2 - 8 smaller intervals */
 118         int c = MIN(s->irq_coalesced, 7) + 1;
 119         int64_t next_clock = qemu_clock_get_ns(rtc_clock) +
 120             muldiv64(s->period / c, get_ticks_per_sec(), RTC_CLOCK_RATE);
 121         timer_mod(s->coalesced_timer, next_clock);
 122     }
 123 }
 124
 125 static void rtc_coalesced_timer(void *opaque)
 126 {
 127     RTCState *s = opaque;
 128
 129     if (s->irq_coalesced != 0) {
 130         apic_reset_irq_delivered();
 131         s->cmos_data[RTC_REG_C] |= 0xc0;
 132         DPRINTF_C("cmos: injecting from timer\n");
 133         qemu_irq_raise(s->irq);
 134         if (apic_get_irq_delivered()) {
 135             s->irq_coalesced--;
 136             DPRINTF_C("cmos: coalesced irqs decreased to %d\n",
 137                       s->irq_coalesced);
 138         }
 139     }
 140
 141     rtc_coalesced_timer_update(s);
 142 }
 143 #endif
 144
 145 /* handle periodic timer */
 146 static void periodic_timer_update(RTCState *s, int64_t current_time)
 147 {
 148     int period_code, period;
 149     int64_t cur_clock, next_irq_clock;
 150
 151     period_code = s->cmos_data[RTC_REG_A] & 0x0f;
 152     if (period_code != 0
 153         && (s->cmos_data[RTC_REG_B] & REG_B_PIE)) {
 154         if (period_code <= 2)
 155             period_code += 7;
 156         /* period in 32 Khz cycles */
 157         period = 1 << (period_code - 1);
 158 #ifdef TARGET_I386
 159         if (period != s->period) {
 160             s->irq_coalesced = (s->irq_coalesced * s->period) / period;
 161             DPRINTF_C("cmos: coalesced irqs scaled to %d\n", s->irq_coalesced);
 162         }
 163         s->period = period;
 164 #endif
 165         /* compute 32 khz clock */
 166         cur_clock = muldiv64(current_time, RTC_CLOCK_RATE, get_ticks_per_sec());
 167         next_irq_clock = (cur_clock & ~(period - 1)) + period;
 168         s->next_periodic_time =
 169             muldiv64(next_irq_clock, get_ticks_per_sec(), RTC_CLOCK_RATE) + 1;
 170         timer_mod(s->periodic_timer, s->next_periodic_time);
 171     } else {
 172 #ifdef TARGET_I386
 173         s->irq_coalesced = 0;
 174 #endif
 175         timer_del(s->periodic_timer);
 176     }
 177 }
 178
 179 static void rtc_periodic_timer(void *opaque)
 180 {
 181     RTCState *s = opaque;
 182
 183     periodic_timer_update(s, s->next_periodic_time);
 184     s->cmos_data[RTC_REG_C] |= REG_C_PF;
 185     if (s->cmos_data[RTC_REG_B] & REG_B_PIE) {
 186         s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
 187 #ifdef TARGET_I386
 188         if (s->lost_tick_policy == LOST_TICK_SLEW) {
 189             if (s->irq_reinject_on_ack_count >= RTC_REINJECT_ON_ACK_COUNT)
 190                 s->irq_reinject_on_ack_count = 0;
 191             apic_reset_irq_delivered();
 192             qemu_irq_raise(s->irq);
 193             if (!apic_get_irq_delivered()) {
 194                 s->irq_coalesced++;
 195                 rtc_coalesced_timer_update(s);
 196                 DPRINTF_C("cmos: coalesced irqs increased to %d\n",
 197                           s->irq_coalesced);
 198             }
 199         } else
 200 #endif
 201         qemu_irq_raise(s->irq);
 202     }
 203 }
 204
 205 /* handle update-ended timer */
 206 static void check_update_timer(RTCState *s)
 207 {
 208     uint64_t next_update_time;
 209     uint64_t guest_nsec;
 210     int next_alarm_sec;
 211
 212     /* From the data sheet: "Holding the dividers in reset prevents
 213      * interrupts from operating, while setting the SET bit allows"
 214      * them to occur.  However, it will prevent an alarm interrupt
 215      * from occurring, because the time of day is not updated.
 216      */
 217     if ((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) {
 218         timer_del(s->update_timer);
 219         return;
 220     }
 221     if ((s->cmos_data[RTC_REG_C] & REG_C_UF) &&
 222         (s->cmos_data[RTC_REG_B] & REG_B_SET)) {
 223         timer_del(s->update_timer);
 224         return;
 225     }
 226     if ((s->cmos_data[RTC_REG_C] & REG_C_UF) &&
 227         (s->cmos_data[RTC_REG_C] & REG_C_AF)) {
 228         timer_del(s->update_timer);
 229         return;
 230     }
 231
 232     guest_nsec = get_guest_rtc_ns(s) % NSEC_PER_SEC;
 233     /* if UF is clear, reprogram to next second */
 234     next_update_time = qemu_clock_get_ns(rtc_clock)
 235         + NSEC_PER_SEC - guest_nsec;
 236
 237     /* Compute time of next alarm.  One second is already accounted
 238      * for in next_update_time.
 239      */
 240     next_alarm_sec = get_next_alarm(s);
 241     s->next_alarm_time = next_update_time + (next_alarm_sec - 1) * NSEC_PER_SEC;
 242
 243     if (s->cmos_data[RTC_REG_C] & REG_C_UF) {
 244         /* UF is set, but AF is clear.  Program the timer to target
 245          * the alarm time.  */
 246         next_update_time = s->next_alarm_time;
 247     }
 248     if (next_update_time != timer_expire_time_ns(s->update_timer)) {
 249         timer_mod(s->update_timer, next_update_time);
 250     }
 251 }
 252
 253 static inline uint8_t convert_hour(RTCState *s, uint8_t hour)
 254 {
 255     if (!(s->cmos_data[RTC_REG_B] & REG_B_24H)) {
 256         hour %= 12;
 257         if (s->cmos_data[RTC_HOURS] & 0x80) {
 258             hour += 12;
 259         }
 260     }
 261     return hour;
 262 }
 263
 264 static uint64_t get_next_alarm(RTCState *s)
 265 {
 266     int32_t alarm_sec, alarm_min, alarm_hour, cur_hour, cur_min, cur_sec;
 267     int32_t hour, min, sec;
 268
 269     rtc_update_time(s);
 270
 271     alarm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS_ALARM]);
 272     alarm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES_ALARM]);
 273     alarm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS_ALARM]);
 274     alarm_hour = alarm_hour == -1 ? -1 : convert_hour(s, alarm_hour);
 275
 276     cur_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]);
 277     cur_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]);
 278     cur_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS]);
 279     cur_hour = convert_hour(s, cur_hour);
 280
 281     if (alarm_hour == -1) {
 282         alarm_hour = cur_hour;
 283         if (alarm_min == -1) {
 284             alarm_min = cur_min;
 285             if (alarm_sec == -1) {
 286                 alarm_sec = cur_sec + 1;
 287             } else if (cur_sec > alarm_sec) {
 288                 alarm_min++;
 289             }
 290         } else if (cur_min == alarm_min) {
 291             if (alarm_sec == -1) {
 292                 alarm_sec = cur_sec + 1;
 293             } else {
 294                 if (cur_sec > alarm_sec) {
 295                     alarm_hour++;
 296                 }
 297             }
 298             if (alarm_sec == SEC_PER_MIN) {
 299                 /* wrap to next hour, minutes is not in don't care mode */
 300                 alarm_sec = 0;
 301                 alarm_hour++;
 302             }
 303         } else if (cur_min > alarm_min) {
 304             alarm_hour++;
 305         }
 306     } else if (cur_hour == alarm_hour) {
 307         if (alarm_min == -1) {
 308             alarm_min = cur_min;
 309             if (alarm_sec == -1) {
 310                 alarm_sec = cur_sec + 1;
 311             } else if (cur_sec > alarm_sec) {
 312                 alarm_min++;
 313             }
 314
 315             if (alarm_sec == SEC_PER_MIN) {
 316                 alarm_sec = 0;
 317                 alarm_min++;
 318             }
 319             /* wrap to next day, hour is not in don't care mode */
 320             alarm_min %= MIN_PER_HOUR;
 321         } else if (cur_min == alarm_min) {
 322             if (alarm_sec == -1) {
 323                 alarm_sec = cur_sec + 1;
 324             }
 325             /* wrap to next day, hours+minutes not in don't care mode */
 326             alarm_sec %= SEC_PER_MIN;
 327         }
 328     }
 329
 330     /* values that are still don't care fire at the next min/sec */
 331     if (alarm_min == -1) {
 332         alarm_min = 0;
 333     }
 334     if (alarm_sec == -1) {
 335         alarm_sec = 0;
 336     }
 337
 338     /* keep values in range */
 339     if (alarm_sec == SEC_PER_MIN) {
 340         alarm_sec = 0;
 341         alarm_min++;
 342     }
 343     if (alarm_min == MIN_PER_HOUR) {
 344         alarm_min = 0;
 345         alarm_hour++;
 346     }
 347     alarm_hour %= HOUR_PER_DAY;
 348
 349     hour = alarm_hour - cur_hour;
 350     min = hour * MIN_PER_HOUR + alarm_min - cur_min;
 351     sec = min * SEC_PER_MIN + alarm_sec - cur_sec;
 352     return sec <= 0 ? sec + SEC_PER_DAY : sec;
 353 }
 354
 355 static void rtc_update_timer(void *opaque)
 356 {
 357     RTCState *s = opaque;
 358     int32_t irqs = REG_C_UF;
 359     int32_t new_irqs;
 360
 361     assert((s->cmos_data[RTC_REG_A] & 0x60) != 0x60);
 362
 363     /* UIP might have been latched, update time and clear it.  */
 364     rtc_update_time(s);
 365     s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 366
 367     if (qemu_clock_get_ns(rtc_clock) >= s->next_alarm_time) {
 368         irqs |= REG_C_AF;
 369         if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
 370             qemu_system_wakeup_request(QEMU_WAKEUP_REASON_RTC);
 371         }
 372     }
 373
 374     new_irqs = irqs & ~s->cmos_data[RTC_REG_C];
 375     s->cmos_data[RTC_REG_C] |= irqs;
 376     if ((new_irqs & s->cmos_data[RTC_REG_B]) != 0) {
 377         s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
 378         qemu_irq_raise(s->irq);
 379     }
 380     check_update_timer(s);
 381 }
 382
 383 static void cmos_ioport_write(void *opaque, hwaddr addr,
 384                               uint64_t data, unsigned size)
 385 {
 386     RTCState *s = opaque;
 387
 388     if ((addr & 1) == 0) {
 389         s->cmos_index = data & 0x7f;
 390     } else {
 391         CMOS_DPRINTF("cmos: write index=0x%02x val=0x%02x\n",
 392                      s->cmos_index, data);
 393         switch(s->cmos_index) {
 394         case RTC_SECONDS_ALARM:
 395         case RTC_MINUTES_ALARM:
 396         case RTC_HOURS_ALARM:
 397             s->cmos_data[s->cmos_index] = data;
 398             check_update_timer(s);
 399             break;
 400         case RTC_IBM_PS2_CENTURY_BYTE:
 401             s->cmos_index = RTC_CENTURY;
 402             /* fall through */
 403         case RTC_CENTURY:
 404         case RTC_SECONDS:
 405         case RTC_MINUTES:
 406         case RTC_HOURS:
 407         case RTC_DAY_OF_WEEK:
 408         case RTC_DAY_OF_MONTH:
 409         case RTC_MONTH:
 410         case RTC_YEAR:
 411             s->cmos_data[s->cmos_index] = data;
 412             /* if in set mode, do not update the time */
 413             if (rtc_running(s)) {
 414                 rtc_set_time(s);
 415                 check_update_timer(s);
 416             }
 417             break;
 418         case RTC_REG_A:
 419             if ((data & 0x60) == 0x60) {
 420                 if (rtc_running(s)) {
 421                     rtc_update_time(s);
 422                 }
 423                 /* What happens to UIP when divider reset is enabled is
 424                  * unclear from the datasheet.  Shouldn't matter much
 425                  * though.
 426                  */
 427                 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 428             } else if (((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) &&
 429                     (data & 0x70)  <= 0x20) {
 430                 /* when the divider reset is removed, the first update cycle
 431                  * begins one-half second later*/
 432                 if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
 433                     s->offset = 500000000;
 434                     rtc_set_time(s);
 435                 }
 436                 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 437             }
 438             /* UIP bit is read only */
 439             s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) |
 440                 (s->cmos_data[RTC_REG_A] & REG_A_UIP);
 441             periodic_timer_update(s, qemu_clock_get_ns(rtc_clock));
 442             check_update_timer(s);
 443             break;
 444         case RTC_REG_B:
 445             if (data & REG_B_SET) {
 446                 /* update cmos to when the rtc was stopping */
 447                 if (rtc_running(s)) {
 448                     rtc_update_time(s);
 449                 }
 450                 /* set mode: reset UIP mode */
 451                 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 452                 data &= ~REG_B_UIE;
 453             } else {
 454                 /* if disabling set mode, update the time */
 455                 if ((s->cmos_data[RTC_REG_B] & REG_B_SET) &&
 456                     (s->cmos_data[RTC_REG_A] & 0x70) <= 0x20) {
 457                     s->offset = get_guest_rtc_ns(s) % NSEC_PER_SEC;
 458                     rtc_set_time(s);
 459                 }
 460             }
 461             /* if an interrupt flag is already set when the interrupt
 462              * becomes enabled, raise an interrupt immediately.  */
 463             if (data & s->cmos_data[RTC_REG_C] & REG_C_MASK) {
 464                 s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
 465                 qemu_irq_raise(s->irq);
 466             } else {
 467                 s->cmos_data[RTC_REG_C] &= ~REG_C_IRQF;
 468                 qemu_irq_lower(s->irq);
 469             }
 470             s->cmos_data[RTC_REG_B] = data;
 471             periodic_timer_update(s, qemu_clock_get_ns(rtc_clock));
 472             check_update_timer(s);
 473             break;
 474         case RTC_REG_C:
 475         case RTC_REG_D:
 476             /* cannot write to them */
 477             break;
 478         default:
 479             s->cmos_data[s->cmos_index] = data;
 480             break;
 481         }
 482     }
 483 }
 484
 485 static inline int rtc_to_bcd(RTCState *s, int a)
 486 {
 487     if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
 488         return a;
 489     } else {
 490         return ((a / 10) << 4) | (a % 10);
 491     }
 492 }
 493
 494 static inline int rtc_from_bcd(RTCState *s, int a)
 495 {
 496     if ((a & 0xc0) == 0xc0) {
 497         return -1;
 498     }
 499     if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
 500         return a;
 501     } else {
 502         return ((a >> 4) * 10) + (a & 0x0f);
 503     }
 504 }
 505
 506 static void rtc_get_time(RTCState *s, struct tm *tm)
 507 {
 508     tm->tm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]);
 509     tm->tm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]);
 510     tm->tm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
 511     if (!(s->cmos_data[RTC_REG_B] & REG_B_24H)) {
 512         tm->tm_hour %= 12;
 513         if (s->cmos_data[RTC_HOURS] & 0x80) {
 514             tm->tm_hour += 12;
 515         }
 516     }
 517     tm->tm_wday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1;
 518     tm->tm_mday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]);
 519     tm->tm_mon = rtc_from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
 520     tm->tm_year =
 521         rtc_from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year +
 522         rtc_from_bcd(s, s->cmos_data[RTC_CENTURY]) * 100 - 1900;
 523 }
 524
 525 static void rtc_set_time(RTCState *s)
 526 {
 527     struct tm tm;
 528
 529     rtc_get_time(s, &tm);
 530     s->base_rtc = mktimegm(&tm);
 531     s->last_update = qemu_clock_get_ns(rtc_clock);
 532
 533     rtc_change_mon_event(&tm);
 534 }
 535
 536 static void rtc_set_cmos(RTCState *s, const struct tm *tm)
 537 {
 538     int year;
 539
 540     s->cmos_data[RTC_SECONDS] = rtc_to_bcd(s, tm->tm_sec);
 541     s->cmos_data[RTC_MINUTES] = rtc_to_bcd(s, tm->tm_min);
 542     if (s->cmos_data[RTC_REG_B] & REG_B_24H) {
 543         /* 24 hour format */
 544         s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour);
 545     } else {
 546         /* 12 hour format */
 547         int h = (tm->tm_hour % 12) ? tm->tm_hour % 12 : 12;
 548         s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, h);
 549         if (tm->tm_hour >= 12)
 550             s->cmos_data[RTC_HOURS] |= 0x80;
 551     }
 552     s->cmos_data[RTC_DAY_OF_WEEK] = rtc_to_bcd(s, tm->tm_wday + 1);
 553     s->cmos_data[RTC_DAY_OF_MONTH] = rtc_to_bcd(s, tm->tm_mday);
 554     s->cmos_data[RTC_MONTH] = rtc_to_bcd(s, tm->tm_mon + 1);
 555     year = tm->tm_year + 1900 - s->base_year;
 556     s->cmos_data[RTC_YEAR] = rtc_to_bcd(s, year % 100);
 557     s->cmos_data[RTC_CENTURY] = rtc_to_bcd(s, year / 100);
 558 }
 559
 560 static void rtc_update_time(RTCState *s)
 561 {
 562     struct tm ret;
 563     time_t guest_sec;
 564     int64_t guest_nsec;
 565
 566     guest_nsec = get_guest_rtc_ns(s);
 567     guest_sec = guest_nsec / NSEC_PER_SEC;
 568     gmtime_r(&guest_sec, &ret);
 569
 570     /* Is SET flag of Register B disabled? */
 571     if ((s->cmos_data[RTC_REG_B] & REG_B_SET) == 0) {
 572         rtc_set_cmos(s, &ret);
 573     }
 574 }
 575
 576 static int update_in_progress(RTCState *s)
 577 {
 578     int64_t guest_nsec;
 579
 580     if (!rtc_running(s)) {
 581         return 0;
 582     }
 583     if (timer_pending(s->update_timer)) {
 584         int64_t next_update_time = timer_expire_time_ns(s->update_timer);
 585         /* Latch UIP until the timer expires.  */
 586         if (qemu_clock_get_ns(rtc_clock) >=
 587             (next_update_time - UIP_HOLD_LENGTH)) {
 588             s->cmos_data[RTC_REG_A] |= REG_A_UIP;
 589             return 1;
 590         }
 591     }
 592
 593     guest_nsec = get_guest_rtc_ns(s);
 594     /* UIP bit will be set at last 244us of every second. */
 595     if ((guest_nsec % NSEC_PER_SEC) >= (NSEC_PER_SEC - UIP_HOLD_LENGTH)) {
 596         return 1;
 597     }
 598     return 0;
 599 }
 600
 601 static uint64_t cmos_ioport_read(void *opaque, hwaddr addr,
 602                                  unsigned size)
 603 {
 604     RTCState *s = opaque;
 605     int ret;
 606     if ((addr & 1) == 0) {
 607         return 0xff;
 608     } else {
 609         switch(s->cmos_index) {
 610         case RTC_IBM_PS2_CENTURY_BYTE:
 611             s->cmos_index = RTC_CENTURY;
 612             /* fall through */
 613         case RTC_CENTURY:
 614         case RTC_SECONDS:
 615         case RTC_MINUTES:
 616         case RTC_HOURS:
 617         case RTC_DAY_OF_WEEK:
 618         case RTC_DAY_OF_MONTH:
 619         case RTC_MONTH:
 620         case RTC_YEAR:
 621             /* if not in set mode, calibrate cmos before
 622              * reading*/
 623             if (rtc_running(s)) {
 624                 rtc_update_time(s);
 625             }
 626             ret = s->cmos_data[s->cmos_index];
 627             break;
 628         case RTC_REG_A:
 629             if (update_in_progress(s)) {
 630                 s->cmos_data[s->cmos_index] |= REG_A_UIP;
 631             } else {
 632                 s->cmos_data[s->cmos_index] &= ~REG_A_UIP;
 633             }
 634             ret = s->cmos_data[s->cmos_index];
 635             break;
 636         case RTC_REG_C:
 637             ret = s->cmos_data[s->cmos_index];
 638             qemu_irq_lower(s->irq);
 639             s->cmos_data[RTC_REG_C] = 0x00;
 640             if (ret & (REG_C_UF | REG_C_AF)) {
 641                 check_update_timer(s);
 642             }
 643 #ifdef TARGET_I386
 644             if(s->irq_coalesced &&
 645                     (s->cmos_data[RTC_REG_B] & REG_B_PIE) &&
 646                     s->irq_reinject_on_ack_count < RTC_REINJECT_ON_ACK_COUNT) {
 647                 s->irq_reinject_on_ack_count++;
 648                 s->cmos_data[RTC_REG_C] |= REG_C_IRQF | REG_C_PF;
 649                 apic_reset_irq_delivered();
 650                 DPRINTF_C("cmos: injecting on ack\n");
 651                 qemu_irq_raise(s->irq);
 652                 if (apic_get_irq_delivered()) {
 653                     s->irq_coalesced--;
 654                     DPRINTF_C("cmos: coalesced irqs decreased to %d\n",
 655                               s->irq_coalesced);
 656                 }
 657             }
 658 #endif
 659             break;
 660         default:
 661             ret = s->cmos_data[s->cmos_index];
 662             break;
 663         }
 664         CMOS_DPRINTF("cmos: read index=0x%02x val=0x%02x\n",
 665                      s->cmos_index, ret);
 666         return ret;
 667     }
 668 }
 669
 670 void rtc_set_memory(ISADevice *dev, int addr, int val)
 671 {
 672     RTCState *s = MC146818_RTC(dev);
 673     if (addr >= 0 && addr <= 127)
 674         s->cmos_data[addr] = val;
 675 }
 676
 677 int rtc_get_memory(ISADevice *dev, int addr)
 678 {
 679     RTCState *s = MC146818_RTC(dev);
 680     assert(addr >= 0 && addr <= 127);
 681     return s->cmos_data[addr];
 682 }
 683
 684 static void rtc_set_date_from_host(ISADevice *dev)
 685 {
 686     RTCState *s = MC146818_RTC(dev);
 687     struct tm tm;
 688
 689     qemu_get_timedate(&tm, 0);
 690
 691     s->base_rtc = mktimegm(&tm);
 692     s->last_update = qemu_clock_get_ns(rtc_clock);
 693     s->offset = 0;
 694
 695     /* set the CMOS date */
 696     rtc_set_cmos(s, &tm);
 697 }
 698
 699 static int rtc_post_load(void *opaque, int version_id)
 700 {
 701     RTCState *s = opaque;
 702
 703     if (version_id <= 2) {
 704         rtc_set_time(s);
 705         s->offset = 0;
 706         check_update_timer(s);
 707     }
 708
 709 #ifdef TARGET_I386
 710     if (version_id >= 2) {
 711         if (s->lost_tick_policy == LOST_TICK_SLEW) {
 712             rtc_coalesced_timer_update(s);
 713         }
 714     }
 715 #endif
 716     return 0;
 717 }
 718
 719 static const VMStateDescription vmstate_rtc = {
 720     .name = "mc146818rtc",
 721     .version_id = 3,
 722     .minimum_version_id = 1,
 723     .minimum_version_id_old = 1,
 724     .post_load = rtc_post_load,
 725     .fields      = (VMStateField []) {
 726         VMSTATE_BUFFER(cmos_data, RTCState),
 727         VMSTATE_UINT8(cmos_index, RTCState),
 728         VMSTATE_UNUSED(7*4),
 729         VMSTATE_TIMER(periodic_timer, RTCState),
 730         VMSTATE_INT64(next_periodic_time, RTCState),
 731         VMSTATE_UNUSED(3*8),
 732         VMSTATE_UINT32_V(irq_coalesced, RTCState, 2),
 733         VMSTATE_UINT32_V(period, RTCState, 2),
 734         VMSTATE_UINT64_V(base_rtc, RTCState, 3),
 735         VMSTATE_UINT64_V(last_update, RTCState, 3),
 736         VMSTATE_INT64_V(offset, RTCState, 3),
 737         VMSTATE_TIMER_V(update_timer, RTCState, 3),
 738         VMSTATE_UINT64_V(next_alarm_time, RTCState, 3),
 739         VMSTATE_END_OF_LIST()
 740     }
 741 };
 742
 743 static void rtc_notify_clock_reset(Notifier *notifier, void *data)
 744 {
 745     RTCState *s = container_of(notifier, RTCState, clock_reset_notifier);
 746     int64_t now = *(int64_t *)data;
 747
 748     rtc_set_date_from_host(ISA_DEVICE(s));
 749     periodic_timer_update(s, now);
 750     check_update_timer(s);
 751 #ifdef TARGET_I386
 752     if (s->lost_tick_policy == LOST_TICK_SLEW) {
 753         rtc_coalesced_timer_update(s);
 754     }
 755 #endif
 756 }
 757
 758 /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
 759    BIOS will read it and start S3 resume at POST Entry */
 760 static void rtc_notify_suspend(Notifier *notifier, void *data)
 761 {
 762     RTCState *s = container_of(notifier, RTCState, suspend_notifier);
 763     rtc_set_memory(ISA_DEVICE(s), 0xF, 0xFE);
 764 }
 765
 766 static void rtc_reset(void *opaque)
 767 {
 768     RTCState *s = opaque;
 769
 770     s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE);
 771     s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF);
 772     check_update_timer(s);
 773
 774     qemu_irq_lower(s->irq);
 775
 776 #ifdef TARGET_I386
 777     if (s->lost_tick_policy == LOST_TICK_SLEW) {
 778         s->irq_coalesced = 0;
 779     }
 780 #endif
 781 }
 782
 783 static const MemoryRegionOps cmos_ops = {
 784     .read = cmos_ioport_read,
 785     .write = cmos_ioport_write,
 786     .impl = {
 787         .min_access_size = 1,
 788         .max_access_size = 1,
 789     },
 790     .endianness = DEVICE_LITTLE_ENDIAN,
 791 };
 792
 793 static void rtc_get_date(Object *obj, Visitor *v, void *opaque,
 794                          const char *name, Error **errp)
 795 {
 796     RTCState *s = MC146818_RTC(obj);
 797     struct tm current_tm;
 798
 799     rtc_update_time(s);
 800     rtc_get_time(s, &current_tm);
 801     visit_start_struct(v, NULL, "struct tm", name, 0, errp);
 802     visit_type_int32(v, &current_tm.tm_year, "tm_year", errp);
 803     visit_type_int32(v, &current_tm.tm_mon, "tm_mon", errp);
 804     visit_type_int32(v, &current_tm.tm_mday, "tm_mday", errp);
 805     visit_type_int32(v, &current_tm.tm_hour, "tm_hour", errp);
 806     visit_type_int32(v, &current_tm.tm_min, "tm_min", errp);
 807     visit_type_int32(v, &current_tm.tm_sec, "tm_sec", errp);
 808     visit_end_struct(v, errp);
 809 }
 810
 811 static void rtc_realizefn(DeviceState *dev, Error **errp)
 812 {
 813     ISADevice *isadev = ISA_DEVICE(dev);
 814     RTCState *s = MC146818_RTC(dev);
 815     int base = 0x70;
 816
 817     s->cmos_data[RTC_REG_A] = 0x26;
 818     s->cmos_data[RTC_REG_B] = 0x02;
 819     s->cmos_data[RTC_REG_C] = 0x00;
 820     s->cmos_data[RTC_REG_D] = 0x80;
 821
 822     /* This is for historical reasons.  The default base year qdev property
 823      * was set to 2000 for most machine types before the century byte was
 824      * implemented.
 825      *
 826      * This if statement means that the century byte will be always 0
 827      * (at least until 2079...) for base_year = 1980, but will be set
 828      * correctly for base_year = 2000.
 829      */
 830     if (s->base_year == 2000) {
 831         s->base_year = 0;
 832     }
 833
 834     rtc_set_date_from_host(isadev);
 835
 836 #ifdef TARGET_I386
 837     switch (s->lost_tick_policy) {
 838     case LOST_TICK_SLEW:
 839         s->coalesced_timer =
 840             timer_new_ns(rtc_clock, rtc_coalesced_timer, s);
 841         break;
 842     case LOST_TICK_DISCARD:
 843         break;
 844     default:
 845         error_setg(errp, "Invalid lost tick policy.");
 846         return;
 847     }
 848 #endif
 849
 850     s->periodic_timer = timer_new_ns(rtc_clock, rtc_periodic_timer, s);
 851     s->update_timer = timer_new_ns(rtc_clock, rtc_update_timer, s);
 852     check_update_timer(s);
 853
 854     s->clock_reset_notifier.notify = rtc_notify_clock_reset;
 855     qemu_clock_register_reset_notifier(QEMU_CLOCK_REALTIME,
 856                                        &s->clock_reset_notifier);
 857
 858     s->suspend_notifier.notify = rtc_notify_suspend;
 859     qemu_register_suspend_notifier(&s->suspend_notifier);
 860
 861     memory_region_init_io(&s->io, OBJECT(s), &cmos_ops, s, "rtc", 2);
 862     isa_register_ioport(isadev, &s->io, base);
 863
 864     qdev_set_legacy_instance_id(dev, base, 3);
 865     qemu_register_reset(rtc_reset, s);
 866
 867     object_property_add(OBJECT(s), "date", "struct tm",
 868                         rtc_get_date, NULL, NULL, s, NULL);
 869 }
 870
 871 ISADevice *rtc_init(ISABus *bus, int base_year, qemu_irq intercept_irq)
 872 {
 873     DeviceState *dev;
 874     ISADevice *isadev;
 875     RTCState *s;
 876
 877     isadev = isa_create(bus, TYPE_MC146818_RTC);
 878     dev = DEVICE(isadev);
 879     s = MC146818_RTC(isadev);
 880     qdev_prop_set_int32(dev, "base_year", base_year);
 881     qdev_init_nofail(dev);
 882     if (intercept_irq) {
 883         s->irq = intercept_irq;
 884     } else {
 885         isa_init_irq(isadev, &s->irq, RTC_ISA_IRQ);
 886     }
 887     return isadev;
 888 }
 889
 890 static Property mc146818rtc_properties[] = {
 891     DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980),
 892     DEFINE_PROP_LOSTTICKPOLICY("lost_tick_policy", RTCState,
 893                                lost_tick_policy, LOST_TICK_DISCARD),
 894     DEFINE_PROP_END_OF_LIST(),
 895 };
 896
 897 static void rtc_class_initfn(ObjectClass *klass, void *data)
 898 {
 899     DeviceClass *dc = DEVICE_CLASS(klass);
 900
 901     dc->realize = rtc_realizefn;
 902     dc->no_user = 1;
 903     dc->vmsd = &vmstate_rtc;
 904     dc->props = mc146818rtc_properties;
 905 }
 906
 907 static const TypeInfo mc146818rtc_info = {
 908     .name          = TYPE_MC146818_RTC,
 909     .parent        = TYPE_ISA_DEVICE,
 910     .instance_size = sizeof(RTCState),
 911     .class_init    = rtc_class_initfn,
 912 };
 913
 914 static void mc146818rtc_register_types(void)
 915 {
 916     type_register_static(&mc146818rtc_info);
 917 }
 918
 919 type_init(mc146818rtc_register_types)