2 * QEMU VMWARE VMXNET3 paravirtual NIC
4 * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com)
6 * Developed by Daynix Computing LTD (http://www.daynix.com)
9 * Dmitry Fleytman <dmitry@daynix.com>
10 * Tamir Shomer <tamirs@daynix.com>
11 * Yan Vugenfirer <yan@daynix.com>
13 * This work is licensed under the terms of the GNU GPL, version 2.
14 * See the COPYING file in the top-level directory.
19 #include "hw/pci/pci.h"
22 #include "net/checksum.h"
23 #include "sysemu/sysemu.h"
24 #include "qemu-common.h"
25 #include "qemu/bswap.h"
26 #include "hw/pci/msix.h"
27 #include "hw/pci/msi.h"
30 #include "vmxnet_debug.h"
31 #include "vmware_utils.h"
32 #include "vmxnet_tx_pkt.h"
33 #include "vmxnet_rx_pkt.h"
35 #define PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION 0x1
36 #define VMXNET3_MSIX_BAR_SIZE 0x2000
38 #define VMXNET3_BAR0_IDX (0)
39 #define VMXNET3_BAR1_IDX (1)
40 #define VMXNET3_MSIX_BAR_IDX (2)
42 #define VMXNET3_OFF_MSIX_TABLE (0x000)
43 #define VMXNET3_OFF_MSIX_PBA (0x800)
45 /* Link speed in Mbps should be shifted by 16 */
46 #define VMXNET3_LINK_SPEED (1000 << 16)
48 /* Link status: 1 - up, 0 - down. */
49 #define VMXNET3_LINK_STATUS_UP 0x1
51 /* Least significant bit should be set for revision and version */
52 #define VMXNET3_DEVICE_VERSION 0x1
53 #define VMXNET3_DEVICE_REVISION 0x1
55 /* Macros for rings descriptors access */
56 #define VMXNET3_READ_TX_QUEUE_DESCR8(dpa, field) \
57 (vmw_shmem_ld8(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
59 #define VMXNET3_WRITE_TX_QUEUE_DESCR8(dpa, field, value) \
60 (vmw_shmem_st8(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field, value)))
62 #define VMXNET3_READ_TX_QUEUE_DESCR32(dpa, field) \
63 (vmw_shmem_ld32(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
65 #define VMXNET3_WRITE_TX_QUEUE_DESCR32(dpa, field, value) \
66 (vmw_shmem_st32(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value))
68 #define VMXNET3_READ_TX_QUEUE_DESCR64(dpa, field) \
69 (vmw_shmem_ld64(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
71 #define VMXNET3_WRITE_TX_QUEUE_DESCR64(dpa, field, value) \
72 (vmw_shmem_st64(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value))
74 #define VMXNET3_READ_RX_QUEUE_DESCR64(dpa, field) \
75 (vmw_shmem_ld64(dpa + offsetof(struct Vmxnet3_RxQueueDesc, field)))
77 #define VMXNET3_READ_RX_QUEUE_DESCR32(dpa, field) \
78 (vmw_shmem_ld32(dpa + offsetof(struct Vmxnet3_RxQueueDesc, field)))
80 #define VMXNET3_WRITE_RX_QUEUE_DESCR64(dpa, field, value) \
81 (vmw_shmem_st64(dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value))
83 #define VMXNET3_WRITE_RX_QUEUE_DESCR8(dpa, field, value) \
84 (vmw_shmem_st8(dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value))
86 /* Macros for guest driver shared area access */
87 #define VMXNET3_READ_DRV_SHARED64(shpa, field) \
88 (vmw_shmem_ld64(shpa + offsetof(struct Vmxnet3_DriverShared, field)))
90 #define VMXNET3_READ_DRV_SHARED32(shpa, field) \
91 (vmw_shmem_ld32(shpa + offsetof(struct Vmxnet3_DriverShared, field)))
93 #define VMXNET3_WRITE_DRV_SHARED32(shpa, field, val) \
94 (vmw_shmem_st32(shpa + offsetof(struct Vmxnet3_DriverShared, field), val))
96 #define VMXNET3_READ_DRV_SHARED16(shpa, field) \
97 (vmw_shmem_ld16(shpa + offsetof(struct Vmxnet3_DriverShared, field)))
99 #define VMXNET3_READ_DRV_SHARED8(shpa, field) \
100 (vmw_shmem_ld8(shpa + offsetof(struct Vmxnet3_DriverShared, field)))
102 #define VMXNET3_READ_DRV_SHARED(shpa, field, b, l) \
103 (vmw_shmem_read(shpa + offsetof(struct Vmxnet3_DriverShared, field), b, l))
105 #define VMXNET_FLAG_IS_SET(field, flag) (((field) & (flag)) == (flag))
107 #define TYPE_VMXNET3 "vmxnet3"
108 #define VMXNET3(obj) OBJECT_CHECK(VMXNET3State, (obj), TYPE_VMXNET3)
110 /* Cyclic ring abstraction */
119 static inline void vmxnet3_ring_init(Vmxnet3Ring
*ring
,
127 ring
->cell_size
= cell_size
;
128 ring
->gen
= VMXNET3_INIT_GEN
;
132 vmw_shmem_set(pa
, 0, size
* cell_size
);
136 #define VMXNET3_RING_DUMP(macro, ring_name, ridx, r) \
137 macro("%s#%d: base %" PRIx64 " size %lu cell_size %lu gen %d next %lu", \
138 (ring_name), (ridx), \
139 (r)->pa, (r)->size, (r)->cell_size, (r)->gen, (r)->next)
141 static inline void vmxnet3_ring_inc(Vmxnet3Ring
*ring
)
143 if (++ring
->next
>= ring
->size
) {
149 static inline void vmxnet3_ring_dec(Vmxnet3Ring
*ring
)
151 if (ring
->next
-- == 0) {
152 ring
->next
= ring
->size
- 1;
157 static inline hwaddr
vmxnet3_ring_curr_cell_pa(Vmxnet3Ring
*ring
)
159 return ring
->pa
+ ring
->next
* ring
->cell_size
;
162 static inline void vmxnet3_ring_read_curr_cell(Vmxnet3Ring
*ring
, void *buff
)
164 vmw_shmem_read(vmxnet3_ring_curr_cell_pa(ring
), buff
, ring
->cell_size
);
167 static inline void vmxnet3_ring_write_curr_cell(Vmxnet3Ring
*ring
, void *buff
)
169 vmw_shmem_write(vmxnet3_ring_curr_cell_pa(ring
), buff
, ring
->cell_size
);
172 static inline size_t vmxnet3_ring_curr_cell_idx(Vmxnet3Ring
*ring
)
177 static inline uint8_t vmxnet3_ring_curr_gen(Vmxnet3Ring
*ring
)
182 /* Debug trace-related functions */
184 vmxnet3_dump_tx_descr(struct Vmxnet3_TxDesc
*descr
)
186 VMW_PKPRN("TX DESCR: "
187 "addr %" PRIx64
", len: %d, gen: %d, rsvd: %d, "
188 "dtype: %d, ext1: %d, msscof: %d, hlen: %d, om: %d, "
189 "eop: %d, cq: %d, ext2: %d, ti: %d, tci: %d",
190 le64_to_cpu(descr
->addr
), descr
->len
, descr
->gen
, descr
->rsvd
,
191 descr
->dtype
, descr
->ext1
, descr
->msscof
, descr
->hlen
, descr
->om
,
192 descr
->eop
, descr
->cq
, descr
->ext2
, descr
->ti
, descr
->tci
);
196 vmxnet3_dump_virt_hdr(struct virtio_net_hdr
*vhdr
)
198 VMW_PKPRN("VHDR: flags 0x%x, gso_type: 0x%x, hdr_len: %d, gso_size: %d, "
199 "csum_start: %d, csum_offset: %d",
200 vhdr
->flags
, vhdr
->gso_type
, vhdr
->hdr_len
, vhdr
->gso_size
,
201 vhdr
->csum_start
, vhdr
->csum_offset
);
205 vmxnet3_dump_rx_descr(struct Vmxnet3_RxDesc
*descr
)
207 VMW_PKPRN("RX DESCR: addr %" PRIx64
", len: %d, gen: %d, rsvd: %d, "
208 "dtype: %d, ext1: %d, btype: %d",
209 le64_to_cpu(descr
->addr
), descr
->len
, descr
->gen
,
210 descr
->rsvd
, descr
->dtype
, descr
->ext1
, descr
->btype
);
213 /* Device state and helper functions */
214 #define VMXNET3_RX_RINGS_PER_QUEUE (2)
218 Vmxnet3Ring comp_ring
;
222 struct UPT1_TxStats txq_stats
;
226 Vmxnet3Ring rx_ring
[VMXNET3_RX_RINGS_PER_QUEUE
];
227 Vmxnet3Ring comp_ring
;
230 struct UPT1_RxStats rxq_stats
;
240 PCIDevice parent_obj
;
245 MemoryRegion msix_bar
;
247 Vmxnet3RxqDescr rxq_descr
[VMXNET3_DEVICE_MAX_RX_QUEUES
];
248 Vmxnet3TxqDescr txq_descr
[VMXNET3_DEVICE_MAX_TX_QUEUES
];
250 /* Whether MSI-X support was installed successfully */
252 /* Whether MSI support was installed successfully */
255 hwaddr temp_shared_guest_driver_memory
;
259 /* This boolean tells whether RX packet being indicated has to */
260 /* be split into head and body chunks from different RX rings */
261 bool rx_packets_compound
;
263 bool rx_vlan_stripping
;
271 /* Maximum number of fragments for indicated TX packets */
272 uint32_t max_tx_frags
;
274 /* Maximum number of fragments for indicated RX packets */
275 uint16_t max_rx_frags
;
277 /* Index for events interrupt */
278 uint8_t event_int_idx
;
280 /* Whether automatic interrupts masking enabled */
281 bool auto_int_masking
;
285 /* TX packets to QEMU interface */
286 struct VmxnetTxPkt
*tx_pkt
;
287 uint32_t offload_mode
;
288 uint32_t cso_or_gso_size
;
292 struct VmxnetRxPkt
*rx_pkt
;
295 bool skip_current_tx_pkt
;
297 uint32_t device_active
;
298 uint32_t last_command
;
300 uint32_t link_status_and_speed
;
302 Vmxnet3IntState interrupt_states
[VMXNET3_MAX_INTRS
];
304 uint32_t temp_mac
; /* To store the low part first */
307 uint32_t vlan_table
[VMXNET3_VFT_SIZE
];
310 uint32_t mcast_list_len
;
311 uint32_t mcast_list_buff_size
; /* needed for live migration. */
314 /* Interrupt management */
317 *This function returns sign whether interrupt line is in asserted state
318 * This depends on the type of interrupt used. For INTX interrupt line will
319 * be asserted until explicit deassertion, for MSI(X) interrupt line will
320 * be deasserted automatically due to notification semantics of the MSI(X)
323 static bool _vmxnet3_assert_interrupt_line(VMXNET3State
*s
, uint32_t int_idx
)
325 PCIDevice
*d
= PCI_DEVICE(s
);
327 if (s
->msix_used
&& msix_enabled(d
)) {
328 VMW_IRPRN("Sending MSI-X notification for vector %u", int_idx
);
329 msix_notify(d
, int_idx
);
332 if (s
->msi_used
&& msi_enabled(d
)) {
333 VMW_IRPRN("Sending MSI notification for vector %u", int_idx
);
334 msi_notify(d
, int_idx
);
338 VMW_IRPRN("Asserting line for interrupt %u", int_idx
);
339 qemu_set_irq(d
->irq
[int_idx
], 1);
343 static void _vmxnet3_deassert_interrupt_line(VMXNET3State
*s
, int lidx
)
345 PCIDevice
*d
= PCI_DEVICE(s
);
348 * This function should never be called for MSI(X) interrupts
349 * because deassertion never required for message interrupts
351 assert(!s
->msix_used
|| !msix_enabled(d
));
353 * This function should never be called for MSI(X) interrupts
354 * because deassertion never required for message interrupts
356 assert(!s
->msi_used
|| !msi_enabled(d
));
358 VMW_IRPRN("Deasserting line for interrupt %u", lidx
);
359 qemu_set_irq(d
->irq
[lidx
], 0);
362 static void vmxnet3_update_interrupt_line_state(VMXNET3State
*s
, int lidx
)
364 if (!s
->interrupt_states
[lidx
].is_pending
&&
365 s
->interrupt_states
[lidx
].is_asserted
) {
366 VMW_IRPRN("New interrupt line state for index %d is DOWN", lidx
);
367 _vmxnet3_deassert_interrupt_line(s
, lidx
);
368 s
->interrupt_states
[lidx
].is_asserted
= false;
372 if (s
->interrupt_states
[lidx
].is_pending
&&
373 !s
->interrupt_states
[lidx
].is_masked
&&
374 !s
->interrupt_states
[lidx
].is_asserted
) {
375 VMW_IRPRN("New interrupt line state for index %d is UP", lidx
);
376 s
->interrupt_states
[lidx
].is_asserted
=
377 _vmxnet3_assert_interrupt_line(s
, lidx
);
378 s
->interrupt_states
[lidx
].is_pending
= false;
383 static void vmxnet3_trigger_interrupt(VMXNET3State
*s
, int lidx
)
385 PCIDevice
*d
= PCI_DEVICE(s
);
386 s
->interrupt_states
[lidx
].is_pending
= true;
387 vmxnet3_update_interrupt_line_state(s
, lidx
);
389 if (s
->msix_used
&& msix_enabled(d
) && s
->auto_int_masking
) {
393 if (s
->msi_used
&& msi_enabled(d
) && s
->auto_int_masking
) {
400 s
->interrupt_states
[lidx
].is_masked
= true;
401 vmxnet3_update_interrupt_line_state(s
, lidx
);
404 static bool vmxnet3_interrupt_asserted(VMXNET3State
*s
, int lidx
)
406 return s
->interrupt_states
[lidx
].is_asserted
;
409 static void vmxnet3_clear_interrupt(VMXNET3State
*s
, int int_idx
)
411 s
->interrupt_states
[int_idx
].is_pending
= false;
412 if (s
->auto_int_masking
) {
413 s
->interrupt_states
[int_idx
].is_masked
= true;
415 vmxnet3_update_interrupt_line_state(s
, int_idx
);
419 vmxnet3_on_interrupt_mask_changed(VMXNET3State
*s
, int lidx
, bool is_masked
)
421 s
->interrupt_states
[lidx
].is_masked
= is_masked
;
422 vmxnet3_update_interrupt_line_state(s
, lidx
);
425 static bool vmxnet3_verify_driver_magic(hwaddr dshmem
)
427 return (VMXNET3_READ_DRV_SHARED32(dshmem
, magic
) == VMXNET3_REV1_MAGIC
);
430 #define VMXNET3_GET_BYTE(x, byte_num) (((x) >> (byte_num)*8) & 0xFF)
431 #define VMXNET3_MAKE_BYTE(byte_num, val) \
432 (((uint32_t)((val) & 0xFF)) << (byte_num)*8)
434 static void vmxnet3_set_variable_mac(VMXNET3State
*s
, uint32_t h
, uint32_t l
)
436 s
->conf
.macaddr
.a
[0] = VMXNET3_GET_BYTE(l
, 0);
437 s
->conf
.macaddr
.a
[1] = VMXNET3_GET_BYTE(l
, 1);
438 s
->conf
.macaddr
.a
[2] = VMXNET3_GET_BYTE(l
, 2);
439 s
->conf
.macaddr
.a
[3] = VMXNET3_GET_BYTE(l
, 3);
440 s
->conf
.macaddr
.a
[4] = VMXNET3_GET_BYTE(h
, 0);
441 s
->conf
.macaddr
.a
[5] = VMXNET3_GET_BYTE(h
, 1);
443 VMW_CFPRN("Variable MAC: " VMXNET_MF
, VMXNET_MA(s
->conf
.macaddr
.a
));
445 qemu_format_nic_info_str(qemu_get_queue(s
->nic
), s
->conf
.macaddr
.a
);
448 static uint64_t vmxnet3_get_mac_low(MACAddr
*addr
)
450 return VMXNET3_MAKE_BYTE(0, addr
->a
[0]) |
451 VMXNET3_MAKE_BYTE(1, addr
->a
[1]) |
452 VMXNET3_MAKE_BYTE(2, addr
->a
[2]) |
453 VMXNET3_MAKE_BYTE(3, addr
->a
[3]);
456 static uint64_t vmxnet3_get_mac_high(MACAddr
*addr
)
458 return VMXNET3_MAKE_BYTE(0, addr
->a
[4]) |
459 VMXNET3_MAKE_BYTE(1, addr
->a
[5]);
463 vmxnet3_inc_tx_consumption_counter(VMXNET3State
*s
, int qidx
)
465 vmxnet3_ring_inc(&s
->txq_descr
[qidx
].tx_ring
);
469 vmxnet3_inc_rx_consumption_counter(VMXNET3State
*s
, int qidx
, int ridx
)
471 vmxnet3_ring_inc(&s
->rxq_descr
[qidx
].rx_ring
[ridx
]);
475 vmxnet3_inc_tx_completion_counter(VMXNET3State
*s
, int qidx
)
477 vmxnet3_ring_inc(&s
->txq_descr
[qidx
].comp_ring
);
481 vmxnet3_inc_rx_completion_counter(VMXNET3State
*s
, int qidx
)
483 vmxnet3_ring_inc(&s
->rxq_descr
[qidx
].comp_ring
);
487 vmxnet3_dec_rx_completion_counter(VMXNET3State
*s
, int qidx
)
489 vmxnet3_ring_dec(&s
->rxq_descr
[qidx
].comp_ring
);
492 static void vmxnet3_complete_packet(VMXNET3State
*s
, int qidx
, uint32 tx_ridx
)
494 struct Vmxnet3_TxCompDesc txcq_descr
;
496 VMXNET3_RING_DUMP(VMW_RIPRN
, "TXC", qidx
, &s
->txq_descr
[qidx
].comp_ring
);
498 txcq_descr
.txdIdx
= tx_ridx
;
499 txcq_descr
.gen
= vmxnet3_ring_curr_gen(&s
->txq_descr
[qidx
].comp_ring
);
501 vmxnet3_ring_write_curr_cell(&s
->txq_descr
[qidx
].comp_ring
, &txcq_descr
);
503 /* Flush changes in TX descriptor before changing the counter value */
506 vmxnet3_inc_tx_completion_counter(s
, qidx
);
507 vmxnet3_trigger_interrupt(s
, s
->txq_descr
[qidx
].intr_idx
);
511 vmxnet3_setup_tx_offloads(VMXNET3State
*s
)
513 switch (s
->offload_mode
) {
514 case VMXNET3_OM_NONE
:
515 vmxnet_tx_pkt_build_vheader(s
->tx_pkt
, false, false, 0);
518 case VMXNET3_OM_CSUM
:
519 vmxnet_tx_pkt_build_vheader(s
->tx_pkt
, false, true, 0);
520 VMW_PKPRN("L4 CSO requested\n");
524 vmxnet_tx_pkt_build_vheader(s
->tx_pkt
, true, true,
526 vmxnet_tx_pkt_update_ip_checksums(s
->tx_pkt
);
527 VMW_PKPRN("GSO offload requested.");
539 vmxnet3_tx_retrieve_metadata(VMXNET3State
*s
,
540 const struct Vmxnet3_TxDesc
*txd
)
542 s
->offload_mode
= txd
->om
;
543 s
->cso_or_gso_size
= txd
->msscof
;
545 s
->needs_vlan
= txd
->ti
;
549 VMXNET3_PKT_STATUS_OK
,
550 VMXNET3_PKT_STATUS_ERROR
,
551 VMXNET3_PKT_STATUS_DISCARD
,/* only for tx */
552 VMXNET3_PKT_STATUS_OUT_OF_BUF
/* only for rx */
556 vmxnet3_on_tx_done_update_stats(VMXNET3State
*s
, int qidx
,
557 Vmxnet3PktStatus status
)
559 size_t tot_len
= vmxnet_tx_pkt_get_total_len(s
->tx_pkt
);
560 struct UPT1_TxStats
*stats
= &s
->txq_descr
[qidx
].txq_stats
;
563 case VMXNET3_PKT_STATUS_OK
:
564 switch (vmxnet_tx_pkt_get_packet_type(s
->tx_pkt
)) {
566 stats
->bcastPktsTxOK
++;
567 stats
->bcastBytesTxOK
+= tot_len
;
570 stats
->mcastPktsTxOK
++;
571 stats
->mcastBytesTxOK
+= tot_len
;
574 stats
->ucastPktsTxOK
++;
575 stats
->ucastBytesTxOK
+= tot_len
;
581 if (s
->offload_mode
== VMXNET3_OM_TSO
) {
583 * According to VMWARE headers this statistic is a number
584 * of packets after segmentation but since we don't have
585 * this information in QEMU model, the best we can do is to
586 * provide number of non-segmented packets
588 stats
->TSOPktsTxOK
++;
589 stats
->TSOBytesTxOK
+= tot_len
;
593 case VMXNET3_PKT_STATUS_DISCARD
:
594 stats
->pktsTxDiscard
++;
597 case VMXNET3_PKT_STATUS_ERROR
:
598 stats
->pktsTxError
++;
607 vmxnet3_on_rx_done_update_stats(VMXNET3State
*s
,
609 Vmxnet3PktStatus status
)
611 struct UPT1_RxStats
*stats
= &s
->rxq_descr
[qidx
].rxq_stats
;
612 size_t tot_len
= vmxnet_rx_pkt_get_total_len(s
->rx_pkt
);
615 case VMXNET3_PKT_STATUS_OUT_OF_BUF
:
616 stats
->pktsRxOutOfBuf
++;
619 case VMXNET3_PKT_STATUS_ERROR
:
620 stats
->pktsRxError
++;
622 case VMXNET3_PKT_STATUS_OK
:
623 switch (vmxnet_rx_pkt_get_packet_type(s
->rx_pkt
)) {
625 stats
->bcastPktsRxOK
++;
626 stats
->bcastBytesRxOK
+= tot_len
;
629 stats
->mcastPktsRxOK
++;
630 stats
->mcastBytesRxOK
+= tot_len
;
633 stats
->ucastPktsRxOK
++;
634 stats
->ucastBytesRxOK
+= tot_len
;
640 if (tot_len
> s
->mtu
) {
641 stats
->LROPktsRxOK
++;
642 stats
->LROBytesRxOK
+= tot_len
;
651 vmxnet3_pop_next_tx_descr(VMXNET3State
*s
,
653 struct Vmxnet3_TxDesc
*txd
,
656 Vmxnet3Ring
*ring
= &s
->txq_descr
[qidx
].tx_ring
;
658 vmxnet3_ring_read_curr_cell(ring
, txd
);
659 if (txd
->gen
== vmxnet3_ring_curr_gen(ring
)) {
660 /* Only read after generation field verification */
662 /* Re-read to be sure we got the latest version */
663 vmxnet3_ring_read_curr_cell(ring
, txd
);
664 VMXNET3_RING_DUMP(VMW_RIPRN
, "TX", qidx
, ring
);
665 *descr_idx
= vmxnet3_ring_curr_cell_idx(ring
);
666 vmxnet3_inc_tx_consumption_counter(s
, qidx
);
674 vmxnet3_send_packet(VMXNET3State
*s
, uint32_t qidx
)
676 Vmxnet3PktStatus status
= VMXNET3_PKT_STATUS_OK
;
678 if (!vmxnet3_setup_tx_offloads(s
)) {
679 status
= VMXNET3_PKT_STATUS_ERROR
;
684 vmxnet3_dump_virt_hdr(vmxnet_tx_pkt_get_vhdr(s
->tx_pkt
));
685 vmxnet_tx_pkt_dump(s
->tx_pkt
);
687 if (!vmxnet_tx_pkt_send(s
->tx_pkt
, qemu_get_queue(s
->nic
))) {
688 status
= VMXNET3_PKT_STATUS_DISCARD
;
693 vmxnet3_on_tx_done_update_stats(s
, qidx
, status
);
694 return (status
== VMXNET3_PKT_STATUS_OK
);
697 static void vmxnet3_process_tx_queue(VMXNET3State
*s
, int qidx
)
699 struct Vmxnet3_TxDesc txd
;
705 if (!vmxnet3_pop_next_tx_descr(s
, qidx
, &txd
, &txd_idx
)) {
709 vmxnet3_dump_tx_descr(&txd
);
711 if (!s
->skip_current_tx_pkt
) {
712 data_len
= (txd
.len
> 0) ? txd
.len
: VMXNET3_MAX_TX_BUF_SIZE
;
713 data_pa
= le64_to_cpu(txd
.addr
);
715 if (!vmxnet_tx_pkt_add_raw_fragment(s
->tx_pkt
,
718 s
->skip_current_tx_pkt
= true;
723 vmxnet3_tx_retrieve_metadata(s
, &txd
);
728 if (!s
->skip_current_tx_pkt
) {
729 vmxnet_tx_pkt_parse(s
->tx_pkt
);
732 vmxnet_tx_pkt_setup_vlan_header(s
->tx_pkt
, s
->tci
);
735 vmxnet3_send_packet(s
, qidx
);
737 vmxnet3_on_tx_done_update_stats(s
, qidx
,
738 VMXNET3_PKT_STATUS_ERROR
);
741 vmxnet3_complete_packet(s
, qidx
, txd_idx
);
743 s
->skip_current_tx_pkt
= false;
744 vmxnet_tx_pkt_reset(s
->tx_pkt
);
750 vmxnet3_read_next_rx_descr(VMXNET3State
*s
, int qidx
, int ridx
,
751 struct Vmxnet3_RxDesc
*dbuf
, uint32_t *didx
)
753 Vmxnet3Ring
*ring
= &s
->rxq_descr
[qidx
].rx_ring
[ridx
];
754 *didx
= vmxnet3_ring_curr_cell_idx(ring
);
755 vmxnet3_ring_read_curr_cell(ring
, dbuf
);
758 static inline uint8_t
759 vmxnet3_get_rx_ring_gen(VMXNET3State
*s
, int qidx
, int ridx
)
761 return s
->rxq_descr
[qidx
].rx_ring
[ridx
].gen
;
765 vmxnet3_pop_rxc_descr(VMXNET3State
*s
, int qidx
, uint32_t *descr_gen
)
768 struct Vmxnet3_RxCompDesc rxcd
;
771 vmxnet3_ring_curr_cell_pa(&s
->rxq_descr
[qidx
].comp_ring
);
773 cpu_physical_memory_read(daddr
, &rxcd
, sizeof(struct Vmxnet3_RxCompDesc
));
774 ring_gen
= vmxnet3_ring_curr_gen(&s
->rxq_descr
[qidx
].comp_ring
);
776 if (rxcd
.gen
!= ring_gen
) {
777 *descr_gen
= ring_gen
;
778 vmxnet3_inc_rx_completion_counter(s
, qidx
);
786 vmxnet3_revert_rxc_descr(VMXNET3State
*s
, int qidx
)
788 vmxnet3_dec_rx_completion_counter(s
, qidx
);
792 #define RX_HEAD_BODY_RING (0)
793 #define RX_BODY_ONLY_RING (1)
796 vmxnet3_get_next_head_rx_descr(VMXNET3State
*s
,
797 struct Vmxnet3_RxDesc
*descr_buf
,
803 vmxnet3_read_next_rx_descr(s
, RXQ_IDX
, RX_HEAD_BODY_RING
,
804 descr_buf
, descr_idx
);
806 /* If no more free descriptors - return */
807 ring_gen
= vmxnet3_get_rx_ring_gen(s
, RXQ_IDX
, RX_HEAD_BODY_RING
);
808 if (descr_buf
->gen
!= ring_gen
) {
812 /* Only read after generation field verification */
814 /* Re-read to be sure we got the latest version */
815 vmxnet3_read_next_rx_descr(s
, RXQ_IDX
, RX_HEAD_BODY_RING
,
816 descr_buf
, descr_idx
);
818 /* Mark current descriptor as used/skipped */
819 vmxnet3_inc_rx_consumption_counter(s
, RXQ_IDX
, RX_HEAD_BODY_RING
);
821 /* If this is what we are looking for - return */
822 if (descr_buf
->btype
== VMXNET3_RXD_BTYPE_HEAD
) {
823 *ridx
= RX_HEAD_BODY_RING
;
830 vmxnet3_get_next_body_rx_descr(VMXNET3State
*s
,
831 struct Vmxnet3_RxDesc
*d
,
835 vmxnet3_read_next_rx_descr(s
, RXQ_IDX
, RX_HEAD_BODY_RING
, d
, didx
);
837 /* Try to find corresponding descriptor in head/body ring */
838 if (d
->gen
== vmxnet3_get_rx_ring_gen(s
, RXQ_IDX
, RX_HEAD_BODY_RING
)) {
839 /* Only read after generation field verification */
841 /* Re-read to be sure we got the latest version */
842 vmxnet3_read_next_rx_descr(s
, RXQ_IDX
, RX_HEAD_BODY_RING
, d
, didx
);
843 if (d
->btype
== VMXNET3_RXD_BTYPE_BODY
) {
844 vmxnet3_inc_rx_consumption_counter(s
, RXQ_IDX
, RX_HEAD_BODY_RING
);
845 *ridx
= RX_HEAD_BODY_RING
;
851 * If there is no free descriptors on head/body ring or next free
852 * descriptor is a head descriptor switch to body only ring
854 vmxnet3_read_next_rx_descr(s
, RXQ_IDX
, RX_BODY_ONLY_RING
, d
, didx
);
856 /* If no more free descriptors - return */
857 if (d
->gen
== vmxnet3_get_rx_ring_gen(s
, RXQ_IDX
, RX_BODY_ONLY_RING
)) {
858 /* Only read after generation field verification */
860 /* Re-read to be sure we got the latest version */
861 vmxnet3_read_next_rx_descr(s
, RXQ_IDX
, RX_BODY_ONLY_RING
, d
, didx
);
862 assert(d
->btype
== VMXNET3_RXD_BTYPE_BODY
);
863 *ridx
= RX_BODY_ONLY_RING
;
864 vmxnet3_inc_rx_consumption_counter(s
, RXQ_IDX
, RX_BODY_ONLY_RING
);
872 vmxnet3_get_next_rx_descr(VMXNET3State
*s
, bool is_head
,
873 struct Vmxnet3_RxDesc
*descr_buf
,
877 if (is_head
|| !s
->rx_packets_compound
) {
878 return vmxnet3_get_next_head_rx_descr(s
, descr_buf
, descr_idx
, ridx
);
880 return vmxnet3_get_next_body_rx_descr(s
, descr_buf
, descr_idx
, ridx
);
884 static void vmxnet3_rx_update_descr(struct VmxnetRxPkt
*pkt
,
885 struct Vmxnet3_RxCompDesc
*rxcd
)
888 bool isip4
, isip6
, istcp
, isudp
;
889 struct virtio_net_hdr
*vhdr
;
890 uint8_t offload_type
;
892 if (vmxnet_rx_pkt_is_vlan_stripped(pkt
)) {
894 rxcd
->tci
= vmxnet_rx_pkt_get_vlan_tag(pkt
);
897 if (!vmxnet_rx_pkt_has_virt_hdr(pkt
)) {
901 vhdr
= vmxnet_rx_pkt_get_vhdr(pkt
);
903 * Checksum is valid when lower level tell so or when lower level
904 * requires checksum offload telling that packet produced/bridged
905 * locally and did travel over network after last checksum calculation
908 csum_ok
= VMXNET_FLAG_IS_SET(vhdr
->flags
, VIRTIO_NET_HDR_F_DATA_VALID
) ||
909 VMXNET_FLAG_IS_SET(vhdr
->flags
, VIRTIO_NET_HDR_F_NEEDS_CSUM
);
911 offload_type
= vhdr
->gso_type
& ~VIRTIO_NET_HDR_GSO_ECN
;
912 is_gso
= (offload_type
!= VIRTIO_NET_HDR_GSO_NONE
) ? 1 : 0;
914 if (!csum_ok
&& !is_gso
) {
918 vmxnet_rx_pkt_get_protocols(pkt
, &isip4
, &isip6
, &isudp
, &istcp
);
919 if ((!istcp
&& !isudp
) || (!isip4
&& !isip6
)) {
924 rxcd
->v4
= isip4
? 1 : 0;
925 rxcd
->v6
= isip6
? 1 : 0;
926 rxcd
->tcp
= istcp
? 1 : 0;
927 rxcd
->udp
= isudp
? 1 : 0;
928 rxcd
->fcs
= rxcd
->tuc
= rxcd
->ipc
= 1;
937 vmxnet3_physical_memory_writev(const struct iovec
*iov
,
938 size_t start_iov_off
,
940 size_t bytes_to_copy
)
945 while (bytes_to_copy
) {
946 if (start_iov_off
< (curr_off
+ iov
->iov_len
)) {
948 MIN((curr_off
+ iov
->iov_len
) - start_iov_off
, bytes_to_copy
);
950 cpu_physical_memory_write(target_addr
+ copied
,
951 iov
->iov_base
+ start_iov_off
- curr_off
,
955 start_iov_off
+= chunk_len
;
956 curr_off
= start_iov_off
;
957 bytes_to_copy
-= chunk_len
;
959 curr_off
+= iov
->iov_len
;
966 vmxnet3_indicate_packet(VMXNET3State
*s
)
968 struct Vmxnet3_RxDesc rxd
;
971 uint32_t rx_ridx
= 0;
973 struct Vmxnet3_RxCompDesc rxcd
;
974 uint32_t new_rxcd_gen
= VMXNET3_INIT_GEN
;
975 hwaddr new_rxcd_pa
= 0;
976 hwaddr ready_rxcd_pa
= 0;
977 struct iovec
*data
= vmxnet_rx_pkt_get_iovec(s
->rx_pkt
);
978 size_t bytes_copied
= 0;
979 size_t bytes_left
= vmxnet_rx_pkt_get_total_len(s
->rx_pkt
);
980 uint16_t num_frags
= 0;
983 vmxnet_rx_pkt_dump(s
->rx_pkt
);
985 while (bytes_left
> 0) {
987 /* cannot add more frags to packet */
988 if (num_frags
== s
->max_rx_frags
) {
992 new_rxcd_pa
= vmxnet3_pop_rxc_descr(s
, RXQ_IDX
, &new_rxcd_gen
);
997 if (!vmxnet3_get_next_rx_descr(s
, is_head
, &rxd
, &rxd_idx
, &rx_ridx
)) {
1001 chunk_size
= MIN(bytes_left
, rxd
.len
);
1002 vmxnet3_physical_memory_writev(data
, bytes_copied
,
1003 le64_to_cpu(rxd
.addr
), chunk_size
);
1004 bytes_copied
+= chunk_size
;
1005 bytes_left
-= chunk_size
;
1007 vmxnet3_dump_rx_descr(&rxd
);
1009 if (0 != ready_rxcd_pa
) {
1010 cpu_physical_memory_write(ready_rxcd_pa
, &rxcd
, sizeof(rxcd
));
1013 memset(&rxcd
, 0, sizeof(struct Vmxnet3_RxCompDesc
));
1014 rxcd
.rxdIdx
= rxd_idx
;
1015 rxcd
.len
= chunk_size
;
1017 rxcd
.gen
= new_rxcd_gen
;
1018 rxcd
.rqID
= RXQ_IDX
+ rx_ridx
* s
->rxq_num
;
1020 if (0 == bytes_left
) {
1021 vmxnet3_rx_update_descr(s
->rx_pkt
, &rxcd
);
1024 VMW_RIPRN("RX Completion descriptor: rxRing: %lu rxIdx %lu len %lu "
1025 "sop %d csum_correct %lu",
1026 (unsigned long) rx_ridx
,
1027 (unsigned long) rxcd
.rxdIdx
,
1028 (unsigned long) rxcd
.len
,
1030 (unsigned long) rxcd
.tuc
);
1033 ready_rxcd_pa
= new_rxcd_pa
;
1037 if (0 != ready_rxcd_pa
) {
1039 rxcd
.err
= (0 != bytes_left
);
1040 cpu_physical_memory_write(ready_rxcd_pa
, &rxcd
, sizeof(rxcd
));
1042 /* Flush RX descriptor changes */
1046 if (0 != new_rxcd_pa
) {
1047 vmxnet3_revert_rxc_descr(s
, RXQ_IDX
);
1050 vmxnet3_trigger_interrupt(s
, s
->rxq_descr
[RXQ_IDX
].intr_idx
);
1052 if (bytes_left
== 0) {
1053 vmxnet3_on_rx_done_update_stats(s
, RXQ_IDX
, VMXNET3_PKT_STATUS_OK
);
1055 } else if (num_frags
== s
->max_rx_frags
) {
1056 vmxnet3_on_rx_done_update_stats(s
, RXQ_IDX
, VMXNET3_PKT_STATUS_ERROR
);
1059 vmxnet3_on_rx_done_update_stats(s
, RXQ_IDX
,
1060 VMXNET3_PKT_STATUS_OUT_OF_BUF
);
1066 vmxnet3_io_bar0_write(void *opaque
, hwaddr addr
,
1067 uint64_t val
, unsigned size
)
1069 VMXNET3State
*s
= opaque
;
1071 if (VMW_IS_MULTIREG_ADDR(addr
, VMXNET3_REG_TXPROD
,
1072 VMXNET3_DEVICE_MAX_TX_QUEUES
, VMXNET3_REG_ALIGN
)) {
1074 VMW_MULTIREG_IDX_BY_ADDR(addr
, VMXNET3_REG_TXPROD
,
1076 assert(tx_queue_idx
<= s
->txq_num
);
1077 vmxnet3_process_tx_queue(s
, tx_queue_idx
);
1081 if (VMW_IS_MULTIREG_ADDR(addr
, VMXNET3_REG_IMR
,
1082 VMXNET3_MAX_INTRS
, VMXNET3_REG_ALIGN
)) {
1083 int l
= VMW_MULTIREG_IDX_BY_ADDR(addr
, VMXNET3_REG_IMR
,
1086 VMW_CBPRN("Interrupt mask for line %d written: 0x%" PRIx64
, l
, val
);
1088 vmxnet3_on_interrupt_mask_changed(s
, l
, val
);
1092 if (VMW_IS_MULTIREG_ADDR(addr
, VMXNET3_REG_RXPROD
,
1093 VMXNET3_DEVICE_MAX_RX_QUEUES
, VMXNET3_REG_ALIGN
) ||
1094 VMW_IS_MULTIREG_ADDR(addr
, VMXNET3_REG_RXPROD2
,
1095 VMXNET3_DEVICE_MAX_RX_QUEUES
, VMXNET3_REG_ALIGN
)) {
1099 VMW_WRPRN("BAR0 unknown write [%" PRIx64
"] = %" PRIx64
", size %d",
1100 (uint64_t) addr
, val
, size
);
1104 vmxnet3_io_bar0_read(void *opaque
, hwaddr addr
, unsigned size
)
1106 if (VMW_IS_MULTIREG_ADDR(addr
, VMXNET3_REG_IMR
,
1107 VMXNET3_MAX_INTRS
, VMXNET3_REG_ALIGN
)) {
1111 VMW_CBPRN("BAR0 unknown read [%" PRIx64
"], size %d", addr
, size
);
1115 static void vmxnet3_reset_interrupt_states(VMXNET3State
*s
)
1118 for (i
= 0; i
< ARRAY_SIZE(s
->interrupt_states
); i
++) {
1119 s
->interrupt_states
[i
].is_asserted
= false;
1120 s
->interrupt_states
[i
].is_pending
= false;
1121 s
->interrupt_states
[i
].is_masked
= true;
1125 static void vmxnet3_reset_mac(VMXNET3State
*s
)
1127 memcpy(&s
->conf
.macaddr
.a
, &s
->perm_mac
.a
, sizeof(s
->perm_mac
.a
));
1128 VMW_CFPRN("MAC address set to: " VMXNET_MF
, VMXNET_MA(s
->conf
.macaddr
.a
));
1131 static void vmxnet3_deactivate_device(VMXNET3State
*s
)
1133 VMW_CBPRN("Deactivating vmxnet3...");
1134 s
->device_active
= false;
1137 static void vmxnet3_reset(VMXNET3State
*s
)
1139 VMW_CBPRN("Resetting vmxnet3...");
1141 vmxnet3_deactivate_device(s
);
1142 vmxnet3_reset_interrupt_states(s
);
1143 vmxnet_tx_pkt_reset(s
->tx_pkt
);
1146 s
->skip_current_tx_pkt
= false;
1149 static void vmxnet3_update_rx_mode(VMXNET3State
*s
)
1151 s
->rx_mode
= VMXNET3_READ_DRV_SHARED32(s
->drv_shmem
,
1152 devRead
.rxFilterConf
.rxMode
);
1153 VMW_CFPRN("RX mode: 0x%08X", s
->rx_mode
);
1156 static void vmxnet3_update_vlan_filters(VMXNET3State
*s
)
1160 /* Copy configuration from shared memory */
1161 VMXNET3_READ_DRV_SHARED(s
->drv_shmem
,
1162 devRead
.rxFilterConf
.vfTable
,
1164 sizeof(s
->vlan_table
));
1166 /* Invert byte order when needed */
1167 for (i
= 0; i
< ARRAY_SIZE(s
->vlan_table
); i
++) {
1168 s
->vlan_table
[i
] = le32_to_cpu(s
->vlan_table
[i
]);
1171 /* Dump configuration for debugging purposes */
1172 VMW_CFPRN("Configured VLANs:");
1173 for (i
= 0; i
< sizeof(s
->vlan_table
) * 8; i
++) {
1174 if (VMXNET3_VFTABLE_ENTRY_IS_SET(s
->vlan_table
, i
)) {
1175 VMW_CFPRN("\tVLAN %d is present", i
);
1180 static void vmxnet3_update_mcast_filters(VMXNET3State
*s
)
1182 uint16_t list_bytes
=
1183 VMXNET3_READ_DRV_SHARED16(s
->drv_shmem
,
1184 devRead
.rxFilterConf
.mfTableLen
);
1186 s
->mcast_list_len
= list_bytes
/ sizeof(s
->mcast_list
[0]);
1188 s
->mcast_list
= g_realloc(s
->mcast_list
, list_bytes
);
1189 if (NULL
== s
->mcast_list
) {
1190 if (0 == s
->mcast_list_len
) {
1191 VMW_CFPRN("Current multicast list is empty");
1193 VMW_ERPRN("Failed to allocate multicast list of %d elements",
1196 s
->mcast_list_len
= 0;
1199 hwaddr mcast_list_pa
=
1200 VMXNET3_READ_DRV_SHARED64(s
->drv_shmem
,
1201 devRead
.rxFilterConf
.mfTablePA
);
1203 cpu_physical_memory_read(mcast_list_pa
, s
->mcast_list
, list_bytes
);
1204 VMW_CFPRN("Current multicast list len is %d:", s
->mcast_list_len
);
1205 for (i
= 0; i
< s
->mcast_list_len
; i
++) {
1206 VMW_CFPRN("\t" VMXNET_MF
, VMXNET_MA(s
->mcast_list
[i
].a
));
1211 static void vmxnet3_setup_rx_filtering(VMXNET3State
*s
)
1213 vmxnet3_update_rx_mode(s
);
1214 vmxnet3_update_vlan_filters(s
);
1215 vmxnet3_update_mcast_filters(s
);
1218 static uint32_t vmxnet3_get_interrupt_config(VMXNET3State
*s
)
1220 uint32_t interrupt_mode
= VMXNET3_IT_AUTO
| (VMXNET3_IMM_AUTO
<< 2);
1221 VMW_CFPRN("Interrupt config is 0x%X", interrupt_mode
);
1222 return interrupt_mode
;
1225 static void vmxnet3_fill_stats(VMXNET3State
*s
)
1228 for (i
= 0; i
< s
->txq_num
; i
++) {
1229 cpu_physical_memory_write(s
->txq_descr
[i
].tx_stats_pa
,
1230 &s
->txq_descr
[i
].txq_stats
,
1231 sizeof(s
->txq_descr
[i
].txq_stats
));
1234 for (i
= 0; i
< s
->rxq_num
; i
++) {
1235 cpu_physical_memory_write(s
->rxq_descr
[i
].rx_stats_pa
,
1236 &s
->rxq_descr
[i
].rxq_stats
,
1237 sizeof(s
->rxq_descr
[i
].rxq_stats
));
1241 static void vmxnet3_adjust_by_guest_type(VMXNET3State
*s
)
1243 struct Vmxnet3_GOSInfo gos
;
1245 VMXNET3_READ_DRV_SHARED(s
->drv_shmem
, devRead
.misc
.driverInfo
.gos
,
1247 s
->rx_packets_compound
=
1248 (gos
.gosType
== VMXNET3_GOS_TYPE_WIN
) ? false : true;
1250 VMW_CFPRN("Guest type specifics: RXCOMPOUND: %d", s
->rx_packets_compound
);
1254 vmxnet3_dump_conf_descr(const char *name
,
1255 struct Vmxnet3_VariableLenConfDesc
*pm_descr
)
1257 VMW_CFPRN("%s descriptor dump: Version %u, Length %u",
1258 name
, pm_descr
->confVer
, pm_descr
->confLen
);
1262 static void vmxnet3_update_pm_state(VMXNET3State
*s
)
1264 struct Vmxnet3_VariableLenConfDesc pm_descr
;
1267 VMXNET3_READ_DRV_SHARED32(s
->drv_shmem
, devRead
.pmConfDesc
.confLen
);
1269 VMXNET3_READ_DRV_SHARED32(s
->drv_shmem
, devRead
.pmConfDesc
.confVer
);
1271 VMXNET3_READ_DRV_SHARED64(s
->drv_shmem
, devRead
.pmConfDesc
.confPA
);
1273 vmxnet3_dump_conf_descr("PM State", &pm_descr
);
1276 static void vmxnet3_update_features(VMXNET3State
*s
)
1278 uint32_t guest_features
;
1279 int rxcso_supported
;
1281 guest_features
= VMXNET3_READ_DRV_SHARED32(s
->drv_shmem
,
1282 devRead
.misc
.uptFeatures
);
1284 rxcso_supported
= VMXNET_FLAG_IS_SET(guest_features
, UPT1_F_RXCSUM
);
1285 s
->rx_vlan_stripping
= VMXNET_FLAG_IS_SET(guest_features
, UPT1_F_RXVLAN
);
1286 s
->lro_supported
= VMXNET_FLAG_IS_SET(guest_features
, UPT1_F_LRO
);
1288 VMW_CFPRN("Features configuration: LRO: %d, RXCSUM: %d, VLANSTRIP: %d",
1289 s
->lro_supported
, rxcso_supported
,
1290 s
->rx_vlan_stripping
);
1291 if (s
->peer_has_vhdr
) {
1292 tap_set_offload(qemu_get_queue(s
->nic
)->peer
,
1301 static void vmxnet3_activate_device(VMXNET3State
*s
)
1304 static const uint32_t VMXNET3_DEF_TX_THRESHOLD
= 1;
1305 hwaddr qdescr_table_pa
;
1309 /* Verify configuration consistency */
1310 if (!vmxnet3_verify_driver_magic(s
->drv_shmem
)) {
1311 VMW_ERPRN("Device configuration received from driver is invalid");
1315 vmxnet3_adjust_by_guest_type(s
);
1316 vmxnet3_update_features(s
);
1317 vmxnet3_update_pm_state(s
);
1318 vmxnet3_setup_rx_filtering(s
);
1319 /* Cache fields from shared memory */
1320 s
->mtu
= VMXNET3_READ_DRV_SHARED32(s
->drv_shmem
, devRead
.misc
.mtu
);
1321 VMW_CFPRN("MTU is %u", s
->mtu
);
1324 VMXNET3_READ_DRV_SHARED16(s
->drv_shmem
, devRead
.misc
.maxNumRxSG
);
1326 VMW_CFPRN("Max RX fragments is %u", s
->max_rx_frags
);
1329 VMXNET3_READ_DRV_SHARED8(s
->drv_shmem
, devRead
.intrConf
.eventIntrIdx
);
1330 VMW_CFPRN("Events interrupt line is %u", s
->event_int_idx
);
1332 s
->auto_int_masking
=
1333 VMXNET3_READ_DRV_SHARED8(s
->drv_shmem
, devRead
.intrConf
.autoMask
);
1334 VMW_CFPRN("Automatic interrupt masking is %d", (int)s
->auto_int_masking
);
1337 VMXNET3_READ_DRV_SHARED8(s
->drv_shmem
, devRead
.misc
.numTxQueues
);
1339 VMXNET3_READ_DRV_SHARED8(s
->drv_shmem
, devRead
.misc
.numRxQueues
);
1341 VMW_CFPRN("Number of TX/RX queues %u/%u", s
->txq_num
, s
->rxq_num
);
1342 assert(s
->txq_num
<= VMXNET3_DEVICE_MAX_TX_QUEUES
);
1345 VMXNET3_READ_DRV_SHARED64(s
->drv_shmem
, devRead
.misc
.queueDescPA
);
1346 VMW_CFPRN("TX queues descriptors table is at 0x%" PRIx64
, qdescr_table_pa
);
1349 * Worst-case scenario is a packet that holds all TX rings space so
1350 * we calculate total size of all TX rings for max TX fragments number
1352 s
->max_tx_frags
= 0;
1355 for (i
= 0; i
< s
->txq_num
; i
++) {
1357 qdescr_table_pa
+ i
* sizeof(struct Vmxnet3_TxQueueDesc
);
1359 /* Read interrupt number for this TX queue */
1360 s
->txq_descr
[i
].intr_idx
=
1361 VMXNET3_READ_TX_QUEUE_DESCR8(qdescr_pa
, conf
.intrIdx
);
1363 VMW_CFPRN("TX Queue %d interrupt: %d", i
, s
->txq_descr
[i
].intr_idx
);
1365 /* Read rings memory locations for TX queues */
1366 pa
= VMXNET3_READ_TX_QUEUE_DESCR64(qdescr_pa
, conf
.txRingBasePA
);
1367 size
= VMXNET3_READ_TX_QUEUE_DESCR32(qdescr_pa
, conf
.txRingSize
);
1369 vmxnet3_ring_init(&s
->txq_descr
[i
].tx_ring
, pa
, size
,
1370 sizeof(struct Vmxnet3_TxDesc
), false);
1371 VMXNET3_RING_DUMP(VMW_CFPRN
, "TX", i
, &s
->txq_descr
[i
].tx_ring
);
1373 s
->max_tx_frags
+= size
;
1376 pa
= VMXNET3_READ_TX_QUEUE_DESCR64(qdescr_pa
, conf
.compRingBasePA
);
1377 size
= VMXNET3_READ_TX_QUEUE_DESCR32(qdescr_pa
, conf
.compRingSize
);
1378 vmxnet3_ring_init(&s
->txq_descr
[i
].comp_ring
, pa
, size
,
1379 sizeof(struct Vmxnet3_TxCompDesc
), true);
1380 VMXNET3_RING_DUMP(VMW_CFPRN
, "TXC", i
, &s
->txq_descr
[i
].comp_ring
);
1382 s
->txq_descr
[i
].tx_stats_pa
=
1383 qdescr_pa
+ offsetof(struct Vmxnet3_TxQueueDesc
, stats
);
1385 memset(&s
->txq_descr
[i
].txq_stats
, 0,
1386 sizeof(s
->txq_descr
[i
].txq_stats
));
1388 /* Fill device-managed parameters for queues */
1389 VMXNET3_WRITE_TX_QUEUE_DESCR32(qdescr_pa
,
1391 VMXNET3_DEF_TX_THRESHOLD
);
1394 /* Preallocate TX packet wrapper */
1395 VMW_CFPRN("Max TX fragments is %u", s
->max_tx_frags
);
1396 vmxnet_tx_pkt_init(&s
->tx_pkt
, s
->max_tx_frags
, s
->peer_has_vhdr
);
1397 vmxnet_rx_pkt_init(&s
->rx_pkt
, s
->peer_has_vhdr
);
1399 /* Read rings memory locations for RX queues */
1400 for (i
= 0; i
< s
->rxq_num
; i
++) {
1403 qdescr_table_pa
+ s
->txq_num
* sizeof(struct Vmxnet3_TxQueueDesc
) +
1404 i
* sizeof(struct Vmxnet3_RxQueueDesc
);
1406 /* Read interrupt number for this RX queue */
1407 s
->rxq_descr
[i
].intr_idx
=
1408 VMXNET3_READ_TX_QUEUE_DESCR8(qd_pa
, conf
.intrIdx
);
1410 VMW_CFPRN("RX Queue %d interrupt: %d", i
, s
->rxq_descr
[i
].intr_idx
);
1412 /* Read rings memory locations */
1413 for (j
= 0; j
< VMXNET3_RX_RINGS_PER_QUEUE
; j
++) {
1415 pa
= VMXNET3_READ_RX_QUEUE_DESCR64(qd_pa
, conf
.rxRingBasePA
[j
]);
1416 size
= VMXNET3_READ_RX_QUEUE_DESCR32(qd_pa
, conf
.rxRingSize
[j
]);
1417 vmxnet3_ring_init(&s
->rxq_descr
[i
].rx_ring
[j
], pa
, size
,
1418 sizeof(struct Vmxnet3_RxDesc
), false);
1419 VMW_CFPRN("RX queue %d:%d: Base: %" PRIx64
", Size: %d",
1424 pa
= VMXNET3_READ_RX_QUEUE_DESCR64(qd_pa
, conf
.compRingBasePA
);
1425 size
= VMXNET3_READ_RX_QUEUE_DESCR32(qd_pa
, conf
.compRingSize
);
1426 vmxnet3_ring_init(&s
->rxq_descr
[i
].comp_ring
, pa
, size
,
1427 sizeof(struct Vmxnet3_RxCompDesc
), true);
1428 VMW_CFPRN("RXC queue %d: Base: %" PRIx64
", Size: %d", i
, pa
, size
);
1430 s
->rxq_descr
[i
].rx_stats_pa
=
1431 qd_pa
+ offsetof(struct Vmxnet3_RxQueueDesc
, stats
);
1432 memset(&s
->rxq_descr
[i
].rxq_stats
, 0,
1433 sizeof(s
->rxq_descr
[i
].rxq_stats
));
1436 /* Make sure everything is in place before device activation */
1439 vmxnet3_reset_mac(s
);
1441 s
->device_active
= true;
1444 static void vmxnet3_handle_command(VMXNET3State
*s
, uint64_t cmd
)
1446 s
->last_command
= cmd
;
1449 case VMXNET3_CMD_GET_PERM_MAC_HI
:
1450 VMW_CBPRN("Set: Get upper part of permanent MAC");
1453 case VMXNET3_CMD_GET_PERM_MAC_LO
:
1454 VMW_CBPRN("Set: Get lower part of permanent MAC");
1457 case VMXNET3_CMD_GET_STATS
:
1458 VMW_CBPRN("Set: Get device statistics");
1459 vmxnet3_fill_stats(s
);
1462 case VMXNET3_CMD_ACTIVATE_DEV
:
1463 VMW_CBPRN("Set: Activating vmxnet3 device");
1464 vmxnet3_activate_device(s
);
1467 case VMXNET3_CMD_UPDATE_RX_MODE
:
1468 VMW_CBPRN("Set: Update rx mode");
1469 vmxnet3_update_rx_mode(s
);
1472 case VMXNET3_CMD_UPDATE_VLAN_FILTERS
:
1473 VMW_CBPRN("Set: Update VLAN filters");
1474 vmxnet3_update_vlan_filters(s
);
1477 case VMXNET3_CMD_UPDATE_MAC_FILTERS
:
1478 VMW_CBPRN("Set: Update MAC filters");
1479 vmxnet3_update_mcast_filters(s
);
1482 case VMXNET3_CMD_UPDATE_FEATURE
:
1483 VMW_CBPRN("Set: Update features");
1484 vmxnet3_update_features(s
);
1487 case VMXNET3_CMD_UPDATE_PMCFG
:
1488 VMW_CBPRN("Set: Update power management config");
1489 vmxnet3_update_pm_state(s
);
1492 case VMXNET3_CMD_GET_LINK
:
1493 VMW_CBPRN("Set: Get link");
1496 case VMXNET3_CMD_RESET_DEV
:
1497 VMW_CBPRN("Set: Reset device");
1501 case VMXNET3_CMD_QUIESCE_DEV
:
1502 VMW_CBPRN("Set: VMXNET3_CMD_QUIESCE_DEV - pause the device");
1503 vmxnet3_deactivate_device(s
);
1506 case VMXNET3_CMD_GET_CONF_INTR
:
1507 VMW_CBPRN("Set: VMXNET3_CMD_GET_CONF_INTR - interrupt configuration");
1511 VMW_CBPRN("Received unknown command: %" PRIx64
, cmd
);
1516 static uint64_t vmxnet3_get_command_status(VMXNET3State
*s
)
1520 switch (s
->last_command
) {
1521 case VMXNET3_CMD_ACTIVATE_DEV
:
1522 ret
= (s
->device_active
) ? 0 : -1;
1523 VMW_CFPRN("Device active: %" PRIx64
, ret
);
1526 case VMXNET3_CMD_GET_LINK
:
1527 ret
= s
->link_status_and_speed
;
1528 VMW_CFPRN("Link and speed: %" PRIx64
, ret
);
1531 case VMXNET3_CMD_GET_PERM_MAC_LO
:
1532 ret
= vmxnet3_get_mac_low(&s
->perm_mac
);
1535 case VMXNET3_CMD_GET_PERM_MAC_HI
:
1536 ret
= vmxnet3_get_mac_high(&s
->perm_mac
);
1539 case VMXNET3_CMD_GET_CONF_INTR
:
1540 ret
= vmxnet3_get_interrupt_config(s
);
1544 VMW_WRPRN("Received request for unknown command: %x", s
->last_command
);
1552 static void vmxnet3_set_events(VMXNET3State
*s
, uint32_t val
)
1556 VMW_CBPRN("Setting events: 0x%x", val
);
1557 events
= VMXNET3_READ_DRV_SHARED32(s
->drv_shmem
, ecr
) | val
;
1558 VMXNET3_WRITE_DRV_SHARED32(s
->drv_shmem
, ecr
, events
);
1561 static void vmxnet3_ack_events(VMXNET3State
*s
, uint32_t val
)
1565 VMW_CBPRN("Clearing events: 0x%x", val
);
1566 events
= VMXNET3_READ_DRV_SHARED32(s
->drv_shmem
, ecr
) & ~val
;
1567 VMXNET3_WRITE_DRV_SHARED32(s
->drv_shmem
, ecr
, events
);
1571 vmxnet3_io_bar1_write(void *opaque
,
1576 VMXNET3State
*s
= opaque
;
1579 /* Vmxnet3 Revision Report Selection */
1580 case VMXNET3_REG_VRRS
:
1581 VMW_CBPRN("Write BAR1 [VMXNET3_REG_VRRS] = %" PRIx64
", size %d",
1585 /* UPT Version Report Selection */
1586 case VMXNET3_REG_UVRS
:
1587 VMW_CBPRN("Write BAR1 [VMXNET3_REG_UVRS] = %" PRIx64
", size %d",
1591 /* Driver Shared Address Low */
1592 case VMXNET3_REG_DSAL
:
1593 VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAL] = %" PRIx64
", size %d",
1596 * Guest driver will first write the low part of the shared
1597 * memory address. We save it to temp variable and set the
1598 * shared address only after we get the high part
1601 s
->device_active
= false;
1603 s
->temp_shared_guest_driver_memory
= val
;
1607 /* Driver Shared Address High */
1608 case VMXNET3_REG_DSAH
:
1609 VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAH] = %" PRIx64
", size %d",
1612 * Set the shared memory between guest driver and device.
1613 * We already should have low address part.
1615 s
->drv_shmem
= s
->temp_shared_guest_driver_memory
| (val
<< 32);
1619 case VMXNET3_REG_CMD
:
1620 VMW_CBPRN("Write BAR1 [VMXNET3_REG_CMD] = %" PRIx64
", size %d",
1622 vmxnet3_handle_command(s
, val
);
1625 /* MAC Address Low */
1626 case VMXNET3_REG_MACL
:
1627 VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACL] = %" PRIx64
", size %d",
1632 /* MAC Address High */
1633 case VMXNET3_REG_MACH
:
1634 VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACH] = %" PRIx64
", size %d",
1636 vmxnet3_set_variable_mac(s
, val
, s
->temp_mac
);
1639 /* Interrupt Cause Register */
1640 case VMXNET3_REG_ICR
:
1641 VMW_CBPRN("Write BAR1 [VMXNET3_REG_ICR] = %" PRIx64
", size %d",
1646 /* Event Cause Register */
1647 case VMXNET3_REG_ECR
:
1648 VMW_CBPRN("Write BAR1 [VMXNET3_REG_ECR] = %" PRIx64
", size %d",
1650 vmxnet3_ack_events(s
, val
);
1654 VMW_CBPRN("Unknown Write to BAR1 [%" PRIx64
"] = %" PRIx64
", size %d",
1661 vmxnet3_io_bar1_read(void *opaque
, hwaddr addr
, unsigned size
)
1663 VMXNET3State
*s
= opaque
;
1667 /* Vmxnet3 Revision Report Selection */
1668 case VMXNET3_REG_VRRS
:
1669 VMW_CBPRN("Read BAR1 [VMXNET3_REG_VRRS], size %d", size
);
1670 ret
= VMXNET3_DEVICE_REVISION
;
1673 /* UPT Version Report Selection */
1674 case VMXNET3_REG_UVRS
:
1675 VMW_CBPRN("Read BAR1 [VMXNET3_REG_UVRS], size %d", size
);
1676 ret
= VMXNET3_DEVICE_VERSION
;
1680 case VMXNET3_REG_CMD
:
1681 VMW_CBPRN("Read BAR1 [VMXNET3_REG_CMD], size %d", size
);
1682 ret
= vmxnet3_get_command_status(s
);
1685 /* MAC Address Low */
1686 case VMXNET3_REG_MACL
:
1687 VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACL], size %d", size
);
1688 ret
= vmxnet3_get_mac_low(&s
->conf
.macaddr
);
1691 /* MAC Address High */
1692 case VMXNET3_REG_MACH
:
1693 VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACH], size %d", size
);
1694 ret
= vmxnet3_get_mac_high(&s
->conf
.macaddr
);
1698 * Interrupt Cause Register
1699 * Used for legacy interrupts only so interrupt index always 0
1701 case VMXNET3_REG_ICR
:
1702 VMW_CBPRN("Read BAR1 [VMXNET3_REG_ICR], size %d", size
);
1703 if (vmxnet3_interrupt_asserted(s
, 0)) {
1704 vmxnet3_clear_interrupt(s
, 0);
1712 VMW_CBPRN("Unknow read BAR1[%" PRIx64
"], %d bytes", addr
, size
);
1720 vmxnet3_can_receive(NetClientState
*nc
)
1722 VMXNET3State
*s
= qemu_get_nic_opaque(nc
);
1723 return s
->device_active
&&
1724 VMXNET_FLAG_IS_SET(s
->link_status_and_speed
, VMXNET3_LINK_STATUS_UP
);
1728 vmxnet3_is_registered_vlan(VMXNET3State
*s
, const void *data
)
1730 uint16_t vlan_tag
= eth_get_pkt_tci(data
) & VLAN_VID_MASK
;
1731 if (IS_SPECIAL_VLAN_ID(vlan_tag
)) {
1735 return VMXNET3_VFTABLE_ENTRY_IS_SET(s
->vlan_table
, vlan_tag
);
1739 vmxnet3_is_allowed_mcast_group(VMXNET3State
*s
, const uint8_t *group_mac
)
1742 for (i
= 0; i
< s
->mcast_list_len
; i
++) {
1743 if (!memcmp(group_mac
, s
->mcast_list
[i
].a
, sizeof(s
->mcast_list
[i
]))) {
1751 vmxnet3_rx_filter_may_indicate(VMXNET3State
*s
, const void *data
,
1754 struct eth_header
*ehdr
= PKT_GET_ETH_HDR(data
);
1756 if (VMXNET_FLAG_IS_SET(s
->rx_mode
, VMXNET3_RXM_PROMISC
)) {
1760 if (!vmxnet3_is_registered_vlan(s
, data
)) {
1764 switch (vmxnet_rx_pkt_get_packet_type(s
->rx_pkt
)) {
1766 if (!VMXNET_FLAG_IS_SET(s
->rx_mode
, VMXNET3_RXM_UCAST
)) {
1769 if (memcmp(s
->conf
.macaddr
.a
, ehdr
->h_dest
, ETH_ALEN
)) {
1775 if (!VMXNET_FLAG_IS_SET(s
->rx_mode
, VMXNET3_RXM_BCAST
)) {
1781 if (VMXNET_FLAG_IS_SET(s
->rx_mode
, VMXNET3_RXM_ALL_MULTI
)) {
1784 if (!VMXNET_FLAG_IS_SET(s
->rx_mode
, VMXNET3_RXM_MCAST
)) {
1787 if (!vmxnet3_is_allowed_mcast_group(s
, ehdr
->h_dest
)) {
1800 vmxnet3_receive(NetClientState
*nc
, const uint8_t *buf
, size_t size
)
1802 VMXNET3State
*s
= qemu_get_nic_opaque(nc
);
1803 size_t bytes_indicated
;
1805 if (!vmxnet3_can_receive(nc
)) {
1806 VMW_PKPRN("Cannot receive now");
1810 if (s
->peer_has_vhdr
) {
1811 vmxnet_rx_pkt_set_vhdr(s
->rx_pkt
, (struct virtio_net_hdr
*)buf
);
1812 buf
+= sizeof(struct virtio_net_hdr
);
1813 size
-= sizeof(struct virtio_net_hdr
);
1816 vmxnet_rx_pkt_set_packet_type(s
->rx_pkt
,
1817 get_eth_packet_type(PKT_GET_ETH_HDR(buf
)));
1819 if (vmxnet3_rx_filter_may_indicate(s
, buf
, size
)) {
1820 vmxnet_rx_pkt_attach_data(s
->rx_pkt
, buf
, size
, s
->rx_vlan_stripping
);
1821 bytes_indicated
= vmxnet3_indicate_packet(s
) ? size
: -1;
1822 if (bytes_indicated
< size
) {
1823 VMW_PKPRN("RX: %lu of %lu bytes indicated", bytes_indicated
, size
);
1826 VMW_PKPRN("Packet dropped by RX filter");
1827 bytes_indicated
= size
;
1831 assert(bytes_indicated
!= 0);
1832 return bytes_indicated
;
1835 static void vmxnet3_cleanup(NetClientState
*nc
)
1837 VMXNET3State
*s
= qemu_get_nic_opaque(nc
);
1841 static void vmxnet3_set_link_status(NetClientState
*nc
)
1843 VMXNET3State
*s
= qemu_get_nic_opaque(nc
);
1845 if (nc
->link_down
) {
1846 s
->link_status_and_speed
&= ~VMXNET3_LINK_STATUS_UP
;
1848 s
->link_status_and_speed
|= VMXNET3_LINK_STATUS_UP
;
1851 vmxnet3_set_events(s
, VMXNET3_ECR_LINK
);
1852 vmxnet3_trigger_interrupt(s
, s
->event_int_idx
);
1855 static NetClientInfo net_vmxnet3_info
= {
1856 .type
= NET_CLIENT_OPTIONS_KIND_NIC
,
1857 .size
= sizeof(NICState
),
1858 .can_receive
= vmxnet3_can_receive
,
1859 .receive
= vmxnet3_receive
,
1860 .cleanup
= vmxnet3_cleanup
,
1861 .link_status_changed
= vmxnet3_set_link_status
,
1864 static bool vmxnet3_peer_has_vnet_hdr(VMXNET3State
*s
)
1866 NetClientState
*peer
= qemu_get_queue(s
->nic
)->peer
;
1868 if ((NULL
!= peer
) &&
1869 (peer
->info
->type
== NET_CLIENT_OPTIONS_KIND_TAP
) &&
1870 tap_has_vnet_hdr(peer
)) {
1874 VMW_WRPRN("Peer has no virtio extension. Task offloads will be emulated.");
1878 static void vmxnet3_net_uninit(VMXNET3State
*s
)
1880 g_free(s
->mcast_list
);
1881 vmxnet_tx_pkt_reset(s
->tx_pkt
);
1882 vmxnet_tx_pkt_uninit(s
->tx_pkt
);
1883 vmxnet_rx_pkt_uninit(s
->rx_pkt
);
1884 qemu_del_net_client(qemu_get_queue(s
->nic
));
1887 static void vmxnet3_net_init(VMXNET3State
*s
)
1889 DeviceState
*d
= DEVICE(s
);
1891 VMW_CBPRN("vmxnet3_net_init called...");
1893 qemu_macaddr_default_if_unset(&s
->conf
.macaddr
);
1895 /* Windows guest will query the address that was set on init */
1896 memcpy(&s
->perm_mac
.a
, &s
->conf
.macaddr
.a
, sizeof(s
->perm_mac
.a
));
1898 s
->mcast_list
= NULL
;
1899 s
->mcast_list_len
= 0;
1901 s
->link_status_and_speed
= VMXNET3_LINK_SPEED
| VMXNET3_LINK_STATUS_UP
;
1903 VMW_CFPRN("Permanent MAC: " MAC_FMT
, MAC_ARG(s
->perm_mac
.a
));
1905 s
->nic
= qemu_new_nic(&net_vmxnet3_info
, &s
->conf
,
1906 object_get_typename(OBJECT(s
)),
1909 s
->peer_has_vhdr
= vmxnet3_peer_has_vnet_hdr(s
);
1911 s
->skip_current_tx_pkt
= false;
1914 s
->rx_vlan_stripping
= false;
1915 s
->lro_supported
= false;
1917 if (s
->peer_has_vhdr
) {
1918 tap_set_vnet_hdr_len(qemu_get_queue(s
->nic
)->peer
,
1919 sizeof(struct virtio_net_hdr
));
1921 tap_using_vnet_hdr(qemu_get_queue(s
->nic
)->peer
, 1);
1924 qemu_format_nic_info_str(qemu_get_queue(s
->nic
), s
->conf
.macaddr
.a
);
1928 vmxnet3_unuse_msix_vectors(VMXNET3State
*s
, int num_vectors
)
1930 PCIDevice
*d
= PCI_DEVICE(s
);
1932 for (i
= 0; i
< num_vectors
; i
++) {
1933 msix_vector_unuse(d
, i
);
1938 vmxnet3_use_msix_vectors(VMXNET3State
*s
, int num_vectors
)
1940 PCIDevice
*d
= PCI_DEVICE(s
);
1942 for (i
= 0; i
< num_vectors
; i
++) {
1943 int res
= msix_vector_use(d
, i
);
1945 VMW_WRPRN("Failed to use MSI-X vector %d, error %d", i
, res
);
1946 vmxnet3_unuse_msix_vectors(s
, i
);
1954 vmxnet3_init_msix(VMXNET3State
*s
)
1956 PCIDevice
*d
= PCI_DEVICE(s
);
1957 int res
= msix_init(d
, VMXNET3_MAX_INTRS
,
1959 VMXNET3_MSIX_BAR_IDX
, VMXNET3_OFF_MSIX_TABLE
,
1961 VMXNET3_MSIX_BAR_IDX
, VMXNET3_OFF_MSIX_PBA
,
1965 VMW_WRPRN("Failed to initialize MSI-X, error %d", res
);
1966 s
->msix_used
= false;
1968 if (!vmxnet3_use_msix_vectors(s
, VMXNET3_MAX_INTRS
)) {
1969 VMW_WRPRN("Failed to use MSI-X vectors, error %d", res
);
1970 msix_uninit(d
, &s
->msix_bar
, &s
->msix_bar
);
1971 s
->msix_used
= false;
1973 s
->msix_used
= true;
1976 return s
->msix_used
;
1980 vmxnet3_cleanup_msix(VMXNET3State
*s
)
1982 PCIDevice
*d
= PCI_DEVICE(s
);
1985 msix_vector_unuse(d
, VMXNET3_MAX_INTRS
);
1986 msix_uninit(d
, &s
->msix_bar
, &s
->msix_bar
);
1990 #define VMXNET3_MSI_NUM_VECTORS (1)
1991 #define VMXNET3_MSI_OFFSET (0x50)
1992 #define VMXNET3_USE_64BIT (true)
1993 #define VMXNET3_PER_VECTOR_MASK (false)
1996 vmxnet3_init_msi(VMXNET3State
*s
)
1998 PCIDevice
*d
= PCI_DEVICE(s
);
2001 res
= msi_init(d
, VMXNET3_MSI_OFFSET
, VMXNET3_MSI_NUM_VECTORS
,
2002 VMXNET3_USE_64BIT
, VMXNET3_PER_VECTOR_MASK
);
2004 VMW_WRPRN("Failed to initialize MSI, error %d", res
);
2005 s
->msi_used
= false;
2014 vmxnet3_cleanup_msi(VMXNET3State
*s
)
2016 PCIDevice
*d
= PCI_DEVICE(s
);
2024 vmxnet3_msix_save(QEMUFile
*f
, void *opaque
)
2026 PCIDevice
*d
= PCI_DEVICE(opaque
);
2031 vmxnet3_msix_load(QEMUFile
*f
, void *opaque
, int version_id
)
2033 PCIDevice
*d
= PCI_DEVICE(opaque
);
2038 static const MemoryRegionOps b0_ops
= {
2039 .read
= vmxnet3_io_bar0_read
,
2040 .write
= vmxnet3_io_bar0_write
,
2041 .endianness
= DEVICE_LITTLE_ENDIAN
,
2043 .min_access_size
= 4,
2044 .max_access_size
= 4,
2048 static const MemoryRegionOps b1_ops
= {
2049 .read
= vmxnet3_io_bar1_read
,
2050 .write
= vmxnet3_io_bar1_write
,
2051 .endianness
= DEVICE_LITTLE_ENDIAN
,
2053 .min_access_size
= 4,
2054 .max_access_size
= 4,
2058 static int vmxnet3_pci_init(PCIDevice
*pci_dev
)
2060 DeviceState
*dev
= DEVICE(pci_dev
);
2061 VMXNET3State
*s
= VMXNET3(pci_dev
);
2063 VMW_CBPRN("Starting init...");
2065 memory_region_init_io(&s
->bar0
, &b0_ops
, s
,
2066 "vmxnet3-b0", VMXNET3_PT_REG_SIZE
);
2067 pci_register_bar(pci_dev
, VMXNET3_BAR0_IDX
,
2068 PCI_BASE_ADDRESS_SPACE_MEMORY
, &s
->bar0
);
2070 memory_region_init_io(&s
->bar1
, &b1_ops
, s
,
2071 "vmxnet3-b1", VMXNET3_VD_REG_SIZE
);
2072 pci_register_bar(pci_dev
, VMXNET3_BAR1_IDX
,
2073 PCI_BASE_ADDRESS_SPACE_MEMORY
, &s
->bar1
);
2075 memory_region_init(&s
->msix_bar
, "vmxnet3-msix-bar",
2076 VMXNET3_MSIX_BAR_SIZE
);
2077 pci_register_bar(pci_dev
, VMXNET3_MSIX_BAR_IDX
,
2078 PCI_BASE_ADDRESS_SPACE_MEMORY
, &s
->msix_bar
);
2080 vmxnet3_reset_interrupt_states(s
);
2082 /* Interrupt pin A */
2083 pci_dev
->config
[PCI_INTERRUPT_PIN
] = 0x01;
2085 if (!vmxnet3_init_msix(s
)) {
2086 VMW_WRPRN("Failed to initialize MSI-X, configuration is inconsistent.");
2089 if (!vmxnet3_init_msi(s
)) {
2090 VMW_WRPRN("Failed to initialize MSI, configuration is inconsistent.");
2093 vmxnet3_net_init(s
);
2095 register_savevm(dev
, "vmxnet3-msix", -1, 1,
2096 vmxnet3_msix_save
, vmxnet3_msix_load
, s
);
2098 add_boot_device_path(s
->conf
.bootindex
, dev
, "/ethernet-phy@0");
2104 static void vmxnet3_pci_uninit(PCIDevice
*pci_dev
)
2106 DeviceState
*dev
= DEVICE(pci_dev
);
2107 VMXNET3State
*s
= VMXNET3(pci_dev
);
2109 VMW_CBPRN("Starting uninit...");
2111 unregister_savevm(dev
, "vmxnet3-msix", s
);
2113 vmxnet3_net_uninit(s
);
2115 vmxnet3_cleanup_msix(s
);
2117 vmxnet3_cleanup_msi(s
);
2119 memory_region_destroy(&s
->bar0
);
2120 memory_region_destroy(&s
->bar1
);
2121 memory_region_destroy(&s
->msix_bar
);
2124 static void vmxnet3_qdev_reset(DeviceState
*dev
)
2126 PCIDevice
*d
= PCI_DEVICE(dev
);
2127 VMXNET3State
*s
= VMXNET3(d
);
2129 VMW_CBPRN("Starting QDEV reset...");
2133 static bool vmxnet3_mc_list_needed(void *opaque
)
2138 static int vmxnet3_mcast_list_pre_load(void *opaque
)
2140 VMXNET3State
*s
= opaque
;
2142 s
->mcast_list
= g_malloc(s
->mcast_list_buff_size
);
2148 static void vmxnet3_pre_save(void *opaque
)
2150 VMXNET3State
*s
= opaque
;
2152 s
->mcast_list_buff_size
= s
->mcast_list_len
* sizeof(MACAddr
);
2155 static const VMStateDescription vmxstate_vmxnet3_mcast_list
= {
2156 .name
= "vmxnet3/mcast_list",
2158 .minimum_version_id
= 1,
2159 .minimum_version_id_old
= 1,
2160 .pre_load
= vmxnet3_mcast_list_pre_load
,
2161 .fields
= (VMStateField
[]) {
2162 VMSTATE_VBUFFER_UINT32(mcast_list
, VMXNET3State
, 0, NULL
, 0,
2163 mcast_list_buff_size
),
2164 VMSTATE_END_OF_LIST()
2168 static void vmxnet3_get_ring_from_file(QEMUFile
*f
, Vmxnet3Ring
*r
)
2170 r
->pa
= qemu_get_be64(f
);
2171 r
->size
= qemu_get_be32(f
);
2172 r
->cell_size
= qemu_get_be32(f
);
2173 r
->next
= qemu_get_be32(f
);
2174 r
->gen
= qemu_get_byte(f
);
2177 static void vmxnet3_put_ring_to_file(QEMUFile
*f
, Vmxnet3Ring
*r
)
2179 qemu_put_be64(f
, r
->pa
);
2180 qemu_put_be32(f
, r
->size
);
2181 qemu_put_be32(f
, r
->cell_size
);
2182 qemu_put_be32(f
, r
->next
);
2183 qemu_put_byte(f
, r
->gen
);
2186 static void vmxnet3_get_tx_stats_from_file(QEMUFile
*f
,
2187 struct UPT1_TxStats
*tx_stat
)
2189 tx_stat
->TSOPktsTxOK
= qemu_get_be64(f
);
2190 tx_stat
->TSOBytesTxOK
= qemu_get_be64(f
);
2191 tx_stat
->ucastPktsTxOK
= qemu_get_be64(f
);
2192 tx_stat
->ucastBytesTxOK
= qemu_get_be64(f
);
2193 tx_stat
->mcastPktsTxOK
= qemu_get_be64(f
);
2194 tx_stat
->mcastBytesTxOK
= qemu_get_be64(f
);
2195 tx_stat
->bcastPktsTxOK
= qemu_get_be64(f
);
2196 tx_stat
->bcastBytesTxOK
= qemu_get_be64(f
);
2197 tx_stat
->pktsTxError
= qemu_get_be64(f
);
2198 tx_stat
->pktsTxDiscard
= qemu_get_be64(f
);
2201 static void vmxnet3_put_tx_stats_to_file(QEMUFile
*f
,
2202 struct UPT1_TxStats
*tx_stat
)
2204 qemu_put_be64(f
, tx_stat
->TSOPktsTxOK
);
2205 qemu_put_be64(f
, tx_stat
->TSOBytesTxOK
);
2206 qemu_put_be64(f
, tx_stat
->ucastPktsTxOK
);
2207 qemu_put_be64(f
, tx_stat
->ucastBytesTxOK
);
2208 qemu_put_be64(f
, tx_stat
->mcastPktsTxOK
);
2209 qemu_put_be64(f
, tx_stat
->mcastBytesTxOK
);
2210 qemu_put_be64(f
, tx_stat
->bcastPktsTxOK
);
2211 qemu_put_be64(f
, tx_stat
->bcastBytesTxOK
);
2212 qemu_put_be64(f
, tx_stat
->pktsTxError
);
2213 qemu_put_be64(f
, tx_stat
->pktsTxDiscard
);
2216 static int vmxnet3_get_txq_descr(QEMUFile
*f
, void *pv
, size_t size
)
2218 Vmxnet3TxqDescr
*r
= pv
;
2220 vmxnet3_get_ring_from_file(f
, &r
->tx_ring
);
2221 vmxnet3_get_ring_from_file(f
, &r
->comp_ring
);
2222 r
->intr_idx
= qemu_get_byte(f
);
2223 r
->tx_stats_pa
= qemu_get_be64(f
);
2225 vmxnet3_get_tx_stats_from_file(f
, &r
->txq_stats
);
2230 static void vmxnet3_put_txq_descr(QEMUFile
*f
, void *pv
, size_t size
)
2232 Vmxnet3TxqDescr
*r
= pv
;
2234 vmxnet3_put_ring_to_file(f
, &r
->tx_ring
);
2235 vmxnet3_put_ring_to_file(f
, &r
->comp_ring
);
2236 qemu_put_byte(f
, r
->intr_idx
);
2237 qemu_put_be64(f
, r
->tx_stats_pa
);
2238 vmxnet3_put_tx_stats_to_file(f
, &r
->txq_stats
);
2241 const VMStateInfo txq_descr_info
= {
2242 .name
= "txq_descr",
2243 .get
= vmxnet3_get_txq_descr
,
2244 .put
= vmxnet3_put_txq_descr
2247 static void vmxnet3_get_rx_stats_from_file(QEMUFile
*f
,
2248 struct UPT1_RxStats
*rx_stat
)
2250 rx_stat
->LROPktsRxOK
= qemu_get_be64(f
);
2251 rx_stat
->LROBytesRxOK
= qemu_get_be64(f
);
2252 rx_stat
->ucastPktsRxOK
= qemu_get_be64(f
);
2253 rx_stat
->ucastBytesRxOK
= qemu_get_be64(f
);
2254 rx_stat
->mcastPktsRxOK
= qemu_get_be64(f
);
2255 rx_stat
->mcastBytesRxOK
= qemu_get_be64(f
);
2256 rx_stat
->bcastPktsRxOK
= qemu_get_be64(f
);
2257 rx_stat
->bcastBytesRxOK
= qemu_get_be64(f
);
2258 rx_stat
->pktsRxOutOfBuf
= qemu_get_be64(f
);
2259 rx_stat
->pktsRxError
= qemu_get_be64(f
);
2262 static void vmxnet3_put_rx_stats_to_file(QEMUFile
*f
,
2263 struct UPT1_RxStats
*rx_stat
)
2265 qemu_put_be64(f
, rx_stat
->LROPktsRxOK
);
2266 qemu_put_be64(f
, rx_stat
->LROBytesRxOK
);
2267 qemu_put_be64(f
, rx_stat
->ucastPktsRxOK
);
2268 qemu_put_be64(f
, rx_stat
->ucastBytesRxOK
);
2269 qemu_put_be64(f
, rx_stat
->mcastPktsRxOK
);
2270 qemu_put_be64(f
, rx_stat
->mcastBytesRxOK
);
2271 qemu_put_be64(f
, rx_stat
->bcastPktsRxOK
);
2272 qemu_put_be64(f
, rx_stat
->bcastBytesRxOK
);
2273 qemu_put_be64(f
, rx_stat
->pktsRxOutOfBuf
);
2274 qemu_put_be64(f
, rx_stat
->pktsRxError
);
2277 static int vmxnet3_get_rxq_descr(QEMUFile
*f
, void *pv
, size_t size
)
2279 Vmxnet3RxqDescr
*r
= pv
;
2282 for (i
= 0; i
< VMXNET3_RX_RINGS_PER_QUEUE
; i
++) {
2283 vmxnet3_get_ring_from_file(f
, &r
->rx_ring
[i
]);
2286 vmxnet3_get_ring_from_file(f
, &r
->comp_ring
);
2287 r
->intr_idx
= qemu_get_byte(f
);
2288 r
->rx_stats_pa
= qemu_get_be64(f
);
2290 vmxnet3_get_rx_stats_from_file(f
, &r
->rxq_stats
);
2295 static void vmxnet3_put_rxq_descr(QEMUFile
*f
, void *pv
, size_t size
)
2297 Vmxnet3RxqDescr
*r
= pv
;
2300 for (i
= 0; i
< VMXNET3_RX_RINGS_PER_QUEUE
; i
++) {
2301 vmxnet3_put_ring_to_file(f
, &r
->rx_ring
[i
]);
2304 vmxnet3_put_ring_to_file(f
, &r
->comp_ring
);
2305 qemu_put_byte(f
, r
->intr_idx
);
2306 qemu_put_be64(f
, r
->rx_stats_pa
);
2307 vmxnet3_put_rx_stats_to_file(f
, &r
->rxq_stats
);
2310 static int vmxnet3_post_load(void *opaque
, int version_id
)
2312 VMXNET3State
*s
= opaque
;
2313 PCIDevice
*d
= PCI_DEVICE(s
);
2315 vmxnet_tx_pkt_init(&s
->tx_pkt
, s
->max_tx_frags
, s
->peer_has_vhdr
);
2316 vmxnet_rx_pkt_init(&s
->rx_pkt
, s
->peer_has_vhdr
);
2319 if (!vmxnet3_use_msix_vectors(s
, VMXNET3_MAX_INTRS
)) {
2320 VMW_WRPRN("Failed to re-use MSI-X vectors");
2321 msix_uninit(d
, &s
->msix_bar
, &s
->msix_bar
);
2322 s
->msix_used
= false;
2330 const VMStateInfo rxq_descr_info
= {
2331 .name
= "rxq_descr",
2332 .get
= vmxnet3_get_rxq_descr
,
2333 .put
= vmxnet3_put_rxq_descr
2336 static int vmxnet3_get_int_state(QEMUFile
*f
, void *pv
, size_t size
)
2338 Vmxnet3IntState
*r
= pv
;
2340 r
->is_masked
= qemu_get_byte(f
);
2341 r
->is_pending
= qemu_get_byte(f
);
2342 r
->is_asserted
= qemu_get_byte(f
);
2347 static void vmxnet3_put_int_state(QEMUFile
*f
, void *pv
, size_t size
)
2349 Vmxnet3IntState
*r
= pv
;
2351 qemu_put_byte(f
, r
->is_masked
);
2352 qemu_put_byte(f
, r
->is_pending
);
2353 qemu_put_byte(f
, r
->is_asserted
);
2356 const VMStateInfo int_state_info
= {
2357 .name
= "int_state",
2358 .get
= vmxnet3_get_int_state
,
2359 .put
= vmxnet3_put_int_state
2362 static const VMStateDescription vmstate_vmxnet3
= {
2365 .minimum_version_id
= 1,
2366 .minimum_version_id_old
= 1,
2367 .pre_save
= vmxnet3_pre_save
,
2368 .post_load
= vmxnet3_post_load
,
2369 .fields
= (VMStateField
[]) {
2370 VMSTATE_PCI_DEVICE(parent_obj
, VMXNET3State
),
2371 VMSTATE_BOOL(rx_packets_compound
, VMXNET3State
),
2372 VMSTATE_BOOL(rx_vlan_stripping
, VMXNET3State
),
2373 VMSTATE_BOOL(lro_supported
, VMXNET3State
),
2374 VMSTATE_UINT32(rx_mode
, VMXNET3State
),
2375 VMSTATE_UINT32(mcast_list_len
, VMXNET3State
),
2376 VMSTATE_UINT32(mcast_list_buff_size
, VMXNET3State
),
2377 VMSTATE_UINT32_ARRAY(vlan_table
, VMXNET3State
, VMXNET3_VFT_SIZE
),
2378 VMSTATE_UINT32(mtu
, VMXNET3State
),
2379 VMSTATE_UINT16(max_rx_frags
, VMXNET3State
),
2380 VMSTATE_UINT32(max_tx_frags
, VMXNET3State
),
2381 VMSTATE_UINT8(event_int_idx
, VMXNET3State
),
2382 VMSTATE_BOOL(auto_int_masking
, VMXNET3State
),
2383 VMSTATE_UINT8(txq_num
, VMXNET3State
),
2384 VMSTATE_UINT8(rxq_num
, VMXNET3State
),
2385 VMSTATE_UINT32(device_active
, VMXNET3State
),
2386 VMSTATE_UINT32(last_command
, VMXNET3State
),
2387 VMSTATE_UINT32(link_status_and_speed
, VMXNET3State
),
2388 VMSTATE_UINT32(temp_mac
, VMXNET3State
),
2389 VMSTATE_UINT64(drv_shmem
, VMXNET3State
),
2390 VMSTATE_UINT64(temp_shared_guest_driver_memory
, VMXNET3State
),
2392 VMSTATE_ARRAY(txq_descr
, VMXNET3State
,
2393 VMXNET3_DEVICE_MAX_TX_QUEUES
, 0, txq_descr_info
,
2395 VMSTATE_ARRAY(rxq_descr
, VMXNET3State
,
2396 VMXNET3_DEVICE_MAX_RX_QUEUES
, 0, rxq_descr_info
,
2398 VMSTATE_ARRAY(interrupt_states
, VMXNET3State
, VMXNET3_MAX_INTRS
,
2399 0, int_state_info
, Vmxnet3IntState
),
2401 VMSTATE_END_OF_LIST()
2403 .subsections
= (VMStateSubsection
[]) {
2405 .vmsd
= &vmxstate_vmxnet3_mcast_list
,
2406 .needed
= vmxnet3_mc_list_needed
2409 /* empty element. */
2415 vmxnet3_write_config(PCIDevice
*pci_dev
, uint32_t addr
, uint32_t val
, int len
)
2417 pci_default_write_config(pci_dev
, addr
, val
, len
);
2418 msix_write_config(pci_dev
, addr
, val
, len
);
2419 msi_write_config(pci_dev
, addr
, val
, len
);
2422 static Property vmxnet3_properties
[] = {
2423 DEFINE_NIC_PROPERTIES(VMXNET3State
, conf
),
2424 DEFINE_PROP_END_OF_LIST(),
2427 static void vmxnet3_class_init(ObjectClass
*class, void *data
)
2429 DeviceClass
*dc
= DEVICE_CLASS(class);
2430 PCIDeviceClass
*c
= PCI_DEVICE_CLASS(class);
2432 c
->init
= vmxnet3_pci_init
;
2433 c
->exit
= vmxnet3_pci_uninit
;
2434 c
->vendor_id
= PCI_VENDOR_ID_VMWARE
;
2435 c
->device_id
= PCI_DEVICE_ID_VMWARE_VMXNET3
;
2436 c
->revision
= PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION
;
2437 c
->class_id
= PCI_CLASS_NETWORK_ETHERNET
;
2438 c
->subsystem_vendor_id
= PCI_VENDOR_ID_VMWARE
;
2439 c
->subsystem_id
= PCI_DEVICE_ID_VMWARE_VMXNET3
;
2440 c
->config_write
= vmxnet3_write_config
,
2441 dc
->desc
= "VMWare Paravirtualized Ethernet v3";
2442 dc
->reset
= vmxnet3_qdev_reset
;
2443 dc
->vmsd
= &vmstate_vmxnet3
;
2444 dc
->props
= vmxnet3_properties
;
2447 static const TypeInfo vmxnet3_info
= {
2448 .name
= TYPE_VMXNET3
,
2449 .parent
= TYPE_PCI_DEVICE
,
2450 .instance_size
= sizeof(VMXNET3State
),
2451 .class_init
= vmxnet3_class_init
,
2454 static void vmxnet3_register_types(void)
2456 VMW_CBPRN("vmxnet3_register_types called...");
2457 type_register_static(&vmxnet3_info
);
2460 type_init(vmxnet3_register_types
)