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pc: limit 64 bit hole to 2G by default
[qemu.git] / include / hw / i386 / pc.h
1 #ifndef HW_PC_H
2 #define HW_PC_H
3
4 #include "qemu-common.h"
5 #include "exec/memory.h"
6 #include "hw/isa/isa.h"
7 #include "hw/block/fdc.h"
8 #include "net/net.h"
9 #include "hw/i386/ioapic.h"
10
11 #include "qemu/range.h"
12
13 /* PC-style peripherals (also used by other machines). */
14
15 typedef struct PcPciInfo {
16 Range w32;
17 Range w64;
18 } PcPciInfo;
19
20 struct PcGuestInfo {
21 bool has_pci_info;
22 FWCfgState *fw_cfg;
23 };
24
25 /* parallel.c */
26 static inline bool parallel_init(ISABus *bus, int index, CharDriverState *chr)
27 {
28 DeviceState *dev;
29 ISADevice *isadev;
30
31 isadev = isa_try_create(bus, "isa-parallel");
32 if (!isadev) {
33 return false;
34 }
35 dev = DEVICE(isadev);
36 qdev_prop_set_uint32(dev, "index", index);
37 qdev_prop_set_chr(dev, "chardev", chr);
38 if (qdev_init(dev) < 0) {
39 return false;
40 }
41 return true;
42 }
43
44 bool parallel_mm_init(MemoryRegion *address_space,
45 hwaddr base, int it_shift, qemu_irq irq,
46 CharDriverState *chr);
47
48 /* i8259.c */
49
50 extern DeviceState *isa_pic;
51 qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq);
52 qemu_irq *kvm_i8259_init(ISABus *bus);
53 int pic_read_irq(DeviceState *d);
54 int pic_get_output(DeviceState *d);
55 void pic_info(Monitor *mon, const QDict *qdict);
56 void irq_info(Monitor *mon, const QDict *qdict);
57
58 /* Global System Interrupts */
59
60 #define GSI_NUM_PINS IOAPIC_NUM_PINS
61
62 typedef struct GSIState {
63 qemu_irq i8259_irq[ISA_NUM_IRQS];
64 qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
65 } GSIState;
66
67 void gsi_handler(void *opaque, int n, int level);
68
69 /* vmport.c */
70 typedef uint32_t (VMPortReadFunc)(void *opaque, uint32_t address);
71
72 static inline void vmport_init(ISABus *bus)
73 {
74 isa_create_simple(bus, "vmport");
75 }
76
77 void vmport_register(unsigned char command, VMPortReadFunc *func, void *opaque);
78 void vmmouse_get_data(uint32_t *data);
79 void vmmouse_set_data(const uint32_t *data);
80
81 /* pckbd.c */
82
83 void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
84 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
85 MemoryRegion *region, ram_addr_t size,
86 hwaddr mask);
87 void i8042_isa_mouse_fake_event(void *opaque);
88 void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out);
89
90 /* pc.c */
91 extern int fd_bootchk;
92
93 void pc_register_ferr_irq(qemu_irq irq);
94 void pc_acpi_smi_interrupt(void *opaque, int irq, int level);
95
96 void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge);
97 void pc_hot_add_cpu(const int64_t id, Error **errp);
98 void pc_acpi_init(const char *default_dsdt);
99
100 PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size,
101 ram_addr_t above_4g_mem_size);
102
103 #define PCI_HOST_PROP_PCI_HOLE_START "pci-hole-start"
104 #define PCI_HOST_PROP_PCI_HOLE_END "pci-hole-end"
105 #define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start"
106 #define PCI_HOST_PROP_PCI_HOLE64_END "pci-hole64-end"
107 #define PCI_HOST_PROP_PCI_HOLE64_SIZE "pci-hole64-size"
108 #define DEFAULT_PCI_HOLE64_SIZE (1ULL << 31)
109
110 void pc_init_pci64_hole(PcPciInfo *pci_info, uint64_t pci_hole64_start,
111 uint64_t pci_hole64_size);
112
113 FWCfgState *pc_memory_init(MemoryRegion *system_memory,
114 const char *kernel_filename,
115 const char *kernel_cmdline,
116 const char *initrd_filename,
117 ram_addr_t below_4g_mem_size,
118 ram_addr_t above_4g_mem_size,
119 MemoryRegion *rom_memory,
120 MemoryRegion **ram_memory,
121 PcGuestInfo *guest_info);
122 qemu_irq *pc_allocate_cpu_irq(void);
123 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus);
124 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
125 ISADevice **rtc_state,
126 ISADevice **floppy,
127 bool no_vmport);
128 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd);
129 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
130 const char *boot_device,
131 ISADevice *floppy, BusState *ide0, BusState *ide1,
132 ISADevice *s);
133 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus);
134 void pc_pci_device_init(PCIBus *pci_bus);
135
136 typedef void (*cpu_set_smm_t)(int smm, void *arg);
137 void cpu_smm_register(cpu_set_smm_t callback, void *arg);
138
139 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name);
140
141 /* acpi_piix.c */
142
143 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
144 qemu_irq sci_irq, qemu_irq smi_irq,
145 int kvm_enabled, FWCfgState *fw_cfg);
146 void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
147
148 /* hpet.c */
149 extern int no_hpet;
150
151 /* piix_pci.c */
152 struct PCII440FXState;
153 typedef struct PCII440FXState PCII440FXState;
154
155 PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn,
156 ISABus **isa_bus, qemu_irq *pic,
157 MemoryRegion *address_space_mem,
158 MemoryRegion *address_space_io,
159 ram_addr_t ram_size,
160 hwaddr pci_hole_start,
161 hwaddr pci_hole_size,
162 ram_addr_t above_4g_mem_size,
163 MemoryRegion *pci_memory,
164 MemoryRegion *ram_memory);
165
166 /* piix4.c */
167 extern PCIDevice *piix4_dev;
168 int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
169
170 /* vga.c */
171 enum vga_retrace_method {
172 VGA_RETRACE_DUMB,
173 VGA_RETRACE_PRECISE
174 };
175
176 extern enum vga_retrace_method vga_retrace_method;
177
178 int isa_vga_mm_init(hwaddr vram_base,
179 hwaddr ctrl_base, int it_shift,
180 MemoryRegion *address_space);
181
182 /* ne2000.c */
183 static inline bool isa_ne2000_init(ISABus *bus, int base, int irq, NICInfo *nd)
184 {
185 DeviceState *dev;
186 ISADevice *isadev;
187
188 qemu_check_nic_model(nd, "ne2k_isa");
189
190 isadev = isa_try_create(bus, "ne2k_isa");
191 if (!isadev) {
192 return false;
193 }
194 dev = DEVICE(isadev);
195 qdev_prop_set_uint32(dev, "iobase", base);
196 qdev_prop_set_uint32(dev, "irq", irq);
197 qdev_set_nic_properties(dev, nd);
198 qdev_init_nofail(dev);
199 return true;
200 }
201
202 /* pc_sysfw.c */
203 void pc_system_firmware_init(MemoryRegion *rom_memory);
204
205 /* pvpanic.c */
206 void pvpanic_init(ISABus *bus);
207
208 /* e820 types */
209 #define E820_RAM 1
210 #define E820_RESERVED 2
211 #define E820_ACPI 3
212 #define E820_NVS 4
213 #define E820_UNUSABLE 5
214
215 int e820_add_entry(uint64_t, uint64_t, uint32_t);
216
217 #define PC_COMPAT_1_5 \
218 {\
219 .driver = "Conroe-" TYPE_X86_CPU,\
220 .property = "model",\
221 .value = stringify(2),\
222 },{\
223 .driver = "Conroe-" TYPE_X86_CPU,\
224 .property = "level",\
225 .value = stringify(2),\
226 },{\
227 .driver = "Penryn-" TYPE_X86_CPU,\
228 .property = "model",\
229 .value = stringify(2),\
230 },{\
231 .driver = "Penryn-" TYPE_X86_CPU,\
232 .property = "level",\
233 .value = stringify(2),\
234 },{\
235 .driver = "Nehalem-" TYPE_X86_CPU,\
236 .property = "model",\
237 .value = stringify(2),\
238 },{\
239 .driver = "Nehalem-" TYPE_X86_CPU,\
240 .property = "level",\
241 .value = stringify(2),\
242 },{\
243 .driver = "virtio-net-pci",\
244 .property = "any_layout",\
245 .value = "off",\
246 },{\
247 .driver = TYPE_X86_CPU,\
248 .property = "pmu",\
249 .value = "on",\
250 }
251
252 #define PC_COMPAT_1_4 \
253 PC_COMPAT_1_5, \
254 {\
255 .driver = "scsi-hd",\
256 .property = "discard_granularity",\
257 .value = stringify(0),\
258 },{\
259 .driver = "scsi-cd",\
260 .property = "discard_granularity",\
261 .value = stringify(0),\
262 },{\
263 .driver = "scsi-disk",\
264 .property = "discard_granularity",\
265 .value = stringify(0),\
266 },{\
267 .driver = "ide-hd",\
268 .property = "discard_granularity",\
269 .value = stringify(0),\
270 },{\
271 .driver = "ide-cd",\
272 .property = "discard_granularity",\
273 .value = stringify(0),\
274 },{\
275 .driver = "ide-drive",\
276 .property = "discard_granularity",\
277 .value = stringify(0),\
278 },{\
279 .driver = "virtio-blk-pci",\
280 .property = "discard_granularity",\
281 .value = stringify(0),\
282 },{\
283 .driver = "virtio-serial-pci",\
284 .property = "vectors",\
285 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string */\
286 .value = stringify(0xFFFFFFFF),\
287 },{ \
288 .driver = "virtio-net-pci", \
289 .property = "ctrl_guest_offloads", \
290 .value = "off", \
291 },{\
292 .driver = "e1000",\
293 .property = "romfile",\
294 .value = "pxe-e1000.rom",\
295 },{\
296 .driver = "ne2k_pci",\
297 .property = "romfile",\
298 .value = "pxe-ne2k_pci.rom",\
299 },{\
300 .driver = "pcnet",\
301 .property = "romfile",\
302 .value = "pxe-pcnet.rom",\
303 },{\
304 .driver = "rtl8139",\
305 .property = "romfile",\
306 .value = "pxe-rtl8139.rom",\
307 },{\
308 .driver = "virtio-net-pci",\
309 .property = "romfile",\
310 .value = "pxe-virtio.rom",\
311 },{\
312 .driver = "486-" TYPE_X86_CPU,\
313 .property = "model",\
314 .value = stringify(0),\
315 }
316
317 #endif