include/hw/pci/pci.h

   1 #ifndef QEMU_PCI_H
   2 #define QEMU_PCI_H
   3
   4 #include "qemu-common.h"
   5
   6 #include "hw/qdev.h"
   7 #include "exec/memory.h"
   8 #include "sysemu/dma.h"
   9
  10 /* PCI includes legacy ISA access.  */
  11 #include "hw/isa/isa.h"
  12
  13 #include "hw/pci/pcie.h"
  14
  15 /* PCI bus */
  16
  17 #define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
  18 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  19 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
  20 #define PCI_SLOT_MAX            32
  21 #define PCI_FUNC_MAX            8
  22
  23 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
  24 #include "hw/pci/pci_ids.h"
  25
  26 /* QEMU-specific Vendor and Device ID definitions */
  27
  28 /* IBM (0x1014) */
  29 #define PCI_DEVICE_ID_IBM_440GX          0x027f
  30 #define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
  31
  32 /* Hitachi (0x1054) */
  33 #define PCI_VENDOR_ID_HITACHI            0x1054
  34 #define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e
  35
  36 /* Apple (0x106b) */
  37 #define PCI_DEVICE_ID_APPLE_343S1201     0x0010
  38 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
  39 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
  40 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
  41 #define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f
  42
  43 /* Realtek (0x10ec) */
  44 #define PCI_DEVICE_ID_REALTEK_8029       0x8029
  45
  46 /* Xilinx (0x10ee) */
  47 #define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300
  48
  49 /* Marvell (0x11ab) */
  50 #define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620
  51
  52 /* QEMU/Bochs VGA (0x1234) */
  53 #define PCI_VENDOR_ID_QEMU               0x1234
  54 #define PCI_DEVICE_ID_QEMU_VGA           0x1111
  55
  56 /* VMWare (0x15ad) */
  57 #define PCI_VENDOR_ID_VMWARE             0x15ad
  58 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
  59 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
  60 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
  61 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
  62 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
  63 #define PCI_DEVICE_ID_VMWARE_VMXNET3     0x07B0
  64
  65 /* Intel (0x8086) */
  66 #define PCI_DEVICE_ID_INTEL_82551IT      0x1209
  67 #define PCI_DEVICE_ID_INTEL_82557        0x1229
  68 #define PCI_DEVICE_ID_INTEL_82801IR      0x2922
  69
  70 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
  71 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
  72 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
  73 #define PCI_SUBDEVICE_ID_QEMU            0x1100
  74
  75 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
  76 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
  77 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
  78 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
  79 #define PCI_DEVICE_ID_VIRTIO_SCSI        0x1004
  80 #define PCI_DEVICE_ID_VIRTIO_RNG         0x1005
  81 #define PCI_DEVICE_ID_VIRTIO_9P          0x1009
  82
  83 #define PCI_VENDOR_ID_REDHAT             0x1b36
  84 #define PCI_DEVICE_ID_REDHAT_BRIDGE      0x0001
  85 #define PCI_DEVICE_ID_REDHAT_SERIAL      0x0002
  86 #define PCI_DEVICE_ID_REDHAT_SERIAL2     0x0003
  87 #define PCI_DEVICE_ID_REDHAT_SERIAL4     0x0004
  88 #define PCI_DEVICE_ID_REDHAT_TEST        0x0005
  89 #define PCI_DEVICE_ID_REDHAT_QXL         0x0100
  90
  91 #define FMT_PCIBUS                      PRIx64
  92
  93 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
  94                                 uint32_t address, uint32_t data, int len);
  95 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
  96                                    uint32_t address, int len);
  97 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
  98                                 pcibus_t addr, pcibus_t size, int type);
  99 typedef void PCIUnregisterFunc(PCIDevice *pci_dev);
 100
 101 typedef struct PCIIORegion {
 102     pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
 103 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
 104     pcibus_t size;
 105     uint8_t type;
 106     MemoryRegion *memory;
 107     MemoryRegion *address_space;
 108 } PCIIORegion;
 109
 110 #define PCI_ROM_SLOT 6
 111 #define PCI_NUM_REGIONS 7
 112
 113 enum {
 114     QEMU_PCI_VGA_MEM,
 115     QEMU_PCI_VGA_IO_LO,
 116     QEMU_PCI_VGA_IO_HI,
 117     QEMU_PCI_VGA_NUM_REGIONS,
 118 };
 119
 120 #define QEMU_PCI_VGA_MEM_BASE 0xa0000
 121 #define QEMU_PCI_VGA_MEM_SIZE 0x20000
 122 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0
 123 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc
 124 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0
 125 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20
 126
 127 #include "hw/pci/pci_regs.h"
 128
 129 /* PCI HEADER_TYPE */
 130 #define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
 131
 132 /* Size of the standard PCI config header */
 133 #define PCI_CONFIG_HEADER_SIZE 0x40
 134 /* Size of the standard PCI config space */
 135 #define PCI_CONFIG_SPACE_SIZE 0x100
 136 /* Size of the standart PCIe config space: 4KB */
 137 #define PCIE_CONFIG_SPACE_SIZE  0x1000
 138
 139 #define PCI_NUM_PINS 4 /* A-D */
 140
 141 /* Bits in cap_present field. */
 142 enum {
 143     QEMU_PCI_CAP_MSI = 0x1,
 144     QEMU_PCI_CAP_MSIX = 0x2,
 145     QEMU_PCI_CAP_EXPRESS = 0x4,
 146
 147     /* multifunction capable device */
 148 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR        3
 149     QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
 150
 151     /* command register SERR bit enabled */
 152 #define QEMU_PCI_CAP_SERR_BITNR 4
 153     QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
 154     /* Standard hot plug controller. */
 155 #define QEMU_PCI_SHPC_BITNR 5
 156     QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
 157 #define QEMU_PCI_SLOTID_BITNR 6
 158     QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR),
 159 };
 160
 161 #define TYPE_PCI_DEVICE "pci-device"
 162 #define PCI_DEVICE(obj) \
 163      OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE)
 164 #define PCI_DEVICE_CLASS(klass) \
 165      OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE)
 166 #define PCI_DEVICE_GET_CLASS(obj) \
 167      OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE)
 168
 169 typedef struct PCIINTxRoute {
 170     enum {
 171         PCI_INTX_ENABLED,
 172         PCI_INTX_INVERTED,
 173         PCI_INTX_DISABLED,
 174     } mode;
 175     int irq;
 176 } PCIINTxRoute;
 177
 178 typedef struct PCIDeviceClass {
 179     DeviceClass parent_class;
 180
 181     int (*init)(PCIDevice *dev);
 182     PCIUnregisterFunc *exit;
 183     PCIConfigReadFunc *config_read;
 184     PCIConfigWriteFunc *config_write;
 185
 186     uint16_t vendor_id;
 187     uint16_t device_id;
 188     uint8_t revision;
 189     uint16_t class_id;
 190     uint16_t subsystem_vendor_id;       /* only for header type = 0 */
 191     uint16_t subsystem_id;              /* only for header type = 0 */
 192
 193     /*
 194      * pci-to-pci bridge or normal device.
 195      * This doesn't mean pci host switch.
 196      * When card bus bridge is supported, this would be enhanced.
 197      */
 198     int is_bridge;
 199
 200     /* pcie stuff */
 201     int is_express;   /* is this device pci express? */
 202
 203     /* device isn't hot-pluggable */
 204     int no_hotplug;
 205
 206     /* rom bar */
 207     const char *romfile;
 208 } PCIDeviceClass;
 209
 210 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev);
 211 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector,
 212                                       MSIMessage msg);
 213 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector);
 214 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev,
 215                                       unsigned int vector_start,
 216                                       unsigned int vector_end);
 217
 218 struct PCIDevice {
 219     DeviceState qdev;
 220
 221     /* PCI config space */
 222     uint8_t *config;
 223
 224     /* Used to enable config checks on load. Note that writable bits are
 225      * never checked even if set in cmask. */
 226     uint8_t *cmask;
 227
 228     /* Used to implement R/W bytes */
 229     uint8_t *wmask;
 230
 231     /* Used to implement RW1C(Write 1 to Clear) bytes */
 232     uint8_t *w1cmask;
 233
 234     /* Used to allocate config space for capabilities. */
 235     uint8_t *used;
 236
 237     /* the following fields are read only */
 238     PCIBus *bus;
 239     int32_t devfn;
 240     char name[64];
 241     PCIIORegion io_regions[PCI_NUM_REGIONS];
 242     AddressSpace bus_master_as;
 243     MemoryRegion bus_master_enable_region;
 244     DMAContext *dma;
 245
 246     /* do not access the following fields */
 247     PCIConfigReadFunc *config_read;
 248     PCIConfigWriteFunc *config_write;
 249
 250     /* IRQ objects for the INTA-INTD pins.  */
 251     qemu_irq *irq;
 252
 253     /* Legacy PCI VGA regions */
 254     MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS];
 255     bool has_vga;
 256
 257     /* Current IRQ levels.  Used internally by the generic PCI code.  */
 258     uint8_t irq_state;
 259
 260     /* Capability bits */
 261     uint32_t cap_present;
 262
 263     /* Offset of MSI-X capability in config space */
 264     uint8_t msix_cap;
 265
 266     /* MSI-X entries */
 267     int msix_entries_nr;
 268
 269     /* Space to store MSIX table & pending bit array */
 270     uint8_t *msix_table;
 271     uint8_t *msix_pba;
 272     /* MemoryRegion container for msix exclusive BAR setup */
 273     MemoryRegion msix_exclusive_bar;
 274     /* Memory Regions for MSIX table and pending bit entries. */
 275     MemoryRegion msix_table_mmio;
 276     MemoryRegion msix_pba_mmio;
 277     /* Reference-count for entries actually in use by driver. */
 278     unsigned *msix_entry_used;
 279     /* MSIX function mask set or MSIX disabled */
 280     bool msix_function_masked;
 281     /* Version id needed for VMState */
 282     int32_t version_id;
 283
 284     /* Offset of MSI capability in config space */
 285     uint8_t msi_cap;
 286
 287     /* PCI Express */
 288     PCIExpressDevice exp;
 289
 290     /* SHPC */
 291     SHPCDevice *shpc;
 292
 293     /* Location of option rom */
 294     char *romfile;
 295     bool has_rom;
 296     MemoryRegion rom;
 297     uint32_t rom_bar;
 298
 299     /* INTx routing notifier */
 300     PCIINTxRoutingNotifier intx_routing_notifier;
 301
 302     /* MSI-X notifiers */
 303     MSIVectorUseNotifier msix_vector_use_notifier;
 304     MSIVectorReleaseNotifier msix_vector_release_notifier;
 305     MSIVectorPollNotifier msix_vector_poll_notifier;
 306 };
 307
 308 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 309                       uint8_t attr, MemoryRegion *memory);
 310 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
 311                       MemoryRegion *io_lo, MemoryRegion *io_hi);
 312 void pci_unregister_vga(PCIDevice *pci_dev);
 313 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
 314
 315 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
 316                        uint8_t offset, uint8_t size);
 317
 318 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 319
 320 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
 321
 322
 323 uint32_t pci_default_read_config(PCIDevice *d,
 324                                  uint32_t address, int len);
 325 void pci_default_write_config(PCIDevice *d,
 326                               uint32_t address, uint32_t val, int len);
 327 void pci_device_save(PCIDevice *s, QEMUFile *f);
 328 int pci_device_load(PCIDevice *s, QEMUFile *f);
 329 MemoryRegion *pci_address_space(PCIDevice *dev);
 330 MemoryRegion *pci_address_space_io(PCIDevice *dev);
 331
 332 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
 333 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 334 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin);
 335
 336 typedef enum {
 337     PCI_HOTPLUG_DISABLED,
 338     PCI_HOTPLUG_ENABLED,
 339     PCI_COLDPLUG_ENABLED,
 340 } PCIHotplugState;
 341
 342 typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev,
 343                               PCIHotplugState state);
 344
 345 #define TYPE_PCI_BUS "PCI"
 346 #define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS)
 347 #define TYPE_PCIE_BUS "PCIE"
 348
 349 bool pci_bus_is_express(PCIBus *bus);
 350 bool pci_bus_is_root(PCIBus *bus);
 351 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 352                          const char *name,
 353                          MemoryRegion *address_space_mem,
 354                          MemoryRegion *address_space_io,
 355                          uint8_t devfn_min, const char *typename);
 356 PCIBus *pci_bus_new(DeviceState *parent, const char *name,
 357                     MemoryRegion *address_space_mem,
 358                     MemoryRegion *address_space_io,
 359                     uint8_t devfn_min, const char *typename);
 360 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 361                   void *irq_opaque, int nirq);
 362 int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
 363 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
 364 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */
 365 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin);
 366 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 367                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 368                          void *irq_opaque,
 369                          MemoryRegion *address_space_mem,
 370                          MemoryRegion *address_space_io,
 371                          uint8_t devfn_min, int nirq, const char *typename);
 372 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn);
 373 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin);
 374 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new);
 375 void pci_bus_fire_intx_routing_notifier(PCIBus *bus);
 376 void pci_device_set_intx_routing_notifier(PCIDevice *dev,
 377                                           PCIINTxRoutingNotifier notifier);
 378 void pci_device_reset(PCIDevice *dev);
 379 void pci_bus_reset(PCIBus *bus);
 380
 381 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
 382                         const char *default_devaddr);
 383 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
 384                                const char *default_devaddr);
 385
 386 PCIDevice *pci_vga_init(PCIBus *bus);
 387
 388 int pci_bus_num(PCIBus *s);
 389 void pci_for_each_device(PCIBus *bus, int bus_num,
 390                          void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque),
 391                          void *opaque);
 392 PCIBus *pci_find_root_bus(int domain);
 393 int pci_find_domain(const PCIBus *bus);
 394 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
 395 int pci_qdev_find_device(const char *id, PCIDevice **pdev);
 396 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr);
 397
 398 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 399                      unsigned *slotp);
 400
 401 void pci_device_deassert_intx(PCIDevice *dev);
 402
 403 typedef DMAContext *(*PCIDMAContextFunc)(PCIBus *, void *, int);
 404
 405 void pci_setup_iommu(PCIBus *bus, PCIDMAContextFunc fn, void *opaque);
 406
 407 static inline void
 408 pci_set_byte(uint8_t *config, uint8_t val)
 409 {
 410     *config = val;
 411 }
 412
 413 static inline uint8_t
 414 pci_get_byte(const uint8_t *config)
 415 {
 416     return *config;
 417 }
 418
 419 static inline void
 420 pci_set_word(uint8_t *config, uint16_t val)
 421 {
 422     cpu_to_le16wu((uint16_t *)config, val);
 423 }
 424
 425 static inline uint16_t
 426 pci_get_word(const uint8_t *config)
 427 {
 428     return le16_to_cpupu((const uint16_t *)config);
 429 }
 430
 431 static inline void
 432 pci_set_long(uint8_t *config, uint32_t val)
 433 {
 434     cpu_to_le32wu((uint32_t *)config, val);
 435 }
 436
 437 static inline uint32_t
 438 pci_get_long(const uint8_t *config)
 439 {
 440     return le32_to_cpupu((const uint32_t *)config);
 441 }
 442
 443 static inline void
 444 pci_set_quad(uint8_t *config, uint64_t val)
 445 {
 446     cpu_to_le64w((uint64_t *)config, val);
 447 }
 448
 449 static inline uint64_t
 450 pci_get_quad(const uint8_t *config)
 451 {
 452     return le64_to_cpup((const uint64_t *)config);
 453 }
 454
 455 static inline void
 456 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
 457 {
 458     pci_set_word(&pci_config[PCI_VENDOR_ID], val);
 459 }
 460
 461 static inline void
 462 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
 463 {
 464     pci_set_word(&pci_config[PCI_DEVICE_ID], val);
 465 }
 466
 467 static inline void
 468 pci_config_set_revision(uint8_t *pci_config, uint8_t val)
 469 {
 470     pci_set_byte(&pci_config[PCI_REVISION_ID], val);
 471 }
 472
 473 static inline void
 474 pci_config_set_class(uint8_t *pci_config, uint16_t val)
 475 {
 476     pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
 477 }
 478
 479 static inline void
 480 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
 481 {
 482     pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
 483 }
 484
 485 static inline void
 486 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
 487 {
 488     pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
 489 }
 490
 491 /*
 492  * helper functions to do bit mask operation on configuration space.
 493  * Just to set bit, use test-and-set and discard returned value.
 494  * Just to clear bit, use test-and-clear and discard returned value.
 495  * NOTE: They aren't atomic.
 496  */
 497 static inline uint8_t
 498 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
 499 {
 500     uint8_t val = pci_get_byte(config);
 501     pci_set_byte(config, val & ~mask);
 502     return val & mask;
 503 }
 504
 505 static inline uint8_t
 506 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
 507 {
 508     uint8_t val = pci_get_byte(config);
 509     pci_set_byte(config, val | mask);
 510     return val & mask;
 511 }
 512
 513 static inline uint16_t
 514 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
 515 {
 516     uint16_t val = pci_get_word(config);
 517     pci_set_word(config, val & ~mask);
 518     return val & mask;
 519 }
 520
 521 static inline uint16_t
 522 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
 523 {
 524     uint16_t val = pci_get_word(config);
 525     pci_set_word(config, val | mask);
 526     return val & mask;
 527 }
 528
 529 static inline uint32_t
 530 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
 531 {
 532     uint32_t val = pci_get_long(config);
 533     pci_set_long(config, val & ~mask);
 534     return val & mask;
 535 }
 536
 537 static inline uint32_t
 538 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
 539 {
 540     uint32_t val = pci_get_long(config);
 541     pci_set_long(config, val | mask);
 542     return val & mask;
 543 }
 544
 545 static inline uint64_t
 546 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
 547 {
 548     uint64_t val = pci_get_quad(config);
 549     pci_set_quad(config, val & ~mask);
 550     return val & mask;
 551 }
 552
 553 static inline uint64_t
 554 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
 555 {
 556     uint64_t val = pci_get_quad(config);
 557     pci_set_quad(config, val | mask);
 558     return val & mask;
 559 }
 560
 561 /* Access a register specified by a mask */
 562 static inline void
 563 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg)
 564 {
 565     uint8_t val = pci_get_byte(config);
 566     uint8_t rval = reg << (ffs(mask) - 1);
 567     pci_set_byte(config, (~mask & val) | (mask & rval));
 568 }
 569
 570 static inline uint8_t
 571 pci_get_byte_by_mask(uint8_t *config, uint8_t mask)
 572 {
 573     uint8_t val = pci_get_byte(config);
 574     return (val & mask) >> (ffs(mask) - 1);
 575 }
 576
 577 static inline void
 578 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg)
 579 {
 580     uint16_t val = pci_get_word(config);
 581     uint16_t rval = reg << (ffs(mask) - 1);
 582     pci_set_word(config, (~mask & val) | (mask & rval));
 583 }
 584
 585 static inline uint16_t
 586 pci_get_word_by_mask(uint8_t *config, uint16_t mask)
 587 {
 588     uint16_t val = pci_get_word(config);
 589     return (val & mask) >> (ffs(mask) - 1);
 590 }
 591
 592 static inline void
 593 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg)
 594 {
 595     uint32_t val = pci_get_long(config);
 596     uint32_t rval = reg << (ffs(mask) - 1);
 597     pci_set_long(config, (~mask & val) | (mask & rval));
 598 }
 599
 600 static inline uint32_t
 601 pci_get_long_by_mask(uint8_t *config, uint32_t mask)
 602 {
 603     uint32_t val = pci_get_long(config);
 604     return (val & mask) >> (ffs(mask) - 1);
 605 }
 606
 607 static inline void
 608 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg)
 609 {
 610     uint64_t val = pci_get_quad(config);
 611     uint64_t rval = reg << (ffs(mask) - 1);
 612     pci_set_quad(config, (~mask & val) | (mask & rval));
 613 }
 614
 615 static inline uint64_t
 616 pci_get_quad_by_mask(uint8_t *config, uint64_t mask)
 617 {
 618     uint64_t val = pci_get_quad(config);
 619     return (val & mask) >> (ffs(mask) - 1);
 620 }
 621
 622 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
 623                                     const char *name);
 624 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
 625                                            bool multifunction,
 626                                            const char *name);
 627 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
 628 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
 629
 630 static inline int pci_is_express(const PCIDevice *d)
 631 {
 632     return d->cap_present & QEMU_PCI_CAP_EXPRESS;
 633 }
 634
 635 static inline uint32_t pci_config_size(const PCIDevice *d)
 636 {
 637     return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
 638 }
 639
 640 /* DMA access functions */
 641 static inline DMAContext *pci_dma_context(PCIDevice *dev)
 642 {
 643     return dev->dma;
 644 }
 645
 646 static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
 647                              void *buf, dma_addr_t len, DMADirection dir)
 648 {
 649     dma_memory_rw(pci_dma_context(dev), addr, buf, len, dir);
 650     return 0;
 651 }
 652
 653 static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr,
 654                                void *buf, dma_addr_t len)
 655 {
 656     return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE);
 657 }
 658
 659 static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr,
 660                                 const void *buf, dma_addr_t len)
 661 {
 662     return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE);
 663 }
 664
 665 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits)                              \
 666     static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev,      \
 667                                                    dma_addr_t addr)     \
 668     {                                                                   \
 669         return ld##_l##_dma(pci_dma_context(dev), addr);                \
 670     }                                                                   \
 671     static inline void st##_s##_pci_dma(PCIDevice *dev,                 \
 672                                         dma_addr_t addr, uint##_bits##_t val) \
 673     {                                                                   \
 674         st##_s##_dma(pci_dma_context(dev), addr, val);                  \
 675     }
 676
 677 PCI_DMA_DEFINE_LDST(ub, b, 8);
 678 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
 679 PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
 680 PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
 681 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
 682 PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
 683 PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
 684
 685 #undef PCI_DMA_DEFINE_LDST
 686
 687 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr,
 688                                 dma_addr_t *plen, DMADirection dir)
 689 {
 690     void *buf;
 691
 692     buf = dma_memory_map(pci_dma_context(dev), addr, plen, dir);
 693     return buf;
 694 }
 695
 696 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len,
 697                                  DMADirection dir, dma_addr_t access_len)
 698 {
 699     dma_memory_unmap(pci_dma_context(dev), buffer, len, dir, access_len);
 700 }
 701
 702 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev,
 703                                        int alloc_hint)
 704 {
 705     qemu_sglist_init(qsg, alloc_hint, pci_dma_context(dev));
 706 }
 707
 708 extern const VMStateDescription vmstate_pci_device;
 709
 710 #define VMSTATE_PCI_DEVICE(_field, _state) {                         \
 711     .name       = (stringify(_field)),                               \
 712     .size       = sizeof(PCIDevice),                                 \
 713     .vmsd       = &vmstate_pci_device,                               \
 714     .flags      = VMS_STRUCT,                                        \
 715     .offset     = vmstate_offset_value(_state, _field, PCIDevice),   \
 716 }
 717
 718 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) {                 \
 719     .name       = (stringify(_field)),                               \
 720     .size       = sizeof(PCIDevice),                                 \
 721     .vmsd       = &vmstate_pci_device,                               \
 722     .flags      = VMS_STRUCT|VMS_POINTER,                            \
 723     .offset     = vmstate_offset_pointer(_state, _field, PCIDevice), \
 724 }
 725
 726 #endif