1 /* Print SPARC instructions.
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2002 Free Software Foundation, Inc.
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
21 /* The SPARC opcode table (and other related data) is defined in
22 the opcodes library in sparc-opc.c. If you change anything here, make
23 sure you fix up that file, and vice versa. */
25 /* FIXME-someday: perhaps the ,a's and such should be embedded in the
26 instruction's name rather than the args. This would make gas faster, pinsn
27 slower, but would mess up some macros a bit. xoxorich. */
29 /* List of instruction sets variations.
30 These values are such that each element is either a superset of a
31 preceding each one or they conflict in which case SPARC_OPCODE_CONFLICT_P
33 The values are indices into `sparc_opcode_archs' defined in sparc-opc.c.
34 Don't change this without updating sparc-opc.c. */
36 enum sparc_opcode_arch_val
{
37 SPARC_OPCODE_ARCH_V6
= 0,
40 SPARC_OPCODE_ARCH_SPARCLET
,
41 SPARC_OPCODE_ARCH_SPARCLITE
,
42 /* v9 variants must appear last */
44 SPARC_OPCODE_ARCH_V9A
, /* v9 with ultrasparc additions */
45 SPARC_OPCODE_ARCH_V9B
, /* v9 with ultrasparc and cheetah additions */
46 SPARC_OPCODE_ARCH_BAD
/* error return from sparc_opcode_lookup_arch */
49 /* The highest architecture in the table. */
50 #define SPARC_OPCODE_ARCH_MAX (SPARC_OPCODE_ARCH_BAD - 1)
52 /* Given an enum sparc_opcode_arch_val, return the bitmask to use in
53 insn encoding/decoding. */
54 #define SPARC_OPCODE_ARCH_MASK(arch) (1 << (arch))
56 /* Given a valid sparc_opcode_arch_val, return non-zero if it's v9. */
57 #define SPARC_OPCODE_ARCH_V9_P(arch) ((arch) >= SPARC_OPCODE_ARCH_V9)
59 /* Table of cpu variants. */
61 struct sparc_opcode_arch
{
63 /* Mask of sparc_opcode_arch_val's supported.
64 EG: For v7 this would be
65 (SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)).
66 These are short's because sparc_opcode.architecture is. */
70 extern const struct sparc_opcode_arch sparc_opcode_archs
[];
72 /* Given architecture name, look up it's sparc_opcode_arch_val value. */
73 extern enum sparc_opcode_arch_val sparc_opcode_lookup_arch
74 PARAMS ((const char *));
76 /* Return the bitmask of supported architectures for ARCH. */
77 #define SPARC_OPCODE_SUPPORTED(ARCH) (sparc_opcode_archs[ARCH].supported)
79 /* Non-zero if ARCH1 conflicts with ARCH2.
80 IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa. */
81 #define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \
82 (((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
83 != SPARC_OPCODE_SUPPORTED (ARCH1)) \
84 && ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
85 != SPARC_OPCODE_SUPPORTED (ARCH2)))
87 /* Structure of an opcode table entry. */
91 unsigned long match
; /* Bits that must be set. */
92 unsigned long lose
; /* Bits that must not be set. */
94 /* This was called "delayed" in versions before the flags. */
96 short architecture
; /* Bitmask of sparc_opcode_arch_val's. */
99 #define F_DELAYED 1 /* Delayed branch */
100 #define F_ALIAS 2 /* Alias for a "real" instruction */
101 #define F_UNBR 4 /* Unconditional branch */
102 #define F_CONDBR 8 /* Conditional branch */
103 #define F_JSR 16 /* Subroutine call */
104 #define F_FLOAT 32 /* Floating point instruction (not a branch) */
105 #define F_FBR 64 /* Floating point branch */
106 /* FIXME: Add F_ANACHRONISTIC flag for v9. */
110 All sparc opcodes are 32 bits, except for the `set' instruction (really a
111 macro), which is 64 bits. It is handled as a special case.
113 The match component is a mask saying which bits must match a particular
114 opcode in order for an instruction to be an instance of that opcode.
116 The args component is a string containing one character for each operand of the
120 # Number used by optimizer. It is ignored.
124 e frs1 floating point register.
125 v frs1 floating point register (double/even).
126 V frs1 floating point register (quad/multiple of 4).
127 f frs2 floating point register.
128 B frs2 floating point register (double/even).
129 R frs2 floating point register (quad/multiple of 4).
130 g frsd floating point register.
131 H frsd floating point register (double/even).
132 J frsd floating point register (quad/multiple of 4).
133 b crs1 coprocessor register
134 c crs2 coprocessor register
135 D crsd coprocessor register
136 m alternate space register (asr) in rd
137 M alternate space register (asr) in rs1
139 X 5 bit unsigned immediate
140 Y 6 bit unsigned immediate
141 3 SIAM mode (3 bits). (v9b)
142 K MEMBAR mask (7 bits). (v9)
143 j 10 bit Immediate. (v9)
144 I 11 bit Immediate. (v9)
147 k 2+14 bit PC relative immediate. (v9)
148 G 19 bit PC relative immediate. (v9)
149 l 22 bit PC relative immediate.
150 L 30 bit PC relative immediate.
151 a Annul. The annul bit is set.
152 A Alternate address space. Stored as 8 bits.
153 C Coprocessor state register.
154 F floating point state register.
155 p Processor state register.
156 N Branch predict clear ",pn" (v9)
157 T Branch predict set ",pt" (v9)
160 q Floating point queue.
161 r Single register that is both rs1 and rd.
162 O Single register that is both rs2 and rd.
165 t Trap base register.
166 w Window invalid mask register.
168 u sparclet coprocessor registers in rd position
169 U sparclet coprocessor registers in rs1 position
179 ! Privileged Register in rd (v9)
180 ? Privileged Register in rs1 (v9)
181 * Prefetch function constant. (v9)
182 x OPF field (v9 impdep).
183 0 32/64 bit immediate for set or setx (v9) insns
184 _ Ancillary state register in rd (v9a)
185 / Ancillary state register in rs1 (v9a)
187 The following chars are unused: (note: ,[] are used as punctuation)
192 #define OP2(x) (((x)&0x7) << 22) /* op2 field of format2 insns */
193 #define OP3(x) (((x)&0x3f) << 19) /* op3 field of format3 insns */
194 #define OP(x) ((unsigned)((x)&0x3) << 30) /* op field of all insns */
195 #define OPF(x) (((x)&0x1ff) << 5) /* opf field of float insns */
196 #define OPF_LOW5(x) OPF((x)&0x1f) /* v9 */
197 #define F3F(x, y, z) (OP(x) | OP3(y) | OPF(z)) /* format3 float insns */
198 #define F3I(x) (((x)&0x1) << 13) /* immediate field of format 3 insns */
199 #define F2(x, y) (OP(x) | OP2(y)) /* format 2 insns */
200 #define F3(x, y, z) (OP(x) | OP3(y) | F3I(z)) /* format3 insns */
201 #define F1(x) (OP(x))
202 #define DISP30(x) ((x)&0x3fffffff)
203 #define ASI(x) (((x)&0xff) << 5) /* asi field of format3 insns */
204 #define RS2(x) ((x)&0x1f) /* rs2 field */
205 #define SIMM13(x) ((x)&0x1fff) /* simm13 field */
206 #define RD(x) (((x)&0x1f) << 25) /* destination register field */
207 #define RS1(x) (((x)&0x1f) << 14) /* rs1 field */
208 #define ASI_RS2(x) (SIMM13(x))
209 #define MEMBAR(x) ((x)&0x7f)
210 #define SLCPOP(x) (((x)&0x7f) << 6) /* sparclet cpop */
212 #define ANNUL (1<<29)
213 #define BPRED (1<<19) /* v9 */
216 #define RS1_G0 RS1(~0)
217 #define RS2_G0 RS2(~0)
219 extern const struct sparc_opcode sparc_opcodes
[];
220 extern const int sparc_num_opcodes
;
222 extern int sparc_encode_asi
PARAMS ((const char *));
223 extern const char *sparc_decode_asi
PARAMS ((int));
224 extern int sparc_encode_membar
PARAMS ((const char *));
225 extern const char *sparc_decode_membar
PARAMS ((int));
226 extern int sparc_encode_prefetch
PARAMS ((const char *));
227 extern const char *sparc_decode_prefetch
PARAMS ((int));
228 extern int sparc_encode_sparclet_cpreg
PARAMS ((const char *));
229 extern const char *sparc_decode_sparclet_cpreg
PARAMS ((int));
231 /* Some defines to make life easy. */
232 #define MASK_V6 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V6)
233 #define MASK_V7 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V7)
234 #define MASK_V8 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8)
235 #define MASK_SPARCLET SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET)
236 #define MASK_SPARCLITE SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
237 #define MASK_V9 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9)
238 #define MASK_V9A SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)
239 #define MASK_V9B SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B)
241 /* Bit masks of architectures supporting the insn. */
243 #define v6 (MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET \
244 | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
245 /* v6 insns not supported on the sparclet */
246 #define v6notlet (MASK_V6 | MASK_V7 | MASK_V8 \
247 | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
248 #define v7 (MASK_V7 | MASK_V8 | MASK_SPARCLET \
249 | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
250 /* Although not all insns are implemented in hardware, sparclite is defined
251 to be a superset of v8. Unimplemented insns trap and are then theoretically
252 implemented in software.
253 It's not clear that the same is true for sparclet, although the docs
254 suggest it is. Rather than complicating things, the sparclet assembler
255 recognizes all v8 insns. */
256 #define v8 (MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE \
257 | MASK_V9 | MASK_V9A | MASK_V9B)
258 #define sparclet (MASK_SPARCLET)
259 #define sparclite (MASK_SPARCLITE)
260 #define v9 (MASK_V9 | MASK_V9A | MASK_V9B)
261 #define v9a (MASK_V9A | MASK_V9B)
262 #define v9b (MASK_V9B)
263 /* v6 insns not supported by v9 */
264 #define v6notv9 (MASK_V6 | MASK_V7 | MASK_V8 \
265 | MASK_SPARCLET | MASK_SPARCLITE)
266 /* v9a instructions which would appear to be aliases to v9's impdep's
268 #define v9notv9a (MASK_V9)
270 /* Table of opcode architectures.
271 The order is defined in opcode/sparc.h. */
273 const struct sparc_opcode_arch sparc_opcode_archs
[] = {
275 { "v7", MASK_V6
| MASK_V7
},
276 { "v8", MASK_V6
| MASK_V7
| MASK_V8
},
277 { "sparclet", MASK_V6
| MASK_V7
| MASK_V8
| MASK_SPARCLET
},
278 { "sparclite", MASK_V6
| MASK_V7
| MASK_V8
| MASK_SPARCLITE
},
279 /* ??? Don't some v8 priviledged insns conflict with v9? */
280 { "v9", MASK_V6
| MASK_V7
| MASK_V8
| MASK_V9
},
281 /* v9 with ultrasparc additions */
282 { "v9a", MASK_V6
| MASK_V7
| MASK_V8
| MASK_V9
| MASK_V9A
},
283 /* v9 with cheetah additions */
284 { "v9b", MASK_V6
| MASK_V7
| MASK_V8
| MASK_V9
| MASK_V9A
| MASK_V9B
},
288 /* Given NAME, return it's architecture entry. */
290 enum sparc_opcode_arch_val
291 sparc_opcode_lookup_arch (name
)
294 const struct sparc_opcode_arch
*p
;
296 for (p
= &sparc_opcode_archs
[0]; p
->name
; ++p
)
298 if (strcmp (name
, p
->name
) == 0)
299 return (enum sparc_opcode_arch_val
) (p
- &sparc_opcode_archs
[0]);
302 return SPARC_OPCODE_ARCH_BAD
;
305 /* Branch condition field. */
306 #define COND(x) (((x)&0xf)<<25)
308 /* v9: Move (MOVcc and FMOVcc) condition field. */
309 #define MCOND(x,i_or_f) ((((i_or_f)&1)<<18)|(((x)>>11)&(0xf<<14))) /* v9 */
311 /* v9: Move register (MOVRcc and FMOVRcc) condition field. */
312 #define RCOND(x) (((x)&0x7)<<10) /* v9 */
314 #define CONDA (COND(0x8))
315 #define CONDCC (COND(0xd))
316 #define CONDCS (COND(0x5))
317 #define CONDE (COND(0x1))
318 #define CONDG (COND(0xa))
319 #define CONDGE (COND(0xb))
320 #define CONDGU (COND(0xc))
321 #define CONDL (COND(0x3))
322 #define CONDLE (COND(0x2))
323 #define CONDLEU (COND(0x4))
324 #define CONDN (COND(0x0))
325 #define CONDNE (COND(0x9))
326 #define CONDNEG (COND(0x6))
327 #define CONDPOS (COND(0xe))
328 #define CONDVC (COND(0xf))
329 #define CONDVS (COND(0x7))
331 #define CONDNZ CONDNE
333 #define CONDGEU CONDCC
334 #define CONDLU CONDCS
336 #define FCONDA (COND(0x8))
337 #define FCONDE (COND(0x9))
338 #define FCONDG (COND(0x6))
339 #define FCONDGE (COND(0xb))
340 #define FCONDL (COND(0x4))
341 #define FCONDLE (COND(0xd))
342 #define FCONDLG (COND(0x2))
343 #define FCONDN (COND(0x0))
344 #define FCONDNE (COND(0x1))
345 #define FCONDO (COND(0xf))
346 #define FCONDU (COND(0x7))
347 #define FCONDUE (COND(0xa))
348 #define FCONDUG (COND(0x5))
349 #define FCONDUGE (COND(0xc))
350 #define FCONDUL (COND(0x3))
351 #define FCONDULE (COND(0xe))
353 #define FCONDNZ FCONDNE
354 #define FCONDZ FCONDE
356 #define ICC (0) /* v9 */
357 #define XCC (1<<12) /* v9 */
358 #define FCC(x) (((x)&0x3)<<11) /* v9 */
359 #define FBFCC(x) (((x)&0x3)<<20) /* v9 */
361 /* The order of the opcodes in the table is significant:
363 * The assembler requires that all instances of the same mnemonic must
364 be consecutive. If they aren't, the assembler will bomb at runtime.
366 * The disassembler should not care about the order of the opcodes.
370 /* Entries for commutative arithmetic operations. */
371 /* ??? More entries can make use of this. */
372 #define COMMUTEOP(opcode, op3, arch_mask) \
373 { opcode, F3(2, op3, 0), F3(~2, ~op3, ~0)|ASI(~0), "1,2,d", 0, arch_mask }, \
374 { opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "1,i,d", 0, arch_mask }, \
375 { opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "i,1,d", 0, arch_mask }
377 const struct sparc_opcode sparc_opcodes
[] = {
379 { "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", 0, v6
},
380 { "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0
, "[1],d", 0, v6
}, /* ld [rs1+%g0],d */
381 { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", 0, v6
},
382 { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", 0, v6
},
383 { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0
, "[i],d", 0, v6
},
384 { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", 0, v6
}, /* ld [rs1+0],d */
385 { "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0), "[1+2],g", 0, v6
},
386 { "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0)|RS2_G0
, "[1],g", 0, v6
}, /* ld [rs1+%g0],d */
387 { "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[1+i],g", 0, v6
},
388 { "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[i+1],g", 0, v6
},
389 { "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|RS1_G0
, "[i],g", 0, v6
},
390 { "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|SIMM13(~0), "[1],g", 0, v6
}, /* ld [rs1+0],d */
392 { "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RD(~0), "[1+2],F", 0, v6
},
393 { "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RS2_G0
|RD(~0),"[1],F", 0, v6
}, /* ld [rs1+%g0],d */
394 { "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[1+i],F", 0, v6
},
395 { "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[i+1],F", 0, v6
},
396 { "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RS1_G0
|RD(~0),"[i],F", 0, v6
},
397 { "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~0),"[1],F", 0, v6
}, /* ld [rs1+0],d */
399 { "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2],D", 0, v6notv9
},
400 { "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0
, "[1],D", 0, v6notv9
}, /* ld [rs1+%g0],d */
401 { "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i],D", 0, v6notv9
},
402 { "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1],D", 0, v6notv9
},
403 { "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0
, "[i],D", 0, v6notv9
},
404 { "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1],D", 0, v6notv9
}, /* ld [rs1+0],d */
405 { "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0), "[1+2],C", 0, v6notv9
},
406 { "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0)|RS2_G0
, "[1],C", 0, v6notv9
}, /* ld [rs1+%g0],d */
407 { "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[1+i],C", 0, v6notv9
},
408 { "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[i+1],C", 0, v6notv9
},
409 { "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|RS1_G0
, "[i],C", 0, v6notv9
},
410 { "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|SIMM13(~0), "[1],C", 0, v6notv9
}, /* ld [rs1+0],d */
412 /* The v9 LDUW is the same as the old 'ld' opcode, it is not the same as the
413 'ld' pseudo-op in v9. */
414 { "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", F_ALIAS
, v9
},
415 { "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0
, "[1],d", F_ALIAS
, v9
}, /* ld [rs1+%g0],d */
416 { "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", F_ALIAS
, v9
},
417 { "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", F_ALIAS
, v9
},
418 { "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0
, "[i],d", F_ALIAS
, v9
},
419 { "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", F_ALIAS
, v9
}, /* ld [rs1+0],d */
421 { "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0), "[1+2],d", 0, v6
},
422 { "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI_RS2(~0), "[1],d", 0, v6
}, /* ldd [rs1+%g0],d */
423 { "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[1+i],d", 0, v6
},
424 { "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[i+1],d", 0, v6
},
425 { "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|RS1_G0
, "[i],d", 0, v6
},
426 { "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|SIMM13(~0), "[1],d", 0, v6
}, /* ldd [rs1+0],d */
427 { "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI(~0), "[1+2],H", 0, v6
},
428 { "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI_RS2(~0), "[1],H", 0, v6
}, /* ldd [rs1+%g0],d */
429 { "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[1+i],H", 0, v6
},
430 { "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[i+1],H", 0, v6
},
431 { "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|RS1_G0
, "[i],H", 0, v6
},
432 { "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|SIMM13(~0), "[1],H", 0, v6
}, /* ldd [rs1+0],d */
434 { "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI(~0), "[1+2],D", 0, v6notv9
},
435 { "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI_RS2(~0), "[1],D", 0, v6notv9
}, /* ldd [rs1+%g0],d */
436 { "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i],D", 0, v6notv9
},
437 { "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1],D", 0, v6notv9
},
438 { "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0
, "[i],D", 0, v6notv9
},
439 { "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1],D", 0, v6notv9
}, /* ldd [rs1+0],d */
441 { "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI(~0), "[1+2],J", 0, v9
},
442 { "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI_RS2(~0), "[1],J", 0, v9
}, /* ldd [rs1+%g0],d */
443 { "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[1+i],J", 0, v9
},
444 { "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[i+1],J", 0, v9
},
445 { "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|RS1_G0
, "[i],J", 0, v9
},
446 { "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|SIMM13(~0), "[1],J", 0, v9
}, /* ldd [rs1+0],d */
448 { "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI(~0), "[1+2],d", 0, v6
},
449 { "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI_RS2(~0), "[1],d", 0, v6
}, /* ldsb [rs1+%g0],d */
450 { "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[1+i],d", 0, v6
},
451 { "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[i+1],d", 0, v6
},
452 { "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|RS1_G0
, "[i],d", 0, v6
},
453 { "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|SIMM13(~0), "[1],d", 0, v6
}, /* ldsb [rs1+0],d */
455 { "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI_RS2(~0), "[1],d", 0, v6
}, /* ldsh [rs1+%g0],d */
456 { "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI(~0), "[1+2],d", 0, v6
},
457 { "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[1+i],d", 0, v6
},
458 { "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[i+1],d", 0, v6
},
459 { "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|RS1_G0
, "[i],d", 0, v6
},
460 { "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|SIMM13(~0), "[1],d", 0, v6
}, /* ldsh [rs1+0],d */
462 { "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI(~0), "[1+2],d", 0, v6
},
463 { "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI_RS2(~0), "[1],d", 0, v6
}, /* ldstub [rs1+%g0],d */
464 { "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[1+i],d", 0, v6
},
465 { "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[i+1],d", 0, v6
},
466 { "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|RS1_G0
, "[i],d", 0, v6
},
467 { "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|SIMM13(~0), "[1],d", 0, v6
}, /* ldstub [rs1+0],d */
469 { "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI(~0), "[1+2],d", 0, v9
},
470 { "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI_RS2(~0), "[1],d", 0, v9
}, /* ldsw [rs1+%g0],d */
471 { "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[1+i],d", 0, v9
},
472 { "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[i+1],d", 0, v9
},
473 { "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|RS1_G0
, "[i],d", 0, v9
},
474 { "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|SIMM13(~0), "[1],d", 0, v9
}, /* ldsw [rs1+0],d */
476 { "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI(~0), "[1+2],d", 0, v6
},
477 { "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI_RS2(~0), "[1],d", 0, v6
}, /* ldub [rs1+%g0],d */
478 { "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[1+i],d", 0, v6
},
479 { "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[i+1],d", 0, v6
},
480 { "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|RS1_G0
, "[i],d", 0, v6
},
481 { "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|SIMM13(~0), "[1],d", 0, v6
}, /* ldub [rs1+0],d */
483 { "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI(~0), "[1+2],d", 0, v6
},
484 { "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI_RS2(~0), "[1],d", 0, v6
}, /* lduh [rs1+%g0],d */
485 { "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[1+i],d", 0, v6
},
486 { "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[i+1],d", 0, v6
},
487 { "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|RS1_G0
, "[i],d", 0, v6
},
488 { "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|SIMM13(~0), "[1],d", 0, v6
}, /* lduh [rs1+0],d */
490 { "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI(~0), "[1+2],d", 0, v9
},
491 { "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI_RS2(~0), "[1],d", 0, v9
}, /* ldx [rs1+%g0],d */
492 { "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[1+i],d", 0, v9
},
493 { "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[i+1],d", 0, v9
},
494 { "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|RS1_G0
, "[i],d", 0, v9
},
495 { "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|SIMM13(~0), "[1],d", 0, v9
}, /* ldx [rs1+0],d */
497 { "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RD(~1), "[1+2],F", 0, v9
},
498 { "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RS2_G0
|RD(~1), "[1],F", 0, v9
}, /* ld [rs1+%g0],d */
499 { "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[1+i],F", 0, v9
},
500 { "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[i+1],F", 0, v9
},
501 { "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RS1_G0
|RD(~1), "[i],F", 0, v9
},
502 { "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~1),"[1],F", 0, v9
}, /* ld [rs1+0],d */
504 { "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", 0, v6
},
505 { "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0
, "[1]A,d", 0, v6
}, /* lda [rs1+%g0],d */
506 { "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", 0, v9
},
507 { "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d", 0, v9
},
508 { "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0
, "[i]o,d", 0, v9
},
509 { "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", 0, v9
}, /* ld [rs1+0],d */
510 { "lda", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2]A,g", 0, v9
},
511 { "lda", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0
, "[1]A,g", 0, v9
}, /* lda [rs1+%g0],d */
512 { "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i]o,g", 0, v9
},
513 { "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1]o,g", 0, v9
},
514 { "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0
, "[i]o,g", 0, v9
},
515 { "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1]o,g", 0, v9
}, /* ld [rs1+0],d */
517 { "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0), "[1+2]A,d", 0, v6
},
518 { "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0)|RS2_G0
, "[1]A,d", 0, v6
}, /* ldda [rs1+%g0],d */
519 { "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[1+i]o,d", 0, v9
},
520 { "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[i+1]o,d", 0, v9
},
521 { "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|RS1_G0
, "[i]o,d", 0, v9
},
522 { "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|SIMM13(~0), "[1]o,d", 0, v9
}, /* ld [rs1+0],d */
524 { "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0), "[1+2]A,H", 0, v9
},
525 { "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|RS2_G0
, "[1]A,H", 0, v9
}, /* ldda [rs1+%g0],d */
526 { "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i]o,H", 0, v9
},
527 { "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1]o,H", 0, v9
},
528 { "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0
, "[i]o,H", 0, v9
},
529 { "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1]o,H", 0, v9
}, /* ld [rs1+0],d */
531 { "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0), "[1+2]A,J", 0, v9
},
532 { "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0)|RS2_G0
, "[1]A,J", 0, v9
}, /* ldd [rs1+%g0],d */
533 { "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[1+i]o,J", 0, v9
},
534 { "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[i+1]o,J", 0, v9
},
535 { "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|RS1_G0
, "[i]o,J", 0, v9
},
536 { "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|SIMM13(~0), "[1]o,J", 0, v9
}, /* ldd [rs1+0],d */
538 { "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0), "[1+2]A,d", 0, v6
},
539 { "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0)|RS2_G0
, "[1]A,d", 0, v6
}, /* ldsba [rs1+%g0],d */
540 { "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[1+i]o,d", 0, v9
},
541 { "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[i+1]o,d", 0, v9
},
542 { "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|RS1_G0
, "[i]o,d", 0, v9
},
543 { "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|SIMM13(~0), "[1]o,d", 0, v9
}, /* ld [rs1+0],d */
545 { "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0), "[1+2]A,d", 0, v6
},
546 { "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0)|RS2_G0
, "[1]A,d", 0, v6
}, /* ldsha [rs1+%g0],d */
547 { "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[1+i]o,d", 0, v9
},
548 { "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[i+1]o,d", 0, v9
},
549 { "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|RS1_G0
, "[i]o,d", 0, v9
},
550 { "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|SIMM13(~0), "[1]o,d", 0, v9
}, /* ld [rs1+0],d */
552 { "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0), "[1+2]A,d", 0, v6
},
553 { "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0)|RS2_G0
, "[1]A,d", 0, v6
}, /* ldstuba [rs1+%g0],d */
554 { "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[1+i]o,d", 0, v9
},
555 { "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[i+1]o,d", 0, v9
},
556 { "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|RS1_G0
, "[i]o,d", 0, v9
},
557 { "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|SIMM13(~0), "[1]o,d", 0, v9
}, /* ld [rs1+0],d */
559 { "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0), "[1+2]A,d", 0, v9
},
560 { "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0)|RS2_G0
, "[1]A,d", 0, v9
}, /* lda [rs1+%g0],d */
561 { "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[1+i]o,d", 0, v9
},
562 { "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[i+1]o,d", 0, v9
},
563 { "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|RS1_G0
, "[i]o,d", 0, v9
},
564 { "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|SIMM13(~0), "[1]o,d", 0, v9
}, /* ld [rs1+0],d */
566 { "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0), "[1+2]A,d", 0, v6
},
567 { "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0)|RS2_G0
, "[1]A,d", 0, v6
}, /* lduba [rs1+%g0],d */
568 { "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[1+i]o,d", 0, v9
},
569 { "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[i+1]o,d", 0, v9
},
570 { "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|RS1_G0
, "[i]o,d", 0, v9
},
571 { "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|SIMM13(~0), "[1]o,d", 0, v9
}, /* ld [rs1+0],d */
573 { "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0), "[1+2]A,d", 0, v6
},
574 { "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0)|RS2_G0
, "[1]A,d", 0, v6
}, /* lduha [rs1+%g0],d */
575 { "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[1+i]o,d", 0, v9
},
576 { "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[i+1]o,d", 0, v9
},
577 { "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|RS1_G0
, "[i]o,d", 0, v9
},
578 { "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|SIMM13(~0), "[1]o,d", 0, v9
}, /* ld [rs1+0],d */
580 { "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", F_ALIAS
, v9
}, /* lduwa === lda */
581 { "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0
, "[1]A,d", F_ALIAS
, v9
}, /* lda [rs1+%g0],d */
582 { "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", F_ALIAS
, v9
},
583 { "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d", F_ALIAS
, v9
},
584 { "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0
, "[i]o,d", F_ALIAS
, v9
},
585 { "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", F_ALIAS
, v9
}, /* ld [rs1+0],d */
587 { "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0), "[1+2]A,d", 0, v9
},
588 { "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0)|RS2_G0
, "[1]A,d", 0, v9
}, /* lda [rs1+%g0],d */
589 { "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[1+i]o,d", 0, v9
},
590 { "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[i+1]o,d", 0, v9
},
591 { "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|RS1_G0
, "[i]o,d", 0, v9
},
592 { "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|SIMM13(~0), "[1]o,d", 0, v9
}, /* ld [rs1+0],d */
594 { "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", 0, v6
},
595 { "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", 0, v6
}, /* st d,[rs1+%g0] */
596 { "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", 0, v6
},
597 { "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", 0, v6
},
598 { "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0
, "d,[i]", 0, v6
},
599 { "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", 0, v6
}, /* st d,[rs1+0] */
600 { "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI(~0), "g,[1+2]", 0, v6
},
601 { "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI_RS2(~0), "g,[1]", 0, v6
}, /* st d[rs1+%g0] */
602 { "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[1+i]", 0, v6
},
603 { "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[i+1]", 0, v6
},
604 { "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|RS1_G0
, "g,[i]", 0, v6
},
605 { "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|SIMM13(~0), "g,[1]", 0, v6
}, /* st d,[rs1+0] */
607 { "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI(~0), "D,[1+2]", 0, v6notv9
},
608 { "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI_RS2(~0), "D,[1]", 0, v6notv9
}, /* st d,[rs1+%g0] */
609 { "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[1+i]", 0, v6notv9
},
610 { "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[i+1]", 0, v6notv9
},
611 { "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0
, "D,[i]", 0, v6notv9
},
612 { "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "D,[1]", 0, v6notv9
}, /* st d,[rs1+0] */
613 { "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI(~0), "C,[1+2]", 0, v6notv9
},
614 { "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI_RS2(~0), "C,[1]", 0, v6notv9
}, /* st d,[rs1+%g0] */
615 { "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[1+i]", 0, v6notv9
},
616 { "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[i+1]", 0, v6notv9
},
617 { "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|RS1_G0
, "C,[i]", 0, v6notv9
},
618 { "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|SIMM13(~0), "C,[1]", 0, v6notv9
}, /* st d,[rs1+0] */
620 { "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0
|ASI(~0), "F,[1+2]", 0, v6
},
621 { "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0
|ASI_RS2(~0), "F,[1]", 0, v6
}, /* st d,[rs1+%g0] */
622 { "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0
, "F,[1+i]", 0, v6
},
623 { "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0
, "F,[i+1]", 0, v6
},
624 { "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0
|RS1_G0
, "F,[i]", 0, v6
},
625 { "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0
|SIMM13(~0), "F,[1]", 0, v6
}, /* st d,[rs1+0] */
627 { "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS
, v9
},
628 { "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS
, v9
}, /* st d,[rs1+%g0] */
629 { "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS
, v9
},
630 { "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS
, v9
},
631 { "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0
, "d,[i]", F_ALIAS
, v9
},
632 { "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS
, v9
}, /* st d,[rs1+0] */
633 { "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS
, v9
},
634 { "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS
, v9
}, /* st d,[rs1+%g0] */
635 { "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS
, v9
},
636 { "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS
, v9
},
637 { "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0
, "d,[i]", F_ALIAS
, v9
},
638 { "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS
, v9
}, /* st d,[rs1+0] */
639 { "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS
, v9
},
640 { "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS
, v9
}, /* st d,[rs1+%g0] */
641 { "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS
, v9
},
642 { "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS
, v9
},
643 { "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0
, "d,[i]", F_ALIAS
, v9
},
644 { "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS
, v9
}, /* st d,[rs1+0] */
646 { "spill", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS
, v6
},
647 { "spill", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS
, v6
}, /* st d,[rs1+%g0] */
648 { "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS
, v6
},
649 { "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS
, v6
},
650 { "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0
, "d,[i]", F_ALIAS
, v6
},
651 { "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS
, v6
}, /* st d,[rs1+0] */
653 { "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", 0, v6
},
654 { "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", 0, v6
}, /* sta d,[rs1+%g0] */
655 { "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", 0, v9
},
656 { "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", 0, v9
},
657 { "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0
, "d,[i]o", 0, v9
},
658 { "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", 0, v9
}, /* st d,[rs1+0] */
660 { "sta", F3(3, 0x34, 0), F3(~3, ~0x34, ~0), "g,[1+2]A", 0, v9
},
661 { "sta", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|RS2(~0), "g,[1]A", 0, v9
}, /* sta d,[rs1+%g0] */
662 { "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[1+i]o", 0, v9
},
663 { "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[i+1]o", 0, v9
},
664 { "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0
, "g,[i]o", 0, v9
},
665 { "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "g,[1]o", 0, v9
}, /* st d,[rs1+0] */
667 { "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS
, v9
},
668 { "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS
, v9
}, /* sta d,[rs1+%g0] */
669 { "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS
, v9
},
670 { "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS
, v9
},
671 { "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0
, "d,[i]o", F_ALIAS
, v9
},
672 { "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS
, v9
}, /* st d,[rs1+0] */
673 { "stswa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS
, v9
},
674 { "stswa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS
, v9
}, /* sta d,[rs1+%g0] */
675 { "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS
, v9
},
676 { "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS
, v9
},
677 { "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0
, "d,[i]o", F_ALIAS
, v9
},
678 { "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS
, v9
}, /* st d,[rs1+0] */
679 { "stuwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS
, v9
},
680 { "stuwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS
, v9
}, /* sta d,[rs1+%g0] */
681 { "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS
, v9
},
682 { "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS
, v9
},
683 { "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0
, "d,[i]o", F_ALIAS
, v9
},
684 { "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS
, v9
}, /* st d,[rs1+0] */
686 { "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", 0, v6
},
687 { "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", 0, v6
}, /* stb d,[rs1+%g0] */
688 { "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", 0, v6
},
689 { "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", 0, v6
},
690 { "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0
, "d,[i]", 0, v6
},
691 { "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", 0, v6
}, /* stb d,[rs1+0] */
693 { "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS
, v6
},
694 { "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS
, v6
}, /* stb d,[rs1+%g0] */
695 { "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", F_ALIAS
, v6
},
696 { "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", F_ALIAS
, v6
},
697 { "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0
, "d,[i]", F_ALIAS
, v6
},
698 { "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", F_ALIAS
, v6
}, /* stb d,[rs1+0] */
699 { "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS
, v6
},
700 { "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS
, v6
}, /* stb d,[rs1+%g0] */
701 { "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", F_ALIAS
, v6
},
702 { "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", F_ALIAS
, v6
},
703 { "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0
, "d,[i]", F_ALIAS
, v6
},
704 { "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", F_ALIAS
, v6
}, /* stb d,[rs1+0] */
706 { "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", 0, v6
},
707 { "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", 0, v6
}, /* stba d,[rs1+%g0] */
708 { "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", 0, v9
},
709 { "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", 0, v9
},
710 { "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0
, "d,[i]o", 0, v9
},
711 { "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", 0, v9
}, /* stb d,[rs1+0] */
713 { "stsba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", F_ALIAS
, v6
},
714 { "stsba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", F_ALIAS
, v6
}, /* stba d,[rs1+%g0] */
715 { "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", F_ALIAS
, v9
},
716 { "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", F_ALIAS
, v9
},
717 { "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0
, "d,[i]o", F_ALIAS
, v9
},
718 { "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS
, v9
}, /* stb d,[rs1+0] */
719 { "stuba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", F_ALIAS
, v6
},
720 { "stuba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", F_ALIAS
, v6
}, /* stba d,[rs1+%g0] */
721 { "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", F_ALIAS
, v9
},
722 { "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", F_ALIAS
, v9
},
723 { "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0
, "d,[i]o", F_ALIAS
, v9
},
724 { "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS
, v9
}, /* stb d,[rs1+0] */
726 { "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", 0, v6
},
727 { "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", 0, v6
}, /* std d,[rs1+%g0] */
728 { "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", 0, v6
},
729 { "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", 0, v6
},
730 { "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0
, "d,[i]", 0, v6
},
731 { "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", 0, v6
}, /* std d,[rs1+0] */
733 { "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "q,[1+2]", 0, v6notv9
},
734 { "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "q,[1]", 0, v6notv9
}, /* std d,[rs1+%g0] */
735 { "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[1+i]", 0, v6notv9
},
736 { "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[i+1]", 0, v6notv9
},
737 { "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0
, "q,[i]", 0, v6notv9
},
738 { "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "q,[1]", 0, v6notv9
}, /* std d,[rs1+0] */
739 { "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI(~0), "H,[1+2]", 0, v6
},
740 { "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI_RS2(~0), "H,[1]", 0, v6
}, /* std d,[rs1+%g0] */
741 { "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[1+i]", 0, v6
},
742 { "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[i+1]", 0, v6
},
743 { "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|RS1_G0
, "H,[i]", 0, v6
},
744 { "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|SIMM13(~0), "H,[1]", 0, v6
}, /* std d,[rs1+0] */
746 { "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "Q,[1+2]", 0, v6notv9
},
747 { "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "Q,[1]", 0, v6notv9
}, /* std d,[rs1+%g0] */
748 { "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[1+i]", 0, v6notv9
},
749 { "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[i+1]", 0, v6notv9
},
750 { "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0
, "Q,[i]", 0, v6notv9
},
751 { "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "Q,[1]", 0, v6notv9
}, /* std d,[rs1+0] */
752 { "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI(~0), "D,[1+2]", 0, v6notv9
},
753 { "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI_RS2(~0), "D,[1]", 0, v6notv9
}, /* std d,[rs1+%g0] */
754 { "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[1+i]", 0, v6notv9
},
755 { "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[i+1]", 0, v6notv9
},
756 { "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0
, "D,[i]", 0, v6notv9
},
757 { "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "D,[1]", 0, v6notv9
}, /* std d,[rs1+0] */
759 { "spilld", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", F_ALIAS
, v6
},
760 { "spilld", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS
, v6
}, /* std d,[rs1+%g0] */
761 { "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", F_ALIAS
, v6
},
762 { "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", F_ALIAS
, v6
},
763 { "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0
, "d,[i]", F_ALIAS
, v6
},
764 { "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", F_ALIAS
, v6
}, /* std d,[rs1+0] */
766 { "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0), "d,[1+2]A", 0, v6
},
767 { "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0)|RS2(~0), "d,[1]A", 0, v6
}, /* stda d,[rs1+%g0] */
768 { "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[1+i]o", 0, v9
},
769 { "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[i+1]o", 0, v9
},
770 { "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|RS1_G0
, "d,[i]o", 0, v9
},
771 { "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|SIMM13(~0), "d,[1]o", 0, v9
}, /* std d,[rs1+0] */
772 { "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0), "H,[1+2]A", 0, v9
},
773 { "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|RS2(~0), "H,[1]A", 0, v9
}, /* stda d,[rs1+%g0] */
774 { "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[1+i]o", 0, v9
},
775 { "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[i+1]o", 0, v9
},
776 { "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0
, "H,[i]o", 0, v9
},
777 { "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "H,[1]o", 0, v9
}, /* std d,[rs1+0] */
779 { "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", 0, v6
},
780 { "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", 0, v6
}, /* sth d,[rs1+%g0] */
781 { "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", 0, v6
},
782 { "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", 0, v6
},
783 { "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0
, "d,[i]", 0, v6
},
784 { "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", 0, v6
}, /* sth d,[rs1+0] */
786 { "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS
, v6
},
787 { "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS
, v6
}, /* sth d,[rs1+%g0] */
788 { "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", F_ALIAS
, v6
},
789 { "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", F_ALIAS
, v6
},
790 { "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0
, "d,[i]", F_ALIAS
, v6
},
791 { "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", F_ALIAS
, v6
}, /* sth d,[rs1+0] */
792 { "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS
, v6
},
793 { "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS
, v6
}, /* sth d,[rs1+%g0] */
794 { "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", F_ALIAS
, v6
},
795 { "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", F_ALIAS
, v6
},
796 { "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0
, "d,[i]", F_ALIAS
, v6
},
797 { "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", F_ALIAS
, v6
}, /* sth d,[rs1+0] */
799 { "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", 0, v6
},
800 { "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", 0, v6
}, /* stha ,[rs1+%g0] */
801 { "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", 0, v9
},
802 { "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", 0, v9
},
803 { "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0
, "d,[i]o", 0, v9
},
804 { "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", 0, v9
}, /* sth d,[rs1+0] */
806 { "stsha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", F_ALIAS
, v6
},
807 { "stsha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", F_ALIAS
, v6
}, /* stha ,[rs1+%g0] */
808 { "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", F_ALIAS
, v9
},
809 { "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", F_ALIAS
, v9
},
810 { "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0
, "d,[i]o", F_ALIAS
, v9
},
811 { "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS
, v9
}, /* sth d,[rs1+0] */
812 { "stuha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", F_ALIAS
, v6
},
813 { "stuha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", F_ALIAS
, v6
}, /* stha ,[rs1+%g0] */
814 { "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", F_ALIAS
, v9
},
815 { "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", F_ALIAS
, v9
},
816 { "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0
, "d,[i]o", F_ALIAS
, v9
},
817 { "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS
, v9
}, /* sth d,[rs1+0] */
819 { "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI(~0), "d,[1+2]", 0, v9
},
820 { "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI_RS2(~0), "d,[1]", 0, v9
}, /* stx d,[rs1+%g0] */
821 { "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[1+i]", 0, v9
},
822 { "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[i+1]", 0, v9
},
823 { "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RS1_G0
, "d,[i]", 0, v9
},
824 { "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|SIMM13(~0), "d,[1]", 0, v9
}, /* stx d,[rs1+0] */
826 { "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI(~0)|RD(~1), "F,[1+2]", 0, v9
},
827 { "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI_RS2(~0)|RD(~1),"F,[1]", 0, v9
}, /* stx d,[rs1+%g0] */
828 { "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1), "F,[1+i]", 0, v9
},
829 { "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1), "F,[i+1]", 0, v9
},
830 { "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RS1_G0
|RD(~1), "F,[i]", 0, v9
},
831 { "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|SIMM13(~0)|RD(~1),"F,[1]", 0, v9
}, /* stx d,[rs1+0] */
833 { "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0), "d,[1+2]A", 0, v9
},
834 { "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0)|RS2(~0), "d,[1]A", 0, v9
}, /* stxa d,[rs1+%g0] */
835 { "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[1+i]o", 0, v9
},
836 { "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[i+1]o", 0, v9
},
837 { "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|RS1_G0
, "d,[i]o", 0, v9
},
838 { "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|SIMM13(~0), "d,[1]o", 0, v9
}, /* stx d,[rs1+0] */
840 { "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "J,[1+2]", 0, v9
},
841 { "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "J,[1]", 0, v9
}, /* stq [rs1+%g0] */
842 { "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[1+i]", 0, v9
},
843 { "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[i+1]", 0, v9
},
844 { "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0
, "J,[i]", 0, v9
},
845 { "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "J,[1]", 0, v9
}, /* stq [rs1+0] */
847 { "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "J,[1+2]A", 0, v9
},
848 { "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "J,[1]A", 0, v9
}, /* stqa [rs1+%g0] */
849 { "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[1+i]o", 0, v9
},
850 { "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[i+1]o", 0, v9
},
851 { "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0
, "J,[i]o", 0, v9
},
852 { "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "J,[1]o", 0, v9
}, /* stqa [rs1+0] */
854 { "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI(~0), "[1+2],d", 0, v7
},
855 { "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI_RS2(~0), "[1],d", 0, v7
}, /* swap [rs1+%g0],d */
856 { "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[1+i],d", 0, v7
},
857 { "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[i+1],d", 0, v7
},
858 { "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|RS1_G0
, "[i],d", 0, v7
},
859 { "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|SIMM13(~0), "[1],d", 0, v7
}, /* swap [rs1+0],d */
861 { "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0), "[1+2]A,d", 0, v7
},
862 { "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0)|RS2(~0), "[1]A,d", 0, v7
}, /* swapa [rs1+%g0],d */
863 { "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[1+i]o,d", 0, v9
},
864 { "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[i+1]o,d", 0, v9
},
865 { "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|RS1_G0
, "[i]o,d", 0, v9
},
866 { "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|SIMM13(~0), "[1]o,d", 0, v9
}, /* swap [rs1+0],d */
868 { "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|ASI(~0), "1,2,d", 0, v6
},
869 { "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|RD_G0
|RS1_G0
|ASI_RS2(~0), "", 0, v6
}, /* restore %g0,%g0,%g0 */
870 { "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1), "1,i,d", 0, v6
},
871 { "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1)|RD_G0
|RS1_G0
|SIMM13(~0), "", 0, v6
}, /* restore %g0,0,%g0 */
873 { "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0
|ASI(~0), "1+2", F_UNBR
|F_DELAYED
, v6
}, /* rett rs1+rs2 */
874 { "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0
|ASI_RS2(~0), "1", F_UNBR
|F_DELAYED
, v6
}, /* rett rs1,%g0 */
875 { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0
, "1+i", F_UNBR
|F_DELAYED
, v6
}, /* rett rs1+X */
876 { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0
, "i+1", F_UNBR
|F_DELAYED
, v6
}, /* rett X+rs1 */
877 { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0
|RS1_G0
, "i", F_UNBR
|F_DELAYED
, v6
}, /* rett X+rs1 */
878 { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0
|RS1_G0
, "i", F_UNBR
|F_DELAYED
, v6
}, /* rett X */
879 { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0
|SIMM13(~0), "1", F_UNBR
|F_DELAYED
, v6
}, /* rett rs1+0 */
881 { "save", F3(2, 0x3c, 0), F3(~2, ~0x3c, ~0)|ASI(~0), "1,2,d", 0, v6
},
882 { "save", F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1), "1,i,d", 0, v6
},
883 { "save", 0x81e00000, ~0x81e00000, "", F_ALIAS
, v6
},
885 { "ret", F3(2, 0x38, 1)|RS1(0x1f)|SIMM13(8), F3(~2, ~0x38, ~1)|SIMM13(~8), "", F_UNBR
|F_DELAYED
, v6
}, /* jmpl %i7+8,%g0 */
886 { "retl", F3(2, 0x38, 1)|RS1(0x0f)|SIMM13(8), F3(~2, ~0x38, ~1)|RS1(~0x0f)|SIMM13(~8), "", F_UNBR
|F_DELAYED
, v6
}, /* jmpl %o7+8,%g0 */
888 { "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI(~0), "1+2,d", F_JSR
|F_DELAYED
, v6
},
889 { "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI_RS2(~0), "1,d", F_JSR
|F_DELAYED
, v6
}, /* jmpl rs1+%g0,d */
890 { "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|SIMM13(~0), "1,d", F_JSR
|F_DELAYED
, v6
}, /* jmpl rs1+0,d */
891 { "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RS1_G0
, "i,d", F_JSR
|F_DELAYED
, v6
}, /* jmpl %g0+i,d */
892 { "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "1+i,d", F_JSR
|F_DELAYED
, v6
},
893 { "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "i+1,d", F_JSR
|F_DELAYED
, v6
},
895 { "done", F3(2, 0x3e, 0)|RD(0), F3(~2, ~0x3e, ~0)|RD(~0)|RS1_G0
|SIMM13(~0), "", 0, v9
},
896 { "retry", F3(2, 0x3e, 0)|RD(1), F3(~2, ~0x3e, ~0)|RD(~1)|RS1_G0
|SIMM13(~0), "", 0, v9
},
897 { "saved", F3(2, 0x31, 0)|RD(0), F3(~2, ~0x31, ~0)|RD(~0)|RS1_G0
|SIMM13(~0), "", 0, v9
},
898 { "restored", F3(2, 0x31, 0)|RD(1), F3(~2, ~0x31, ~0)|RD(~1)|RS1_G0
|SIMM13(~0), "", 0, v9
},
899 { "sir", F3(2, 0x30, 1)|RD(0xf), F3(~2, ~0x30, ~1)|RD(~0xf)|RS1_G0
, "i", 0, v9
},
901 { "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", 0, v8
},
902 { "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", 0, v8
}, /* flush rs1+%g0 */
903 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", 0, v8
}, /* flush rs1+0 */
904 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0
, "i", 0, v8
}, /* flush %g0+i */
905 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", 0, v8
},
906 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", 0, v8
},
908 /* IFLUSH was renamed to FLUSH in v8. */
909 { "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", F_ALIAS
, v6
},
910 { "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", F_ALIAS
, v6
}, /* flush rs1+%g0 */
911 { "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", F_ALIAS
, v6
}, /* flush rs1+0 */
912 { "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0
, "i", F_ALIAS
, v6
},
913 { "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", F_ALIAS
, v6
},
914 { "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", F_ALIAS
, v6
},
916 { "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI(~0), "1+2", 0, v9
},
917 { "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI_RS2(~0), "1", 0, v9
}, /* return rs1+%g0 */
918 { "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|SIMM13(~0), "1", 0, v9
}, /* return rs1+0 */
919 { "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RS1_G0
, "i", 0, v9
}, /* return %g0+i */
920 { "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "1+i", 0, v9
},
921 { "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "i+1", 0, v9
},
923 { "flushw", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RD_G0
|RS1_G0
|ASI_RS2(~0), "", 0, v9
},
925 { "membar", F3(2, 0x28, 1)|RS1(0xf), F3(~2, ~0x28, ~1)|RD_G0
|RS1(~0xf)|SIMM13(~127), "K", 0, v9
},
926 { "stbar", F3(2, 0x28, 0)|RS1(0xf), F3(~2, ~0x28, ~0)|RD_G0
|RS1(~0xf)|SIMM13(~0), "", 0, v8
},
928 { "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0), "[1+2],*", 0, v9
},
929 { "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0)|RS2_G0
, "[1],*", 0, v9
}, /* prefetch [rs1+%g0],prefetch_fcn */
930 { "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1), "[1+i],*", 0, v9
},
931 { "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1), "[i+1],*", 0, v9
},
932 { "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|RS1_G0
, "[i],*", 0, v9
},
933 { "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|SIMM13(~0), "[1],*", 0, v9
}, /* prefetch [rs1+0],prefetch_fcn */
934 { "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0), "[1+2]A,*", 0, v9
},
935 { "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0)|RS2_G0
, "[1]A,*", 0, v9
}, /* prefetcha [rs1+%g0],prefetch_fcn */
936 { "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1), "[1+i]o,*", 0, v9
},
937 { "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1), "[i+1]o,*", 0, v9
},
938 { "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|RS1_G0
, "[i]o,*", 0, v9
},
939 { "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|SIMM13(~0), "[1]o,*", 0, v9
}, /* prefetcha [rs1+0],d */
941 { "sll", F3(2, 0x25, 0), F3(~2, ~0x25, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, v6
},
942 { "sll", F3(2, 0x25, 1), F3(~2, ~0x25, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, v6
},
943 { "sra", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, v6
},
944 { "sra", F3(2, 0x27, 1), F3(~2, ~0x27, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, v6
},
945 { "srl", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, v6
},
946 { "srl", F3(2, 0x26, 1), F3(~2, ~0x26, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, v6
},
948 { "sllx", F3(2, 0x25, 0)|(1<<12), F3(~2, ~0x25, ~0)|(0x7f<<5), "1,2,d", 0, v9
},
949 { "sllx", F3(2, 0x25, 1)|(1<<12), F3(~2, ~0x25, ~1)|(0x3f<<6), "1,Y,d", 0, v9
},
950 { "srax", F3(2, 0x27, 0)|(1<<12), F3(~2, ~0x27, ~0)|(0x7f<<5), "1,2,d", 0, v9
},
951 { "srax", F3(2, 0x27, 1)|(1<<12), F3(~2, ~0x27, ~1)|(0x3f<<6), "1,Y,d", 0, v9
},
952 { "srlx", F3(2, 0x26, 0)|(1<<12), F3(~2, ~0x26, ~0)|(0x7f<<5), "1,2,d", 0, v9
},
953 { "srlx", F3(2, 0x26, 1)|(1<<12), F3(~2, ~0x26, ~1)|(0x3f<<6), "1,Y,d", 0, v9
},
955 { "mulscc", F3(2, 0x24, 0), F3(~2, ~0x24, ~0)|ASI(~0), "1,2,d", 0, v6
},
956 { "mulscc", F3(2, 0x24, 1), F3(~2, ~0x24, ~1), "1,i,d", 0, v6
},
958 { "divscc", F3(2, 0x1d, 0), F3(~2, ~0x1d, ~0)|ASI(~0), "1,2,d", 0, sparclite
},
959 { "divscc", F3(2, 0x1d, 1), F3(~2, ~0x1d, ~1), "1,i,d", 0, sparclite
},
961 { "scan", F3(2, 0x2c, 0), F3(~2, ~0x2c, ~0)|ASI(~0), "1,2,d", 0, sparclet
|sparclite
},
962 { "scan", F3(2, 0x2c, 1), F3(~2, ~0x2c, ~1), "1,i,d", 0, sparclet
|sparclite
},
964 { "popc", F3(2, 0x2e, 0), F3(~2, ~0x2e, ~0)|RS1_G0
|ASI(~0),"2,d", 0, v9
},
965 { "popc", F3(2, 0x2e, 1), F3(~2, ~0x2e, ~1)|RS1_G0
, "i,d", 0, v9
},
967 { "clr", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RD_G0
|RS1_G0
|ASI_RS2(~0), "d", F_ALIAS
, v6
}, /* or %g0,%g0,d */
968 { "clr", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0
|SIMM13(~0), "d", F_ALIAS
, v6
}, /* or %g0,0,d */
969 { "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0
|ASI(~0), "[1+2]", F_ALIAS
, v6
},
970 { "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0
|ASI_RS2(~0), "[1]", F_ALIAS
, v6
}, /* st %g0,[rs1+%g0] */
971 { "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0
, "[1+i]", F_ALIAS
, v6
},
972 { "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0
, "[i+1]", F_ALIAS
, v6
},
973 { "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0
|RS1_G0
, "[i]", F_ALIAS
, v6
},
974 { "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0
|SIMM13(~0), "[1]", F_ALIAS
, v6
}, /* st %g0,[rs1+0] */
976 { "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0
|ASI(~0), "[1+2]", F_ALIAS
, v6
},
977 { "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0
|ASI_RS2(~0), "[1]", F_ALIAS
, v6
}, /* stb %g0,[rs1+%g0] */
978 { "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0
, "[1+i]", F_ALIAS
, v6
},
979 { "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0
, "[i+1]", F_ALIAS
, v6
},
980 { "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0
|RS1_G0
, "[i]", F_ALIAS
, v6
},
981 { "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0
|SIMM13(~0), "[1]", F_ALIAS
, v6
}, /* stb %g0,[rs1+0] */
983 { "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0
|ASI(~0), "[1+2]", F_ALIAS
, v6
},
984 { "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0
|ASI_RS2(~0), "[1]", F_ALIAS
, v6
}, /* sth %g0,[rs1+%g0] */
985 { "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0
, "[1+i]", F_ALIAS
, v6
},
986 { "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0
, "[i+1]", F_ALIAS
, v6
},
987 { "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0
|RS1_G0
, "[i]", F_ALIAS
, v6
},
988 { "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0
|SIMM13(~0), "[1]", F_ALIAS
, v6
}, /* sth %g0,[rs1+0] */
990 { "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0
|ASI(~0), "[1+2]", F_ALIAS
, v9
},
991 { "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0
|ASI_RS2(~0), "[1]", F_ALIAS
, v9
}, /* stx %g0,[rs1+%g0] */
992 { "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0
, "[1+i]", F_ALIAS
, v9
},
993 { "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0
, "[i+1]", F_ALIAS
, v9
},
994 { "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0
|RS1_G0
, "[i]", F_ALIAS
, v9
},
995 { "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0
|SIMM13(~0), "[1]", F_ALIAS
, v9
}, /* stx %g0,[rs1+0] */
997 { "orcc", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|ASI(~0), "1,2,d", 0, v6
},
998 { "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "1,i,d", 0, v6
},
999 { "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "i,1,d", 0, v6
},
1001 /* This is not a commutative instruction. */
1002 { "orncc", F3(2, 0x16, 0), F3(~2, ~0x16, ~0)|ASI(~0), "1,2,d", 0, v6
},
1003 { "orncc", F3(2, 0x16, 1), F3(~2, ~0x16, ~1), "1,i,d", 0, v6
},
1005 /* This is not a commutative instruction. */
1006 { "orn", F3(2, 0x06, 0), F3(~2, ~0x06, ~0)|ASI(~0), "1,2,d", 0, v6
},
1007 { "orn", F3(2, 0x06, 1), F3(~2, ~0x06, ~1), "1,i,d", 0, v6
},
1009 { "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0
|ASI_RS2(~0), "1", 0, v6
}, /* orcc rs1, %g0, %g0 */
1010 { "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0
|RS1_G0
|ASI(~0), "2", 0, v6
}, /* orcc %g0, rs2, %g0 */
1011 { "tst", F3(2, 0x12, 1), F3(~2, ~0x12, ~1)|RD_G0
|SIMM13(~0), "1", 0, v6
}, /* orcc rs1, 0, %g0 */
1013 { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", 0, v8
}, /* wr r,r,%asrX */
1014 { "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", 0, v8
}, /* wr r,i,%asrX */
1015 { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0), "1,m", F_ALIAS
, v8
}, /* wr rs1,%g0,%asrX */
1016 { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0
|ASI(~0), "1,2,y", 0, v6
}, /* wr r,r,%y */
1017 { "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0
, "1,i,y", 0, v6
}, /* wr r,i,%y */
1018 { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0
|ASI_RS2(~0), "1,y", F_ALIAS
, v6
}, /* wr rs1,%g0,%y */
1019 { "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0
|ASI(~0), "1,2,p", 0, v6notv9
}, /* wr r,r,%psr */
1020 { "wr", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0
, "1,i,p", 0, v6notv9
}, /* wr r,i,%psr */
1021 { "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0
|ASI_RS2(~0), "1,p", F_ALIAS
, v6notv9
}, /* wr rs1,%g0,%psr */
1022 { "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0
|ASI(~0), "1,2,w", 0, v6notv9
}, /* wr r,r,%wim */
1023 { "wr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0
, "1,i,w", 0, v6notv9
}, /* wr r,i,%wim */
1024 { "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0
|ASI_RS2(~0), "1,w", F_ALIAS
, v6notv9
}, /* wr rs1,%g0,%wim */
1025 { "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0
|ASI(~0), "1,2,t", 0, v6notv9
}, /* wr r,r,%tbr */
1026 { "wr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0
, "1,i,t", 0, v6notv9
}, /* wr r,i,%tbr */
1027 { "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0
|ASI_RS2(~0), "1,t", F_ALIAS
, v6notv9
}, /* wr rs1,%g0,%tbr */
1029 { "wr", F3(2, 0x30, 0)|RD(2), F3(~2, ~0x30, ~0)|RD(~2)|ASI(~0), "1,2,E", 0, v9
}, /* wr r,r,%ccr */
1030 { "wr", F3(2, 0x30, 1)|RD(2), F3(~2, ~0x30, ~1)|RD(~2), "1,i,E", 0, v9
}, /* wr r,i,%ccr */
1031 { "wr", F3(2, 0x30, 0)|RD(3), F3(~2, ~0x30, ~0)|RD(~3)|ASI(~0), "1,2,o", 0, v9
}, /* wr r,r,%asi */
1032 { "wr", F3(2, 0x30, 1)|RD(3), F3(~2, ~0x30, ~1)|RD(~3), "1,i,o", 0, v9
}, /* wr r,i,%asi */
1033 { "wr", F3(2, 0x30, 0)|RD(6), F3(~2, ~0x30, ~0)|RD(~6)|ASI(~0), "1,2,s", 0, v9
}, /* wr r,r,%fprs */
1034 { "wr", F3(2, 0x30, 1)|RD(6), F3(~2, ~0x30, ~1)|RD(~6), "1,i,s", 0, v9
}, /* wr r,i,%fprs */
1036 { "wr", F3(2, 0x30, 0)|RD(16), F3(~2, ~0x30, ~0)|RD(~16)|ASI(~0), "1,2,_", 0, v9a
}, /* wr r,r,%pcr */
1037 { "wr", F3(2, 0x30, 1)|RD(16), F3(~2, ~0x30, ~1)|RD(~16), "1,i,_", 0, v9a
}, /* wr r,i,%pcr */
1038 { "wr", F3(2, 0x30, 0)|RD(17), F3(~2, ~0x30, ~0)|RD(~17)|ASI(~0), "1,2,_", 0, v9a
}, /* wr r,r,%pic */
1039 { "wr", F3(2, 0x30, 1)|RD(17), F3(~2, ~0x30, ~1)|RD(~17), "1,i,_", 0, v9a
}, /* wr r,i,%pic */
1040 { "wr", F3(2, 0x30, 0)|RD(18), F3(~2, ~0x30, ~0)|RD(~18)|ASI(~0), "1,2,_", 0, v9a
}, /* wr r,r,%dcr */
1041 { "wr", F3(2, 0x30, 1)|RD(18), F3(~2, ~0x30, ~1)|RD(~18), "1,i,_", 0, v9a
}, /* wr r,i,%dcr */
1042 { "wr", F3(2, 0x30, 0)|RD(19), F3(~2, ~0x30, ~0)|RD(~19)|ASI(~0), "1,2,_", 0, v9a
}, /* wr r,r,%gsr */
1043 { "wr", F3(2, 0x30, 1)|RD(19), F3(~2, ~0x30, ~1)|RD(~19), "1,i,_", 0, v9a
}, /* wr r,i,%gsr */
1044 { "wr", F3(2, 0x30, 0)|RD(20), F3(~2, ~0x30, ~0)|RD(~20)|ASI(~0), "1,2,_", 0, v9a
}, /* wr r,r,%set_softint */
1045 { "wr", F3(2, 0x30, 1)|RD(20), F3(~2, ~0x30, ~1)|RD(~20), "1,i,_", 0, v9a
}, /* wr r,i,%set_softint */
1046 { "wr", F3(2, 0x30, 0)|RD(21), F3(~2, ~0x30, ~0)|RD(~21)|ASI(~0), "1,2,_", 0, v9a
}, /* wr r,r,%clear_softint */
1047 { "wr", F3(2, 0x30, 1)|RD(21), F3(~2, ~0x30, ~1)|RD(~21), "1,i,_", 0, v9a
}, /* wr r,i,%clear_softint */
1048 { "wr", F3(2, 0x30, 0)|RD(22), F3(~2, ~0x30, ~0)|RD(~22)|ASI(~0), "1,2,_", 0, v9a
}, /* wr r,r,%softint */
1049 { "wr", F3(2, 0x30, 1)|RD(22), F3(~2, ~0x30, ~1)|RD(~22), "1,i,_", 0, v9a
}, /* wr r,i,%softint */
1050 { "wr", F3(2, 0x30, 0)|RD(23), F3(~2, ~0x30, ~0)|RD(~23)|ASI(~0), "1,2,_", 0, v9a
}, /* wr r,r,%tick_cmpr */
1051 { "wr", F3(2, 0x30, 1)|RD(23), F3(~2, ~0x30, ~1)|RD(~23), "1,i,_", 0, v9a
}, /* wr r,i,%tick_cmpr */
1052 { "wr", F3(2, 0x30, 0)|RD(24), F3(~2, ~0x30, ~0)|RD(~24)|ASI(~0), "1,2,_", 0, v9b
}, /* wr r,r,%sys_tick */
1053 { "wr", F3(2, 0x30, 1)|RD(24), F3(~2, ~0x30, ~1)|RD(~24), "1,i,_", 0, v9b
}, /* wr r,i,%sys_tick */
1054 { "wr", F3(2, 0x30, 0)|RD(25), F3(~2, ~0x30, ~0)|RD(~25)|ASI(~0), "1,2,_", 0, v9b
}, /* wr r,r,%sys_tick_cmpr */
1055 { "wr", F3(2, 0x30, 1)|RD(25), F3(~2, ~0x30, ~1)|RD(~25), "1,i,_", 0, v9b
}, /* wr r,i,%sys_tick_cmpr */
1057 { "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", 0, v8
}, /* rd %asrX,r */
1058 { "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0
|SIMM13(~0), "y,d", 0, v6
}, /* rd %y,r */
1059 { "rd", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0
|SIMM13(~0), "p,d", 0, v6notv9
}, /* rd %psr,r */
1060 { "rd", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0
|SIMM13(~0), "w,d", 0, v6notv9
}, /* rd %wim,r */
1061 { "rd", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0
|SIMM13(~0), "t,d", 0, v6notv9
}, /* rd %tbr,r */
1063 { "rd", F3(2, 0x28, 0)|RS1(2), F3(~2, ~0x28, ~0)|RS1(~2)|SIMM13(~0), "E,d", 0, v9
}, /* rd %ccr,r */
1064 { "rd", F3(2, 0x28, 0)|RS1(3), F3(~2, ~0x28, ~0)|RS1(~3)|SIMM13(~0), "o,d", 0, v9
}, /* rd %asi,r */
1065 { "rd", F3(2, 0x28, 0)|RS1(4), F3(~2, ~0x28, ~0)|RS1(~4)|SIMM13(~0), "W,d", 0, v9
}, /* rd %tick,r */
1066 { "rd", F3(2, 0x28, 0)|RS1(5), F3(~2, ~0x28, ~0)|RS1(~5)|SIMM13(~0), "P,d", 0, v9
}, /* rd %pc,r */
1067 { "rd", F3(2, 0x28, 0)|RS1(6), F3(~2, ~0x28, ~0)|RS1(~6)|SIMM13(~0), "s,d", 0, v9
}, /* rd %fprs,r */
1069 { "rd", F3(2, 0x28, 0)|RS1(16), F3(~2, ~0x28, ~0)|RS1(~16)|SIMM13(~0), "/,d", 0, v9a
}, /* rd %pcr,r */
1070 { "rd", F3(2, 0x28, 0)|RS1(17), F3(~2, ~0x28, ~0)|RS1(~17)|SIMM13(~0), "/,d", 0, v9a
}, /* rd %pic,r */
1071 { "rd", F3(2, 0x28, 0)|RS1(18), F3(~2, ~0x28, ~0)|RS1(~18)|SIMM13(~0), "/,d", 0, v9a
}, /* rd %dcr,r */
1072 { "rd", F3(2, 0x28, 0)|RS1(19), F3(~2, ~0x28, ~0)|RS1(~19)|SIMM13(~0), "/,d", 0, v9a
}, /* rd %gsr,r */
1073 { "rd", F3(2, 0x28, 0)|RS1(22), F3(~2, ~0x28, ~0)|RS1(~22)|SIMM13(~0), "/,d", 0, v9a
}, /* rd %softint,r */
1074 { "rd", F3(2, 0x28, 0)|RS1(23), F3(~2, ~0x28, ~0)|RS1(~23)|SIMM13(~0), "/,d", 0, v9a
}, /* rd %tick_cmpr,r */
1075 { "rd", F3(2, 0x28, 0)|RS1(24), F3(~2, ~0x28, ~0)|RS1(~24)|SIMM13(~0), "/,d", 0, v9b
}, /* rd %sys_tick,r */
1076 { "rd", F3(2, 0x28, 0)|RS1(25), F3(~2, ~0x28, ~0)|RS1(~25)|SIMM13(~0), "/,d", 0, v9b
}, /* rd %sys_tick_cmpr,r */
1078 { "rdpr", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|SIMM13(~0), "?,d", 0, v9
}, /* rdpr %priv,r */
1079 { "wrpr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0), "1,2,!", 0, v9
}, /* wrpr r1,r2,%priv */
1080 { "wrpr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|SIMM13(~0), "1,!", 0, v9
}, /* wrpr r1,%priv */
1081 { "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1), "1,i,!", 0, v9
}, /* wrpr r1,i,%priv */
1082 { "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1), "i,1,!", F_ALIAS
, v9
}, /* wrpr i,r1,%priv */
1083 { "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RS1(~0), "i,!", 0, v9
}, /* wrpr i,%priv */
1085 /* ??? This group seems wrong. A three operand move? */
1086 { "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", F_ALIAS
, v8
}, /* wr r,r,%asrX */
1087 { "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", F_ALIAS
, v8
}, /* wr r,i,%asrX */
1088 { "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0
|ASI(~0), "1,2,y", F_ALIAS
, v6
}, /* wr r,r,%y */
1089 { "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0
, "1,i,y", F_ALIAS
, v6
}, /* wr r,i,%y */
1090 { "mov", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0
|ASI(~0), "1,2,p", F_ALIAS
, v6notv9
}, /* wr r,r,%psr */
1091 { "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0
, "1,i,p", F_ALIAS
, v6notv9
}, /* wr r,i,%psr */
1092 { "mov", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0
|ASI(~0), "1,2,w", F_ALIAS
, v6notv9
}, /* wr r,r,%wim */
1093 { "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0
, "1,i,w", F_ALIAS
, v6notv9
}, /* wr r,i,%wim */
1094 { "mov", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0
|ASI(~0), "1,2,t", F_ALIAS
, v6notv9
}, /* wr r,r,%tbr */
1095 { "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0
, "1,i,t", F_ALIAS
, v6notv9
}, /* wr r,i,%tbr */
1097 { "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", F_ALIAS
, v8
}, /* rd %asr1,r */
1098 { "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0
|SIMM13(~0), "y,d", F_ALIAS
, v6
}, /* rd %y,r */
1099 { "mov", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0
|SIMM13(~0), "p,d", F_ALIAS
, v6notv9
}, /* rd %psr,r */
1100 { "mov", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0
|SIMM13(~0), "w,d", F_ALIAS
, v6notv9
}, /* rd %wim,r */
1101 { "mov", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0
|SIMM13(~0), "t,d", F_ALIAS
, v6notv9
}, /* rd %tbr,r */
1103 { "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0), "1,m", F_ALIAS
, v8
}, /* wr rs1,%g0,%asrX */
1104 { "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "i,m", F_ALIAS
, v8
}, /* wr %g0,i,%asrX */
1105 { "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|SIMM13(~0), "1,m", F_ALIAS
, v8
}, /* wr rs1,0,%asrX */
1106 { "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0
|ASI_RS2(~0), "1,y", F_ALIAS
, v6
}, /* wr rs1,%g0,%y */
1107 { "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0
, "i,y", F_ALIAS
, v6
}, /* wr %g0,i,%y */
1108 { "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0
|SIMM13(~0), "1,y", F_ALIAS
, v6
}, /* wr rs1,0,%y */
1109 { "mov", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0
|ASI_RS2(~0), "1,p", F_ALIAS
, v6notv9
}, /* wr rs1,%g0,%psr */
1110 { "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0
, "i,p", F_ALIAS
, v6notv9
}, /* wr %g0,i,%psr */
1111 { "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0
|SIMM13(~0), "1,p", F_ALIAS
, v6notv9
}, /* wr rs1,0,%psr */
1112 { "mov", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0
|ASI_RS2(~0), "1,w", F_ALIAS
, v6notv9
}, /* wr rs1,%g0,%wim */
1113 { "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0
, "i,w", F_ALIAS
, v6notv9
}, /* wr %g0,i,%wim */
1114 { "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0
|SIMM13(~0), "1,w", F_ALIAS
, v6notv9
}, /* wr rs1,0,%wim */
1115 { "mov", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0
|ASI_RS2(~0), "1,t", F_ALIAS
, v6notv9
}, /* wr rs1,%g0,%tbr */
1116 { "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0
, "i,t", F_ALIAS
, v6notv9
}, /* wr %g0,i,%tbr */
1117 { "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0
|SIMM13(~0), "1,t", F_ALIAS
, v6notv9
}, /* wr rs1,0,%tbr */
1119 { "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RS1_G0
|ASI(~0), "2,d", 0, v6
}, /* or %g0,rs2,d */
1120 { "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0
, "i,d", 0, v6
}, /* or %g0,i,d */
1121 { "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI_RS2(~0), "1,d", 0, v6
}, /* or rs1,%g0,d */
1122 { "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|SIMM13(~0), "1,d", 0, v6
}, /* or rs1,0,d */
1124 { "or", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "1,2,d", 0, v6
},
1125 { "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "1,i,d", 0, v6
},
1126 { "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,1,d", 0, v6
},
1128 { "bset", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "2,r", F_ALIAS
, v6
}, /* or rd,rs2,rd */
1129 { "bset", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,r", F_ALIAS
, v6
}, /* or rd,i,rd */
1131 /* This is not a commutative instruction. */
1132 { "andn", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "1,2,d", 0, v6
},
1133 { "andn", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "1,i,d", 0, v6
},
1135 /* This is not a commutative instruction. */
1136 { "andncc", F3(2, 0x15, 0), F3(~2, ~0x15, ~0)|ASI(~0), "1,2,d", 0, v6
},
1137 { "andncc", F3(2, 0x15, 1), F3(~2, ~0x15, ~1), "1,i,d", 0, v6
},
1139 { "bclr", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "2,r", F_ALIAS
, v6
}, /* andn rd,rs2,rd */
1140 { "bclr", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "i,r", F_ALIAS
, v6
}, /* andn rd,i,rd */
1142 { "cmp", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|RD_G0
|ASI(~0), "1,2", 0, v6
}, /* subcc rs1,rs2,%g0 */
1143 { "cmp", F3(2, 0x14, 1), F3(~2, ~0x14, ~1)|RD_G0
, "1,i", 0, v6
}, /* subcc rs1,i,%g0 */
1145 { "sub", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|ASI(~0), "1,2,d", 0, v6
},
1146 { "sub", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "1,i,d", 0, v6
},
1148 { "subcc", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|ASI(~0), "1,2,d", 0, v6
},
1149 { "subcc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "1,i,d", 0, v6
},
1151 { "subx", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, v6notv9
},
1152 { "subx", F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d", 0, v6notv9
},
1153 { "subc", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, v9
},
1154 { "subc", F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d", 0, v9
},
1156 { "subxcc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, v6notv9
},
1157 { "subxcc", F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d", 0, v6notv9
},
1158 { "subccc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, v9
},
1159 { "subccc", F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d", 0, v9
},
1161 { "and", F3(2, 0x01, 0), F3(~2, ~0x01, ~0)|ASI(~0), "1,2,d", 0, v6
},
1162 { "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "1,i,d", 0, v6
},
1163 { "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "i,1,d", 0, v6
},
1165 { "andcc", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|ASI(~0), "1,2,d", 0, v6
},
1166 { "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "1,i,d", 0, v6
},
1167 { "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "i,1,d", 0, v6
},
1169 { "dec", F3(2, 0x04, 1)|SIMM13(0x1), F3(~2, ~0x04, ~1)|SIMM13(~0x0001), "r", F_ALIAS
, v6
}, /* sub rd,1,rd */
1170 { "dec", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "i,r", F_ALIAS
, v8
}, /* sub rd,imm,rd */
1171 { "deccc", F3(2, 0x14, 1)|SIMM13(0x1), F3(~2, ~0x14, ~1)|SIMM13(~0x0001), "r", F_ALIAS
, v6
}, /* subcc rd,1,rd */
1172 { "deccc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "i,r", F_ALIAS
, v8
}, /* subcc rd,imm,rd */
1173 { "inc", F3(2, 0x00, 1)|SIMM13(0x1), F3(~2, ~0x00, ~1)|SIMM13(~0x0001), "r", F_ALIAS
, v6
}, /* add rd,1,rd */
1174 { "inc", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,r", F_ALIAS
, v8
}, /* add rd,imm,rd */
1175 { "inccc", F3(2, 0x10, 1)|SIMM13(0x1), F3(~2, ~0x10, ~1)|SIMM13(~0x0001), "r", F_ALIAS
, v6
}, /* addcc rd,1,rd */
1176 { "inccc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,r", F_ALIAS
, v8
}, /* addcc rd,imm,rd */
1178 { "btst", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|RD_G0
|ASI(~0), "1,2", F_ALIAS
, v6
}, /* andcc rs1,rs2,%g0 */
1179 { "btst", F3(2, 0x11, 1), F3(~2, ~0x11, ~1)|RD_G0
, "i,1", F_ALIAS
, v6
}, /* andcc rs1,i,%g0 */
1181 { "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0
|ASI(~0), "2,d", F_ALIAS
, v6
}, /* sub %g0,rs2,rd */
1182 { "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0
|ASI(~0), "O", F_ALIAS
, v6
}, /* sub %g0,rd,rd */
1184 { "add", F3(2, 0x00, 0), F3(~2, ~0x00, ~0)|ASI(~0), "1,2,d", 0, v6
},
1185 { "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "1,i,d", 0, v6
},
1186 { "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,1,d", 0, v6
},
1187 { "addcc", F3(2, 0x10, 0), F3(~2, ~0x10, ~0)|ASI(~0), "1,2,d", 0, v6
},
1188 { "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "1,i,d", 0, v6
},
1189 { "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,1,d", 0, v6
},
1191 { "addx", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, v6notv9
},
1192 { "addx", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d", 0, v6notv9
},
1193 { "addx", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d", 0, v6notv9
},
1194 { "addc", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, v9
},
1195 { "addc", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d", 0, v9
},
1196 { "addc", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d", 0, v9
},
1198 { "addxcc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, v6notv9
},
1199 { "addxcc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d", 0, v6notv9
},
1200 { "addxcc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d", 0, v6notv9
},
1201 { "addccc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, v9
},
1202 { "addccc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d", 0, v9
},
1203 { "addccc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d", 0, v9
},
1205 { "smul", F3(2, 0x0b, 0), F3(~2, ~0x0b, ~0)|ASI(~0), "1,2,d", 0, v8
},
1206 { "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "1,i,d", 0, v8
},
1207 { "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "i,1,d", 0, v8
},
1208 { "smulcc", F3(2, 0x1b, 0), F3(~2, ~0x1b, ~0)|ASI(~0), "1,2,d", 0, v8
},
1209 { "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "1,i,d", 0, v8
},
1210 { "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "i,1,d", 0, v8
},
1211 { "umul", F3(2, 0x0a, 0), F3(~2, ~0x0a, ~0)|ASI(~0), "1,2,d", 0, v8
},
1212 { "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "1,i,d", 0, v8
},
1213 { "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "i,1,d", 0, v8
},
1214 { "umulcc", F3(2, 0x1a, 0), F3(~2, ~0x1a, ~0)|ASI(~0), "1,2,d", 0, v8
},
1215 { "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "1,i,d", 0, v8
},
1216 { "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "i,1,d", 0, v8
},
1217 { "sdiv", F3(2, 0x0f, 0), F3(~2, ~0x0f, ~0)|ASI(~0), "1,2,d", 0, v8
},
1218 { "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "1,i,d", 0, v8
},
1219 { "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "i,1,d", 0, v8
},
1220 { "sdivcc", F3(2, 0x1f, 0), F3(~2, ~0x1f, ~0)|ASI(~0), "1,2,d", 0, v8
},
1221 { "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "1,i,d", 0, v8
},
1222 { "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "i,1,d", 0, v8
},
1223 { "udiv", F3(2, 0x0e, 0), F3(~2, ~0x0e, ~0)|ASI(~0), "1,2,d", 0, v8
},
1224 { "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "1,i,d", 0, v8
},
1225 { "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "i,1,d", 0, v8
},
1226 { "udivcc", F3(2, 0x1e, 0), F3(~2, ~0x1e, ~0)|ASI(~0), "1,2,d", 0, v8
},
1227 { "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "1,i,d", 0, v8
},
1228 { "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "i,1,d", 0, v8
},
1230 { "mulx", F3(2, 0x09, 0), F3(~2, ~0x09, ~0)|ASI(~0), "1,2,d", 0, v9
},
1231 { "mulx", F3(2, 0x09, 1), F3(~2, ~0x09, ~1), "1,i,d", 0, v9
},
1232 { "sdivx", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, v9
},
1233 { "sdivx", F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d", 0, v9
},
1234 { "udivx", F3(2, 0x0d, 0), F3(~2, ~0x0d, ~0)|ASI(~0), "1,2,d", 0, v9
},
1235 { "udivx", F3(2, 0x0d, 1), F3(~2, ~0x0d, ~1), "1,i,d", 0, v9
},
1237 { "call", F1(0x1), F1(~0x1), "L", F_JSR
|F_DELAYED
, v6
},
1238 { "call", F1(0x1), F1(~0x1), "L,#", F_JSR
|F_DELAYED
, v6
},
1240 { "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2", F_JSR
|F_DELAYED
, v6
}, /* jmpl rs1+rs2,%o7 */
1241 { "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2,#", F_JSR
|F_DELAYED
, v6
},
1242 { "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1", F_JSR
|F_DELAYED
, v6
}, /* jmpl rs1+%g0,%o7 */
1243 { "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1,#", F_JSR
|F_DELAYED
, v6
},
1244 { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "1+i", F_JSR
|F_DELAYED
, v6
}, /* jmpl rs1+i,%o7 */
1245 { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "1+i,#", F_JSR
|F_DELAYED
, v6
},
1246 { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "i+1", F_JSR
|F_DELAYED
, v6
}, /* jmpl i+rs1,%o7 */
1247 { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "i+1,#", F_JSR
|F_DELAYED
, v6
},
1248 { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0
, "i", F_JSR
|F_DELAYED
, v6
}, /* jmpl %g0+i,%o7 */
1249 { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0
, "i,#", F_JSR
|F_DELAYED
, v6
},
1250 { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1", F_JSR
|F_DELAYED
, v6
}, /* jmpl rs1+0,%o7 */
1251 { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1,#", F_JSR
|F_DELAYED
, v6
},
1254 /* Conditional instructions.
1256 Because this part of the table was such a mess earlier, I have
1257 macrofied it so that all the branches and traps are generated from
1258 a single-line description of each condition value. John Gilmore. */
1260 /* Define branches -- one annulled, one without, etc. */
1261 #define br(opcode, mask, lose, flags) \
1262 { opcode, (mask)|ANNUL, (lose), ",a l", (flags), v6 }, \
1263 { opcode, (mask) , (lose)|ANNUL, "l", (flags), v6 }
1265 #define brx(opcode, mask, lose, flags) /* v9 */ \
1266 { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), "Z,G", (flags), v9 }, \
1267 { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), ",T Z,G", (flags), v9 }, \
1268 { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a Z,G", (flags), v9 }, \
1269 { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a,T Z,G", (flags), v9 }, \
1270 { opcode, (mask)|(2<<20), ANNUL|BPRED|(lose), ",N Z,G", (flags), v9 }, \
1271 { opcode, (mask)|(2<<20)|ANNUL, BPRED|(lose), ",a,N Z,G", (flags), v9 }, \
1272 { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), "z,G", (flags), v9 }, \
1273 { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), ",T z,G", (flags), v9 }, \
1274 { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a z,G", (flags), v9 }, \
1275 { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a,T z,G", (flags), v9 }, \
1276 { opcode, (mask), ANNUL|BPRED|(lose)|(2<<20), ",N z,G", (flags), v9 }, \
1277 { opcode, (mask)|ANNUL, BPRED|(lose)|(2<<20), ",a,N z,G", (flags), v9 }
1279 /* Define four traps: reg+reg, reg + immediate, immediate alone, reg alone. */
1280 #define tr(opcode, mask, lose, flags) \
1281 { opcode, (mask)|(2<<11)|IMMED, (lose)|RS1_G0, "Z,i", (flags), v9 }, /* %g0 + imm */ \
1282 { opcode, (mask)|(2<<11)|IMMED, (lose), "Z,1+i", (flags), v9 }, /* rs1 + imm */ \
1283 { opcode, (mask)|(2<<11), IMMED|(lose), "Z,1+2", (flags), v9 }, /* rs1 + rs2 */ \
1284 { opcode, (mask)|(2<<11), IMMED|(lose)|RS2_G0, "Z,1", (flags), v9 }, /* rs1 + %g0 */ \
1285 { opcode, (mask)|IMMED, (lose)|RS1_G0, "z,i", (flags)|F_ALIAS, v9 }, /* %g0 + imm */ \
1286 { opcode, (mask)|IMMED, (lose), "z,1+i", (flags)|F_ALIAS, v9 }, /* rs1 + imm */ \
1287 { opcode, (mask), IMMED|(lose), "z,1+2", (flags)|F_ALIAS, v9 }, /* rs1 + rs2 */ \
1288 { opcode, (mask), IMMED|(lose)|RS2_G0, "z,1", (flags)|F_ALIAS, v9 }, /* rs1 + %g0 */ \
1289 { opcode, (mask)|IMMED, (lose)|RS1_G0, "i", (flags), v6 }, /* %g0 + imm */ \
1290 { opcode, (mask)|IMMED, (lose), "1+i", (flags), v6 }, /* rs1 + imm */ \
1291 { opcode, (mask), IMMED|(lose), "1+2", (flags), v6 }, /* rs1 + rs2 */ \
1292 { opcode, (mask), IMMED|(lose)|RS2_G0, "1", (flags), v6 } /* rs1 + %g0 */
1294 /* v9: We must put `brx' before `br', to ensure that we never match something
1295 v9: against an expression unless it is an expression. Otherwise, we end
1296 v9: up with undefined symbol tables entries, because they get added, but
1297 v9: are not deleted if the pattern fails to match. */
1299 /* Define both branches and traps based on condition mask */
1300 #define cond(bop, top, mask, flags) \
1301 brx(bop, F2(0, 1)|(mask), F2(~0, ~1)|((~mask)&COND(~0)), F_DELAYED|(flags)), /* v9 */ \
1302 br(bop, F2(0, 2)|(mask), F2(~0, ~2)|((~mask)&COND(~0)), F_DELAYED|(flags)), \
1303 tr(top, F3(2, 0x3a, 0)|(mask), F3(~2, ~0x3a, 0)|((~mask)&COND(~0)), ((flags) & ~(F_UNBR|F_CONDBR)))
1305 /* Define all the conditions, all the branches, all the traps. */
1307 /* Standard branch, trap mnemonics */
1308 cond ("b", "ta", CONDA
, F_UNBR
),
1309 /* Alternative form (just for assembly, not for disassembly) */
1310 cond ("ba", "t", CONDA
, F_UNBR
|F_ALIAS
),
1312 cond ("bcc", "tcc", CONDCC
, F_CONDBR
),
1313 cond ("bcs", "tcs", CONDCS
, F_CONDBR
),
1314 cond ("be", "te", CONDE
, F_CONDBR
),
1315 cond ("beq", "teq", CONDE
, F_CONDBR
|F_ALIAS
),
1316 cond ("bg", "tg", CONDG
, F_CONDBR
),
1317 cond ("bgt", "tgt", CONDG
, F_CONDBR
|F_ALIAS
),
1318 cond ("bge", "tge", CONDGE
, F_CONDBR
),
1319 cond ("bgeu", "tgeu", CONDGEU
, F_CONDBR
|F_ALIAS
), /* for cc */
1320 cond ("bgu", "tgu", CONDGU
, F_CONDBR
),
1321 cond ("bl", "tl", CONDL
, F_CONDBR
),
1322 cond ("blt", "tlt", CONDL
, F_CONDBR
|F_ALIAS
),
1323 cond ("ble", "tle", CONDLE
, F_CONDBR
),
1324 cond ("bleu", "tleu", CONDLEU
, F_CONDBR
),
1325 cond ("blu", "tlu", CONDLU
, F_CONDBR
|F_ALIAS
), /* for cs */
1326 cond ("bn", "tn", CONDN
, F_CONDBR
),
1327 cond ("bne", "tne", CONDNE
, F_CONDBR
),
1328 cond ("bneg", "tneg", CONDNEG
, F_CONDBR
),
1329 cond ("bnz", "tnz", CONDNZ
, F_CONDBR
|F_ALIAS
), /* for ne */
1330 cond ("bpos", "tpos", CONDPOS
, F_CONDBR
),
1331 cond ("bvc", "tvc", CONDVC
, F_CONDBR
),
1332 cond ("bvs", "tvs", CONDVS
, F_CONDBR
),
1333 cond ("bz", "tz", CONDZ
, F_CONDBR
|F_ALIAS
), /* for e */
1340 #define brr(opcode, mask, lose, flags) /* v9 */ \
1341 { opcode, (mask)|BPRED, ANNUL|(lose), "1,k", F_DELAYED|(flags), v9 }, \
1342 { opcode, (mask)|BPRED, ANNUL|(lose), ",T 1,k", F_DELAYED|(flags), v9 }, \
1343 { opcode, (mask)|BPRED|ANNUL, (lose), ",a 1,k", F_DELAYED|(flags), v9 }, \
1344 { opcode, (mask)|BPRED|ANNUL, (lose), ",a,T 1,k", F_DELAYED|(flags), v9 }, \
1345 { opcode, (mask), ANNUL|BPRED|(lose), ",N 1,k", F_DELAYED|(flags), v9 }, \
1346 { opcode, (mask)|ANNUL, BPRED|(lose), ",a,N 1,k", F_DELAYED|(flags), v9 }
1348 #define condr(bop, mask, flags) /* v9 */ \
1349 brr(bop, F2(0, 3)|COND(mask), F2(~0, ~3)|COND(~(mask)), (flags)) /* v9 */
1351 /* v9 */ condr("brnz", 0x5, F_CONDBR
),
1352 /* v9 */ condr("brz", 0x1, F_CONDBR
),
1353 /* v9 */ condr("brgez", 0x7, F_CONDBR
),
1354 /* v9 */ condr("brlz", 0x3, F_CONDBR
),
1355 /* v9 */ condr("brlez", 0x2, F_CONDBR
),
1356 /* v9 */ condr("brgz", 0x6, F_CONDBR
),
1358 #undef condr /* v9 */
1361 #define movr(opcode, mask, flags) /* v9 */ \
1362 { opcode, F3(2, 0x2f, 0)|RCOND(mask), F3(~2, ~0x2f, ~0)|RCOND(~(mask)), "1,2,d", (flags), v9 }, \
1363 { opcode, F3(2, 0x2f, 1)|RCOND(mask), F3(~2, ~0x2f, ~1)|RCOND(~(mask)), "1,j,d", (flags), v9 }
1365 #define fmrrs(opcode, mask, lose, flags) /* v9 */ \
1366 { opcode, (mask), (lose), "1,f,g", (flags) | F_FLOAT, v9 }
1367 #define fmrrd(opcode, mask, lose, flags) /* v9 */ \
1368 { opcode, (mask), (lose), "1,B,H", (flags) | F_FLOAT, v9 }
1369 #define fmrrq(opcode, mask, lose, flags) /* v9 */ \
1370 { opcode, (mask), (lose), "1,R,J", (flags) | F_FLOAT, v9 }
1372 #define fmovrs(mop, mask, flags) /* v9 */ \
1373 fmrrs(mop, F3(2, 0x35, 0)|OPF_LOW5(5)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~5)|RCOND(~(mask)), (flags)) /* v9 */
1374 #define fmovrd(mop, mask, flags) /* v9 */ \
1375 fmrrd(mop, F3(2, 0x35, 0)|OPF_LOW5(6)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~6)|RCOND(~(mask)), (flags)) /* v9 */
1376 #define fmovrq(mop, mask, flags) /* v9 */ \
1377 fmrrq(mop, F3(2, 0x35, 0)|OPF_LOW5(7)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~7)|RCOND(~(mask)), (flags)) /* v9 */
1379 /* v9 */ movr("movrne", 0x5, 0),
1380 /* v9 */ movr("movre", 0x1, 0),
1381 /* v9 */ movr("movrgez", 0x7, 0),
1382 /* v9 */ movr("movrlz", 0x3, 0),
1383 /* v9 */ movr("movrlez", 0x2, 0),
1384 /* v9 */ movr("movrgz", 0x6, 0),
1385 /* v9 */ movr("movrnz", 0x5, F_ALIAS
),
1386 /* v9 */ movr("movrz", 0x1, F_ALIAS
),
1388 /* v9 */ fmovrs("fmovrsne", 0x5, 0),
1389 /* v9 */ fmovrs("fmovrse", 0x1, 0),
1390 /* v9 */ fmovrs("fmovrsgez", 0x7, 0),
1391 /* v9 */ fmovrs("fmovrslz", 0x3, 0),
1392 /* v9 */ fmovrs("fmovrslez", 0x2, 0),
1393 /* v9 */ fmovrs("fmovrsgz", 0x6, 0),
1394 /* v9 */ fmovrs("fmovrsnz", 0x5, F_ALIAS
),
1395 /* v9 */ fmovrs("fmovrsz", 0x1, F_ALIAS
),
1397 /* v9 */ fmovrd("fmovrdne", 0x5, 0),
1398 /* v9 */ fmovrd("fmovrde", 0x1, 0),
1399 /* v9 */ fmovrd("fmovrdgez", 0x7, 0),
1400 /* v9 */ fmovrd("fmovrdlz", 0x3, 0),
1401 /* v9 */ fmovrd("fmovrdlez", 0x2, 0),
1402 /* v9 */ fmovrd("fmovrdgz", 0x6, 0),
1403 /* v9 */ fmovrd("fmovrdnz", 0x5, F_ALIAS
),
1404 /* v9 */ fmovrd("fmovrdz", 0x1, F_ALIAS
),
1406 /* v9 */ fmovrq("fmovrqne", 0x5, 0),
1407 /* v9 */ fmovrq("fmovrqe", 0x1, 0),
1408 /* v9 */ fmovrq("fmovrqgez", 0x7, 0),
1409 /* v9 */ fmovrq("fmovrqlz", 0x3, 0),
1410 /* v9 */ fmovrq("fmovrqlez", 0x2, 0),
1411 /* v9 */ fmovrq("fmovrqgz", 0x6, 0),
1412 /* v9 */ fmovrq("fmovrqnz", 0x5, F_ALIAS
),
1413 /* v9 */ fmovrq("fmovrqz", 0x1, F_ALIAS
),
1415 #undef movr /* v9 */
1416 #undef fmovr /* v9 */
1417 #undef fmrr /* v9 */
1419 #define movicc(opcode, cond, flags) /* v9 */ \
1420 { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|XCC|(1<<11), "z,2,d", flags, v9 }, \
1421 { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|XCC|(1<<11), "z,I,d", flags, v9 }, \
1422 { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|(1<<11), "Z,2,d", flags, v9 }, \
1423 { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|(1<<11), "Z,I,d", flags, v9 }
1425 #define movfcc(opcode, fcond, flags) /* v9 */ \
1426 { opcode, F3(2, 0x2c, 0)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~0), "6,2,d", flags, v9 }, \
1427 { opcode, F3(2, 0x2c, 1)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~1), "6,I,d", flags, v9 }, \
1428 { opcode, F3(2, 0x2c, 0)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~0), "7,2,d", flags, v9 }, \
1429 { opcode, F3(2, 0x2c, 1)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~1), "7,I,d", flags, v9 }, \
1430 { opcode, F3(2, 0x2c, 0)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~0), "8,2,d", flags, v9 }, \
1431 { opcode, F3(2, 0x2c, 1)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~1), "8,I,d", flags, v9 }, \
1432 { opcode, F3(2, 0x2c, 0)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~0), "9,2,d", flags, v9 }, \
1433 { opcode, F3(2, 0x2c, 1)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~1), "9,I,d", flags, v9 }
1435 #define movcc(opcode, cond, fcond, flags) /* v9 */ \
1436 movfcc (opcode, fcond, flags), /* v9 */ \
1437 movicc (opcode, cond, flags) /* v9 */
1439 /* v9 */ movcc ("mova", CONDA
, FCONDA
, 0),
1440 /* v9 */ movicc ("movcc", CONDCC
, 0),
1441 /* v9 */ movicc ("movgeu", CONDGEU
, F_ALIAS
),
1442 /* v9 */ movicc ("movcs", CONDCS
, 0),
1443 /* v9 */ movicc ("movlu", CONDLU
, F_ALIAS
),
1444 /* v9 */ movcc ("move", CONDE
, FCONDE
, 0),
1445 /* v9 */ movcc ("movg", CONDG
, FCONDG
, 0),
1446 /* v9 */ movcc ("movge", CONDGE
, FCONDGE
, 0),
1447 /* v9 */ movicc ("movgu", CONDGU
, 0),
1448 /* v9 */ movcc ("movl", CONDL
, FCONDL
, 0),
1449 /* v9 */ movcc ("movle", CONDLE
, FCONDLE
, 0),
1450 /* v9 */ movicc ("movleu", CONDLEU
, 0),
1451 /* v9 */ movfcc ("movlg", FCONDLG
, 0),
1452 /* v9 */ movcc ("movn", CONDN
, FCONDN
, 0),
1453 /* v9 */ movcc ("movne", CONDNE
, FCONDNE
, 0),
1454 /* v9 */ movicc ("movneg", CONDNEG
, 0),
1455 /* v9 */ movcc ("movnz", CONDNZ
, FCONDNZ
, F_ALIAS
),
1456 /* v9 */ movfcc ("movo", FCONDO
, 0),
1457 /* v9 */ movicc ("movpos", CONDPOS
, 0),
1458 /* v9 */ movfcc ("movu", FCONDU
, 0),
1459 /* v9 */ movfcc ("movue", FCONDUE
, 0),
1460 /* v9 */ movfcc ("movug", FCONDUG
, 0),
1461 /* v9 */ movfcc ("movuge", FCONDUGE
, 0),
1462 /* v9 */ movfcc ("movul", FCONDUL
, 0),
1463 /* v9 */ movfcc ("movule", FCONDULE
, 0),
1464 /* v9 */ movicc ("movvc", CONDVC
, 0),
1465 /* v9 */ movicc ("movvs", CONDVS
, 0),
1466 /* v9 */ movcc ("movz", CONDZ
, FCONDZ
, F_ALIAS
),
1468 #undef movicc /* v9 */
1469 #undef movfcc /* v9 */
1470 #undef movcc /* v9 */
1472 #define FM_SF 1 /* v9 - values for fpsize */
1473 #define FM_DF 2 /* v9 */
1474 #define FM_QF 3 /* v9 */
1476 #define fmovicc(opcode, fpsize, cond, flags) /* v9 */ \
1477 { opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z,f,g", flags, v9 }, \
1478 { opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z,f,g", flags, v9 }
1480 #define fmovfcc(opcode, fpsize, fcond, flags) /* v9 */ \
1481 { opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6,f,g", flags, v9 }, \
1482 { opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7,f,g", flags, v9 }, \
1483 { opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8,f,g", flags, v9 }, \
1484 { opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9,f,g", flags, v9 }
1486 /* FIXME: use fmovicc/fmovfcc? */ /* v9 */
1487 #define fmovcc(opcode, fpsize, cond, fcond, flags) /* v9 */ \
1488 { opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z,f,g", flags | F_FLOAT, v9 }, \
1489 { opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6,f,g", flags | F_FLOAT, v9 }, \
1490 { opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z,f,g", flags | F_FLOAT, v9 }, \
1491 { opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7,f,g", flags | F_FLOAT, v9 }, \
1492 { opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8,f,g", flags | F_FLOAT, v9 }, \
1493 { opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9,f,g", flags | F_FLOAT, v9 }
1495 /* v9 */ fmovcc ("fmovda", FM_DF
, CONDA
, FCONDA
, 0),
1496 /* v9 */ fmovcc ("fmovqa", FM_QF
, CONDA
, FCONDA
, 0),
1497 /* v9 */ fmovcc ("fmovsa", FM_SF
, CONDA
, FCONDA
, 0),
1498 /* v9 */ fmovicc ("fmovdcc", FM_DF
, CONDCC
, 0),
1499 /* v9 */ fmovicc ("fmovqcc", FM_QF
, CONDCC
, 0),
1500 /* v9 */ fmovicc ("fmovscc", FM_SF
, CONDCC
, 0),
1501 /* v9 */ fmovicc ("fmovdcs", FM_DF
, CONDCS
, 0),
1502 /* v9 */ fmovicc ("fmovqcs", FM_QF
, CONDCS
, 0),
1503 /* v9 */ fmovicc ("fmovscs", FM_SF
, CONDCS
, 0),
1504 /* v9 */ fmovcc ("fmovde", FM_DF
, CONDE
, FCONDE
, 0),
1505 /* v9 */ fmovcc ("fmovqe", FM_QF
, CONDE
, FCONDE
, 0),
1506 /* v9 */ fmovcc ("fmovse", FM_SF
, CONDE
, FCONDE
, 0),
1507 /* v9 */ fmovcc ("fmovdg", FM_DF
, CONDG
, FCONDG
, 0),
1508 /* v9 */ fmovcc ("fmovqg", FM_QF
, CONDG
, FCONDG
, 0),
1509 /* v9 */ fmovcc ("fmovsg", FM_SF
, CONDG
, FCONDG
, 0),
1510 /* v9 */ fmovcc ("fmovdge", FM_DF
, CONDGE
, FCONDGE
, 0),
1511 /* v9 */ fmovcc ("fmovqge", FM_QF
, CONDGE
, FCONDGE
, 0),
1512 /* v9 */ fmovcc ("fmovsge", FM_SF
, CONDGE
, FCONDGE
, 0),
1513 /* v9 */ fmovicc ("fmovdgeu", FM_DF
, CONDGEU
, F_ALIAS
),
1514 /* v9 */ fmovicc ("fmovqgeu", FM_QF
, CONDGEU
, F_ALIAS
),
1515 /* v9 */ fmovicc ("fmovsgeu", FM_SF
, CONDGEU
, F_ALIAS
),
1516 /* v9 */ fmovicc ("fmovdgu", FM_DF
, CONDGU
, 0),
1517 /* v9 */ fmovicc ("fmovqgu", FM_QF
, CONDGU
, 0),
1518 /* v9 */ fmovicc ("fmovsgu", FM_SF
, CONDGU
, 0),
1519 /* v9 */ fmovcc ("fmovdl", FM_DF
, CONDL
, FCONDL
, 0),
1520 /* v9 */ fmovcc ("fmovql", FM_QF
, CONDL
, FCONDL
, 0),
1521 /* v9 */ fmovcc ("fmovsl", FM_SF
, CONDL
, FCONDL
, 0),
1522 /* v9 */ fmovcc ("fmovdle", FM_DF
, CONDLE
, FCONDLE
, 0),
1523 /* v9 */ fmovcc ("fmovqle", FM_QF
, CONDLE
, FCONDLE
, 0),
1524 /* v9 */ fmovcc ("fmovsle", FM_SF
, CONDLE
, FCONDLE
, 0),
1525 /* v9 */ fmovicc ("fmovdleu", FM_DF
, CONDLEU
, 0),
1526 /* v9 */ fmovicc ("fmovqleu", FM_QF
, CONDLEU
, 0),
1527 /* v9 */ fmovicc ("fmovsleu", FM_SF
, CONDLEU
, 0),
1528 /* v9 */ fmovfcc ("fmovdlg", FM_DF
, FCONDLG
, 0),
1529 /* v9 */ fmovfcc ("fmovqlg", FM_QF
, FCONDLG
, 0),
1530 /* v9 */ fmovfcc ("fmovslg", FM_SF
, FCONDLG
, 0),
1531 /* v9 */ fmovicc ("fmovdlu", FM_DF
, CONDLU
, F_ALIAS
),
1532 /* v9 */ fmovicc ("fmovqlu", FM_QF
, CONDLU
, F_ALIAS
),
1533 /* v9 */ fmovicc ("fmovslu", FM_SF
, CONDLU
, F_ALIAS
),
1534 /* v9 */ fmovcc ("fmovdn", FM_DF
, CONDN
, FCONDN
, 0),
1535 /* v9 */ fmovcc ("fmovqn", FM_QF
, CONDN
, FCONDN
, 0),
1536 /* v9 */ fmovcc ("fmovsn", FM_SF
, CONDN
, FCONDN
, 0),
1537 /* v9 */ fmovcc ("fmovdne", FM_DF
, CONDNE
, FCONDNE
, 0),
1538 /* v9 */ fmovcc ("fmovqne", FM_QF
, CONDNE
, FCONDNE
, 0),
1539 /* v9 */ fmovcc ("fmovsne", FM_SF
, CONDNE
, FCONDNE
, 0),
1540 /* v9 */ fmovicc ("fmovdneg", FM_DF
, CONDNEG
, 0),
1541 /* v9 */ fmovicc ("fmovqneg", FM_QF
, CONDNEG
, 0),
1542 /* v9 */ fmovicc ("fmovsneg", FM_SF
, CONDNEG
, 0),
1543 /* v9 */ fmovcc ("fmovdnz", FM_DF
, CONDNZ
, FCONDNZ
, F_ALIAS
),
1544 /* v9 */ fmovcc ("fmovqnz", FM_QF
, CONDNZ
, FCONDNZ
, F_ALIAS
),
1545 /* v9 */ fmovcc ("fmovsnz", FM_SF
, CONDNZ
, FCONDNZ
, F_ALIAS
),
1546 /* v9 */ fmovfcc ("fmovdo", FM_DF
, FCONDO
, 0),
1547 /* v9 */ fmovfcc ("fmovqo", FM_QF
, FCONDO
, 0),
1548 /* v9 */ fmovfcc ("fmovso", FM_SF
, FCONDO
, 0),
1549 /* v9 */ fmovicc ("fmovdpos", FM_DF
, CONDPOS
, 0),
1550 /* v9 */ fmovicc ("fmovqpos", FM_QF
, CONDPOS
, 0),
1551 /* v9 */ fmovicc ("fmovspos", FM_SF
, CONDPOS
, 0),
1552 /* v9 */ fmovfcc ("fmovdu", FM_DF
, FCONDU
, 0),
1553 /* v9 */ fmovfcc ("fmovqu", FM_QF
, FCONDU
, 0),
1554 /* v9 */ fmovfcc ("fmovsu", FM_SF
, FCONDU
, 0),
1555 /* v9 */ fmovfcc ("fmovdue", FM_DF
, FCONDUE
, 0),
1556 /* v9 */ fmovfcc ("fmovque", FM_QF
, FCONDUE
, 0),
1557 /* v9 */ fmovfcc ("fmovsue", FM_SF
, FCONDUE
, 0),
1558 /* v9 */ fmovfcc ("fmovdug", FM_DF
, FCONDUG
, 0),
1559 /* v9 */ fmovfcc ("fmovqug", FM_QF
, FCONDUG
, 0),
1560 /* v9 */ fmovfcc ("fmovsug", FM_SF
, FCONDUG
, 0),
1561 /* v9 */ fmovfcc ("fmovduge", FM_DF
, FCONDUGE
, 0),
1562 /* v9 */ fmovfcc ("fmovquge", FM_QF
, FCONDUGE
, 0),
1563 /* v9 */ fmovfcc ("fmovsuge", FM_SF
, FCONDUGE
, 0),
1564 /* v9 */ fmovfcc ("fmovdul", FM_DF
, FCONDUL
, 0),
1565 /* v9 */ fmovfcc ("fmovqul", FM_QF
, FCONDUL
, 0),
1566 /* v9 */ fmovfcc ("fmovsul", FM_SF
, FCONDUL
, 0),
1567 /* v9 */ fmovfcc ("fmovdule", FM_DF
, FCONDULE
, 0),
1568 /* v9 */ fmovfcc ("fmovqule", FM_QF
, FCONDULE
, 0),
1569 /* v9 */ fmovfcc ("fmovsule", FM_SF
, FCONDULE
, 0),
1570 /* v9 */ fmovicc ("fmovdvc", FM_DF
, CONDVC
, 0),
1571 /* v9 */ fmovicc ("fmovqvc", FM_QF
, CONDVC
, 0),
1572 /* v9 */ fmovicc ("fmovsvc", FM_SF
, CONDVC
, 0),
1573 /* v9 */ fmovicc ("fmovdvs", FM_DF
, CONDVS
, 0),
1574 /* v9 */ fmovicc ("fmovqvs", FM_QF
, CONDVS
, 0),
1575 /* v9 */ fmovicc ("fmovsvs", FM_SF
, CONDVS
, 0),
1576 /* v9 */ fmovcc ("fmovdz", FM_DF
, CONDZ
, FCONDZ
, F_ALIAS
),
1577 /* v9 */ fmovcc ("fmovqz", FM_QF
, CONDZ
, FCONDZ
, F_ALIAS
),
1578 /* v9 */ fmovcc ("fmovsz", FM_SF
, CONDZ
, FCONDZ
, F_ALIAS
),
1580 #undef fmovicc /* v9 */
1581 #undef fmovfcc /* v9 */
1582 #undef fmovcc /* v9 */
1583 #undef FM_DF /* v9 */
1584 #undef FM_QF /* v9 */
1585 #undef FM_SF /* v9 */
1587 /* Coprocessor branches. */
1588 #define CBR(opcode, mask, lose, flags, arch) \
1589 { opcode, (mask), ANNUL|(lose), "l", flags|F_DELAYED, arch }, \
1590 { opcode, (mask)|ANNUL, (lose), ",a l", flags|F_DELAYED, arch }
1592 /* Floating point branches. */
1593 #define FBR(opcode, mask, lose, flags) \
1594 { opcode, (mask), ANNUL|(lose), "l", flags|F_DELAYED|F_FBR, v6 }, \
1595 { opcode, (mask)|ANNUL, (lose), ",a l", flags|F_DELAYED|F_FBR, v6 }
1597 /* V9 extended floating point branches. */
1598 #define FBRX(opcode, mask, lose, flags) /* v9 */ \
1599 { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), "6,G", flags|F_DELAYED|F_FBR, v9 }, \
1600 { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), ",T 6,G", flags|F_DELAYED|F_FBR, v9 }, \
1601 { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a 6,G", flags|F_DELAYED|F_FBR, v9 }, \
1602 { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a,T 6,G", flags|F_DELAYED|F_FBR, v9 }, \
1603 { opcode, FBFCC(0)|(mask), ANNUL|BPRED|FBFCC(~0)|(lose), ",N 6,G", flags|F_DELAYED|F_FBR, v9 }, \
1604 { opcode, FBFCC(0)|(mask)|ANNUL, BPRED|FBFCC(~0)|(lose), ",a,N 6,G", flags|F_DELAYED|F_FBR, v9 }, \
1605 { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), "7,G", flags|F_DELAYED|F_FBR, v9 }, \
1606 { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), ",T 7,G", flags|F_DELAYED|F_FBR, v9 }, \
1607 { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a 7,G", flags|F_DELAYED|F_FBR, v9 }, \
1608 { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a,T 7,G", flags|F_DELAYED|F_FBR, v9 }, \
1609 { opcode, FBFCC(1)|(mask), ANNUL|BPRED|FBFCC(~1)|(lose), ",N 7,G", flags|F_DELAYED|F_FBR, v9 }, \
1610 { opcode, FBFCC(1)|(mask)|ANNUL, BPRED|FBFCC(~1)|(lose), ",a,N 7,G", flags|F_DELAYED|F_FBR, v9 }, \
1611 { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), "8,G", flags|F_DELAYED|F_FBR, v9 }, \
1612 { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), ",T 8,G", flags|F_DELAYED|F_FBR, v9 }, \
1613 { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a 8,G", flags|F_DELAYED|F_FBR, v9 }, \
1614 { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a,T 8,G", flags|F_DELAYED|F_FBR, v9 }, \
1615 { opcode, FBFCC(2)|(mask), ANNUL|BPRED|FBFCC(~2)|(lose), ",N 8,G", flags|F_DELAYED|F_FBR, v9 }, \
1616 { opcode, FBFCC(2)|(mask)|ANNUL, BPRED|FBFCC(~2)|(lose), ",a,N 8,G", flags|F_DELAYED|F_FBR, v9 }, \
1617 { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), "9,G", flags|F_DELAYED|F_FBR, v9 }, \
1618 { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), ",T 9,G", flags|F_DELAYED|F_FBR, v9 }, \
1619 { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a 9,G", flags|F_DELAYED|F_FBR, v9 }, \
1620 { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a,T 9,G", flags|F_DELAYED|F_FBR, v9 }, \
1621 { opcode, FBFCC(3)|(mask), ANNUL|BPRED|FBFCC(~3)|(lose), ",N 9,G", flags|F_DELAYED|F_FBR, v9 }, \
1622 { opcode, FBFCC(3)|(mask)|ANNUL, BPRED|FBFCC(~3)|(lose), ",a,N 9,G", flags|F_DELAYED|F_FBR, v9 }
1624 /* v9: We must put `FBRX' before `FBR', to ensure that we never match
1625 v9: something against an expression unless it is an expression. Otherwise,
1626 v9: we end up with undefined symbol tables entries, because they get added,
1627 v9: but are not deleted if the pattern fails to match. */
1629 #define CONDFC(fop, cop, mask, flags) \
1630 FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \
1631 FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \
1632 CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6notlet)
1634 #define CONDFCL(fop, cop, mask, flags) \
1635 FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \
1636 FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \
1637 CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6)
1639 #define CONDF(fop, mask, flags) \
1640 FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \
1641 FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags)
1643 CONDFC ("fb", "cb", 0x8, F_UNBR
),
1644 CONDFCL ("fba", "cba", 0x8, F_UNBR
|F_ALIAS
),
1645 CONDFC ("fbe", "cb0", 0x9, F_CONDBR
),
1646 CONDF ("fbz", 0x9, F_CONDBR
|F_ALIAS
),
1647 CONDFC ("fbg", "cb2", 0x6, F_CONDBR
),
1648 CONDFC ("fbge", "cb02", 0xb, F_CONDBR
),
1649 CONDFC ("fbl", "cb1", 0x4, F_CONDBR
),
1650 CONDFC ("fble", "cb01", 0xd, F_CONDBR
),
1651 CONDFC ("fblg", "cb12", 0x2, F_CONDBR
),
1652 CONDFCL ("fbn", "cbn", 0x0, F_UNBR
),
1653 CONDFC ("fbne", "cb123", 0x1, F_CONDBR
),
1654 CONDF ("fbnz", 0x1, F_CONDBR
|F_ALIAS
),
1655 CONDFC ("fbo", "cb012", 0xf, F_CONDBR
),
1656 CONDFC ("fbu", "cb3", 0x7, F_CONDBR
),
1657 CONDFC ("fbue", "cb03", 0xa, F_CONDBR
),
1658 CONDFC ("fbug", "cb23", 0x5, F_CONDBR
),
1659 CONDFC ("fbuge", "cb023", 0xc, F_CONDBR
),
1660 CONDFC ("fbul", "cb13", 0x3, F_CONDBR
),
1661 CONDFC ("fbule", "cb013", 0xe, F_CONDBR
),
1668 #undef FBRX /* v9 */
1670 { "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0
|ASI(~0), "1+2", F_UNBR
|F_DELAYED
, v6
}, /* jmpl rs1+rs2,%g0 */
1671 { "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0
|ASI_RS2(~0), "1", F_UNBR
|F_DELAYED
, v6
}, /* jmpl rs1+%g0,%g0 */
1672 { "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0
, "1+i", F_UNBR
|F_DELAYED
, v6
}, /* jmpl rs1+i,%g0 */
1673 { "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0
, "i+1", F_UNBR
|F_DELAYED
, v6
}, /* jmpl i+rs1,%g0 */
1674 { "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0
|RS1_G0
, "i", F_UNBR
|F_DELAYED
, v6
}, /* jmpl %g0+i,%g0 */
1675 { "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0
|SIMM13(~0), "1", F_UNBR
|F_DELAYED
, v6
}, /* jmpl rs1+0,%g0 */
1677 { "nop", F2(0, 4), 0xfeffffff, "", 0, v6
}, /* sethi 0, %g0 */
1679 { "set", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS
, v6
},
1680 { "setuw", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS
, v9
},
1681 { "setsw", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS
, v9
},
1682 { "setx", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,1,d", F_ALIAS
, v9
},
1684 { "sethi", F2(0x0, 0x4), F2(~0x0, ~0x4), "h,d", 0, v6
},
1686 { "taddcc", F3(2, 0x20, 0), F3(~2, ~0x20, ~0)|ASI(~0), "1,2,d", 0, v6
},
1687 { "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "1,i,d", 0, v6
},
1688 { "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "i,1,d", 0, v6
},
1689 { "taddcctv", F3(2, 0x22, 0), F3(~2, ~0x22, ~0)|ASI(~0), "1,2,d", 0, v6
},
1690 { "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "1,i,d", 0, v6
},
1691 { "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "i,1,d", 0, v6
},
1693 { "tsubcc", F3(2, 0x21, 0), F3(~2, ~0x21, ~0)|ASI(~0), "1,2,d", 0, v6
},
1694 { "tsubcc", F3(2, 0x21, 1), F3(~2, ~0x21, ~1), "1,i,d", 0, v6
},
1695 { "tsubcctv", F3(2, 0x23, 0), F3(~2, ~0x23, ~0)|ASI(~0), "1,2,d", 0, v6
},
1696 { "tsubcctv", F3(2, 0x23, 1), F3(~2, ~0x23, ~1), "1,i,d", 0, v6
},
1698 { "unimp", F2(0x0, 0x0), 0xffc00000, "n", 0, v6notv9
},
1699 { "illtrap", F2(0, 0), F2(~0, ~0)|RD_G0
, "n", 0, v9
},
1701 /* This *is* a commutative instruction. */
1702 { "xnor", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,2,d", 0, v6
},
1703 { "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "1,i,d", 0, v6
},
1704 { "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "i,1,d", 0, v6
},
1705 /* This *is* a commutative instruction. */
1706 { "xnorcc", F3(2, 0x17, 0), F3(~2, ~0x17, ~0)|ASI(~0), "1,2,d", 0, v6
},
1707 { "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "1,i,d", 0, v6
},
1708 { "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "i,1,d", 0, v6
},
1709 { "xor", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "1,2,d", 0, v6
},
1710 { "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "1,i,d", 0, v6
},
1711 { "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,1,d", 0, v6
},
1712 { "xorcc", F3(2, 0x13, 0), F3(~2, ~0x13, ~0)|ASI(~0), "1,2,d", 0, v6
},
1713 { "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "1,i,d", 0, v6
},
1714 { "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "i,1,d", 0, v6
},
1716 { "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,d", F_ALIAS
, v6
}, /* xnor rs1,%0,rd */
1717 { "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "r", F_ALIAS
, v6
}, /* xnor rd,%0,rd */
1719 { "btog", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "2,r", F_ALIAS
, v6
}, /* xor rd,rs2,rd */
1720 { "btog", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,r", F_ALIAS
, v6
}, /* xor rd,i,rd */
1722 /* FPop1 and FPop2 are not instructions. Don't accept them. */
1724 { "fdtoi", F3F(2, 0x34, 0x0d2), F3F(~2, ~0x34, ~0x0d2)|RS1_G0
, "B,g", F_FLOAT
, v6
},
1725 { "fstoi", F3F(2, 0x34, 0x0d1), F3F(~2, ~0x34, ~0x0d1)|RS1_G0
, "f,g", F_FLOAT
, v6
},
1726 { "fqtoi", F3F(2, 0x34, 0x0d3), F3F(~2, ~0x34, ~0x0d3)|RS1_G0
, "R,g", F_FLOAT
, v8
},
1728 { "fdtox", F3F(2, 0x34, 0x082), F3F(~2, ~0x34, ~0x082)|RS1_G0
, "B,g", F_FLOAT
, v9
},
1729 { "fstox", F3F(2, 0x34, 0x081), F3F(~2, ~0x34, ~0x081)|RS1_G0
, "f,g", F_FLOAT
, v9
},
1730 { "fqtox", F3F(2, 0x34, 0x083), F3F(~2, ~0x34, ~0x083)|RS1_G0
, "R,g", F_FLOAT
, v9
},
1732 { "fitod", F3F(2, 0x34, 0x0c8), F3F(~2, ~0x34, ~0x0c8)|RS1_G0
, "f,H", F_FLOAT
, v6
},
1733 { "fitos", F3F(2, 0x34, 0x0c4), F3F(~2, ~0x34, ~0x0c4)|RS1_G0
, "f,g", F_FLOAT
, v6
},
1734 { "fitoq", F3F(2, 0x34, 0x0cc), F3F(~2, ~0x34, ~0x0cc)|RS1_G0
, "f,J", F_FLOAT
, v8
},
1736 { "fxtod", F3F(2, 0x34, 0x088), F3F(~2, ~0x34, ~0x088)|RS1_G0
, "f,H", F_FLOAT
, v9
},
1737 { "fxtos", F3F(2, 0x34, 0x084), F3F(~2, ~0x34, ~0x084)|RS1_G0
, "f,g", F_FLOAT
, v9
},
1738 { "fxtoq", F3F(2, 0x34, 0x08c), F3F(~2, ~0x34, ~0x08c)|RS1_G0
, "f,J", F_FLOAT
, v9
},
1740 { "fdtoq", F3F(2, 0x34, 0x0ce), F3F(~2, ~0x34, ~0x0ce)|RS1_G0
, "B,J", F_FLOAT
, v8
},
1741 { "fdtos", F3F(2, 0x34, 0x0c6), F3F(~2, ~0x34, ~0x0c6)|RS1_G0
, "B,g", F_FLOAT
, v6
},
1742 { "fqtod", F3F(2, 0x34, 0x0cb), F3F(~2, ~0x34, ~0x0cb)|RS1_G0
, "R,H", F_FLOAT
, v8
},
1743 { "fqtos", F3F(2, 0x34, 0x0c7), F3F(~2, ~0x34, ~0x0c7)|RS1_G0
, "R,g", F_FLOAT
, v8
},
1744 { "fstod", F3F(2, 0x34, 0x0c9), F3F(~2, ~0x34, ~0x0c9)|RS1_G0
, "f,H", F_FLOAT
, v6
},
1745 { "fstoq", F3F(2, 0x34, 0x0cd), F3F(~2, ~0x34, ~0x0cd)|RS1_G0
, "f,J", F_FLOAT
, v8
},
1747 { "fdivd", F3F(2, 0x34, 0x04e), F3F(~2, ~0x34, ~0x04e), "v,B,H", F_FLOAT
, v6
},
1748 { "fdivq", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT
, v8
},
1749 { "fdivx", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT
|F_ALIAS
, v8
},
1750 { "fdivs", F3F(2, 0x34, 0x04d), F3F(~2, ~0x34, ~0x04d), "e,f,g", F_FLOAT
, v6
},
1751 { "fmuld", F3F(2, 0x34, 0x04a), F3F(~2, ~0x34, ~0x04a), "v,B,H", F_FLOAT
, v6
},
1752 { "fmulq", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT
, v8
},
1753 { "fmulx", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT
|F_ALIAS
, v8
},
1754 { "fmuls", F3F(2, 0x34, 0x049), F3F(~2, ~0x34, ~0x049), "e,f,g", F_FLOAT
, v6
},
1756 { "fdmulq", F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT
, v8
},
1757 { "fdmulx", F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT
|F_ALIAS
, v8
},
1758 { "fsmuld", F3F(2, 0x34, 0x069), F3F(~2, ~0x34, ~0x069), "e,f,H", F_FLOAT
, v8
},
1760 { "fsqrtd", F3F(2, 0x34, 0x02a), F3F(~2, ~0x34, ~0x02a)|RS1_G0
, "B,H", F_FLOAT
, v7
},
1761 { "fsqrtq", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0
, "R,J", F_FLOAT
, v8
},
1762 { "fsqrtx", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0
, "R,J", F_FLOAT
|F_ALIAS
, v8
},
1763 { "fsqrts", F3F(2, 0x34, 0x029), F3F(~2, ~0x34, ~0x029)|RS1_G0
, "f,g", F_FLOAT
, v7
},
1765 { "fabsd", F3F(2, 0x34, 0x00a), F3F(~2, ~0x34, ~0x00a)|RS1_G0
, "B,H", F_FLOAT
, v9
},
1766 { "fabsq", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0
, "R,J", F_FLOAT
, v9
},
1767 { "fabsx", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0
, "R,J", F_FLOAT
|F_ALIAS
, v9
},
1768 { "fabss", F3F(2, 0x34, 0x009), F3F(~2, ~0x34, ~0x009)|RS1_G0
, "f,g", F_FLOAT
, v6
},
1769 { "fmovd", F3F(2, 0x34, 0x002), F3F(~2, ~0x34, ~0x002)|RS1_G0
, "B,H", F_FLOAT
, v9
},
1770 { "fmovq", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0
, "R,J", F_FLOAT
, v9
},
1771 { "fmovx", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0
, "R,J", F_FLOAT
|F_ALIAS
, v9
},
1772 { "fmovs", F3F(2, 0x34, 0x001), F3F(~2, ~0x34, ~0x001)|RS1_G0
, "f,g", F_FLOAT
, v6
},
1773 { "fnegd", F3F(2, 0x34, 0x006), F3F(~2, ~0x34, ~0x006)|RS1_G0
, "B,H", F_FLOAT
, v9
},
1774 { "fnegq", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0
, "R,J", F_FLOAT
, v9
},
1775 { "fnegx", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0
, "R,J", F_FLOAT
|F_ALIAS
, v9
},
1776 { "fnegs", F3F(2, 0x34, 0x005), F3F(~2, ~0x34, ~0x005)|RS1_G0
, "f,g", F_FLOAT
, v6
},
1778 { "faddd", F3F(2, 0x34, 0x042), F3F(~2, ~0x34, ~0x042), "v,B,H", F_FLOAT
, v6
},
1779 { "faddq", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT
, v8
},
1780 { "faddx", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT
|F_ALIAS
, v8
},
1781 { "fadds", F3F(2, 0x34, 0x041), F3F(~2, ~0x34, ~0x041), "e,f,g", F_FLOAT
, v6
},
1782 { "fsubd", F3F(2, 0x34, 0x046), F3F(~2, ~0x34, ~0x046), "v,B,H", F_FLOAT
, v6
},
1783 { "fsubq", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT
, v8
},
1784 { "fsubx", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT
|F_ALIAS
, v8
},
1785 { "fsubs", F3F(2, 0x34, 0x045), F3F(~2, ~0x34, ~0x045), "e,f,g", F_FLOAT
, v6
},
1787 #define CMPFCC(x) (((x)&0x3)<<25)
1789 { "fcmpd", F3F(2, 0x35, 0x052), F3F(~2, ~0x35, ~0x052)|RD_G0
, "v,B", F_FLOAT
, v6
},
1790 { "fcmpd", CMPFCC(0)|F3F(2, 0x35, 0x052), CMPFCC(~0)|F3F(~2, ~0x35, ~0x052), "6,v,B", F_FLOAT
, v9
},
1791 { "fcmpd", CMPFCC(1)|F3F(2, 0x35, 0x052), CMPFCC(~1)|F3F(~2, ~0x35, ~0x052), "7,v,B", F_FLOAT
, v9
},
1792 { "fcmpd", CMPFCC(2)|F3F(2, 0x35, 0x052), CMPFCC(~2)|F3F(~2, ~0x35, ~0x052), "8,v,B", F_FLOAT
, v9
},
1793 { "fcmpd", CMPFCC(3)|F3F(2, 0x35, 0x052), CMPFCC(~3)|F3F(~2, ~0x35, ~0x052), "9,v,B", F_FLOAT
, v9
},
1794 { "fcmped", F3F(2, 0x35, 0x056), F3F(~2, ~0x35, ~0x056)|RD_G0
, "v,B", F_FLOAT
, v6
},
1795 { "fcmped", CMPFCC(0)|F3F(2, 0x35, 0x056), CMPFCC(~0)|F3F(~2, ~0x35, ~0x056), "6,v,B", F_FLOAT
, v9
},
1796 { "fcmped", CMPFCC(1)|F3F(2, 0x35, 0x056), CMPFCC(~1)|F3F(~2, ~0x35, ~0x056), "7,v,B", F_FLOAT
, v9
},
1797 { "fcmped", CMPFCC(2)|F3F(2, 0x35, 0x056), CMPFCC(~2)|F3F(~2, ~0x35, ~0x056), "8,v,B", F_FLOAT
, v9
},
1798 { "fcmped", CMPFCC(3)|F3F(2, 0x35, 0x056), CMPFCC(~3)|F3F(~2, ~0x35, ~0x056), "9,v,B", F_FLOAT
, v9
},
1799 { "fcmpq", F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0
, "V,R", F_FLOAT
, v8
},
1800 { "fcmpq", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R", F_FLOAT
, v9
},
1801 { "fcmpq", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R", F_FLOAT
, v9
},
1802 { "fcmpq", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R", F_FLOAT
, v9
},
1803 { "fcmpq", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R", F_FLOAT
, v9
},
1804 { "fcmpeq", F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0
, "V,R", F_FLOAT
, v8
},
1805 { "fcmpeq", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R", F_FLOAT
, v9
},
1806 { "fcmpeq", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R", F_FLOAT
, v9
},
1807 { "fcmpeq", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R", F_FLOAT
, v9
},
1808 { "fcmpeq", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R", F_FLOAT
, v9
},
1809 { "fcmpx", F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0
, "V,R", F_FLOAT
|F_ALIAS
, v8
},
1810 { "fcmpx", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R", F_FLOAT
|F_ALIAS
, v9
},
1811 { "fcmpx", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R", F_FLOAT
|F_ALIAS
, v9
},
1812 { "fcmpx", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R", F_FLOAT
|F_ALIAS
, v9
},
1813 { "fcmpx", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R", F_FLOAT
|F_ALIAS
, v9
},
1814 { "fcmpex", F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0
, "V,R", F_FLOAT
|F_ALIAS
, v8
},
1815 { "fcmpex", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R", F_FLOAT
|F_ALIAS
, v9
},
1816 { "fcmpex", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R", F_FLOAT
|F_ALIAS
, v9
},
1817 { "fcmpex", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R", F_FLOAT
|F_ALIAS
, v9
},
1818 { "fcmpex", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R", F_FLOAT
|F_ALIAS
, v9
},
1819 { "fcmps", F3F(2, 0x35, 0x051), F3F(~2, ~0x35, ~0x051)|RD_G0
, "e,f", F_FLOAT
, v6
},
1820 { "fcmps", CMPFCC(0)|F3F(2, 0x35, 0x051), CMPFCC(~0)|F3F(~2, ~0x35, ~0x051), "6,e,f", F_FLOAT
, v9
},
1821 { "fcmps", CMPFCC(1)|F3F(2, 0x35, 0x051), CMPFCC(~1)|F3F(~2, ~0x35, ~0x051), "7,e,f", F_FLOAT
, v9
},
1822 { "fcmps", CMPFCC(2)|F3F(2, 0x35, 0x051), CMPFCC(~2)|F3F(~2, ~0x35, ~0x051), "8,e,f", F_FLOAT
, v9
},
1823 { "fcmps", CMPFCC(3)|F3F(2, 0x35, 0x051), CMPFCC(~3)|F3F(~2, ~0x35, ~0x051), "9,e,f", F_FLOAT
, v9
},
1824 { "fcmpes", F3F(2, 0x35, 0x055), F3F(~2, ~0x35, ~0x055)|RD_G0
, "e,f", F_FLOAT
, v6
},
1825 { "fcmpes", CMPFCC(0)|F3F(2, 0x35, 0x055), CMPFCC(~0)|F3F(~2, ~0x35, ~0x055), "6,e,f", F_FLOAT
, v9
},
1826 { "fcmpes", CMPFCC(1)|F3F(2, 0x35, 0x055), CMPFCC(~1)|F3F(~2, ~0x35, ~0x055), "7,e,f", F_FLOAT
, v9
},
1827 { "fcmpes", CMPFCC(2)|F3F(2, 0x35, 0x055), CMPFCC(~2)|F3F(~2, ~0x35, ~0x055), "8,e,f", F_FLOAT
, v9
},
1828 { "fcmpes", CMPFCC(3)|F3F(2, 0x35, 0x055), CMPFCC(~3)|F3F(~2, ~0x35, ~0x055), "9,e,f", F_FLOAT
, v9
},
1830 /* These Extended FPop (FIFO) instructions are new in the Fujitsu
1831 MB86934, replacing the CPop instructions from v6 and later
1834 #define EFPOP1_2(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op)|RS1_G0, args, 0, sparclite }
1835 #define EFPOP1_3(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op), args, 0, sparclite }
1836 #define EFPOP2_2(name, op, args) { name, F3F(2, 0x37, op), F3F(~2, ~0x37, ~op)|RD_G0, args, 0, sparclite }
1838 EFPOP1_2 ("efitod", 0x0c8, "f,H"),
1839 EFPOP1_2 ("efitos", 0x0c4, "f,g"),
1840 EFPOP1_2 ("efdtoi", 0x0d2, "B,g"),
1841 EFPOP1_2 ("efstoi", 0x0d1, "f,g"),
1842 EFPOP1_2 ("efstod", 0x0c9, "f,H"),
1843 EFPOP1_2 ("efdtos", 0x0c6, "B,g"),
1844 EFPOP1_2 ("efmovs", 0x001, "f,g"),
1845 EFPOP1_2 ("efnegs", 0x005, "f,g"),
1846 EFPOP1_2 ("efabss", 0x009, "f,g"),
1847 EFPOP1_2 ("efsqrtd", 0x02a, "B,H"),
1848 EFPOP1_2 ("efsqrts", 0x029, "f,g"),
1849 EFPOP1_3 ("efaddd", 0x042, "v,B,H"),
1850 EFPOP1_3 ("efadds", 0x041, "e,f,g"),
1851 EFPOP1_3 ("efsubd", 0x046, "v,B,H"),
1852 EFPOP1_3 ("efsubs", 0x045, "e,f,g"),
1853 EFPOP1_3 ("efdivd", 0x04e, "v,B,H"),
1854 EFPOP1_3 ("efdivs", 0x04d, "e,f,g"),
1855 EFPOP1_3 ("efmuld", 0x04a, "v,B,H"),
1856 EFPOP1_3 ("efmuls", 0x049, "e,f,g"),
1857 EFPOP1_3 ("efsmuld", 0x069, "e,f,H"),
1858 EFPOP2_2 ("efcmpd", 0x052, "v,B"),
1859 EFPOP2_2 ("efcmped", 0x056, "v,B"),
1860 EFPOP2_2 ("efcmps", 0x051, "e,f"),
1861 EFPOP2_2 ("efcmpes", 0x055, "e,f"),
1867 /* These are marked F_ALIAS, so that they won't conflict with sparclite insns
1868 present. Otherwise, the F_ALIAS flag is ignored. */
1869 { "cpop1", F3(2, 0x36, 0), F3(~2, ~0x36, ~1), "[1+2],d", F_ALIAS
, v6notv9
},
1870 { "cpop2", F3(2, 0x37, 0), F3(~2, ~0x37, ~1), "[1+2],d", F_ALIAS
, v6notv9
},
1872 /* sparclet specific insns */
1874 COMMUTEOP ("umac", 0x3e, sparclet
),
1875 COMMUTEOP ("smac", 0x3f, sparclet
),
1876 COMMUTEOP ("umacd", 0x2e, sparclet
),
1877 COMMUTEOP ("smacd", 0x2f, sparclet
),
1878 COMMUTEOP ("umuld", 0x09, sparclet
),
1879 COMMUTEOP ("smuld", 0x0d, sparclet
),
1881 { "shuffle", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, sparclet
},
1882 { "shuffle", F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d", 0, sparclet
},
1884 /* The manual isn't completely accurate on these insns. The `rs2' field is
1885 treated as being 6 bits to account for 6 bit immediates to cpush. It is
1886 assumed that it is intended that bit 5 is 0 when rs2 contains a reg. */
1888 { "crdcxt", F3(2, 0x36, 0)|SLCPOP(4), F3(~2, ~0x36, ~0)|SLCPOP(~4)|BIT5
|RS2(~0), "U,d", 0, sparclet
},
1889 { "cwrcxt", F3(2, 0x36, 0)|SLCPOP(3), F3(~2, ~0x36, ~0)|SLCPOP(~3)|BIT5
|RS2(~0), "1,u", 0, sparclet
},
1890 { "cpush", F3(2, 0x36, 0)|SLCPOP(0), F3(~2, ~0x36, ~0)|SLCPOP(~0)|BIT5
|RD(~0), "1,2", 0, sparclet
},
1891 { "cpush", F3(2, 0x36, 1)|SLCPOP(0), F3(~2, ~0x36, ~1)|SLCPOP(~0)|RD(~0), "1,Y", 0, sparclet
},
1892 { "cpusha", F3(2, 0x36, 0)|SLCPOP(1), F3(~2, ~0x36, ~0)|SLCPOP(~1)|BIT5
|RD(~0), "1,2", 0, sparclet
},
1893 { "cpusha", F3(2, 0x36, 1)|SLCPOP(1), F3(~2, ~0x36, ~1)|SLCPOP(~1)|RD(~0), "1,Y", 0, sparclet
},
1894 { "cpull", F3(2, 0x36, 0)|SLCPOP(2), F3(~2, ~0x36, ~0)|SLCPOP(~2)|BIT5
|RS1(~0)|RS2(~0), "d", 0, sparclet
},
1897 /* sparclet coprocessor branch insns */
1898 #define SLCBCC2(opcode, mask, lose) \
1899 { opcode, (mask), ANNUL|(lose), "l", F_DELAYED|F_CONDBR, sparclet }, \
1900 { opcode, (mask)|ANNUL, (lose), ",a l", F_DELAYED|F_CONDBR, sparclet }
1901 #define SLCBCC(opcode, mask) \
1902 SLCBCC2(opcode, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)))
1904 /* cbn,cba can't be defined here because they're defined elsewhere and GAS
1905 requires all mnemonics of the same name to be consecutive. */
1906 /*SLCBCC("cbn", 0), - already defined */
1914 /*SLCBCC("cba", 8), - already defined */
1917 SLCBCC("cbnef", 11),
1919 SLCBCC("cbner", 13),
1920 SLCBCC("cbnfr", 14),
1921 SLCBCC("cbnefr", 15),
1926 { "casa", F3(3, 0x3c, 0), F3(~3, ~0x3c, ~0), "[1]A,2,d", 0, v9
},
1927 { "casa", F3(3, 0x3c, 1), F3(~3, ~0x3c, ~1), "[1]o,2,d", 0, v9
},
1928 { "casxa", F3(3, 0x3e, 0), F3(~3, ~0x3e, ~0), "[1]A,2,d", 0, v9
},
1929 { "casxa", F3(3, 0x3e, 1), F3(~3, ~0x3e, ~1), "[1]o,2,d", 0, v9
},
1931 /* v9 synthetic insns */
1932 { "iprefetch", F2(0, 1)|(2<<20)|BPRED
, F2(~0, ~1)|(1<<20)|ANNUL
|COND(~0), "G", 0, v9
}, /* bn,a,pt %xcc,label */
1933 { "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0
, "1,d", F_ALIAS
, v9
}, /* sra rs1,%g0,rd */
1934 { "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0
, "r", F_ALIAS
, v9
}, /* sra rd,%g0,rd */
1935 { "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0
, "1,d", F_ALIAS
, v9
}, /* srl rs1,%g0,rd */
1936 { "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0
, "r", F_ALIAS
, v9
}, /* srl rd,%g0,rd */
1937 { "cas", F3(3, 0x3c, 0)|ASI(0x80), F3(~3, ~0x3c, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS
, v9
}, /* casa [rs1]ASI_P,rs2,rd */
1938 { "casl", F3(3, 0x3c, 0)|ASI(0x88), F3(~3, ~0x3c, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS
, v9
}, /* casa [rs1]ASI_P_L,rs2,rd */
1939 { "casx", F3(3, 0x3e, 0)|ASI(0x80), F3(~3, ~0x3e, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS
, v9
}, /* casxa [rs1]ASI_P,rs2,rd */
1940 { "casxl", F3(3, 0x3e, 0)|ASI(0x88), F3(~3, ~0x3e, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS
, v9
}, /* casxa [rs1]ASI_P_L,rs2,rd */
1942 /* Ultrasparc extensions */
1943 { "shutdown", F3F(2, 0x36, 0x080), F3F(~2, ~0x36, ~0x080)|RD_G0
|RS1_G0
|RS2_G0
, "", 0, v9a
},
1945 /* FIXME: Do we want to mark these as F_FLOAT, or something similar? */
1946 { "fpadd16", F3F(2, 0x36, 0x050), F3F(~2, ~0x36, ~0x050), "v,B,H", 0, v9a
},
1947 { "fpadd16s", F3F(2, 0x36, 0x051), F3F(~2, ~0x36, ~0x051), "e,f,g", 0, v9a
},
1948 { "fpadd32", F3F(2, 0x36, 0x052), F3F(~2, ~0x36, ~0x052), "v,B,H", 0, v9a
},
1949 { "fpadd32s", F3F(2, 0x36, 0x053), F3F(~2, ~0x36, ~0x053), "e,f,g", 0, v9a
},
1950 { "fpsub16", F3F(2, 0x36, 0x054), F3F(~2, ~0x36, ~0x054), "v,B,H", 0, v9a
},
1951 { "fpsub16s", F3F(2, 0x36, 0x055), F3F(~2, ~0x36, ~0x055), "e,f,g", 0, v9a
},
1952 { "fpsub32", F3F(2, 0x36, 0x056), F3F(~2, ~0x36, ~0x056), "v,B,H", 0, v9a
},
1953 { "fpsub32s", F3F(2, 0x36, 0x057), F3F(~2, ~0x36, ~0x057), "e,f,g", 0, v9a
},
1955 { "fpack32", F3F(2, 0x36, 0x03a), F3F(~2, ~0x36, ~0x03a), "v,B,H", 0, v9a
},
1956 { "fpack16", F3F(2, 0x36, 0x03b), F3F(~2, ~0x36, ~0x03b)|RS1_G0
, "B,g", 0, v9a
},
1957 { "fpackfix", F3F(2, 0x36, 0x03d), F3F(~2, ~0x36, ~0x03d)|RS1_G0
, "B,g", 0, v9a
},
1958 { "fexpand", F3F(2, 0x36, 0x04d), F3F(~2, ~0x36, ~0x04d)|RS1_G0
, "f,H", 0, v9a
},
1959 { "fpmerge", F3F(2, 0x36, 0x04b), F3F(~2, ~0x36, ~0x04b), "e,f,H", 0, v9a
},
1961 /* Note that the mixing of 32/64 bit regs is intentional. */
1962 { "fmul8x16", F3F(2, 0x36, 0x031), F3F(~2, ~0x36, ~0x031), "e,B,H", 0, v9a
},
1963 { "fmul8x16au", F3F(2, 0x36, 0x033), F3F(~2, ~0x36, ~0x033), "e,f,H", 0, v9a
},
1964 { "fmul8x16al", F3F(2, 0x36, 0x035), F3F(~2, ~0x36, ~0x035), "e,f,H", 0, v9a
},
1965 { "fmul8sux16", F3F(2, 0x36, 0x036), F3F(~2, ~0x36, ~0x036), "v,B,H", 0, v9a
},
1966 { "fmul8ulx16", F3F(2, 0x36, 0x037), F3F(~2, ~0x36, ~0x037), "v,B,H", 0, v9a
},
1967 { "fmuld8sux16", F3F(2, 0x36, 0x038), F3F(~2, ~0x36, ~0x038), "e,f,H", 0, v9a
},
1968 { "fmuld8ulx16", F3F(2, 0x36, 0x039), F3F(~2, ~0x36, ~0x039), "e,f,H", 0, v9a
},
1970 { "alignaddr", F3F(2, 0x36, 0x018), F3F(~2, ~0x36, ~0x018), "1,2,d", 0, v9a
},
1971 { "alignaddrl", F3F(2, 0x36, 0x01a), F3F(~2, ~0x36, ~0x01a), "1,2,d", 0, v9a
},
1972 { "faligndata", F3F(2, 0x36, 0x048), F3F(~2, ~0x36, ~0x048), "v,B,H", 0, v9a
},
1974 { "fzero", F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H", 0, v9a
},
1975 { "fzeros", F3F(2, 0x36, 0x061), F3F(~2, ~0x36, ~0x061), "g", 0, v9a
},
1976 { "fone", F3F(2, 0x36, 0x07e), F3F(~2, ~0x36, ~0x07e), "H", 0, v9a
},
1977 { "fones", F3F(2, 0x36, 0x07f), F3F(~2, ~0x36, ~0x07f), "g", 0, v9a
},
1978 { "fsrc1", F3F(2, 0x36, 0x074), F3F(~2, ~0x36, ~0x074), "v,H", 0, v9a
},
1979 { "fsrc1s", F3F(2, 0x36, 0x075), F3F(~2, ~0x36, ~0x075), "e,g", 0, v9a
},
1980 { "fsrc2", F3F(2, 0x36, 0x078), F3F(~2, ~0x36, ~0x078), "B,H", 0, v9a
},
1981 { "fsrc2s", F3F(2, 0x36, 0x079), F3F(~2, ~0x36, ~0x079), "f,g", 0, v9a
},
1982 { "fnot1", F3F(2, 0x36, 0x06a), F3F(~2, ~0x36, ~0x06a), "v,H", 0, v9a
},
1983 { "fnot1s", F3F(2, 0x36, 0x06b), F3F(~2, ~0x36, ~0x06b), "e,g", 0, v9a
},
1984 { "fnot2", F3F(2, 0x36, 0x066), F3F(~2, ~0x36, ~0x066), "B,H", 0, v9a
},
1985 { "fnot2s", F3F(2, 0x36, 0x067), F3F(~2, ~0x36, ~0x067), "f,g", 0, v9a
},
1986 { "for", F3F(2, 0x36, 0x07c), F3F(~2, ~0x36, ~0x07c), "v,B,H", 0, v9a
},
1987 { "fors", F3F(2, 0x36, 0x07d), F3F(~2, ~0x36, ~0x07d), "e,f,g", 0, v9a
},
1988 { "fnor", F3F(2, 0x36, 0x062), F3F(~2, ~0x36, ~0x062), "v,B,H", 0, v9a
},
1989 { "fnors", F3F(2, 0x36, 0x063), F3F(~2, ~0x36, ~0x063), "e,f,g", 0, v9a
},
1990 { "fand", F3F(2, 0x36, 0x070), F3F(~2, ~0x36, ~0x070), "v,B,H", 0, v9a
},
1991 { "fands", F3F(2, 0x36, 0x071), F3F(~2, ~0x36, ~0x071), "e,f,g", 0, v9a
},
1992 { "fnand", F3F(2, 0x36, 0x06e), F3F(~2, ~0x36, ~0x06e), "v,B,H", 0, v9a
},
1993 { "fnands", F3F(2, 0x36, 0x06f), F3F(~2, ~0x36, ~0x06f), "e,f,g", 0, v9a
},
1994 { "fxor", F3F(2, 0x36, 0x06c), F3F(~2, ~0x36, ~0x06c), "v,B,H", 0, v9a
},
1995 { "fxors", F3F(2, 0x36, 0x06d), F3F(~2, ~0x36, ~0x06d), "e,f,g", 0, v9a
},
1996 { "fxnor", F3F(2, 0x36, 0x072), F3F(~2, ~0x36, ~0x072), "v,B,H", 0, v9a
},
1997 { "fxnors", F3F(2, 0x36, 0x073), F3F(~2, ~0x36, ~0x073), "e,f,g", 0, v9a
},
1998 { "fornot1", F3F(2, 0x36, 0x07a), F3F(~2, ~0x36, ~0x07a), "v,B,H", 0, v9a
},
1999 { "fornot1s", F3F(2, 0x36, 0x07b), F3F(~2, ~0x36, ~0x07b), "e,f,g", 0, v9a
},
2000 { "fornot2", F3F(2, 0x36, 0x076), F3F(~2, ~0x36, ~0x076), "v,B,H", 0, v9a
},
2001 { "fornot2s", F3F(2, 0x36, 0x077), F3F(~2, ~0x36, ~0x077), "e,f,g", 0, v9a
},
2002 { "fandnot1", F3F(2, 0x36, 0x068), F3F(~2, ~0x36, ~0x068), "v,B,H", 0, v9a
},
2003 { "fandnot1s", F3F(2, 0x36, 0x069), F3F(~2, ~0x36, ~0x069), "e,f,g", 0, v9a
},
2004 { "fandnot2", F3F(2, 0x36, 0x064), F3F(~2, ~0x36, ~0x064), "v,B,H", 0, v9a
},
2005 { "fandnot2s", F3F(2, 0x36, 0x065), F3F(~2, ~0x36, ~0x065), "e,f,g", 0, v9a
},
2007 { "fcmpgt16", F3F(2, 0x36, 0x028), F3F(~2, ~0x36, ~0x028), "v,B,d", 0, v9a
},
2008 { "fcmpgt32", F3F(2, 0x36, 0x02c), F3F(~2, ~0x36, ~0x02c), "v,B,d", 0, v9a
},
2009 { "fcmple16", F3F(2, 0x36, 0x020), F3F(~2, ~0x36, ~0x020), "v,B,d", 0, v9a
},
2010 { "fcmple32", F3F(2, 0x36, 0x024), F3F(~2, ~0x36, ~0x024), "v,B,d", 0, v9a
},
2011 { "fcmpne16", F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", 0, v9a
},
2012 { "fcmpne32", F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", 0, v9a
},
2013 { "fcmpeq16", F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", 0, v9a
},
2014 { "fcmpeq32", F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", 0, v9a
},
2016 { "edge8", F3F(2, 0x36, 0x000), F3F(~2, ~0x36, ~0x000), "1,2,d", 0, v9a
},
2017 { "edge8l", F3F(2, 0x36, 0x002), F3F(~2, ~0x36, ~0x002), "1,2,d", 0, v9a
},
2018 { "edge16", F3F(2, 0x36, 0x004), F3F(~2, ~0x36, ~0x004), "1,2,d", 0, v9a
},
2019 { "edge16l", F3F(2, 0x36, 0x006), F3F(~2, ~0x36, ~0x006), "1,2,d", 0, v9a
},
2020 { "edge32", F3F(2, 0x36, 0x008), F3F(~2, ~0x36, ~0x008), "1,2,d", 0, v9a
},
2021 { "edge32l", F3F(2, 0x36, 0x00a), F3F(~2, ~0x36, ~0x00a), "1,2,d", 0, v9a
},
2023 { "pdist", F3F(2, 0x36, 0x03e), F3F(~2, ~0x36, ~0x03e), "v,B,H", 0, v9a
},
2025 { "array8", F3F(2, 0x36, 0x010), F3F(~2, ~0x36, ~0x010), "1,2,d", 0, v9a
},
2026 { "array16", F3F(2, 0x36, 0x012), F3F(~2, ~0x36, ~0x012), "1,2,d", 0, v9a
},
2027 { "array32", F3F(2, 0x36, 0x014), F3F(~2, ~0x36, ~0x014), "1,2,d", 0, v9a
},
2029 /* Cheetah instructions */
2030 { "edge8n", F3F(2, 0x36, 0x001), F3F(~2, ~0x36, ~0x001), "1,2,d", 0, v9b
},
2031 { "edge8ln", F3F(2, 0x36, 0x003), F3F(~2, ~0x36, ~0x003), "1,2,d", 0, v9b
},
2032 { "edge16n", F3F(2, 0x36, 0x005), F3F(~2, ~0x36, ~0x005), "1,2,d", 0, v9b
},
2033 { "edge16ln", F3F(2, 0x36, 0x007), F3F(~2, ~0x36, ~0x007), "1,2,d", 0, v9b
},
2034 { "edge32n", F3F(2, 0x36, 0x009), F3F(~2, ~0x36, ~0x009), "1,2,d", 0, v9b
},
2035 { "edge32ln", F3F(2, 0x36, 0x00b), F3F(~2, ~0x36, ~0x00b), "1,2,d", 0, v9b
},
2037 { "bmask", F3F(2, 0x36, 0x019), F3F(~2, ~0x36, ~0x019), "1,2,d", 0, v9b
},
2038 { "bshuffle", F3F(2, 0x36, 0x04c), F3F(~2, ~0x36, ~0x04c), "v,B,H", 0, v9b
},
2040 { "siam", F3F(2, 0x36, 0x081), F3F(~2, ~0x36, ~0x081)|RD_G0
|RS1_G0
|RS2(~7), "3", 0, v9b
},
2042 /* More v9 specific insns, these need to come last so they do not clash
2043 with v9a instructions such as "edge8" which looks like impdep1. */
2045 #define IMPDEP(name, code) \
2046 { name, F3(2, code, 0), F3(~2, ~code, ~0)|ASI(~0), "1,2,d", 0, v9notv9a }, \
2047 { name, F3(2, code, 1), F3(~2, ~code, ~1), "1,i,d", 0, v9notv9a }, \
2048 { name, F3(2, code, 0), F3(~2, ~code, ~0), "x,1,2,d", 0, v9notv9a }, \
2049 { name, F3(2, code, 0), F3(~2, ~code, ~0), "x,e,f,g", 0, v9notv9a }
2051 IMPDEP ("impdep1", 0x36),
2052 IMPDEP ("impdep2", 0x37),
2058 const int sparc_num_opcodes
= ((sizeof sparc_opcodes
)/(sizeof sparc_opcodes
[0]));
2060 /* Utilities for argument parsing. */
2068 /* Look up NAME in TABLE. */
2070 static int lookup_name
PARAMS ((const arg
*, const char *));
2071 static const char *lookup_value
PARAMS ((const arg
*, int));
2074 lookup_name (table
, name
)
2080 for (p
= table
; p
->name
; ++p
)
2081 if (strcmp (name
, p
->name
) == 0)
2087 /* Look up VALUE in TABLE. */
2090 lookup_value (table
, value
)
2096 for (p
= table
; p
->name
; ++p
)
2097 if (value
== p
->value
)
2105 static arg asi_table
[] =
2107 /* These are in the v9 architecture manual. */
2108 /* The shorter versions appear first, they're here because Sun's as has them.
2109 Sun's as uses #ASI_P_L instead of #ASI_PL (which appears in the
2110 UltraSPARC architecture manual). */
2112 { 0x0c, "#ASI_N_L" },
2113 { 0x10, "#ASI_AIUP" },
2114 { 0x11, "#ASI_AIUS" },
2115 { 0x18, "#ASI_AIUP_L" },
2116 { 0x19, "#ASI_AIUS_L" },
2119 { 0x82, "#ASI_PNF" },
2120 { 0x83, "#ASI_SNF" },
2121 { 0x88, "#ASI_P_L" },
2122 { 0x89, "#ASI_S_L" },
2123 { 0x8a, "#ASI_PNF_L" },
2124 { 0x8b, "#ASI_SNF_L" },
2125 { 0x04, "#ASI_NUCLEUS" },
2126 { 0x0c, "#ASI_NUCLEUS_LITTLE" },
2127 { 0x10, "#ASI_AS_IF_USER_PRIMARY" },
2128 { 0x11, "#ASI_AS_IF_USER_SECONDARY" },
2129 { 0x18, "#ASI_AS_IF_USER_PRIMARY_LITTLE" },
2130 { 0x19, "#ASI_AS_IF_USER_SECONDARY_LITTLE" },
2131 { 0x80, "#ASI_PRIMARY" },
2132 { 0x81, "#ASI_SECONDARY" },
2133 { 0x82, "#ASI_PRIMARY_NOFAULT" },
2134 { 0x83, "#ASI_SECONDARY_NOFAULT" },
2135 { 0x88, "#ASI_PRIMARY_LITTLE" },
2136 { 0x89, "#ASI_SECONDARY_LITTLE" },
2137 { 0x8a, "#ASI_PRIMARY_NOFAULT_LITTLE" },
2138 { 0x8b, "#ASI_SECONDARY_NOFAULT_LITTLE" },
2139 /* These are UltraSPARC extensions. */
2140 /* FIXME: There are dozens of them. Not sure we want them all.
2141 Most are for kernel building but some are for vis type stuff. */
2145 /* Return the value for ASI NAME, or -1 if not found. */
2148 sparc_encode_asi (name
)
2151 return lookup_name (asi_table
, name
);
2154 /* Return the name for ASI value VALUE or NULL if not found. */
2157 sparc_decode_asi (value
)
2160 return lookup_value (asi_table
, value
);
2163 /* Handle membar masks. */
2165 static arg membar_table
[] =
2168 { 0x20, "#MemIssue" },
2169 { 0x10, "#Lookaside" },
2170 { 0x08, "#StoreStore" },
2171 { 0x04, "#LoadStore" },
2172 { 0x02, "#StoreLoad" },
2173 { 0x01, "#LoadLoad" },
2177 /* Return the value for membar arg NAME, or -1 if not found. */
2180 sparc_encode_membar (name
)
2183 return lookup_name (membar_table
, name
);
2186 /* Return the name for membar value VALUE or NULL if not found. */
2189 sparc_decode_membar (value
)
2192 return lookup_value (membar_table
, value
);
2195 /* Handle prefetch args. */
2197 static arg prefetch_table
[] =
2202 { 3, "#one_write" },
2204 { 16, "#invalidate" },
2208 /* Return the value for prefetch arg NAME, or -1 if not found. */
2211 sparc_encode_prefetch (name
)
2214 return lookup_name (prefetch_table
, name
);
2217 /* Return the name for prefetch value VALUE or NULL if not found. */
2220 sparc_decode_prefetch (value
)
2223 return lookup_value (prefetch_table
, value
);
2226 /* Handle sparclet coprocessor registers. */
2228 static arg sparclet_cpreg_table
[] =
2240 /* Return the value for sparclet cpreg arg NAME, or -1 if not found. */
2243 sparc_encode_sparclet_cpreg (name
)
2246 return lookup_name (sparclet_cpreg_table
, name
);
2249 /* Return the name for sparclet cpreg value VALUE or NULL if not found. */
2252 sparc_decode_sparclet_cpreg (value
)
2255 return lookup_value (sparclet_cpreg_table
, value
);
2260 /* Bitmask of v9 architectures. */
2261 #define MASK_V9 ((1 << SPARC_OPCODE_ARCH_V9) \
2262 | (1 << SPARC_OPCODE_ARCH_V9A) \
2263 | (1 << SPARC_OPCODE_ARCH_V9B))
2264 /* 1 if INSN is for v9 only. */
2265 #define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9))
2266 /* 1 if INSN is for v9. */
2267 #define V9_P(insn) (((insn)->architecture & MASK_V9) != 0)
2269 /* The sorted opcode table. */
2270 static const struct sparc_opcode
**sorted_opcodes
;
2272 /* For faster lookup, after insns are sorted they are hashed. */
2273 /* ??? I think there is room for even more improvement. */
2275 #define HASH_SIZE 256
2276 /* It is important that we only look at insn code bits as that is how the
2277 opcode table is hashed. OPCODE_BITS is a table of valid bits for each
2278 of the main types (0,1,2,3). */
2279 static int opcode_bits
[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 };
2280 #define HASH_INSN(INSN) \
2281 ((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19))
2282 struct opcode_hash
{
2283 struct opcode_hash
*next
;
2284 const struct sparc_opcode
*opcode
;
2286 static struct opcode_hash
*opcode_hash_table
[HASH_SIZE
];
2288 static void build_hash_table
2289 PARAMS ((const struct sparc_opcode
**, struct opcode_hash
**, int));
2290 static int is_delayed_branch
PARAMS ((unsigned long));
2291 static int compare_opcodes
PARAMS ((const void *, const void *));
2292 static int compute_arch_mask
PARAMS ((unsigned long));
2294 /* Sign-extend a value which is N bits long. */
2295 #define SEX(value, bits) \
2296 ((((int)(value)) << ((8 * sizeof (int)) - bits)) \
2297 >> ((8 * sizeof (int)) - bits) )
2299 static char *reg_names
[] =
2300 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
2301 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
2302 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
2303 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
2304 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
2305 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
2306 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
2307 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
2308 "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
2309 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
2310 "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
2311 "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
2312 /* psr, wim, tbr, fpsr, cpsr are v8 only. */
2313 "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr"
2316 #define freg_names (®_names[4 * 8])
2318 /* These are ordered according to there register number in
2319 rdpr and wrpr insns. */
2320 static char *v9_priv_reg_names
[] =
2322 "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl",
2323 "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
2325 /* "ver" - special cased */
2328 /* These are ordered according to there register number in
2329 rd and wr insns (-16). */
2330 static char *v9a_asr_reg_names
[] =
2332 "pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint",
2333 "softint", "tick_cmpr", "sys_tick", "sys_tick_cmpr"
2336 /* Macros used to extract instruction fields. Not all fields have
2337 macros defined here, only those which are actually used. */
2339 #define X_RD(i) (((i) >> 25) & 0x1f)
2340 #define X_RS1(i) (((i) >> 14) & 0x1f)
2341 #define X_LDST_I(i) (((i) >> 13) & 1)
2342 #define X_ASI(i) (((i) >> 5) & 0xff)
2343 #define X_RS2(i) (((i) >> 0) & 0x1f)
2344 #define X_IMM(i,n) (((i) >> 0) & ((1 << (n)) - 1))
2345 #define X_SIMM(i,n) SEX (X_IMM ((i), (n)), (n))
2346 #define X_DISP22(i) (((i) >> 0) & 0x3fffff)
2347 #define X_IMM22(i) X_DISP22 (i)
2348 #define X_DISP30(i) (((i) >> 0) & 0x3fffffff)
2350 /* These are for v9. */
2351 #define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff))
2352 #define X_DISP19(i) (((i) >> 0) & 0x7ffff)
2353 #define X_MEMBAR(i) ((i) & 0x7f)
2355 /* Here is the union which was used to extract instruction fields
2356 before the shift and mask macros were written.
2360 unsigned long int code;
2363 unsigned int anop:2;
2364 #define op ldst.anop
2365 unsigned int anrd:5;
2366 #define rd ldst.anrd
2368 unsigned int anrs1:5;
2369 #define rs1 ldst.anrs1
2371 unsigned int anasi:8;
2372 #define asi ldst.anasi
2373 unsigned int anrs2:5;
2374 #define rs2 ldst.anrs2
2379 unsigned int anop:2, anrd:5, op3:6, anrs1:5, i:1;
2380 unsigned int IMM13:13;
2381 #define imm13 IMM13.IMM13
2385 unsigned int anop:2;
2387 unsigned int cond:4;
2389 unsigned int DISP22:22;
2390 #define disp22 branch.DISP22
2391 #define imm22 disp22
2395 unsigned int anop:2;
2398 unsigned int rcond:3;
2400 unsigned int DISP16HI:2;
2402 unsigned int _rs1:5;
2403 unsigned int DISP16LO:14;
2407 unsigned int anop:2;
2408 unsigned int adisp30:30;
2409 #define disp30 call.adisp30
2415 /* Nonzero if INSN is the opcode for a delayed branch. */
2417 is_delayed_branch (insn
)
2420 struct opcode_hash
*op
;
2422 for (op
= opcode_hash_table
[HASH_INSN (insn
)]; op
; op
= op
->next
)
2424 const struct sparc_opcode
*opcode
= op
->opcode
;
2425 if ((opcode
->match
& insn
) == opcode
->match
2426 && (opcode
->lose
& insn
) == 0)
2427 return (opcode
->flags
& F_DELAYED
);
2432 /* extern void qsort (); */
2434 /* Records current mask of SPARC_OPCODE_ARCH_FOO values, used to pass value
2435 to compare_opcodes. */
2436 static unsigned int current_arch_mask
;
2438 /* Print one instruction from MEMADDR on INFO->STREAM.
2440 We suffix the instruction with a comment that gives the absolute
2441 address involved, as well as its symbolic form, if the instruction
2442 is preceded by a findable `sethi' and it either adds an immediate
2443 displacement to that register, or it is an `add' or `or' instruction
2444 on that register. */
2447 print_insn_sparc (memaddr
, info
)
2449 disassemble_info
*info
;
2451 FILE *stream
= info
->stream
;
2454 register struct opcode_hash
*op
;
2455 /* Nonzero of opcode table has been initialized. */
2456 static int opcodes_initialized
= 0;
2457 /* bfd mach number of last call. */
2458 static unsigned long current_mach
= 0;
2459 bfd_vma (*getword
) PARAMS ((const unsigned char *));
2461 if (!opcodes_initialized
2462 || info
->mach
!= current_mach
)
2466 current_arch_mask
= compute_arch_mask (info
->mach
);
2468 if (!opcodes_initialized
)
2469 sorted_opcodes
= (const struct sparc_opcode
**)
2470 malloc (sparc_num_opcodes
* sizeof (struct sparc_opcode
*));
2471 /* Reset the sorted table so we can resort it. */
2472 for (i
= 0; i
< sparc_num_opcodes
; ++i
)
2473 sorted_opcodes
[i
] = &sparc_opcodes
[i
];
2474 qsort ((char *) sorted_opcodes
, sparc_num_opcodes
,
2475 sizeof (sorted_opcodes
[0]), compare_opcodes
);
2477 build_hash_table (sorted_opcodes
, opcode_hash_table
, sparc_num_opcodes
);
2478 current_mach
= info
->mach
;
2479 opcodes_initialized
= 1;
2484 (*info
->read_memory_func
) (memaddr
, buffer
, sizeof (buffer
), info
);
2487 (*info
->memory_error_func
) (status
, memaddr
, info
);
2492 /* On SPARClite variants such as DANlite (sparc86x), instructions
2493 are always big-endian even when the machine is in little-endian mode. */
2494 if (info
->endian
== BFD_ENDIAN_BIG
|| info
->mach
== bfd_mach_sparc_sparclite
)
2495 getword
= bfd_getb32
;
2497 getword
= bfd_getl32
;
2499 insn
= getword (buffer
);
2501 info
->insn_info_valid
= 1; /* We do return this info */
2502 info
->insn_type
= dis_nonbranch
; /* Assume non branch insn */
2503 info
->branch_delay_insns
= 0; /* Assume no delay */
2504 info
->target
= 0; /* Assume no target known */
2506 for (op
= opcode_hash_table
[HASH_INSN (insn
)]; op
; op
= op
->next
)
2508 const struct sparc_opcode
*opcode
= op
->opcode
;
2510 /* If the insn isn't supported by the current architecture, skip it. */
2511 if (! (opcode
->architecture
& current_arch_mask
))
2514 if ((opcode
->match
& insn
) == opcode
->match
2515 && (opcode
->lose
& insn
) == 0)
2517 /* Nonzero means that we have found an instruction which has
2518 the effect of adding or or'ing the imm13 field to rs1. */
2519 int imm_added_to_rs1
= 0;
2520 int imm_ored_to_rs1
= 0;
2522 /* Nonzero means that we have found a plus sign in the args
2523 field of the opcode table. */
2526 /* Nonzero means we have an annulled branch. */
2527 int is_annulled
= 0;
2529 /* Do we have an `add' or `or' instruction combining an
2530 immediate with rs1? */
2531 if (opcode
->match
== 0x80102000) /* or */
2532 imm_ored_to_rs1
= 1;
2533 if (opcode
->match
== 0x80002000) /* add */
2534 imm_added_to_rs1
= 1;
2536 if (X_RS1 (insn
) != X_RD (insn
)
2537 && strchr (opcode
->args
, 'r') != 0)
2538 /* Can't do simple format if source and dest are different. */
2540 if (X_RS2 (insn
) != X_RD (insn
)
2541 && strchr (opcode
->args
, 'O') != 0)
2542 /* Can't do simple format if source and dest are different. */
2545 (*info
->fprintf_func
) (stream
, opcode
->name
);
2548 register const char *s
;
2550 if (opcode
->args
[0] != ',')
2551 (*info
->fprintf_func
) (stream
, " ");
2552 for (s
= opcode
->args
; *s
!= '\0'; ++s
)
2556 (*info
->fprintf_func
) (stream
, ",");
2560 (*info
->fprintf_func
) (stream
, "a");
2565 (*info
->fprintf_func
) (stream
, "pn");
2570 (*info
->fprintf_func
) (stream
, "pt");
2576 } /* switch on arg */
2577 } /* while there are comma started args */
2579 (*info
->fprintf_func
) (stream
, " ");
2586 /* note fall-through */
2588 (*info
->fprintf_func
) (stream
, "%c", *s
);
2592 (*info
->fprintf_func
) (stream
, "0");
2595 #define reg(n) (*info->fprintf_func) (stream, "%%%s", reg_names[n])
2611 #define freg(n) (*info->fprintf_func) (stream, "%%%s", freg_names[n])
2612 #define fregx(n) (*info->fprintf_func) (stream, "%%%s", freg_names[((n) & ~1) | (((n) & 1) << 5)])
2614 freg (X_RS1 (insn
));
2616 case 'v': /* double/even */
2617 case 'V': /* quad/multiple of 4 */
2618 fregx (X_RS1 (insn
));
2622 freg (X_RS2 (insn
));
2624 case 'B': /* double/even */
2625 case 'R': /* quad/multiple of 4 */
2626 fregx (X_RS2 (insn
));
2632 case 'H': /* double/even */
2633 case 'J': /* quad/multiple of 4 */
2634 fregx (X_RD (insn
));
2639 #define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n))
2641 creg (X_RS1 (insn
));
2645 creg (X_RS2 (insn
));
2654 (*info
->fprintf_func
) (stream
, "%%hi(%#x)",
2655 ((unsigned) 0xFFFFFFFF
2656 & ((int) X_IMM22 (insn
) << 10)));
2659 case 'i': /* 13 bit immediate */
2660 case 'I': /* 11 bit immediate */
2661 case 'j': /* 10 bit immediate */
2666 imm
= X_SIMM (insn
, 13);
2668 imm
= X_SIMM (insn
, 11);
2670 imm
= X_SIMM (insn
, 10);
2672 /* Check to see whether we have a 1+i, and take
2675 Note: because of the way we sort the table,
2676 we will be matching 1+i rather than i+1,
2677 so it is OK to assume that i is after +,
2680 imm_added_to_rs1
= 1;
2683 (*info
->fprintf_func
) (stream
, "%d", imm
);
2685 (*info
->fprintf_func
) (stream
, "%#x", imm
);
2689 case 'X': /* 5 bit unsigned immediate */
2690 case 'Y': /* 6 bit unsigned immediate */
2692 int imm
= X_IMM (insn
, *s
== 'X' ? 5 : 6);
2695 (info
->fprintf_func
) (stream
, "%d", imm
);
2697 (info
->fprintf_func
) (stream
, "%#x", (unsigned) imm
);
2702 (info
->fprintf_func
) (stream
, "%d", X_IMM (insn
, 3));
2707 int mask
= X_MEMBAR (insn
);
2708 int bit
= 0x40, printed_one
= 0;
2712 (info
->fprintf_func
) (stream
, "0");
2719 (info
->fprintf_func
) (stream
, "|");
2720 name
= sparc_decode_membar (bit
);
2721 (info
->fprintf_func
) (stream
, "%s", name
);
2730 info
->target
= memaddr
+ SEX (X_DISP16 (insn
), 16) * 4;
2731 (*info
->print_address_func
) (info
->target
, info
);
2735 info
->target
= memaddr
+ SEX (X_DISP19 (insn
), 19) * 4;
2736 (*info
->print_address_func
) (info
->target
, info
);
2743 (*info
->fprintf_func
) (stream
, "%%fcc%c", *s
- '6' + '0');
2747 (*info
->fprintf_func
) (stream
, "%%icc");
2751 (*info
->fprintf_func
) (stream
, "%%xcc");
2755 (*info
->fprintf_func
) (stream
, "%%ccr");
2759 (*info
->fprintf_func
) (stream
, "%%fprs");
2763 (*info
->fprintf_func
) (stream
, "%%asi");
2767 (*info
->fprintf_func
) (stream
, "%%tick");
2771 (*info
->fprintf_func
) (stream
, "%%pc");
2775 if (X_RS1 (insn
) == 31)
2776 (*info
->fprintf_func
) (stream
, "%%ver");
2777 else if ((unsigned) X_RS1 (insn
) < 16)
2778 (*info
->fprintf_func
) (stream
, "%%%s",
2779 v9_priv_reg_names
[X_RS1 (insn
)]);
2781 (*info
->fprintf_func
) (stream
, "%%reserved");
2785 if ((unsigned) X_RD (insn
) < 15)
2786 (*info
->fprintf_func
) (stream
, "%%%s",
2787 v9_priv_reg_names
[X_RD (insn
)]);
2789 (*info
->fprintf_func
) (stream
, "%%reserved");
2793 if (X_RS1 (insn
) < 16 || X_RS1 (insn
) > 25)
2794 (*info
->fprintf_func
) (stream
, "%%reserved");
2796 (*info
->fprintf_func
) (stream
, "%%%s",
2797 v9a_asr_reg_names
[X_RS1 (insn
)-16]);
2801 if (X_RD (insn
) < 16 || X_RD (insn
) > 25)
2802 (*info
->fprintf_func
) (stream
, "%%reserved");
2804 (*info
->fprintf_func
) (stream
, "%%%s",
2805 v9a_asr_reg_names
[X_RD (insn
)-16]);
2810 const char *name
= sparc_decode_prefetch (X_RD (insn
));
2813 (*info
->fprintf_func
) (stream
, "%s", name
);
2815 (*info
->fprintf_func
) (stream
, "%d", X_RD (insn
));
2820 (*info
->fprintf_func
) (stream
, "%%asr%d", X_RS1 (insn
));
2824 (*info
->fprintf_func
) (stream
, "%%asr%d", X_RD (insn
));
2828 info
->target
= memaddr
+ SEX (X_DISP30 (insn
), 30) * 4;
2829 (*info
->print_address_func
) (info
->target
, info
);
2833 (*info
->fprintf_func
)
2834 (stream
, "%#x", SEX (X_DISP22 (insn
), 22));
2838 info
->target
= memaddr
+ SEX (X_DISP22 (insn
), 22) * 4;
2839 (*info
->print_address_func
) (info
->target
, info
);
2844 const char *name
= sparc_decode_asi (X_ASI (insn
));
2847 (*info
->fprintf_func
) (stream
, "%s", name
);
2849 (*info
->fprintf_func
) (stream
, "(%d)", X_ASI (insn
));
2854 (*info
->fprintf_func
) (stream
, "%%csr");
2858 (*info
->fprintf_func
) (stream
, "%%fsr");
2862 (*info
->fprintf_func
) (stream
, "%%psr");
2866 (*info
->fprintf_func
) (stream
, "%%fq");
2870 (*info
->fprintf_func
) (stream
, "%%cq");
2874 (*info
->fprintf_func
) (stream
, "%%tbr");
2878 (*info
->fprintf_func
) (stream
, "%%wim");
2882 (*info
->fprintf_func
) (stream
, "%d",
2883 ((X_LDST_I (insn
) << 8)
2888 (*info
->fprintf_func
) (stream
, "%%y");
2894 int val
= *s
== 'U' ? X_RS1 (insn
) : X_RD (insn
);
2895 const char *name
= sparc_decode_sparclet_cpreg (val
);
2898 (*info
->fprintf_func
) (stream
, "%s", name
);
2900 (*info
->fprintf_func
) (stream
, "%%cpreg(%d)", val
);
2907 /* If we are adding or or'ing something to rs1, then
2908 check to see whether the previous instruction was
2909 a sethi to the same register as in the sethi.
2910 If so, attempt to print the result of the add or
2911 or (in this context add and or do the same thing)
2912 and its symbolic value. */
2913 if (imm_ored_to_rs1
|| imm_added_to_rs1
)
2915 unsigned long prev_insn
;
2919 (*info
->read_memory_func
)
2920 (memaddr
- 4, buffer
, sizeof (buffer
), info
);
2921 prev_insn
= getword (buffer
);
2925 /* If it is a delayed branch, we need to look at the
2926 instruction before the delayed branch. This handles
2929 sethi %o1, %hi(_foo), %o1
2931 or %o1, %lo(_foo), %o1
2934 if (is_delayed_branch (prev_insn
))
2936 errcode
= (*info
->read_memory_func
)
2937 (memaddr
- 8, buffer
, sizeof (buffer
), info
);
2938 prev_insn
= getword (buffer
);
2942 /* If there was a problem reading memory, then assume
2943 the previous instruction was not sethi. */
2946 /* Is it sethi to the same register? */
2947 if ((prev_insn
& 0xc1c00000) == 0x01000000
2948 && X_RD (prev_insn
) == X_RS1 (insn
))
2950 (*info
->fprintf_func
) (stream
, "\t! ");
2952 ((unsigned) 0xFFFFFFFF
2953 & ((int) X_IMM22 (prev_insn
) << 10));
2954 if (imm_added_to_rs1
)
2955 info
->target
+= X_SIMM (insn
, 13);
2957 info
->target
|= X_SIMM (insn
, 13);
2958 (*info
->print_address_func
) (info
->target
, info
);
2959 info
->insn_type
= dis_dref
;
2960 info
->data_size
= 4; /* FIXME!!! */
2965 if (opcode
->flags
& (F_UNBR
|F_CONDBR
|F_JSR
))
2967 /* FIXME -- check is_annulled flag */
2968 if (opcode
->flags
& F_UNBR
)
2969 info
->insn_type
= dis_branch
;
2970 if (opcode
->flags
& F_CONDBR
)
2971 info
->insn_type
= dis_condbranch
;
2972 if (opcode
->flags
& F_JSR
)
2973 info
->insn_type
= dis_jsr
;
2974 if (opcode
->flags
& F_DELAYED
)
2975 info
->branch_delay_insns
= 1;
2978 return sizeof (buffer
);
2982 info
->insn_type
= dis_noninsn
; /* Mark as non-valid instruction */
2983 (*info
->fprintf_func
) (stream
, _("unknown"));
2984 return sizeof (buffer
);
2987 /* Given BFD mach number, return a mask of SPARC_OPCODE_ARCH_FOO values. */
2990 compute_arch_mask (mach
)
2996 case bfd_mach_sparc
:
2997 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8
);
2998 case bfd_mach_sparc_sparclet
:
2999 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET
);
3000 case bfd_mach_sparc_sparclite
:
3001 case bfd_mach_sparc_sparclite_le
:
3002 /* sparclites insns are recognized by default (because that's how
3003 they've always been treated, for better or worse). Kludge this by
3004 indicating generic v8 is also selected. */
3005 return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE
)
3006 | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8
));
3007 case bfd_mach_sparc_v8plus
:
3008 case bfd_mach_sparc_v9
:
3009 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9
);
3010 case bfd_mach_sparc_v8plusa
:
3011 case bfd_mach_sparc_v9a
:
3012 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A
);
3013 case bfd_mach_sparc_v8plusb
:
3014 case bfd_mach_sparc_v9b
:
3015 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B
);
3020 /* Compare opcodes A and B. */
3023 compare_opcodes (const void *a
, const void *b
)
3025 struct sparc_opcode
*op0
= * (struct sparc_opcode
**) a
;
3026 struct sparc_opcode
*op1
= * (struct sparc_opcode
**) b
;
3027 unsigned long int match0
= op0
->match
, match1
= op1
->match
;
3028 unsigned long int lose0
= op0
->lose
, lose1
= op1
->lose
;
3029 register unsigned int i
;
3031 /* If one (and only one) insn isn't supported by the current architecture,
3032 prefer the one that is. If neither are supported, but they're both for
3033 the same architecture, continue processing. Otherwise (both unsupported
3034 and for different architectures), prefer lower numbered arch's (fudged
3035 by comparing the bitmasks). */
3036 if (op0
->architecture
& current_arch_mask
)
3038 if (! (op1
->architecture
& current_arch_mask
))
3043 if (op1
->architecture
& current_arch_mask
)
3045 else if (op0
->architecture
!= op1
->architecture
)
3046 return op0
->architecture
- op1
->architecture
;
3049 /* If a bit is set in both match and lose, there is something
3050 wrong with the opcode table. */
3055 /* xgettext:c-format */
3056 _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
3057 op0
->name
, match0
, lose0
);
3058 op0
->lose
&= ~op0
->match
;
3066 /* xgettext:c-format */
3067 _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
3068 op1
->name
, match1
, lose1
);
3069 op1
->lose
&= ~op1
->match
;
3073 /* Because the bits that are variable in one opcode are constant in
3074 another, it is important to order the opcodes in the right order. */
3075 for (i
= 0; i
< 32; ++i
)
3077 unsigned long int x
= 1 << i
;
3078 int x0
= (match0
& x
) != 0;
3079 int x1
= (match1
& x
) != 0;
3085 for (i
= 0; i
< 32; ++i
)
3087 unsigned long int x
= 1 << i
;
3088 int x0
= (lose0
& x
) != 0;
3089 int x1
= (lose1
& x
) != 0;
3095 /* They are functionally equal. So as long as the opcode table is
3096 valid, we can put whichever one first we want, on aesthetic grounds. */
3098 /* Our first aesthetic ground is that aliases defer to real insns. */
3100 int alias_diff
= (op0
->flags
& F_ALIAS
) - (op1
->flags
& F_ALIAS
);
3101 if (alias_diff
!= 0)
3102 /* Put the one that isn't an alias first. */
3106 /* Except for aliases, two "identical" instructions had
3107 better have the same opcode. This is a sanity check on the table. */
3108 i
= strcmp (op0
->name
, op1
->name
);
3111 if (op0
->flags
& F_ALIAS
) /* If they're both aliases, be arbitrary. */
3115 /* xgettext:c-format */
3116 _("Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"),
3117 op0
->name
, op1
->name
);
3120 /* Fewer arguments are preferred. */
3122 int length_diff
= strlen (op0
->args
) - strlen (op1
->args
);
3123 if (length_diff
!= 0)
3124 /* Put the one with fewer arguments first. */
3128 /* Put 1+i before i+1. */
3130 char *p0
= (char *) strchr (op0
->args
, '+');
3131 char *p1
= (char *) strchr (op1
->args
, '+');
3135 /* There is a plus in both operands. Note that a plus
3136 sign cannot be the first character in args,
3137 so the following [-1]'s are valid. */
3138 if (p0
[-1] == 'i' && p1
[1] == 'i')
3139 /* op0 is i+1 and op1 is 1+i, so op1 goes first. */
3141 if (p0
[1] == 'i' && p1
[-1] == 'i')
3142 /* op0 is 1+i and op1 is i+1, so op0 goes first. */
3147 /* Put 1,i before i,1. */
3149 int i0
= strncmp (op0
->args
, "i,1", 3) == 0;
3150 int i1
= strncmp (op1
->args
, "i,1", 3) == 0;
3156 /* They are, as far as we can tell, identical.
3157 Since qsort may have rearranged the table partially, there is
3158 no way to tell which one was first in the opcode table as
3159 written, so just say there are equal. */
3160 /* ??? This is no longer true now that we sort a vector of pointers,
3161 not the table itself. */
3165 /* Build a hash table from the opcode table.
3166 OPCODE_TABLE is a sorted list of pointers into the opcode table. */
3169 build_hash_table (opcode_table
, hash_table
, num_opcodes
)
3170 const struct sparc_opcode
**opcode_table
;
3171 struct opcode_hash
**hash_table
;
3175 int hash_count
[HASH_SIZE
];
3176 static struct opcode_hash
*hash_buf
= NULL
;
3178 /* Start at the end of the table and work backwards so that each
3181 memset (hash_table
, 0, HASH_SIZE
* sizeof (hash_table
[0]));
3182 memset (hash_count
, 0, HASH_SIZE
* sizeof (hash_count
[0]));
3183 if (hash_buf
!= NULL
)
3185 hash_buf
= (struct opcode_hash
*) malloc (sizeof (struct opcode_hash
) * num_opcodes
);
3186 for (i
= num_opcodes
- 1; i
>= 0; --i
)
3188 register int hash
= HASH_INSN (opcode_table
[i
]->match
);
3189 register struct opcode_hash
*h
= &hash_buf
[i
];
3190 h
->next
= hash_table
[hash
];
3191 h
->opcode
= opcode_table
[i
];
3192 hash_table
[hash
] = h
;
3196 #if 0 /* for debugging */
3198 int min_count
= num_opcodes
, max_count
= 0;
3201 for (i
= 0; i
< HASH_SIZE
; ++i
)
3203 if (hash_count
[i
] < min_count
)
3204 min_count
= hash_count
[i
];
3205 if (hash_count
[i
] > max_count
)
3206 max_count
= hash_count
[i
];
3207 total
+= hash_count
[i
];
3210 printf ("Opcode hash table stats: min %d, max %d, ave %f\n",
3211 min_count
, max_count
, (double) total
/ HASH_SIZE
);
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