]> git.proxmox.com Git - qemu.git/blob - target-cris/cpu.c
Merge remote-tracking branch 'afaerber/tags/qom-cpu-for-anthony' into staging
[qemu.git] / target-cris / cpu.c
1 /*
2 * QEMU CRIS CPU
3 *
4 * Copyright (c) 2008 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
6 *
7 * Copyright (c) 2012 SUSE LINUX Products GmbH
8 *
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2.1 of the License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
18 *
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this library; if not, see
21 * <http://www.gnu.org/licenses/lgpl-2.1.html>
22 */
23
24 #include "cpu.h"
25 #include "qemu-common.h"
26 #include "mmu.h"
27
28
29 /* CPUClass::reset() */
30 static void cris_cpu_reset(CPUState *s)
31 {
32 CRISCPU *cpu = CRIS_CPU(s);
33 CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(cpu);
34 CPUCRISState *env = &cpu->env;
35 uint32_t vr;
36
37 ccc->parent_reset(s);
38
39 vr = env->pregs[PR_VR];
40 memset(env, 0, offsetof(CPUCRISState, breakpoints));
41 env->pregs[PR_VR] = vr;
42 tlb_flush(env, 1);
43
44 #if defined(CONFIG_USER_ONLY)
45 /* start in user mode with interrupts enabled. */
46 env->pregs[PR_CCS] |= U_FLAG | I_FLAG | P_FLAG;
47 #else
48 cris_mmu_init(env);
49 env->pregs[PR_CCS] = 0;
50 #endif
51 }
52
53 static ObjectClass *cris_cpu_class_by_name(const char *cpu_model)
54 {
55 ObjectClass *oc;
56 char *typename;
57
58 if (cpu_model == NULL) {
59 return NULL;
60 }
61
62 typename = g_strdup_printf("%s-" TYPE_CRIS_CPU, cpu_model);
63 oc = object_class_by_name(typename);
64 g_free(typename);
65 if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_CRIS_CPU) ||
66 object_class_is_abstract(oc))) {
67 oc = NULL;
68 }
69 return oc;
70 }
71
72 CRISCPU *cpu_cris_init(const char *cpu_model)
73 {
74 CRISCPU *cpu;
75 ObjectClass *oc;
76
77 oc = cris_cpu_class_by_name(cpu_model);
78 if (oc == NULL) {
79 return NULL;
80 }
81 cpu = CRIS_CPU(object_new(object_class_get_name(oc)));
82
83 object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
84
85 return cpu;
86 }
87
88 /* Sort alphabetically by VR. */
89 static gint cris_cpu_list_compare(gconstpointer a, gconstpointer b)
90 {
91 CRISCPUClass *ccc_a = CRIS_CPU_CLASS(a);
92 CRISCPUClass *ccc_b = CRIS_CPU_CLASS(b);
93
94 /* */
95 if (ccc_a->vr > ccc_b->vr) {
96 return 1;
97 } else if (ccc_a->vr < ccc_b->vr) {
98 return -1;
99 } else {
100 return 0;
101 }
102 }
103
104 static void cris_cpu_list_entry(gpointer data, gpointer user_data)
105 {
106 ObjectClass *oc = data;
107 CPUListState *s = user_data;
108 const char *typename = object_class_get_name(oc);
109 char *name;
110
111 name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_CRIS_CPU));
112 (*s->cpu_fprintf)(s->file, " %s\n", name);
113 g_free(name);
114 }
115
116 void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf)
117 {
118 CPUListState s = {
119 .file = f,
120 .cpu_fprintf = cpu_fprintf,
121 };
122 GSList *list;
123
124 list = object_class_get_list(TYPE_CRIS_CPU, false);
125 list = g_slist_sort(list, cris_cpu_list_compare);
126 (*cpu_fprintf)(f, "Available CPUs:\n");
127 g_slist_foreach(list, cris_cpu_list_entry, &s);
128 g_slist_free(list);
129 }
130
131 static void cris_cpu_realizefn(DeviceState *dev, Error **errp)
132 {
133 CRISCPU *cpu = CRIS_CPU(dev);
134 CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(dev);
135
136 cpu_reset(CPU(cpu));
137
138 ccc->parent_realize(dev, errp);
139 }
140
141 static void cris_cpu_initfn(Object *obj)
142 {
143 CPUState *cs = CPU(obj);
144 CRISCPU *cpu = CRIS_CPU(obj);
145 CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(obj);
146 CPUCRISState *env = &cpu->env;
147 static bool tcg_initialized;
148
149 cs->env_ptr = env;
150 cpu_exec_init(env);
151
152 env->pregs[PR_VR] = ccc->vr;
153
154 if (tcg_enabled() && !tcg_initialized) {
155 tcg_initialized = true;
156 if (env->pregs[PR_VR] < 32) {
157 cris_initialize_crisv10_tcg();
158 } else {
159 cris_initialize_tcg();
160 }
161 }
162 }
163
164 static void crisv8_cpu_class_init(ObjectClass *oc, void *data)
165 {
166 CPUClass *cc = CPU_CLASS(oc);
167 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
168
169 ccc->vr = 8;
170 cc->do_interrupt = crisv10_cpu_do_interrupt;
171 }
172
173 static void crisv9_cpu_class_init(ObjectClass *oc, void *data)
174 {
175 CPUClass *cc = CPU_CLASS(oc);
176 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
177
178 ccc->vr = 9;
179 cc->do_interrupt = crisv10_cpu_do_interrupt;
180 }
181
182 static void crisv10_cpu_class_init(ObjectClass *oc, void *data)
183 {
184 CPUClass *cc = CPU_CLASS(oc);
185 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
186
187 ccc->vr = 10;
188 cc->do_interrupt = crisv10_cpu_do_interrupt;
189 }
190
191 static void crisv11_cpu_class_init(ObjectClass *oc, void *data)
192 {
193 CPUClass *cc = CPU_CLASS(oc);
194 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
195
196 ccc->vr = 11;
197 cc->do_interrupt = crisv10_cpu_do_interrupt;
198 }
199
200 static void crisv32_cpu_class_init(ObjectClass *oc, void *data)
201 {
202 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
203
204 ccc->vr = 32;
205 }
206
207 #define TYPE(model) model "-" TYPE_CRIS_CPU
208
209 static const TypeInfo cris_cpu_model_type_infos[] = {
210 {
211 .name = TYPE("crisv8"),
212 .parent = TYPE_CRIS_CPU,
213 .class_init = crisv8_cpu_class_init,
214 }, {
215 .name = TYPE("crisv9"),
216 .parent = TYPE_CRIS_CPU,
217 .class_init = crisv9_cpu_class_init,
218 }, {
219 .name = TYPE("crisv10"),
220 .parent = TYPE_CRIS_CPU,
221 .class_init = crisv10_cpu_class_init,
222 }, {
223 .name = TYPE("crisv11"),
224 .parent = TYPE_CRIS_CPU,
225 .class_init = crisv11_cpu_class_init,
226 }, {
227 .name = TYPE("crisv32"),
228 .parent = TYPE_CRIS_CPU,
229 .class_init = crisv32_cpu_class_init,
230 }
231 };
232
233 #undef TYPE
234
235 static void cris_cpu_class_init(ObjectClass *oc, void *data)
236 {
237 DeviceClass *dc = DEVICE_CLASS(oc);
238 CPUClass *cc = CPU_CLASS(oc);
239 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
240
241 ccc->parent_realize = dc->realize;
242 dc->realize = cris_cpu_realizefn;
243
244 ccc->parent_reset = cc->reset;
245 cc->reset = cris_cpu_reset;
246
247 cc->class_by_name = cris_cpu_class_by_name;
248 cc->do_interrupt = cris_cpu_do_interrupt;
249 cc->dump_state = cris_cpu_dump_state;
250 }
251
252 static const TypeInfo cris_cpu_type_info = {
253 .name = TYPE_CRIS_CPU,
254 .parent = TYPE_CPU,
255 .instance_size = sizeof(CRISCPU),
256 .instance_init = cris_cpu_initfn,
257 .abstract = true,
258 .class_size = sizeof(CRISCPUClass),
259 .class_init = cris_cpu_class_init,
260 };
261
262 static void cris_cpu_register_types(void)
263 {
264 int i;
265
266 type_register_static(&cris_cpu_type_info);
267 for (i = 0; i < ARRAY_SIZE(cris_cpu_model_type_infos); i++) {
268 type_register_static(&cris_cpu_model_type_infos[i]);
269 }
270 }
271
272 type_init(cris_cpu_register_types)