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1 /*
2 * QEMU CRIS CPU
3 *
4 * Copyright (c) 2008 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
6 *
7 * Copyright (c) 2012 SUSE LINUX Products GmbH
8 *
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2.1 of the License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
18 *
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this library; if not, see
21 * <http://www.gnu.org/licenses/lgpl-2.1.html>
22 */
23
24 #include "cpu.h"
25 #include "qemu-common.h"
26 #include "mmu.h"
27
28
29 static void cris_cpu_set_pc(CPUState *cs, vaddr value)
30 {
31 CRISCPU *cpu = CRIS_CPU(cs);
32
33 cpu->env.pc = value;
34 }
35
36 /* CPUClass::reset() */
37 static void cris_cpu_reset(CPUState *s)
38 {
39 CRISCPU *cpu = CRIS_CPU(s);
40 CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(cpu);
41 CPUCRISState *env = &cpu->env;
42 uint32_t vr;
43
44 ccc->parent_reset(s);
45
46 vr = env->pregs[PR_VR];
47 memset(env, 0, offsetof(CPUCRISState, breakpoints));
48 env->pregs[PR_VR] = vr;
49 tlb_flush(env, 1);
50
51 #if defined(CONFIG_USER_ONLY)
52 /* start in user mode with interrupts enabled. */
53 env->pregs[PR_CCS] |= U_FLAG | I_FLAG | P_FLAG;
54 #else
55 cris_mmu_init(env);
56 env->pregs[PR_CCS] = 0;
57 #endif
58 }
59
60 static ObjectClass *cris_cpu_class_by_name(const char *cpu_model)
61 {
62 ObjectClass *oc;
63 char *typename;
64
65 if (cpu_model == NULL) {
66 return NULL;
67 }
68
69 typename = g_strdup_printf("%s-" TYPE_CRIS_CPU, cpu_model);
70 oc = object_class_by_name(typename);
71 g_free(typename);
72 if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_CRIS_CPU) ||
73 object_class_is_abstract(oc))) {
74 oc = NULL;
75 }
76 return oc;
77 }
78
79 CRISCPU *cpu_cris_init(const char *cpu_model)
80 {
81 CRISCPU *cpu;
82 ObjectClass *oc;
83
84 oc = cris_cpu_class_by_name(cpu_model);
85 if (oc == NULL) {
86 return NULL;
87 }
88 cpu = CRIS_CPU(object_new(object_class_get_name(oc)));
89
90 object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
91
92 return cpu;
93 }
94
95 /* Sort alphabetically by VR. */
96 static gint cris_cpu_list_compare(gconstpointer a, gconstpointer b)
97 {
98 CRISCPUClass *ccc_a = CRIS_CPU_CLASS(a);
99 CRISCPUClass *ccc_b = CRIS_CPU_CLASS(b);
100
101 /* */
102 if (ccc_a->vr > ccc_b->vr) {
103 return 1;
104 } else if (ccc_a->vr < ccc_b->vr) {
105 return -1;
106 } else {
107 return 0;
108 }
109 }
110
111 static void cris_cpu_list_entry(gpointer data, gpointer user_data)
112 {
113 ObjectClass *oc = data;
114 CPUListState *s = user_data;
115 const char *typename = object_class_get_name(oc);
116 char *name;
117
118 name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_CRIS_CPU));
119 (*s->cpu_fprintf)(s->file, " %s\n", name);
120 g_free(name);
121 }
122
123 void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf)
124 {
125 CPUListState s = {
126 .file = f,
127 .cpu_fprintf = cpu_fprintf,
128 };
129 GSList *list;
130
131 list = object_class_get_list(TYPE_CRIS_CPU, false);
132 list = g_slist_sort(list, cris_cpu_list_compare);
133 (*cpu_fprintf)(f, "Available CPUs:\n");
134 g_slist_foreach(list, cris_cpu_list_entry, &s);
135 g_slist_free(list);
136 }
137
138 static void cris_cpu_realizefn(DeviceState *dev, Error **errp)
139 {
140 CRISCPU *cpu = CRIS_CPU(dev);
141 CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(dev);
142
143 cpu_reset(CPU(cpu));
144
145 ccc->parent_realize(dev, errp);
146 }
147
148 static void cris_cpu_initfn(Object *obj)
149 {
150 CPUState *cs = CPU(obj);
151 CRISCPU *cpu = CRIS_CPU(obj);
152 CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(obj);
153 CPUCRISState *env = &cpu->env;
154 static bool tcg_initialized;
155
156 cs->env_ptr = env;
157 cpu_exec_init(env);
158
159 env->pregs[PR_VR] = ccc->vr;
160
161 if (tcg_enabled() && !tcg_initialized) {
162 tcg_initialized = true;
163 if (env->pregs[PR_VR] < 32) {
164 cris_initialize_crisv10_tcg();
165 } else {
166 cris_initialize_tcg();
167 }
168 }
169 }
170
171 static void crisv8_cpu_class_init(ObjectClass *oc, void *data)
172 {
173 CPUClass *cc = CPU_CLASS(oc);
174 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
175
176 ccc->vr = 8;
177 cc->do_interrupt = crisv10_cpu_do_interrupt;
178 }
179
180 static void crisv9_cpu_class_init(ObjectClass *oc, void *data)
181 {
182 CPUClass *cc = CPU_CLASS(oc);
183 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
184
185 ccc->vr = 9;
186 cc->do_interrupt = crisv10_cpu_do_interrupt;
187 }
188
189 static void crisv10_cpu_class_init(ObjectClass *oc, void *data)
190 {
191 CPUClass *cc = CPU_CLASS(oc);
192 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
193
194 ccc->vr = 10;
195 cc->do_interrupt = crisv10_cpu_do_interrupt;
196 }
197
198 static void crisv11_cpu_class_init(ObjectClass *oc, void *data)
199 {
200 CPUClass *cc = CPU_CLASS(oc);
201 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
202
203 ccc->vr = 11;
204 cc->do_interrupt = crisv10_cpu_do_interrupt;
205 }
206
207 static void crisv32_cpu_class_init(ObjectClass *oc, void *data)
208 {
209 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
210
211 ccc->vr = 32;
212 }
213
214 #define TYPE(model) model "-" TYPE_CRIS_CPU
215
216 static const TypeInfo cris_cpu_model_type_infos[] = {
217 {
218 .name = TYPE("crisv8"),
219 .parent = TYPE_CRIS_CPU,
220 .class_init = crisv8_cpu_class_init,
221 }, {
222 .name = TYPE("crisv9"),
223 .parent = TYPE_CRIS_CPU,
224 .class_init = crisv9_cpu_class_init,
225 }, {
226 .name = TYPE("crisv10"),
227 .parent = TYPE_CRIS_CPU,
228 .class_init = crisv10_cpu_class_init,
229 }, {
230 .name = TYPE("crisv11"),
231 .parent = TYPE_CRIS_CPU,
232 .class_init = crisv11_cpu_class_init,
233 }, {
234 .name = TYPE("crisv32"),
235 .parent = TYPE_CRIS_CPU,
236 .class_init = crisv32_cpu_class_init,
237 }
238 };
239
240 #undef TYPE
241
242 static void cris_cpu_class_init(ObjectClass *oc, void *data)
243 {
244 DeviceClass *dc = DEVICE_CLASS(oc);
245 CPUClass *cc = CPU_CLASS(oc);
246 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
247
248 ccc->parent_realize = dc->realize;
249 dc->realize = cris_cpu_realizefn;
250
251 ccc->parent_reset = cc->reset;
252 cc->reset = cris_cpu_reset;
253
254 cc->class_by_name = cris_cpu_class_by_name;
255 cc->do_interrupt = cris_cpu_do_interrupt;
256 cc->dump_state = cris_cpu_dump_state;
257 cc->set_pc = cris_cpu_set_pc;
258 }
259
260 static const TypeInfo cris_cpu_type_info = {
261 .name = TYPE_CRIS_CPU,
262 .parent = TYPE_CPU,
263 .instance_size = sizeof(CRISCPU),
264 .instance_init = cris_cpu_initfn,
265 .abstract = true,
266 .class_size = sizeof(CRISCPUClass),
267 .class_init = cris_cpu_class_init,
268 };
269
270 static void cris_cpu_register_types(void)
271 {
272 int i;
273
274 type_register_static(&cris_cpu_type_info);
275 for (i = 0; i < ARRAY_SIZE(cris_cpu_model_type_infos); i++) {
276 type_register_static(&cris_cpu_model_type_infos[i]);
277 }
278 }
279
280 type_init(cris_cpu_register_types)