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target-i386: do not override nr_cores for -cpu host
[qemu.git] / target-i386 / cpu.c
1 /*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include <stdio.h>
21 #include <string.h>
22 #include <inttypes.h>
23
24 #include "cpu.h"
25 #include "sysemu/kvm.h"
26 #include "sysemu/cpus.h"
27 #include "topology.h"
28
29 #include "qemu/option.h"
30 #include "qemu/config-file.h"
31 #include "qapi/qmp/qerror.h"
32
33 #include "qapi-types.h"
34 #include "qapi-visit.h"
35 #include "qapi/visitor.h"
36 #include "sysemu/arch_init.h"
37
38 #include "hw/hw.h"
39 #if defined(CONFIG_KVM)
40 #include <linux/kvm_para.h>
41 #endif
42
43 #include "sysemu/sysemu.h"
44 #include "hw/qdev-properties.h"
45 #include "hw/cpu/icc_bus.h"
46 #ifndef CONFIG_USER_ONLY
47 #include "hw/xen/xen.h"
48 #include "hw/i386/apic_internal.h"
49 #endif
50
51
52 /* Cache topology CPUID constants: */
53
54 /* CPUID Leaf 2 Descriptors */
55
56 #define CPUID_2_L1D_32KB_8WAY_64B 0x2c
57 #define CPUID_2_L1I_32KB_8WAY_64B 0x30
58 #define CPUID_2_L2_2MB_8WAY_64B 0x7d
59
60
61 /* CPUID Leaf 4 constants: */
62
63 /* EAX: */
64 #define CPUID_4_TYPE_DCACHE 1
65 #define CPUID_4_TYPE_ICACHE 2
66 #define CPUID_4_TYPE_UNIFIED 3
67
68 #define CPUID_4_LEVEL(l) ((l) << 5)
69
70 #define CPUID_4_SELF_INIT_LEVEL (1 << 8)
71 #define CPUID_4_FULLY_ASSOC (1 << 9)
72
73 /* EDX: */
74 #define CPUID_4_NO_INVD_SHARING (1 << 0)
75 #define CPUID_4_INCLUSIVE (1 << 1)
76 #define CPUID_4_COMPLEX_IDX (1 << 2)
77
78 #define ASSOC_FULL 0xFF
79
80 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
81 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
82 a == 2 ? 0x2 : \
83 a == 4 ? 0x4 : \
84 a == 8 ? 0x6 : \
85 a == 16 ? 0x8 : \
86 a == 32 ? 0xA : \
87 a == 48 ? 0xB : \
88 a == 64 ? 0xC : \
89 a == 96 ? 0xD : \
90 a == 128 ? 0xE : \
91 a == ASSOC_FULL ? 0xF : \
92 0 /* invalid value */)
93
94
95 /* Definitions of the hardcoded cache entries we expose: */
96
97 /* L1 data cache: */
98 #define L1D_LINE_SIZE 64
99 #define L1D_ASSOCIATIVITY 8
100 #define L1D_SETS 64
101 #define L1D_PARTITIONS 1
102 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
103 #define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
104 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
105 #define L1D_LINES_PER_TAG 1
106 #define L1D_SIZE_KB_AMD 64
107 #define L1D_ASSOCIATIVITY_AMD 2
108
109 /* L1 instruction cache: */
110 #define L1I_LINE_SIZE 64
111 #define L1I_ASSOCIATIVITY 8
112 #define L1I_SETS 64
113 #define L1I_PARTITIONS 1
114 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
115 #define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
116 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
117 #define L1I_LINES_PER_TAG 1
118 #define L1I_SIZE_KB_AMD 64
119 #define L1I_ASSOCIATIVITY_AMD 2
120
121 /* Level 2 unified cache: */
122 #define L2_LINE_SIZE 64
123 #define L2_ASSOCIATIVITY 16
124 #define L2_SETS 4096
125 #define L2_PARTITIONS 1
126 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
127 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
128 #define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
129 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
130 #define L2_LINES_PER_TAG 1
131 #define L2_SIZE_KB_AMD 512
132
133 /* No L3 cache: */
134 #define L3_SIZE_KB 0 /* disabled */
135 #define L3_ASSOCIATIVITY 0 /* disabled */
136 #define L3_LINES_PER_TAG 0 /* disabled */
137 #define L3_LINE_SIZE 0 /* disabled */
138
139 /* TLB definitions: */
140
141 #define L1_DTLB_2M_ASSOC 1
142 #define L1_DTLB_2M_ENTRIES 255
143 #define L1_DTLB_4K_ASSOC 1
144 #define L1_DTLB_4K_ENTRIES 255
145
146 #define L1_ITLB_2M_ASSOC 1
147 #define L1_ITLB_2M_ENTRIES 255
148 #define L1_ITLB_4K_ASSOC 1
149 #define L1_ITLB_4K_ENTRIES 255
150
151 #define L2_DTLB_2M_ASSOC 0 /* disabled */
152 #define L2_DTLB_2M_ENTRIES 0 /* disabled */
153 #define L2_DTLB_4K_ASSOC 4
154 #define L2_DTLB_4K_ENTRIES 512
155
156 #define L2_ITLB_2M_ASSOC 0 /* disabled */
157 #define L2_ITLB_2M_ENTRIES 0 /* disabled */
158 #define L2_ITLB_4K_ASSOC 4
159 #define L2_ITLB_4K_ENTRIES 512
160
161
162
163 static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
164 uint32_t vendor2, uint32_t vendor3)
165 {
166 int i;
167 for (i = 0; i < 4; i++) {
168 dst[i] = vendor1 >> (8 * i);
169 dst[i + 4] = vendor2 >> (8 * i);
170 dst[i + 8] = vendor3 >> (8 * i);
171 }
172 dst[CPUID_VENDOR_SZ] = '\0';
173 }
174
175 /* feature flags taken from "Intel Processor Identification and the CPUID
176 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
177 * between feature naming conventions, aliases may be added.
178 */
179 static const char *feature_name[] = {
180 "fpu", "vme", "de", "pse",
181 "tsc", "msr", "pae", "mce",
182 "cx8", "apic", NULL, "sep",
183 "mtrr", "pge", "mca", "cmov",
184 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
185 NULL, "ds" /* Intel dts */, "acpi", "mmx",
186 "fxsr", "sse", "sse2", "ss",
187 "ht" /* Intel htt */, "tm", "ia64", "pbe",
188 };
189 static const char *ext_feature_name[] = {
190 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
191 "ds_cpl", "vmx", "smx", "est",
192 "tm2", "ssse3", "cid", NULL,
193 "fma", "cx16", "xtpr", "pdcm",
194 NULL, "pcid", "dca", "sse4.1|sse4_1",
195 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
196 "tsc-deadline", "aes", "xsave", "osxsave",
197 "avx", "f16c", "rdrand", "hypervisor",
198 };
199 /* Feature names that are already defined on feature_name[] but are set on
200 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
201 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
202 * if and only if CPU vendor is AMD.
203 */
204 static const char *ext2_feature_name[] = {
205 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
206 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
207 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
208 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
209 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
210 "nx|xd", NULL, "mmxext", NULL /* mmx */,
211 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
212 NULL, "lm|i64", "3dnowext", "3dnow",
213 };
214 static const char *ext3_feature_name[] = {
215 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
216 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
217 "3dnowprefetch", "osvw", "ibs", "xop",
218 "skinit", "wdt", NULL, "lwp",
219 "fma4", "tce", NULL, "nodeid_msr",
220 NULL, "tbm", "topoext", "perfctr_core",
221 "perfctr_nb", NULL, NULL, NULL,
222 NULL, NULL, NULL, NULL,
223 };
224
225 static const char *ext4_feature_name[] = {
226 NULL, NULL, "xstore", "xstore-en",
227 NULL, NULL, "xcrypt", "xcrypt-en",
228 "ace2", "ace2-en", "phe", "phe-en",
229 "pmm", "pmm-en", NULL, NULL,
230 NULL, NULL, NULL, NULL,
231 NULL, NULL, NULL, NULL,
232 NULL, NULL, NULL, NULL,
233 NULL, NULL, NULL, NULL,
234 };
235
236 static const char *kvm_feature_name[] = {
237 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
238 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
239 NULL, NULL, NULL, NULL,
240 NULL, NULL, NULL, NULL,
241 NULL, NULL, NULL, NULL,
242 NULL, NULL, NULL, NULL,
243 NULL, NULL, NULL, NULL,
244 NULL, NULL, NULL, NULL,
245 };
246
247 static const char *svm_feature_name[] = {
248 "npt", "lbrv", "svm_lock", "nrip_save",
249 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
250 NULL, NULL, "pause_filter", NULL,
251 "pfthreshold", NULL, NULL, NULL,
252 NULL, NULL, NULL, NULL,
253 NULL, NULL, NULL, NULL,
254 NULL, NULL, NULL, NULL,
255 NULL, NULL, NULL, NULL,
256 };
257
258 static const char *cpuid_7_0_ebx_feature_name[] = {
259 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
260 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
261 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
262 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
263 };
264
265 typedef struct FeatureWordInfo {
266 const char **feat_names;
267 uint32_t cpuid_eax; /* Input EAX for CPUID */
268 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
269 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
270 int cpuid_reg; /* output register (R_* constant) */
271 } FeatureWordInfo;
272
273 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
274 [FEAT_1_EDX] = {
275 .feat_names = feature_name,
276 .cpuid_eax = 1, .cpuid_reg = R_EDX,
277 },
278 [FEAT_1_ECX] = {
279 .feat_names = ext_feature_name,
280 .cpuid_eax = 1, .cpuid_reg = R_ECX,
281 },
282 [FEAT_8000_0001_EDX] = {
283 .feat_names = ext2_feature_name,
284 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
285 },
286 [FEAT_8000_0001_ECX] = {
287 .feat_names = ext3_feature_name,
288 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
289 },
290 [FEAT_C000_0001_EDX] = {
291 .feat_names = ext4_feature_name,
292 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
293 },
294 [FEAT_KVM] = {
295 .feat_names = kvm_feature_name,
296 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
297 },
298 [FEAT_SVM] = {
299 .feat_names = svm_feature_name,
300 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
301 },
302 [FEAT_7_0_EBX] = {
303 .feat_names = cpuid_7_0_ebx_feature_name,
304 .cpuid_eax = 7,
305 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
306 .cpuid_reg = R_EBX,
307 },
308 };
309
310 typedef struct X86RegisterInfo32 {
311 /* Name of register */
312 const char *name;
313 /* QAPI enum value register */
314 X86CPURegister32 qapi_enum;
315 } X86RegisterInfo32;
316
317 #define REGISTER(reg) \
318 [R_##reg] = { .name = #reg, .qapi_enum = X86_C_P_U_REGISTER32_##reg }
319 X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
320 REGISTER(EAX),
321 REGISTER(ECX),
322 REGISTER(EDX),
323 REGISTER(EBX),
324 REGISTER(ESP),
325 REGISTER(EBP),
326 REGISTER(ESI),
327 REGISTER(EDI),
328 };
329 #undef REGISTER
330
331 typedef struct ExtSaveArea {
332 uint32_t feature, bits;
333 uint32_t offset, size;
334 } ExtSaveArea;
335
336 static const ExtSaveArea ext_save_areas[] = {
337 [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
338 .offset = 0x100, .size = 0x240 },
339 };
340
341 const char *get_register_name_32(unsigned int reg)
342 {
343 if (reg >= CPU_NB_REGS32) {
344 return NULL;
345 }
346 return x86_reg_info_32[reg].name;
347 }
348
349 /* collects per-function cpuid data
350 */
351 typedef struct model_features_t {
352 uint32_t *guest_feat;
353 uint32_t *host_feat;
354 FeatureWord feat_word;
355 } model_features_t;
356
357 int check_cpuid = 0;
358 int enforce_cpuid = 0;
359
360 static uint32_t kvm_default_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
361 (1 << KVM_FEATURE_NOP_IO_DELAY) |
362 (1 << KVM_FEATURE_CLOCKSOURCE2) |
363 (1 << KVM_FEATURE_ASYNC_PF) |
364 (1 << KVM_FEATURE_STEAL_TIME) |
365 (1 << KVM_FEATURE_PV_EOI) |
366 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
367
368 void disable_kvm_pv_eoi(void)
369 {
370 kvm_default_features &= ~(1UL << KVM_FEATURE_PV_EOI);
371 }
372
373 void host_cpuid(uint32_t function, uint32_t count,
374 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
375 {
376 #if defined(CONFIG_KVM)
377 uint32_t vec[4];
378
379 #ifdef __x86_64__
380 asm volatile("cpuid"
381 : "=a"(vec[0]), "=b"(vec[1]),
382 "=c"(vec[2]), "=d"(vec[3])
383 : "0"(function), "c"(count) : "cc");
384 #else
385 asm volatile("pusha \n\t"
386 "cpuid \n\t"
387 "mov %%eax, 0(%2) \n\t"
388 "mov %%ebx, 4(%2) \n\t"
389 "mov %%ecx, 8(%2) \n\t"
390 "mov %%edx, 12(%2) \n\t"
391 "popa"
392 : : "a"(function), "c"(count), "S"(vec)
393 : "memory", "cc");
394 #endif
395
396 if (eax)
397 *eax = vec[0];
398 if (ebx)
399 *ebx = vec[1];
400 if (ecx)
401 *ecx = vec[2];
402 if (edx)
403 *edx = vec[3];
404 #endif
405 }
406
407 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
408
409 /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
410 * a substring. ex if !NULL points to the first char after a substring,
411 * otherwise the string is assumed to sized by a terminating nul.
412 * Return lexical ordering of *s1:*s2.
413 */
414 static int sstrcmp(const char *s1, const char *e1, const char *s2,
415 const char *e2)
416 {
417 for (;;) {
418 if (!*s1 || !*s2 || *s1 != *s2)
419 return (*s1 - *s2);
420 ++s1, ++s2;
421 if (s1 == e1 && s2 == e2)
422 return (0);
423 else if (s1 == e1)
424 return (*s2);
425 else if (s2 == e2)
426 return (*s1);
427 }
428 }
429
430 /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
431 * '|' delimited (possibly empty) strings in which case search for a match
432 * within the alternatives proceeds left to right. Return 0 for success,
433 * non-zero otherwise.
434 */
435 static int altcmp(const char *s, const char *e, const char *altstr)
436 {
437 const char *p, *q;
438
439 for (q = p = altstr; ; ) {
440 while (*p && *p != '|')
441 ++p;
442 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
443 return (0);
444 if (!*p)
445 return (1);
446 else
447 q = ++p;
448 }
449 }
450
451 /* search featureset for flag *[s..e), if found set corresponding bit in
452 * *pval and return true, otherwise return false
453 */
454 static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
455 const char **featureset)
456 {
457 uint32_t mask;
458 const char **ppc;
459 bool found = false;
460
461 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
462 if (*ppc && !altcmp(s, e, *ppc)) {
463 *pval |= mask;
464 found = true;
465 }
466 }
467 return found;
468 }
469
470 static void add_flagname_to_bitmaps(const char *flagname,
471 FeatureWordArray words)
472 {
473 FeatureWord w;
474 for (w = 0; w < FEATURE_WORDS; w++) {
475 FeatureWordInfo *wi = &feature_word_info[w];
476 if (wi->feat_names &&
477 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
478 break;
479 }
480 }
481 if (w == FEATURE_WORDS) {
482 fprintf(stderr, "CPU feature %s not found\n", flagname);
483 }
484 }
485
486 typedef struct x86_def_t {
487 const char *name;
488 uint32_t level;
489 uint32_t xlevel;
490 uint32_t xlevel2;
491 /* vendor is zero-terminated, 12 character ASCII string */
492 char vendor[CPUID_VENDOR_SZ + 1];
493 int family;
494 int model;
495 int stepping;
496 FeatureWordArray features;
497 char model_id[48];
498 bool cache_info_passthrough;
499 } x86_def_t;
500
501 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
502 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
503 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
504 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
505 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
506 CPUID_PSE36 | CPUID_FXSR)
507 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
508 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
509 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
510 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
511 CPUID_PAE | CPUID_SEP | CPUID_APIC)
512
513 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
514 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
515 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
516 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
517 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
518 /* partly implemented:
519 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
520 CPUID_PSE36 (needed for Solaris) */
521 /* missing:
522 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
523 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
524 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
525 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
526 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
527 /* missing:
528 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
529 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
530 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
531 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
532 CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
533 CPUID_EXT_RDRAND */
534 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
535 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
536 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
537 /* missing:
538 CPUID_EXT2_PDPE1GB */
539 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
540 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
541 #define TCG_SVM_FEATURES 0
542 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP \
543 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
544 /* missing:
545 CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
546 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
547 CPUID_7_0_EBX_RDSEED */
548
549 /* built-in CPU model definitions
550 */
551 static x86_def_t builtin_x86_defs[] = {
552 {
553 .name = "qemu64",
554 .level = 4,
555 .vendor = CPUID_VENDOR_AMD,
556 .family = 6,
557 .model = 6,
558 .stepping = 3,
559 .features[FEAT_1_EDX] =
560 PPRO_FEATURES |
561 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
562 CPUID_PSE36,
563 .features[FEAT_1_ECX] =
564 CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
565 .features[FEAT_8000_0001_EDX] =
566 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
567 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
568 .features[FEAT_8000_0001_ECX] =
569 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
570 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
571 .xlevel = 0x8000000A,
572 },
573 {
574 .name = "phenom",
575 .level = 5,
576 .vendor = CPUID_VENDOR_AMD,
577 .family = 16,
578 .model = 2,
579 .stepping = 3,
580 .features[FEAT_1_EDX] =
581 PPRO_FEATURES |
582 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
583 CPUID_PSE36 | CPUID_VME | CPUID_HT,
584 .features[FEAT_1_ECX] =
585 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
586 CPUID_EXT_POPCNT,
587 .features[FEAT_8000_0001_EDX] =
588 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
589 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
590 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
591 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
592 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
593 CPUID_EXT3_CR8LEG,
594 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
595 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
596 .features[FEAT_8000_0001_ECX] =
597 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
598 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
599 .features[FEAT_SVM] =
600 CPUID_SVM_NPT | CPUID_SVM_LBRV,
601 .xlevel = 0x8000001A,
602 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
603 },
604 {
605 .name = "core2duo",
606 .level = 10,
607 .vendor = CPUID_VENDOR_INTEL,
608 .family = 6,
609 .model = 15,
610 .stepping = 11,
611 .features[FEAT_1_EDX] =
612 PPRO_FEATURES |
613 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
614 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
615 CPUID_HT | CPUID_TM | CPUID_PBE,
616 .features[FEAT_1_ECX] =
617 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
618 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
619 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
620 .features[FEAT_8000_0001_EDX] =
621 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
622 .features[FEAT_8000_0001_ECX] =
623 CPUID_EXT3_LAHF_LM,
624 .xlevel = 0x80000008,
625 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
626 },
627 {
628 .name = "kvm64",
629 .level = 5,
630 .vendor = CPUID_VENDOR_INTEL,
631 .family = 15,
632 .model = 6,
633 .stepping = 1,
634 /* Missing: CPUID_VME, CPUID_HT */
635 .features[FEAT_1_EDX] =
636 PPRO_FEATURES |
637 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
638 CPUID_PSE36,
639 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
640 .features[FEAT_1_ECX] =
641 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
642 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
643 .features[FEAT_8000_0001_EDX] =
644 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
645 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
646 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
647 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
648 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
649 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
650 .features[FEAT_8000_0001_ECX] =
651 0,
652 .xlevel = 0x80000008,
653 .model_id = "Common KVM processor"
654 },
655 {
656 .name = "qemu32",
657 .level = 4,
658 .vendor = CPUID_VENDOR_INTEL,
659 .family = 6,
660 .model = 6,
661 .stepping = 3,
662 .features[FEAT_1_EDX] =
663 PPRO_FEATURES,
664 .features[FEAT_1_ECX] =
665 CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
666 .xlevel = 0x80000004,
667 },
668 {
669 .name = "kvm32",
670 .level = 5,
671 .vendor = CPUID_VENDOR_INTEL,
672 .family = 15,
673 .model = 6,
674 .stepping = 1,
675 .features[FEAT_1_EDX] =
676 PPRO_FEATURES |
677 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
678 .features[FEAT_1_ECX] =
679 CPUID_EXT_SSE3,
680 .features[FEAT_8000_0001_EDX] =
681 PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
682 .features[FEAT_8000_0001_ECX] =
683 0,
684 .xlevel = 0x80000008,
685 .model_id = "Common 32-bit KVM processor"
686 },
687 {
688 .name = "coreduo",
689 .level = 10,
690 .vendor = CPUID_VENDOR_INTEL,
691 .family = 6,
692 .model = 14,
693 .stepping = 8,
694 .features[FEAT_1_EDX] =
695 PPRO_FEATURES | CPUID_VME |
696 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
697 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
698 .features[FEAT_1_ECX] =
699 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
700 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
701 .features[FEAT_8000_0001_EDX] =
702 CPUID_EXT2_NX,
703 .xlevel = 0x80000008,
704 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
705 },
706 {
707 .name = "486",
708 .level = 1,
709 .vendor = CPUID_VENDOR_INTEL,
710 .family = 4,
711 .model = 8,
712 .stepping = 0,
713 .features[FEAT_1_EDX] =
714 I486_FEATURES,
715 .xlevel = 0,
716 },
717 {
718 .name = "pentium",
719 .level = 1,
720 .vendor = CPUID_VENDOR_INTEL,
721 .family = 5,
722 .model = 4,
723 .stepping = 3,
724 .features[FEAT_1_EDX] =
725 PENTIUM_FEATURES,
726 .xlevel = 0,
727 },
728 {
729 .name = "pentium2",
730 .level = 2,
731 .vendor = CPUID_VENDOR_INTEL,
732 .family = 6,
733 .model = 5,
734 .stepping = 2,
735 .features[FEAT_1_EDX] =
736 PENTIUM2_FEATURES,
737 .xlevel = 0,
738 },
739 {
740 .name = "pentium3",
741 .level = 2,
742 .vendor = CPUID_VENDOR_INTEL,
743 .family = 6,
744 .model = 7,
745 .stepping = 3,
746 .features[FEAT_1_EDX] =
747 PENTIUM3_FEATURES,
748 .xlevel = 0,
749 },
750 {
751 .name = "athlon",
752 .level = 2,
753 .vendor = CPUID_VENDOR_AMD,
754 .family = 6,
755 .model = 2,
756 .stepping = 3,
757 .features[FEAT_1_EDX] =
758 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
759 CPUID_MCA,
760 .features[FEAT_8000_0001_EDX] =
761 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
762 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
763 .xlevel = 0x80000008,
764 },
765 {
766 .name = "n270",
767 /* original is on level 10 */
768 .level = 5,
769 .vendor = CPUID_VENDOR_INTEL,
770 .family = 6,
771 .model = 28,
772 .stepping = 2,
773 .features[FEAT_1_EDX] =
774 PPRO_FEATURES |
775 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
776 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
777 /* Some CPUs got no CPUID_SEP */
778 .features[FEAT_1_ECX] =
779 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
780 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR |
781 CPUID_EXT_MOVBE,
782 .features[FEAT_8000_0001_EDX] =
783 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
784 CPUID_EXT2_NX,
785 .features[FEAT_8000_0001_ECX] =
786 CPUID_EXT3_LAHF_LM,
787 .xlevel = 0x8000000A,
788 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
789 },
790 {
791 .name = "Conroe",
792 .level = 4,
793 .vendor = CPUID_VENDOR_INTEL,
794 .family = 6,
795 .model = 15,
796 .stepping = 3,
797 .features[FEAT_1_EDX] =
798 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
799 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
800 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
801 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
802 CPUID_DE | CPUID_FP87,
803 .features[FEAT_1_ECX] =
804 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
805 .features[FEAT_8000_0001_EDX] =
806 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
807 .features[FEAT_8000_0001_ECX] =
808 CPUID_EXT3_LAHF_LM,
809 .xlevel = 0x8000000A,
810 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
811 },
812 {
813 .name = "Penryn",
814 .level = 4,
815 .vendor = CPUID_VENDOR_INTEL,
816 .family = 6,
817 .model = 23,
818 .stepping = 3,
819 .features[FEAT_1_EDX] =
820 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
821 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
822 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
823 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
824 CPUID_DE | CPUID_FP87,
825 .features[FEAT_1_ECX] =
826 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
827 CPUID_EXT_SSE3,
828 .features[FEAT_8000_0001_EDX] =
829 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
830 .features[FEAT_8000_0001_ECX] =
831 CPUID_EXT3_LAHF_LM,
832 .xlevel = 0x8000000A,
833 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
834 },
835 {
836 .name = "Nehalem",
837 .level = 4,
838 .vendor = CPUID_VENDOR_INTEL,
839 .family = 6,
840 .model = 26,
841 .stepping = 3,
842 .features[FEAT_1_EDX] =
843 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
844 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
845 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
846 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
847 CPUID_DE | CPUID_FP87,
848 .features[FEAT_1_ECX] =
849 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
850 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
851 .features[FEAT_8000_0001_EDX] =
852 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
853 .features[FEAT_8000_0001_ECX] =
854 CPUID_EXT3_LAHF_LM,
855 .xlevel = 0x8000000A,
856 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
857 },
858 {
859 .name = "Westmere",
860 .level = 11,
861 .vendor = CPUID_VENDOR_INTEL,
862 .family = 6,
863 .model = 44,
864 .stepping = 1,
865 .features[FEAT_1_EDX] =
866 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
867 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
868 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
869 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
870 CPUID_DE | CPUID_FP87,
871 .features[FEAT_1_ECX] =
872 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
873 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
874 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
875 .features[FEAT_8000_0001_EDX] =
876 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
877 .features[FEAT_8000_0001_ECX] =
878 CPUID_EXT3_LAHF_LM,
879 .xlevel = 0x8000000A,
880 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
881 },
882 {
883 .name = "SandyBridge",
884 .level = 0xd,
885 .vendor = CPUID_VENDOR_INTEL,
886 .family = 6,
887 .model = 42,
888 .stepping = 1,
889 .features[FEAT_1_EDX] =
890 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
891 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
892 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
893 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
894 CPUID_DE | CPUID_FP87,
895 .features[FEAT_1_ECX] =
896 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
897 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
898 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
899 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
900 CPUID_EXT_SSE3,
901 .features[FEAT_8000_0001_EDX] =
902 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
903 CPUID_EXT2_SYSCALL,
904 .features[FEAT_8000_0001_ECX] =
905 CPUID_EXT3_LAHF_LM,
906 .xlevel = 0x8000000A,
907 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
908 },
909 {
910 .name = "Haswell",
911 .level = 0xd,
912 .vendor = CPUID_VENDOR_INTEL,
913 .family = 6,
914 .model = 60,
915 .stepping = 1,
916 .features[FEAT_1_EDX] =
917 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
918 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
919 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
920 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
921 CPUID_DE | CPUID_FP87,
922 .features[FEAT_1_ECX] =
923 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
924 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
925 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
926 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
927 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
928 CPUID_EXT_PCID,
929 .features[FEAT_8000_0001_EDX] =
930 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
931 CPUID_EXT2_SYSCALL,
932 .features[FEAT_8000_0001_ECX] =
933 CPUID_EXT3_LAHF_LM,
934 .features[FEAT_7_0_EBX] =
935 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
936 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
937 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
938 CPUID_7_0_EBX_RTM,
939 .xlevel = 0x8000000A,
940 .model_id = "Intel Core Processor (Haswell)",
941 },
942 {
943 .name = "Opteron_G1",
944 .level = 5,
945 .vendor = CPUID_VENDOR_AMD,
946 .family = 15,
947 .model = 6,
948 .stepping = 1,
949 .features[FEAT_1_EDX] =
950 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
951 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
952 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
953 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
954 CPUID_DE | CPUID_FP87,
955 .features[FEAT_1_ECX] =
956 CPUID_EXT_SSE3,
957 .features[FEAT_8000_0001_EDX] =
958 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
959 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
960 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
961 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
962 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
963 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
964 .xlevel = 0x80000008,
965 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
966 },
967 {
968 .name = "Opteron_G2",
969 .level = 5,
970 .vendor = CPUID_VENDOR_AMD,
971 .family = 15,
972 .model = 6,
973 .stepping = 1,
974 .features[FEAT_1_EDX] =
975 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
976 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
977 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
978 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
979 CPUID_DE | CPUID_FP87,
980 .features[FEAT_1_ECX] =
981 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
982 .features[FEAT_8000_0001_EDX] =
983 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
984 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
985 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
986 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
987 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
988 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
989 CPUID_EXT2_DE | CPUID_EXT2_FPU,
990 .features[FEAT_8000_0001_ECX] =
991 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
992 .xlevel = 0x80000008,
993 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
994 },
995 {
996 .name = "Opteron_G3",
997 .level = 5,
998 .vendor = CPUID_VENDOR_AMD,
999 .family = 15,
1000 .model = 6,
1001 .stepping = 1,
1002 .features[FEAT_1_EDX] =
1003 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1004 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1005 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1006 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1007 CPUID_DE | CPUID_FP87,
1008 .features[FEAT_1_ECX] =
1009 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
1010 CPUID_EXT_SSE3,
1011 .features[FEAT_8000_0001_EDX] =
1012 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
1013 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1014 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1015 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1016 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1017 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1018 CPUID_EXT2_DE | CPUID_EXT2_FPU,
1019 .features[FEAT_8000_0001_ECX] =
1020 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
1021 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1022 .xlevel = 0x80000008,
1023 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1024 },
1025 {
1026 .name = "Opteron_G4",
1027 .level = 0xd,
1028 .vendor = CPUID_VENDOR_AMD,
1029 .family = 21,
1030 .model = 1,
1031 .stepping = 2,
1032 .features[FEAT_1_EDX] =
1033 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1034 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1035 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1036 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1037 CPUID_DE | CPUID_FP87,
1038 .features[FEAT_1_ECX] =
1039 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1040 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1041 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1042 CPUID_EXT_SSE3,
1043 .features[FEAT_8000_0001_EDX] =
1044 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
1045 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1046 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1047 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1048 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1049 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1050 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1051 .features[FEAT_8000_0001_ECX] =
1052 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
1053 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1054 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1055 CPUID_EXT3_LAHF_LM,
1056 .xlevel = 0x8000001A,
1057 .model_id = "AMD Opteron 62xx class CPU",
1058 },
1059 {
1060 .name = "Opteron_G5",
1061 .level = 0xd,
1062 .vendor = CPUID_VENDOR_AMD,
1063 .family = 21,
1064 .model = 2,
1065 .stepping = 0,
1066 .features[FEAT_1_EDX] =
1067 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1068 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1069 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1070 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1071 CPUID_DE | CPUID_FP87,
1072 .features[FEAT_1_ECX] =
1073 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
1074 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1075 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1076 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1077 .features[FEAT_8000_0001_EDX] =
1078 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
1079 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1080 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1081 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1082 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1083 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1084 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1085 .features[FEAT_8000_0001_ECX] =
1086 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
1087 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1088 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1089 CPUID_EXT3_LAHF_LM,
1090 .xlevel = 0x8000001A,
1091 .model_id = "AMD Opteron 63xx class CPU",
1092 },
1093 };
1094
1095 /**
1096 * x86_cpu_compat_set_features:
1097 * @cpu_model: CPU model name to be changed. If NULL, all CPU models are changed
1098 * @w: Identifies the feature word to be changed.
1099 * @feat_add: Feature bits to be added to feature word
1100 * @feat_remove: Feature bits to be removed from feature word
1101 *
1102 * Change CPU model feature bits for compatibility.
1103 *
1104 * This function may be used by machine-type compatibility functions
1105 * to enable or disable feature bits on specific CPU models.
1106 */
1107 void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w,
1108 uint32_t feat_add, uint32_t feat_remove)
1109 {
1110 x86_def_t *def;
1111 int i;
1112 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1113 def = &builtin_x86_defs[i];
1114 if (!cpu_model || !strcmp(cpu_model, def->name)) {
1115 def->features[w] |= feat_add;
1116 def->features[w] &= ~feat_remove;
1117 }
1118 }
1119 }
1120
1121 #ifdef CONFIG_KVM
1122 static int cpu_x86_fill_model_id(char *str)
1123 {
1124 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1125 int i;
1126
1127 for (i = 0; i < 3; i++) {
1128 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1129 memcpy(str + i * 16 + 0, &eax, 4);
1130 memcpy(str + i * 16 + 4, &ebx, 4);
1131 memcpy(str + i * 16 + 8, &ecx, 4);
1132 memcpy(str + i * 16 + 12, &edx, 4);
1133 }
1134 return 0;
1135 }
1136 #endif
1137
1138 /* Fill a x86_def_t struct with information about the host CPU, and
1139 * the CPU features supported by the host hardware + host kernel
1140 *
1141 * This function may be called only if KVM is enabled.
1142 */
1143 static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def)
1144 {
1145 #ifdef CONFIG_KVM
1146 KVMState *s = kvm_state;
1147 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1148
1149 assert(kvm_enabled());
1150
1151 x86_cpu_def->name = "host";
1152 x86_cpu_def->cache_info_passthrough = true;
1153 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1154 x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx);
1155
1156 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1157 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1158 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1159 x86_cpu_def->stepping = eax & 0x0F;
1160
1161 x86_cpu_def->level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1162 x86_cpu_def->features[FEAT_1_EDX] =
1163 kvm_arch_get_supported_cpuid(s, 0x1, 0, R_EDX);
1164 x86_cpu_def->features[FEAT_1_ECX] =
1165 kvm_arch_get_supported_cpuid(s, 0x1, 0, R_ECX);
1166
1167 if (x86_cpu_def->level >= 7) {
1168 x86_cpu_def->features[FEAT_7_0_EBX] =
1169 kvm_arch_get_supported_cpuid(s, 0x7, 0, R_EBX);
1170 } else {
1171 x86_cpu_def->features[FEAT_7_0_EBX] = 0;
1172 }
1173
1174 x86_cpu_def->xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1175 x86_cpu_def->features[FEAT_8000_0001_EDX] =
1176 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
1177 x86_cpu_def->features[FEAT_8000_0001_ECX] =
1178 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
1179
1180 cpu_x86_fill_model_id(x86_cpu_def->model_id);
1181
1182 /* Call Centaur's CPUID instruction. */
1183 if (!strcmp(x86_cpu_def->vendor, CPUID_VENDOR_VIA)) {
1184 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
1185 eax = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
1186 if (eax >= 0xC0000001) {
1187 /* Support VIA max extended level */
1188 x86_cpu_def->xlevel2 = eax;
1189 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
1190 x86_cpu_def->features[FEAT_C000_0001_EDX] =
1191 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
1192 }
1193 }
1194
1195 /* Other KVM-specific feature fields: */
1196 x86_cpu_def->features[FEAT_SVM] =
1197 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
1198 x86_cpu_def->features[FEAT_KVM] =
1199 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
1200
1201 #endif /* CONFIG_KVM */
1202 }
1203
1204 static int unavailable_host_feature(FeatureWordInfo *f, uint32_t mask)
1205 {
1206 int i;
1207
1208 for (i = 0; i < 32; ++i)
1209 if (1 << i & mask) {
1210 const char *reg = get_register_name_32(f->cpuid_reg);
1211 assert(reg);
1212 fprintf(stderr, "warning: host doesn't support requested feature: "
1213 "CPUID.%02XH:%s%s%s [bit %d]\n",
1214 f->cpuid_eax, reg,
1215 f->feat_names[i] ? "." : "",
1216 f->feat_names[i] ? f->feat_names[i] : "", i);
1217 break;
1218 }
1219 return 0;
1220 }
1221
1222 /* Check if all requested cpu flags are making their way to the guest
1223 *
1224 * Returns 0 if all flags are supported by the host, non-zero otherwise.
1225 *
1226 * This function may be called only if KVM is enabled.
1227 */
1228 static int kvm_check_features_against_host(X86CPU *cpu)
1229 {
1230 CPUX86State *env = &cpu->env;
1231 x86_def_t host_def;
1232 uint32_t mask;
1233 int rv, i;
1234 struct model_features_t ft[] = {
1235 {&env->features[FEAT_1_EDX],
1236 &host_def.features[FEAT_1_EDX],
1237 FEAT_1_EDX },
1238 {&env->features[FEAT_1_ECX],
1239 &host_def.features[FEAT_1_ECX],
1240 FEAT_1_ECX },
1241 {&env->features[FEAT_8000_0001_EDX],
1242 &host_def.features[FEAT_8000_0001_EDX],
1243 FEAT_8000_0001_EDX },
1244 {&env->features[FEAT_8000_0001_ECX],
1245 &host_def.features[FEAT_8000_0001_ECX],
1246 FEAT_8000_0001_ECX },
1247 {&env->features[FEAT_C000_0001_EDX],
1248 &host_def.features[FEAT_C000_0001_EDX],
1249 FEAT_C000_0001_EDX },
1250 {&env->features[FEAT_7_0_EBX],
1251 &host_def.features[FEAT_7_0_EBX],
1252 FEAT_7_0_EBX },
1253 {&env->features[FEAT_SVM],
1254 &host_def.features[FEAT_SVM],
1255 FEAT_SVM },
1256 {&env->features[FEAT_KVM],
1257 &host_def.features[FEAT_KVM],
1258 FEAT_KVM },
1259 };
1260
1261 assert(kvm_enabled());
1262
1263 kvm_cpu_fill_host(&host_def);
1264 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i) {
1265 FeatureWord w = ft[i].feat_word;
1266 FeatureWordInfo *wi = &feature_word_info[w];
1267 for (mask = 1; mask; mask <<= 1) {
1268 if (*ft[i].guest_feat & mask &&
1269 !(*ft[i].host_feat & mask)) {
1270 unavailable_host_feature(wi, mask);
1271 rv = 1;
1272 }
1273 }
1274 }
1275 return rv;
1276 }
1277
1278 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1279 const char *name, Error **errp)
1280 {
1281 X86CPU *cpu = X86_CPU(obj);
1282 CPUX86State *env = &cpu->env;
1283 int64_t value;
1284
1285 value = (env->cpuid_version >> 8) & 0xf;
1286 if (value == 0xf) {
1287 value += (env->cpuid_version >> 20) & 0xff;
1288 }
1289 visit_type_int(v, &value, name, errp);
1290 }
1291
1292 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1293 const char *name, Error **errp)
1294 {
1295 X86CPU *cpu = X86_CPU(obj);
1296 CPUX86State *env = &cpu->env;
1297 const int64_t min = 0;
1298 const int64_t max = 0xff + 0xf;
1299 int64_t value;
1300
1301 visit_type_int(v, &value, name, errp);
1302 if (error_is_set(errp)) {
1303 return;
1304 }
1305 if (value < min || value > max) {
1306 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1307 name ? name : "null", value, min, max);
1308 return;
1309 }
1310
1311 env->cpuid_version &= ~0xff00f00;
1312 if (value > 0x0f) {
1313 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
1314 } else {
1315 env->cpuid_version |= value << 8;
1316 }
1317 }
1318
1319 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1320 const char *name, Error **errp)
1321 {
1322 X86CPU *cpu = X86_CPU(obj);
1323 CPUX86State *env = &cpu->env;
1324 int64_t value;
1325
1326 value = (env->cpuid_version >> 4) & 0xf;
1327 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1328 visit_type_int(v, &value, name, errp);
1329 }
1330
1331 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1332 const char *name, Error **errp)
1333 {
1334 X86CPU *cpu = X86_CPU(obj);
1335 CPUX86State *env = &cpu->env;
1336 const int64_t min = 0;
1337 const int64_t max = 0xff;
1338 int64_t value;
1339
1340 visit_type_int(v, &value, name, errp);
1341 if (error_is_set(errp)) {
1342 return;
1343 }
1344 if (value < min || value > max) {
1345 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1346 name ? name : "null", value, min, max);
1347 return;
1348 }
1349
1350 env->cpuid_version &= ~0xf00f0;
1351 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
1352 }
1353
1354 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1355 void *opaque, const char *name,
1356 Error **errp)
1357 {
1358 X86CPU *cpu = X86_CPU(obj);
1359 CPUX86State *env = &cpu->env;
1360 int64_t value;
1361
1362 value = env->cpuid_version & 0xf;
1363 visit_type_int(v, &value, name, errp);
1364 }
1365
1366 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1367 void *opaque, const char *name,
1368 Error **errp)
1369 {
1370 X86CPU *cpu = X86_CPU(obj);
1371 CPUX86State *env = &cpu->env;
1372 const int64_t min = 0;
1373 const int64_t max = 0xf;
1374 int64_t value;
1375
1376 visit_type_int(v, &value, name, errp);
1377 if (error_is_set(errp)) {
1378 return;
1379 }
1380 if (value < min || value > max) {
1381 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1382 name ? name : "null", value, min, max);
1383 return;
1384 }
1385
1386 env->cpuid_version &= ~0xf;
1387 env->cpuid_version |= value & 0xf;
1388 }
1389
1390 static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1391 const char *name, Error **errp)
1392 {
1393 X86CPU *cpu = X86_CPU(obj);
1394
1395 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1396 }
1397
1398 static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1399 const char *name, Error **errp)
1400 {
1401 X86CPU *cpu = X86_CPU(obj);
1402
1403 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1404 }
1405
1406 static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1407 const char *name, Error **errp)
1408 {
1409 X86CPU *cpu = X86_CPU(obj);
1410
1411 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1412 }
1413
1414 static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1415 const char *name, Error **errp)
1416 {
1417 X86CPU *cpu = X86_CPU(obj);
1418
1419 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1420 }
1421
1422 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1423 {
1424 X86CPU *cpu = X86_CPU(obj);
1425 CPUX86State *env = &cpu->env;
1426 char *value;
1427
1428 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
1429 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1430 env->cpuid_vendor3);
1431 return value;
1432 }
1433
1434 static void x86_cpuid_set_vendor(Object *obj, const char *value,
1435 Error **errp)
1436 {
1437 X86CPU *cpu = X86_CPU(obj);
1438 CPUX86State *env = &cpu->env;
1439 int i;
1440
1441 if (strlen(value) != CPUID_VENDOR_SZ) {
1442 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1443 "vendor", value);
1444 return;
1445 }
1446
1447 env->cpuid_vendor1 = 0;
1448 env->cpuid_vendor2 = 0;
1449 env->cpuid_vendor3 = 0;
1450 for (i = 0; i < 4; i++) {
1451 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1452 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1453 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1454 }
1455 }
1456
1457 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1458 {
1459 X86CPU *cpu = X86_CPU(obj);
1460 CPUX86State *env = &cpu->env;
1461 char *value;
1462 int i;
1463
1464 value = g_malloc(48 + 1);
1465 for (i = 0; i < 48; i++) {
1466 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1467 }
1468 value[48] = '\0';
1469 return value;
1470 }
1471
1472 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1473 Error **errp)
1474 {
1475 X86CPU *cpu = X86_CPU(obj);
1476 CPUX86State *env = &cpu->env;
1477 int c, len, i;
1478
1479 if (model_id == NULL) {
1480 model_id = "";
1481 }
1482 len = strlen(model_id);
1483 memset(env->cpuid_model, 0, 48);
1484 for (i = 0; i < 48; i++) {
1485 if (i >= len) {
1486 c = '\0';
1487 } else {
1488 c = (uint8_t)model_id[i];
1489 }
1490 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1491 }
1492 }
1493
1494 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1495 const char *name, Error **errp)
1496 {
1497 X86CPU *cpu = X86_CPU(obj);
1498 int64_t value;
1499
1500 value = cpu->env.tsc_khz * 1000;
1501 visit_type_int(v, &value, name, errp);
1502 }
1503
1504 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1505 const char *name, Error **errp)
1506 {
1507 X86CPU *cpu = X86_CPU(obj);
1508 const int64_t min = 0;
1509 const int64_t max = INT64_MAX;
1510 int64_t value;
1511
1512 visit_type_int(v, &value, name, errp);
1513 if (error_is_set(errp)) {
1514 return;
1515 }
1516 if (value < min || value > max) {
1517 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1518 name ? name : "null", value, min, max);
1519 return;
1520 }
1521
1522 cpu->env.tsc_khz = value / 1000;
1523 }
1524
1525 static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
1526 const char *name, Error **errp)
1527 {
1528 X86CPU *cpu = X86_CPU(obj);
1529 int64_t value = cpu->env.cpuid_apic_id;
1530
1531 visit_type_int(v, &value, name, errp);
1532 }
1533
1534 static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque,
1535 const char *name, Error **errp)
1536 {
1537 X86CPU *cpu = X86_CPU(obj);
1538 DeviceState *dev = DEVICE(obj);
1539 const int64_t min = 0;
1540 const int64_t max = UINT32_MAX;
1541 Error *error = NULL;
1542 int64_t value;
1543
1544 if (dev->realized) {
1545 error_setg(errp, "Attempt to set property '%s' on '%s' after "
1546 "it was realized", name, object_get_typename(obj));
1547 return;
1548 }
1549
1550 visit_type_int(v, &value, name, &error);
1551 if (error) {
1552 error_propagate(errp, error);
1553 return;
1554 }
1555 if (value < min || value > max) {
1556 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1557 " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1558 object_get_typename(obj), name, value, min, max);
1559 return;
1560 }
1561
1562 if ((value != cpu->env.cpuid_apic_id) && cpu_exists(value)) {
1563 error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1564 return;
1565 }
1566 cpu->env.cpuid_apic_id = value;
1567 }
1568
1569 /* Generic getter for "feature-words" and "filtered-features" properties */
1570 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, void *opaque,
1571 const char *name, Error **errp)
1572 {
1573 uint32_t *array = (uint32_t *)opaque;
1574 FeatureWord w;
1575 Error *err = NULL;
1576 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1577 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1578 X86CPUFeatureWordInfoList *list = NULL;
1579
1580 for (w = 0; w < FEATURE_WORDS; w++) {
1581 FeatureWordInfo *wi = &feature_word_info[w];
1582 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1583 qwi->cpuid_input_eax = wi->cpuid_eax;
1584 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1585 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1586 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
1587 qwi->features = array[w];
1588
1589 /* List will be in reverse order, but order shouldn't matter */
1590 list_entries[w].next = list;
1591 list_entries[w].value = &word_infos[w];
1592 list = &list_entries[w];
1593 }
1594
1595 visit_type_X86CPUFeatureWordInfoList(v, &list, "feature-words", &err);
1596 error_propagate(errp, err);
1597 }
1598
1599 static int cpu_x86_find_by_name(X86CPU *cpu, x86_def_t *x86_cpu_def,
1600 const char *name)
1601 {
1602 x86_def_t *def;
1603 Error *err = NULL;
1604 int i;
1605
1606 if (name == NULL) {
1607 return -1;
1608 }
1609 if (kvm_enabled() && strcmp(name, "host") == 0) {
1610 kvm_cpu_fill_host(x86_cpu_def);
1611 object_property_set_bool(OBJECT(cpu), true, "pmu", &err);
1612 assert_no_error(err);
1613 return 0;
1614 }
1615
1616 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1617 def = &builtin_x86_defs[i];
1618 if (strcmp(name, def->name) == 0) {
1619 memcpy(x86_cpu_def, def, sizeof(*def));
1620 /* sysenter isn't supported in compatibility mode on AMD,
1621 * syscall isn't supported in compatibility mode on Intel.
1622 * Normally we advertise the actual CPU vendor, but you can
1623 * override this using the 'vendor' property if you want to use
1624 * KVM's sysenter/syscall emulation in compatibility mode and
1625 * when doing cross vendor migration
1626 */
1627 if (kvm_enabled()) {
1628 uint32_t ebx = 0, ecx = 0, edx = 0;
1629 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
1630 x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx);
1631 }
1632 return 0;
1633 }
1634 }
1635
1636 return -1;
1637 }
1638
1639 /* Convert all '_' in a feature string option name to '-', to make feature
1640 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1641 */
1642 static inline void feat2prop(char *s)
1643 {
1644 while ((s = strchr(s, '_'))) {
1645 *s = '-';
1646 }
1647 }
1648
1649 /* Parse "+feature,-feature,feature=foo" CPU feature string
1650 */
1651 static void cpu_x86_parse_featurestr(X86CPU *cpu, char *features, Error **errp)
1652 {
1653 char *featurestr; /* Single 'key=value" string being parsed */
1654 /* Features to be added */
1655 FeatureWordArray plus_features = { 0 };
1656 /* Features to be removed */
1657 FeatureWordArray minus_features = { 0 };
1658 uint32_t numvalue;
1659 CPUX86State *env = &cpu->env;
1660
1661 featurestr = features ? strtok(features, ",") : NULL;
1662
1663 while (featurestr) {
1664 char *val;
1665 if (featurestr[0] == '+') {
1666 add_flagname_to_bitmaps(featurestr + 1, plus_features);
1667 } else if (featurestr[0] == '-') {
1668 add_flagname_to_bitmaps(featurestr + 1, minus_features);
1669 } else if ((val = strchr(featurestr, '='))) {
1670 *val = 0; val++;
1671 feat2prop(featurestr);
1672 if (!strcmp(featurestr, "family")) {
1673 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1674 } else if (!strcmp(featurestr, "model")) {
1675 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1676 } else if (!strcmp(featurestr, "stepping")) {
1677 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1678 } else if (!strcmp(featurestr, "level")) {
1679 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1680 } else if (!strcmp(featurestr, "xlevel")) {
1681 char *err;
1682 char num[32];
1683
1684 numvalue = strtoul(val, &err, 0);
1685 if (!*val || *err) {
1686 error_setg(errp, "bad numerical value %s", val);
1687 goto out;
1688 }
1689 if (numvalue < 0x80000000) {
1690 fprintf(stderr, "xlevel value shall always be >= 0x80000000"
1691 ", fixup will be removed in future versions\n");
1692 numvalue += 0x80000000;
1693 }
1694 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
1695 object_property_parse(OBJECT(cpu), num, featurestr, errp);
1696 } else if (!strcmp(featurestr, "vendor")) {
1697 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1698 } else if (!strcmp(featurestr, "model-id")) {
1699 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1700 } else if (!strcmp(featurestr, "tsc-freq")) {
1701 int64_t tsc_freq;
1702 char *err;
1703 char num[32];
1704
1705 tsc_freq = strtosz_suffix_unit(val, &err,
1706 STRTOSZ_DEFSUFFIX_B, 1000);
1707 if (tsc_freq < 0 || *err) {
1708 error_setg(errp, "bad numerical value %s", val);
1709 goto out;
1710 }
1711 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
1712 object_property_parse(OBJECT(cpu), num, "tsc-frequency", errp);
1713 } else if (!strcmp(featurestr, "hv-spinlocks")) {
1714 char *err;
1715 const int min = 0xFFF;
1716 numvalue = strtoul(val, &err, 0);
1717 if (!*val || *err) {
1718 error_setg(errp, "bad numerical value %s", val);
1719 goto out;
1720 }
1721 if (numvalue < min) {
1722 fprintf(stderr, "hv-spinlocks value shall always be >= 0x%x"
1723 ", fixup will be removed in future versions\n",
1724 min);
1725 numvalue = min;
1726 }
1727 cpu->hyperv_spinlock_attempts = numvalue;
1728 } else {
1729 error_setg(errp, "unrecognized feature %s", featurestr);
1730 goto out;
1731 }
1732 } else if (!strcmp(featurestr, "check")) {
1733 check_cpuid = 1;
1734 } else if (!strcmp(featurestr, "enforce")) {
1735 check_cpuid = enforce_cpuid = 1;
1736 } else if (!strcmp(featurestr, "hv_relaxed")) {
1737 cpu->hyperv_relaxed_timing = true;
1738 } else if (!strcmp(featurestr, "hv_vapic")) {
1739 cpu->hyperv_vapic = true;
1740 } else {
1741 error_setg(errp, "feature string `%s' not in format (+feature|"
1742 "-feature|feature=xyz)", featurestr);
1743 goto out;
1744 }
1745 if (error_is_set(errp)) {
1746 goto out;
1747 }
1748 featurestr = strtok(NULL, ",");
1749 }
1750 env->features[FEAT_1_EDX] |= plus_features[FEAT_1_EDX];
1751 env->features[FEAT_1_ECX] |= plus_features[FEAT_1_ECX];
1752 env->features[FEAT_8000_0001_EDX] |= plus_features[FEAT_8000_0001_EDX];
1753 env->features[FEAT_8000_0001_ECX] |= plus_features[FEAT_8000_0001_ECX];
1754 env->features[FEAT_C000_0001_EDX] |= plus_features[FEAT_C000_0001_EDX];
1755 env->features[FEAT_KVM] |= plus_features[FEAT_KVM];
1756 env->features[FEAT_SVM] |= plus_features[FEAT_SVM];
1757 env->features[FEAT_7_0_EBX] |= plus_features[FEAT_7_0_EBX];
1758 env->features[FEAT_1_EDX] &= ~minus_features[FEAT_1_EDX];
1759 env->features[FEAT_1_ECX] &= ~minus_features[FEAT_1_ECX];
1760 env->features[FEAT_8000_0001_EDX] &= ~minus_features[FEAT_8000_0001_EDX];
1761 env->features[FEAT_8000_0001_ECX] &= ~minus_features[FEAT_8000_0001_ECX];
1762 env->features[FEAT_C000_0001_EDX] &= ~minus_features[FEAT_C000_0001_EDX];
1763 env->features[FEAT_KVM] &= ~minus_features[FEAT_KVM];
1764 env->features[FEAT_SVM] &= ~minus_features[FEAT_SVM];
1765 env->features[FEAT_7_0_EBX] &= ~minus_features[FEAT_7_0_EBX];
1766
1767 out:
1768 return;
1769 }
1770
1771 /* generate a composite string into buf of all cpuid names in featureset
1772 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1773 * if flags, suppress names undefined in featureset.
1774 */
1775 static void listflags(char *buf, int bufsize, uint32_t fbits,
1776 const char **featureset, uint32_t flags)
1777 {
1778 const char **p = &featureset[31];
1779 char *q, *b, bit;
1780 int nc;
1781
1782 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1783 *buf = '\0';
1784 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1785 if (fbits & 1 << bit && (*p || !flags)) {
1786 if (*p)
1787 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1788 else
1789 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1790 if (bufsize <= nc) {
1791 if (b) {
1792 memcpy(b, "...", sizeof("..."));
1793 }
1794 return;
1795 }
1796 q += nc;
1797 bufsize -= nc;
1798 }
1799 }
1800
1801 /* generate CPU information. */
1802 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1803 {
1804 x86_def_t *def;
1805 char buf[256];
1806 int i;
1807
1808 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1809 def = &builtin_x86_defs[i];
1810 snprintf(buf, sizeof(buf), "%s", def->name);
1811 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
1812 }
1813 #ifdef CONFIG_KVM
1814 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
1815 "KVM processor with all supported host features "
1816 "(only available in KVM mode)");
1817 #endif
1818
1819 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1820 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
1821 FeatureWordInfo *fw = &feature_word_info[i];
1822
1823 listflags(buf, sizeof(buf), (uint32_t)~0, fw->feat_names, 1);
1824 (*cpu_fprintf)(f, " %s\n", buf);
1825 }
1826 }
1827
1828 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
1829 {
1830 CpuDefinitionInfoList *cpu_list = NULL;
1831 x86_def_t *def;
1832 int i;
1833
1834 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1835 CpuDefinitionInfoList *entry;
1836 CpuDefinitionInfo *info;
1837
1838 def = &builtin_x86_defs[i];
1839 info = g_malloc0(sizeof(*info));
1840 info->name = g_strdup(def->name);
1841
1842 entry = g_malloc0(sizeof(*entry));
1843 entry->value = info;
1844 entry->next = cpu_list;
1845 cpu_list = entry;
1846 }
1847
1848 return cpu_list;
1849 }
1850
1851 #ifdef CONFIG_KVM
1852 static void filter_features_for_kvm(X86CPU *cpu)
1853 {
1854 CPUX86State *env = &cpu->env;
1855 KVMState *s = kvm_state;
1856 FeatureWord w;
1857
1858 for (w = 0; w < FEATURE_WORDS; w++) {
1859 FeatureWordInfo *wi = &feature_word_info[w];
1860 uint32_t host_feat = kvm_arch_get_supported_cpuid(s, wi->cpuid_eax,
1861 wi->cpuid_ecx,
1862 wi->cpuid_reg);
1863 uint32_t requested_features = env->features[w];
1864 env->features[w] &= host_feat;
1865 cpu->filtered_features[w] = requested_features & ~env->features[w];
1866 }
1867 }
1868 #endif
1869
1870 static void cpu_x86_register(X86CPU *cpu, const char *name, Error **errp)
1871 {
1872 CPUX86State *env = &cpu->env;
1873 x86_def_t def1, *def = &def1;
1874
1875 memset(def, 0, sizeof(*def));
1876
1877 if (cpu_x86_find_by_name(cpu, def, name) < 0) {
1878 error_setg(errp, "Unable to find CPU definition: %s", name);
1879 return;
1880 }
1881
1882 if (kvm_enabled()) {
1883 def->features[FEAT_KVM] |= kvm_default_features;
1884 }
1885 def->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
1886
1887 object_property_set_str(OBJECT(cpu), def->vendor, "vendor", errp);
1888 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
1889 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
1890 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
1891 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
1892 env->features[FEAT_1_EDX] = def->features[FEAT_1_EDX];
1893 env->features[FEAT_1_ECX] = def->features[FEAT_1_ECX];
1894 env->features[FEAT_8000_0001_EDX] = def->features[FEAT_8000_0001_EDX];
1895 env->features[FEAT_8000_0001_ECX] = def->features[FEAT_8000_0001_ECX];
1896 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
1897 env->features[FEAT_KVM] = def->features[FEAT_KVM];
1898 env->features[FEAT_SVM] = def->features[FEAT_SVM];
1899 env->features[FEAT_C000_0001_EDX] = def->features[FEAT_C000_0001_EDX];
1900 env->features[FEAT_7_0_EBX] = def->features[FEAT_7_0_EBX];
1901 env->cpuid_xlevel2 = def->xlevel2;
1902 cpu->cache_info_passthrough = def->cache_info_passthrough;
1903
1904 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
1905 }
1906
1907 X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge,
1908 Error **errp)
1909 {
1910 X86CPU *cpu = NULL;
1911 gchar **model_pieces;
1912 char *name, *features;
1913 char *typename;
1914 Error *error = NULL;
1915
1916 model_pieces = g_strsplit(cpu_model, ",", 2);
1917 if (!model_pieces[0]) {
1918 error_setg(&error, "Invalid/empty CPU model name");
1919 goto out;
1920 }
1921 name = model_pieces[0];
1922 features = model_pieces[1];
1923
1924 cpu = X86_CPU(object_new(TYPE_X86_CPU));
1925 #ifndef CONFIG_USER_ONLY
1926 if (icc_bridge == NULL) {
1927 error_setg(&error, "Invalid icc-bridge value");
1928 goto out;
1929 }
1930 qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc"));
1931 object_unref(OBJECT(cpu));
1932 #endif
1933
1934 cpu_x86_register(cpu, name, &error);
1935 if (error) {
1936 goto out;
1937 }
1938
1939 /* Emulate per-model subclasses for global properties */
1940 typename = g_strdup_printf("%s-" TYPE_X86_CPU, name);
1941 qdev_prop_set_globals_for_type(DEVICE(cpu), typename, &error);
1942 g_free(typename);
1943 if (error) {
1944 goto out;
1945 }
1946
1947 cpu_x86_parse_featurestr(cpu, features, &error);
1948 if (error) {
1949 goto out;
1950 }
1951
1952 out:
1953 if (error != NULL) {
1954 error_propagate(errp, error);
1955 object_unref(OBJECT(cpu));
1956 cpu = NULL;
1957 }
1958 g_strfreev(model_pieces);
1959 return cpu;
1960 }
1961
1962 X86CPU *cpu_x86_init(const char *cpu_model)
1963 {
1964 Error *error = NULL;
1965 X86CPU *cpu;
1966
1967 cpu = cpu_x86_create(cpu_model, NULL, &error);
1968 if (error) {
1969 goto out;
1970 }
1971
1972 object_property_set_bool(OBJECT(cpu), true, "realized", &error);
1973
1974 out:
1975 if (error) {
1976 error_report("%s", error_get_pretty(error));
1977 error_free(error);
1978 if (cpu != NULL) {
1979 object_unref(OBJECT(cpu));
1980 cpu = NULL;
1981 }
1982 }
1983 return cpu;
1984 }
1985
1986 #if !defined(CONFIG_USER_ONLY)
1987
1988 void cpu_clear_apic_feature(CPUX86State *env)
1989 {
1990 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
1991 }
1992
1993 #endif /* !CONFIG_USER_ONLY */
1994
1995 /* Initialize list of CPU models, filling some non-static fields if necessary
1996 */
1997 void x86_cpudef_setup(void)
1998 {
1999 int i, j;
2000 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
2001
2002 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
2003 x86_def_t *def = &builtin_x86_defs[i];
2004
2005 /* Look for specific "cpudef" models that */
2006 /* have the QEMU version in .model_id */
2007 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
2008 if (strcmp(model_with_versions[j], def->name) == 0) {
2009 pstrcpy(def->model_id, sizeof(def->model_id),
2010 "QEMU Virtual CPU version ");
2011 pstrcat(def->model_id, sizeof(def->model_id),
2012 qemu_get_version());
2013 break;
2014 }
2015 }
2016 }
2017 }
2018
2019 static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
2020 uint32_t *ecx, uint32_t *edx)
2021 {
2022 *ebx = env->cpuid_vendor1;
2023 *edx = env->cpuid_vendor2;
2024 *ecx = env->cpuid_vendor3;
2025 }
2026
2027 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2028 uint32_t *eax, uint32_t *ebx,
2029 uint32_t *ecx, uint32_t *edx)
2030 {
2031 X86CPU *cpu = x86_env_get_cpu(env);
2032 CPUState *cs = CPU(cpu);
2033
2034 /* test if maximum index reached */
2035 if (index & 0x80000000) {
2036 if (index > env->cpuid_xlevel) {
2037 if (env->cpuid_xlevel2 > 0) {
2038 /* Handle the Centaur's CPUID instruction. */
2039 if (index > env->cpuid_xlevel2) {
2040 index = env->cpuid_xlevel2;
2041 } else if (index < 0xC0000000) {
2042 index = env->cpuid_xlevel;
2043 }
2044 } else {
2045 /* Intel documentation states that invalid EAX input will
2046 * return the same information as EAX=cpuid_level
2047 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2048 */
2049 index = env->cpuid_level;
2050 }
2051 }
2052 } else {
2053 if (index > env->cpuid_level)
2054 index = env->cpuid_level;
2055 }
2056
2057 switch(index) {
2058 case 0:
2059 *eax = env->cpuid_level;
2060 get_cpuid_vendor(env, ebx, ecx, edx);
2061 break;
2062 case 1:
2063 *eax = env->cpuid_version;
2064 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
2065 *ecx = env->features[FEAT_1_ECX];
2066 *edx = env->features[FEAT_1_EDX];
2067 if (cs->nr_cores * cs->nr_threads > 1) {
2068 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
2069 *edx |= 1 << 28; /* HTT bit */
2070 }
2071 break;
2072 case 2:
2073 /* cache info: needed for Pentium Pro compatibility */
2074 if (cpu->cache_info_passthrough) {
2075 host_cpuid(index, 0, eax, ebx, ecx, edx);
2076 break;
2077 }
2078 *eax = 1; /* Number of CPUID[EAX=2] calls required */
2079 *ebx = 0;
2080 *ecx = 0;
2081 *edx = (L1D_DESCRIPTOR << 16) | \
2082 (L1I_DESCRIPTOR << 8) | \
2083 (L2_DESCRIPTOR);
2084 break;
2085 case 4:
2086 /* cache info: needed for Core compatibility */
2087 if (cpu->cache_info_passthrough) {
2088 host_cpuid(index, count, eax, ebx, ecx, edx);
2089 *eax &= ~0xFC000000;
2090 } else {
2091 *eax = 0;
2092 switch (count) {
2093 case 0: /* L1 dcache info */
2094 *eax |= CPUID_4_TYPE_DCACHE | \
2095 CPUID_4_LEVEL(1) | \
2096 CPUID_4_SELF_INIT_LEVEL;
2097 *ebx = (L1D_LINE_SIZE - 1) | \
2098 ((L1D_PARTITIONS - 1) << 12) | \
2099 ((L1D_ASSOCIATIVITY - 1) << 22);
2100 *ecx = L1D_SETS - 1;
2101 *edx = CPUID_4_NO_INVD_SHARING;
2102 break;
2103 case 1: /* L1 icache info */
2104 *eax |= CPUID_4_TYPE_ICACHE | \
2105 CPUID_4_LEVEL(1) | \
2106 CPUID_4_SELF_INIT_LEVEL;
2107 *ebx = (L1I_LINE_SIZE - 1) | \
2108 ((L1I_PARTITIONS - 1) << 12) | \
2109 ((L1I_ASSOCIATIVITY - 1) << 22);
2110 *ecx = L1I_SETS - 1;
2111 *edx = CPUID_4_NO_INVD_SHARING;
2112 break;
2113 case 2: /* L2 cache info */
2114 *eax |= CPUID_4_TYPE_UNIFIED | \
2115 CPUID_4_LEVEL(2) | \
2116 CPUID_4_SELF_INIT_LEVEL;
2117 if (cs->nr_threads > 1) {
2118 *eax |= (cs->nr_threads - 1) << 14;
2119 }
2120 *ebx = (L2_LINE_SIZE - 1) | \
2121 ((L2_PARTITIONS - 1) << 12) | \
2122 ((L2_ASSOCIATIVITY - 1) << 22);
2123 *ecx = L2_SETS - 1;
2124 *edx = CPUID_4_NO_INVD_SHARING;
2125 break;
2126 default: /* end of info */
2127 *eax = 0;
2128 *ebx = 0;
2129 *ecx = 0;
2130 *edx = 0;
2131 break;
2132 }
2133 }
2134
2135 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2136 if ((*eax & 31) && cs->nr_cores > 1) {
2137 *eax |= (cs->nr_cores - 1) << 26;
2138 }
2139 break;
2140 case 5:
2141 /* mwait info: needed for Core compatibility */
2142 *eax = 0; /* Smallest monitor-line size in bytes */
2143 *ebx = 0; /* Largest monitor-line size in bytes */
2144 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2145 *edx = 0;
2146 break;
2147 case 6:
2148 /* Thermal and Power Leaf */
2149 *eax = 0;
2150 *ebx = 0;
2151 *ecx = 0;
2152 *edx = 0;
2153 break;
2154 case 7:
2155 /* Structured Extended Feature Flags Enumeration Leaf */
2156 if (count == 0) {
2157 *eax = 0; /* Maximum ECX value for sub-leaves */
2158 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
2159 *ecx = 0; /* Reserved */
2160 *edx = 0; /* Reserved */
2161 } else {
2162 *eax = 0;
2163 *ebx = 0;
2164 *ecx = 0;
2165 *edx = 0;
2166 }
2167 break;
2168 case 9:
2169 /* Direct Cache Access Information Leaf */
2170 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2171 *ebx = 0;
2172 *ecx = 0;
2173 *edx = 0;
2174 break;
2175 case 0xA:
2176 /* Architectural Performance Monitoring Leaf */
2177 if (kvm_enabled() && cpu->enable_pmu) {
2178 KVMState *s = cs->kvm_state;
2179
2180 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2181 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2182 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2183 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2184 } else {
2185 *eax = 0;
2186 *ebx = 0;
2187 *ecx = 0;
2188 *edx = 0;
2189 }
2190 break;
2191 case 0xD: {
2192 KVMState *s = cs->kvm_state;
2193 uint64_t kvm_mask;
2194 int i;
2195
2196 /* Processor Extended State */
2197 *eax = 0;
2198 *ebx = 0;
2199 *ecx = 0;
2200 *edx = 0;
2201 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) || !kvm_enabled()) {
2202 break;
2203 }
2204 kvm_mask =
2205 kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX) |
2206 ((uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32);
2207
2208 if (count == 0) {
2209 *ecx = 0x240;
2210 for (i = 2; i < ARRAY_SIZE(ext_save_areas); i++) {
2211 const ExtSaveArea *esa = &ext_save_areas[i];
2212 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2213 (kvm_mask & (1 << i)) != 0) {
2214 if (i < 32) {
2215 *eax |= 1 << i;
2216 } else {
2217 *edx |= 1 << (i - 32);
2218 }
2219 *ecx = MAX(*ecx, esa->offset + esa->size);
2220 }
2221 }
2222 *eax |= kvm_mask & (XSTATE_FP | XSTATE_SSE);
2223 *ebx = *ecx;
2224 } else if (count == 1) {
2225 *eax = kvm_arch_get_supported_cpuid(s, 0xd, 1, R_EAX);
2226 } else if (count < ARRAY_SIZE(ext_save_areas)) {
2227 const ExtSaveArea *esa = &ext_save_areas[count];
2228 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2229 (kvm_mask & (1 << count)) != 0) {
2230 *eax = esa->offset;
2231 *ebx = esa->size;
2232 }
2233 }
2234 break;
2235 }
2236 case 0x80000000:
2237 *eax = env->cpuid_xlevel;
2238 *ebx = env->cpuid_vendor1;
2239 *edx = env->cpuid_vendor2;
2240 *ecx = env->cpuid_vendor3;
2241 break;
2242 case 0x80000001:
2243 *eax = env->cpuid_version;
2244 *ebx = 0;
2245 *ecx = env->features[FEAT_8000_0001_ECX];
2246 *edx = env->features[FEAT_8000_0001_EDX];
2247
2248 /* The Linux kernel checks for the CMPLegacy bit and
2249 * discards multiple thread information if it is set.
2250 * So dont set it here for Intel to make Linux guests happy.
2251 */
2252 if (cs->nr_cores * cs->nr_threads > 1) {
2253 uint32_t tebx, tecx, tedx;
2254 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
2255 if (tebx != CPUID_VENDOR_INTEL_1 ||
2256 tedx != CPUID_VENDOR_INTEL_2 ||
2257 tecx != CPUID_VENDOR_INTEL_3) {
2258 *ecx |= 1 << 1; /* CmpLegacy bit */
2259 }
2260 }
2261 break;
2262 case 0x80000002:
2263 case 0x80000003:
2264 case 0x80000004:
2265 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2266 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2267 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2268 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2269 break;
2270 case 0x80000005:
2271 /* cache info (L1 cache) */
2272 if (cpu->cache_info_passthrough) {
2273 host_cpuid(index, 0, eax, ebx, ecx, edx);
2274 break;
2275 }
2276 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2277 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2278 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2279 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2280 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2281 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2282 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2283 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
2284 break;
2285 case 0x80000006:
2286 /* cache info (L2 cache) */
2287 if (cpu->cache_info_passthrough) {
2288 host_cpuid(index, 0, eax, ebx, ecx, edx);
2289 break;
2290 }
2291 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2292 (L2_DTLB_2M_ENTRIES << 16) | \
2293 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2294 (L2_ITLB_2M_ENTRIES);
2295 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2296 (L2_DTLB_4K_ENTRIES << 16) | \
2297 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2298 (L2_ITLB_4K_ENTRIES);
2299 *ecx = (L2_SIZE_KB_AMD << 16) | \
2300 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2301 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2302 *edx = ((L3_SIZE_KB/512) << 18) | \
2303 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2304 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
2305 break;
2306 case 0x80000008:
2307 /* virtual & phys address size in low 2 bytes. */
2308 /* XXX: This value must match the one used in the MMU code. */
2309 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
2310 /* 64 bit processor */
2311 /* XXX: The physical address space is limited to 42 bits in exec.c. */
2312 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
2313 } else {
2314 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
2315 *eax = 0x00000024; /* 36 bits physical */
2316 } else {
2317 *eax = 0x00000020; /* 32 bits physical */
2318 }
2319 }
2320 *ebx = 0;
2321 *ecx = 0;
2322 *edx = 0;
2323 if (cs->nr_cores * cs->nr_threads > 1) {
2324 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
2325 }
2326 break;
2327 case 0x8000000A:
2328 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
2329 *eax = 0x00000001; /* SVM Revision */
2330 *ebx = 0x00000010; /* nr of ASIDs */
2331 *ecx = 0;
2332 *edx = env->features[FEAT_SVM]; /* optional features */
2333 } else {
2334 *eax = 0;
2335 *ebx = 0;
2336 *ecx = 0;
2337 *edx = 0;
2338 }
2339 break;
2340 case 0xC0000000:
2341 *eax = env->cpuid_xlevel2;
2342 *ebx = 0;
2343 *ecx = 0;
2344 *edx = 0;
2345 break;
2346 case 0xC0000001:
2347 /* Support for VIA CPU's CPUID instruction */
2348 *eax = env->cpuid_version;
2349 *ebx = 0;
2350 *ecx = 0;
2351 *edx = env->features[FEAT_C000_0001_EDX];
2352 break;
2353 case 0xC0000002:
2354 case 0xC0000003:
2355 case 0xC0000004:
2356 /* Reserved for the future, and now filled with zero */
2357 *eax = 0;
2358 *ebx = 0;
2359 *ecx = 0;
2360 *edx = 0;
2361 break;
2362 default:
2363 /* reserved values: zero */
2364 *eax = 0;
2365 *ebx = 0;
2366 *ecx = 0;
2367 *edx = 0;
2368 break;
2369 }
2370 }
2371
2372 /* CPUClass::reset() */
2373 static void x86_cpu_reset(CPUState *s)
2374 {
2375 X86CPU *cpu = X86_CPU(s);
2376 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2377 CPUX86State *env = &cpu->env;
2378 int i;
2379
2380 xcc->parent_reset(s);
2381
2382
2383 memset(env, 0, offsetof(CPUX86State, breakpoints));
2384
2385 tlb_flush(env, 1);
2386
2387 env->old_exception = -1;
2388
2389 /* init to reset state */
2390
2391 #ifdef CONFIG_SOFTMMU
2392 env->hflags |= HF_SOFTMMU_MASK;
2393 #endif
2394 env->hflags2 |= HF2_GIF_MASK;
2395
2396 cpu_x86_update_cr0(env, 0x60000010);
2397 env->a20_mask = ~0x0;
2398 env->smbase = 0x30000;
2399
2400 env->idt.limit = 0xffff;
2401 env->gdt.limit = 0xffff;
2402 env->ldt.limit = 0xffff;
2403 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2404 env->tr.limit = 0xffff;
2405 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2406
2407 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2408 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2409 DESC_R_MASK | DESC_A_MASK);
2410 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2411 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2412 DESC_A_MASK);
2413 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2414 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2415 DESC_A_MASK);
2416 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2417 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2418 DESC_A_MASK);
2419 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2420 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2421 DESC_A_MASK);
2422 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2423 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2424 DESC_A_MASK);
2425
2426 env->eip = 0xfff0;
2427 env->regs[R_EDX] = env->cpuid_version;
2428
2429 env->eflags = 0x2;
2430
2431 /* FPU init */
2432 for (i = 0; i < 8; i++) {
2433 env->fptags[i] = 1;
2434 }
2435 env->fpuc = 0x37f;
2436
2437 env->mxcsr = 0x1f80;
2438 env->xstate_bv = XSTATE_FP | XSTATE_SSE;
2439
2440 env->pat = 0x0007040600070406ULL;
2441 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2442
2443 memset(env->dr, 0, sizeof(env->dr));
2444 env->dr[6] = DR6_FIXED_1;
2445 env->dr[7] = DR7_FIXED_1;
2446 cpu_breakpoint_remove_all(env, BP_CPU);
2447 cpu_watchpoint_remove_all(env, BP_CPU);
2448
2449 #if !defined(CONFIG_USER_ONLY)
2450 /* We hard-wire the BSP to the first CPU. */
2451 if (s->cpu_index == 0) {
2452 apic_designate_bsp(env->apic_state);
2453 }
2454
2455 s->halted = !cpu_is_bsp(cpu);
2456 #endif
2457 }
2458
2459 #ifndef CONFIG_USER_ONLY
2460 bool cpu_is_bsp(X86CPU *cpu)
2461 {
2462 return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
2463 }
2464
2465 /* TODO: remove me, when reset over QOM tree is implemented */
2466 static void x86_cpu_machine_reset_cb(void *opaque)
2467 {
2468 X86CPU *cpu = opaque;
2469 cpu_reset(CPU(cpu));
2470 }
2471 #endif
2472
2473 static void mce_init(X86CPU *cpu)
2474 {
2475 CPUX86State *cenv = &cpu->env;
2476 unsigned int bank;
2477
2478 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2479 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
2480 (CPUID_MCE | CPUID_MCA)) {
2481 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2482 cenv->mcg_ctl = ~(uint64_t)0;
2483 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2484 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2485 }
2486 }
2487 }
2488
2489 #ifndef CONFIG_USER_ONLY
2490 static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
2491 {
2492 CPUX86State *env = &cpu->env;
2493 DeviceState *dev = DEVICE(cpu);
2494 APICCommonState *apic;
2495 const char *apic_type = "apic";
2496
2497 if (kvm_irqchip_in_kernel()) {
2498 apic_type = "kvm-apic";
2499 } else if (xen_enabled()) {
2500 apic_type = "xen-apic";
2501 }
2502
2503 env->apic_state = qdev_try_create(qdev_get_parent_bus(dev), apic_type);
2504 if (env->apic_state == NULL) {
2505 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2506 return;
2507 }
2508
2509 object_property_add_child(OBJECT(cpu), "apic",
2510 OBJECT(env->apic_state), NULL);
2511 qdev_prop_set_uint8(env->apic_state, "id", env->cpuid_apic_id);
2512 /* TODO: convert to link<> */
2513 apic = APIC_COMMON(env->apic_state);
2514 apic->cpu = cpu;
2515 }
2516
2517 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2518 {
2519 CPUX86State *env = &cpu->env;
2520
2521 if (env->apic_state == NULL) {
2522 return;
2523 }
2524
2525 if (qdev_init(env->apic_state)) {
2526 error_setg(errp, "APIC device '%s' could not be initialized",
2527 object_get_typename(OBJECT(env->apic_state)));
2528 return;
2529 }
2530 }
2531 #else
2532 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2533 {
2534 }
2535 #endif
2536
2537 static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
2538 {
2539 CPUState *cs = CPU(dev);
2540 X86CPU *cpu = X86_CPU(dev);
2541 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
2542 CPUX86State *env = &cpu->env;
2543 Error *local_err = NULL;
2544
2545 if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
2546 env->cpuid_level = 7;
2547 }
2548
2549 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2550 * CPUID[1].EDX.
2551 */
2552 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2553 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2554 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
2555 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2556 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
2557 & CPUID_EXT2_AMD_ALIASES);
2558 }
2559
2560 if (!kvm_enabled()) {
2561 env->features[FEAT_1_EDX] &= TCG_FEATURES;
2562 env->features[FEAT_1_ECX] &= TCG_EXT_FEATURES;
2563 env->features[FEAT_8000_0001_EDX] &= (TCG_EXT2_FEATURES
2564 #ifdef TARGET_X86_64
2565 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
2566 #endif
2567 );
2568 env->features[FEAT_8000_0001_ECX] &= TCG_EXT3_FEATURES;
2569 env->features[FEAT_SVM] &= TCG_SVM_FEATURES;
2570 } else {
2571 if (check_cpuid && kvm_check_features_against_host(cpu)
2572 && enforce_cpuid) {
2573 error_setg(&local_err,
2574 "Host's CPU doesn't support requested features");
2575 goto out;
2576 }
2577 #ifdef CONFIG_KVM
2578 filter_features_for_kvm(cpu);
2579 #endif
2580 }
2581
2582 #ifndef CONFIG_USER_ONLY
2583 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
2584
2585 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
2586 x86_cpu_apic_create(cpu, &local_err);
2587 if (local_err != NULL) {
2588 goto out;
2589 }
2590 }
2591 #endif
2592
2593 mce_init(cpu);
2594 qemu_init_vcpu(cs);
2595
2596 x86_cpu_apic_realize(cpu, &local_err);
2597 if (local_err != NULL) {
2598 goto out;
2599 }
2600 cpu_reset(cs);
2601
2602 xcc->parent_realize(dev, &local_err);
2603 out:
2604 if (local_err != NULL) {
2605 error_propagate(errp, local_err);
2606 return;
2607 }
2608 }
2609
2610 /* Enables contiguous-apic-ID mode, for compatibility */
2611 static bool compat_apic_id_mode;
2612
2613 void enable_compat_apic_id_mode(void)
2614 {
2615 compat_apic_id_mode = true;
2616 }
2617
2618 /* Calculates initial APIC ID for a specific CPU index
2619 *
2620 * Currently we need to be able to calculate the APIC ID from the CPU index
2621 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2622 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2623 * all CPUs up to max_cpus.
2624 */
2625 uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2626 {
2627 uint32_t correct_id;
2628 static bool warned;
2629
2630 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
2631 if (compat_apic_id_mode) {
2632 if (cpu_index != correct_id && !warned) {
2633 error_report("APIC IDs set in compatibility mode, "
2634 "CPU topology won't match the configuration");
2635 warned = true;
2636 }
2637 return cpu_index;
2638 } else {
2639 return correct_id;
2640 }
2641 }
2642
2643 static void x86_cpu_initfn(Object *obj)
2644 {
2645 CPUState *cs = CPU(obj);
2646 X86CPU *cpu = X86_CPU(obj);
2647 CPUX86State *env = &cpu->env;
2648 static int inited;
2649
2650 cs->env_ptr = env;
2651 cpu_exec_init(env);
2652
2653 object_property_add(obj, "family", "int",
2654 x86_cpuid_version_get_family,
2655 x86_cpuid_version_set_family, NULL, NULL, NULL);
2656 object_property_add(obj, "model", "int",
2657 x86_cpuid_version_get_model,
2658 x86_cpuid_version_set_model, NULL, NULL, NULL);
2659 object_property_add(obj, "stepping", "int",
2660 x86_cpuid_version_get_stepping,
2661 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
2662 object_property_add(obj, "level", "int",
2663 x86_cpuid_get_level,
2664 x86_cpuid_set_level, NULL, NULL, NULL);
2665 object_property_add(obj, "xlevel", "int",
2666 x86_cpuid_get_xlevel,
2667 x86_cpuid_set_xlevel, NULL, NULL, NULL);
2668 object_property_add_str(obj, "vendor",
2669 x86_cpuid_get_vendor,
2670 x86_cpuid_set_vendor, NULL);
2671 object_property_add_str(obj, "model-id",
2672 x86_cpuid_get_model_id,
2673 x86_cpuid_set_model_id, NULL);
2674 object_property_add(obj, "tsc-frequency", "int",
2675 x86_cpuid_get_tsc_freq,
2676 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
2677 object_property_add(obj, "apic-id", "int",
2678 x86_cpuid_get_apic_id,
2679 x86_cpuid_set_apic_id, NULL, NULL, NULL);
2680 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
2681 x86_cpu_get_feature_words,
2682 NULL, NULL, (void *)env->features, NULL);
2683 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
2684 x86_cpu_get_feature_words,
2685 NULL, NULL, (void *)cpu->filtered_features, NULL);
2686
2687 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
2688 env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
2689
2690 /* init various static tables used in TCG mode */
2691 if (tcg_enabled() && !inited) {
2692 inited = 1;
2693 optimize_flags_init();
2694 #ifndef CONFIG_USER_ONLY
2695 cpu_set_debug_excp_handler(breakpoint_handler);
2696 #endif
2697 }
2698 }
2699
2700 static int64_t x86_cpu_get_arch_id(CPUState *cs)
2701 {
2702 X86CPU *cpu = X86_CPU(cs);
2703 CPUX86State *env = &cpu->env;
2704
2705 return env->cpuid_apic_id;
2706 }
2707
2708 static bool x86_cpu_get_paging_enabled(const CPUState *cs)
2709 {
2710 X86CPU *cpu = X86_CPU(cs);
2711
2712 return cpu->env.cr[0] & CR0_PG_MASK;
2713 }
2714
2715 static void x86_cpu_set_pc(CPUState *cs, vaddr value)
2716 {
2717 X86CPU *cpu = X86_CPU(cs);
2718
2719 cpu->env.eip = value;
2720 }
2721
2722 static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
2723 {
2724 X86CPU *cpu = X86_CPU(cs);
2725
2726 cpu->env.eip = tb->pc - tb->cs_base;
2727 }
2728
2729 static Property x86_cpu_properties[] = {
2730 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
2731 DEFINE_PROP_END_OF_LIST()
2732 };
2733
2734 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2735 {
2736 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2737 CPUClass *cc = CPU_CLASS(oc);
2738 DeviceClass *dc = DEVICE_CLASS(oc);
2739
2740 xcc->parent_realize = dc->realize;
2741 dc->realize = x86_cpu_realizefn;
2742 dc->bus_type = TYPE_ICC_BUS;
2743 dc->props = x86_cpu_properties;
2744
2745 xcc->parent_reset = cc->reset;
2746 cc->reset = x86_cpu_reset;
2747 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
2748
2749 cc->do_interrupt = x86_cpu_do_interrupt;
2750 cc->dump_state = x86_cpu_dump_state;
2751 cc->set_pc = x86_cpu_set_pc;
2752 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
2753 cc->gdb_read_register = x86_cpu_gdb_read_register;
2754 cc->gdb_write_register = x86_cpu_gdb_write_register;
2755 cc->get_arch_id = x86_cpu_get_arch_id;
2756 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
2757 #ifndef CONFIG_USER_ONLY
2758 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
2759 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
2760 cc->write_elf64_note = x86_cpu_write_elf64_note;
2761 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
2762 cc->write_elf32_note = x86_cpu_write_elf32_note;
2763 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
2764 cc->vmsd = &vmstate_x86_cpu;
2765 #endif
2766 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
2767 }
2768
2769 static const TypeInfo x86_cpu_type_info = {
2770 .name = TYPE_X86_CPU,
2771 .parent = TYPE_CPU,
2772 .instance_size = sizeof(X86CPU),
2773 .instance_init = x86_cpu_initfn,
2774 .abstract = false,
2775 .class_size = sizeof(X86CPUClass),
2776 .class_init = x86_cpu_common_class_init,
2777 };
2778
2779 static void x86_cpu_register_types(void)
2780 {
2781 type_register_static(&x86_cpu_type_info);
2782 }
2783
2784 type_init(x86_cpu_register_types)
Qemu copy for testing