4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
26 #include "qemu/host-utils.h"
28 #include "disas/disas.h"
35 #define PREFIX_REPZ 0x01
36 #define PREFIX_REPNZ 0x02
37 #define PREFIX_LOCK 0x04
38 #define PREFIX_DATA 0x08
39 #define PREFIX_ADR 0x10
42 #define CODE64(s) ((s)->code64)
43 #define REX_X(s) ((s)->rex_x)
44 #define REX_B(s) ((s)->rex_b)
59 //#define MACRO_TEST 1
61 /* global register indexes */
62 static TCGv_ptr cpu_env
;
64 static TCGv cpu_cc_src
, cpu_cc_dst
, cpu_cc_srcT
;
65 static TCGv_i32 cpu_cc_op
;
66 static TCGv cpu_regs
[CPU_NB_REGS
];
69 /* local register indexes (only used inside old micro ops) */
70 static TCGv cpu_tmp0
, cpu_tmp4
;
71 static TCGv_ptr cpu_ptr0
, cpu_ptr1
;
72 static TCGv_i32 cpu_tmp2_i32
, cpu_tmp3_i32
;
73 static TCGv_i64 cpu_tmp1_i64
;
76 static uint8_t gen_opc_cc_op
[OPC_BUF_SIZE
];
78 #include "exec/gen-icount.h"
81 static int x86_64_hregs
;
84 typedef struct DisasContext
{
85 /* current insn context */
86 int override
; /* -1 if no override */
89 target_ulong pc
; /* pc = eip + cs_base */
90 int is_jmp
; /* 1 = means jump (stop translation), 2 means CPU
91 static state change (stop translation) */
92 /* current block context */
93 target_ulong cs_base
; /* base of CS segment */
94 int pe
; /* protected mode */
95 int code32
; /* 32 bit code segment */
97 int lma
; /* long mode active */
98 int code64
; /* 64 bit code segment */
101 int ss32
; /* 32 bit stack segment */
102 CCOp cc_op
; /* current CC operation */
104 int addseg
; /* non zero if either DS/ES/SS have a non zero base */
105 int f_st
; /* currently unused */
106 int vm86
; /* vm86 mode */
109 int tf
; /* TF cpu flag */
110 int singlestep_enabled
; /* "hardware" single step enabled */
111 int jmp_opt
; /* use direct block chaining for direct jumps */
112 int mem_index
; /* select memory access functions */
113 uint64_t flags
; /* all execution flags */
114 struct TranslationBlock
*tb
;
115 int popl_esp_hack
; /* for correct popl with esp base handling */
116 int rip_offset
; /* only used in x86_64, but left for simplicity */
118 int cpuid_ext_features
;
119 int cpuid_ext2_features
;
120 int cpuid_ext3_features
;
121 int cpuid_7_0_ebx_features
;
124 static void gen_eob(DisasContext
*s
);
125 static void gen_jmp(DisasContext
*s
, target_ulong eip
);
126 static void gen_jmp_tb(DisasContext
*s
, target_ulong eip
, int tb_num
);
127 static void gen_op(DisasContext
*s1
, int op
, int ot
, int d
);
129 /* i386 arith/logic operations */
149 OP_SHL1
, /* undocumented */
173 /* I386 int registers */
174 OR_EAX
, /* MUST be even numbered */
183 OR_TMP0
= 16, /* temporary operand register */
185 OR_A0
, /* temporary register used when doing address evaluation */
194 /* Bit set if the global variable is live after setting CC_OP to X. */
195 static const uint8_t cc_op_live
[CC_OP_NB
] = {
196 [CC_OP_DYNAMIC
] = USES_CC_DST
| USES_CC_SRC
,
197 [CC_OP_EFLAGS
] = USES_CC_SRC
,
198 [CC_OP_MULB
... CC_OP_MULQ
] = USES_CC_DST
| USES_CC_SRC
,
199 [CC_OP_ADDB
... CC_OP_ADDQ
] = USES_CC_DST
| USES_CC_SRC
,
200 [CC_OP_ADCB
... CC_OP_ADCQ
] = USES_CC_DST
| USES_CC_SRC
,
201 [CC_OP_SUBB
... CC_OP_SUBQ
] = USES_CC_DST
| USES_CC_SRC
| USES_CC_SRCT
,
202 [CC_OP_SBBB
... CC_OP_SBBQ
] = USES_CC_DST
| USES_CC_SRC
,
203 [CC_OP_LOGICB
... CC_OP_LOGICQ
] = USES_CC_DST
,
204 [CC_OP_INCB
... CC_OP_INCQ
] = USES_CC_DST
| USES_CC_SRC
,
205 [CC_OP_DECB
... CC_OP_DECQ
] = USES_CC_DST
| USES_CC_SRC
,
206 [CC_OP_SHLB
... CC_OP_SHLQ
] = USES_CC_DST
| USES_CC_SRC
,
207 [CC_OP_SARB
... CC_OP_SARQ
] = USES_CC_DST
| USES_CC_SRC
,
210 static void set_cc_op(DisasContext
*s
, CCOp op
)
214 if (s
->cc_op
== op
) {
218 /* Discard CC computation that will no longer be used. */
219 dead
= cc_op_live
[s
->cc_op
] & ~cc_op_live
[op
];
220 if (dead
& USES_CC_DST
) {
221 tcg_gen_discard_tl(cpu_cc_dst
);
223 if (dead
& USES_CC_SRC
) {
224 tcg_gen_discard_tl(cpu_cc_src
);
226 if (dead
& USES_CC_SRCT
) {
227 tcg_gen_discard_tl(cpu_cc_srcT
);
231 /* The DYNAMIC setting is translator only, and should never be
232 stored. Thus we always consider it clean. */
233 s
->cc_op_dirty
= (op
!= CC_OP_DYNAMIC
);
236 static void gen_update_cc_op(DisasContext
*s
)
238 if (s
->cc_op_dirty
) {
239 tcg_gen_movi_i32(cpu_cc_op
, s
->cc_op
);
240 s
->cc_op_dirty
= false;
244 static inline void gen_op_movl_T0_0(void)
246 tcg_gen_movi_tl(cpu_T
[0], 0);
249 static inline void gen_op_movl_T0_im(int32_t val
)
251 tcg_gen_movi_tl(cpu_T
[0], val
);
254 static inline void gen_op_movl_T0_imu(uint32_t val
)
256 tcg_gen_movi_tl(cpu_T
[0], val
);
259 static inline void gen_op_movl_T1_im(int32_t val
)
261 tcg_gen_movi_tl(cpu_T
[1], val
);
264 static inline void gen_op_movl_T1_imu(uint32_t val
)
266 tcg_gen_movi_tl(cpu_T
[1], val
);
269 static inline void gen_op_movl_A0_im(uint32_t val
)
271 tcg_gen_movi_tl(cpu_A0
, val
);
275 static inline void gen_op_movq_A0_im(int64_t val
)
277 tcg_gen_movi_tl(cpu_A0
, val
);
281 static inline void gen_movtl_T0_im(target_ulong val
)
283 tcg_gen_movi_tl(cpu_T
[0], val
);
286 static inline void gen_movtl_T1_im(target_ulong val
)
288 tcg_gen_movi_tl(cpu_T
[1], val
);
291 static inline void gen_op_andl_T0_ffff(void)
293 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xffff);
296 static inline void gen_op_andl_T0_im(uint32_t val
)
298 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], val
);
301 static inline void gen_op_movl_T0_T1(void)
303 tcg_gen_mov_tl(cpu_T
[0], cpu_T
[1]);
306 static inline void gen_op_andl_A0_ffff(void)
308 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffff);
313 #define NB_OP_SIZES 4
315 #else /* !TARGET_X86_64 */
317 #define NB_OP_SIZES 3
319 #endif /* !TARGET_X86_64 */
321 #if defined(HOST_WORDS_BIGENDIAN)
322 #define REG_B_OFFSET (sizeof(target_ulong) - 1)
323 #define REG_H_OFFSET (sizeof(target_ulong) - 2)
324 #define REG_W_OFFSET (sizeof(target_ulong) - 2)
325 #define REG_L_OFFSET (sizeof(target_ulong) - 4)
326 #define REG_LH_OFFSET (sizeof(target_ulong) - 8)
328 #define REG_B_OFFSET 0
329 #define REG_H_OFFSET 1
330 #define REG_W_OFFSET 0
331 #define REG_L_OFFSET 0
332 #define REG_LH_OFFSET 4
335 /* In instruction encodings for byte register accesses the
336 * register number usually indicates "low 8 bits of register N";
337 * however there are some special cases where N 4..7 indicates
338 * [AH, CH, DH, BH], ie "bits 15..8 of register N-4". Return
339 * true for this special case, false otherwise.
341 static inline bool byte_reg_is_xH(int reg
)
347 if (reg
>= 8 || x86_64_hregs
) {
354 static inline void gen_op_mov_reg_v(int ot
, int reg
, TCGv t0
)
358 if (!byte_reg_is_xH(reg
)) {
359 tcg_gen_deposit_tl(cpu_regs
[reg
], cpu_regs
[reg
], t0
, 0, 8);
361 tcg_gen_deposit_tl(cpu_regs
[reg
- 4], cpu_regs
[reg
- 4], t0
, 8, 8);
365 tcg_gen_deposit_tl(cpu_regs
[reg
], cpu_regs
[reg
], t0
, 0, 16);
367 default: /* XXX this shouldn't be reached; abort? */
369 /* For x86_64, this sets the higher half of register to zero.
370 For i386, this is equivalent to a mov. */
371 tcg_gen_ext32u_tl(cpu_regs
[reg
], t0
);
375 tcg_gen_mov_tl(cpu_regs
[reg
], t0
);
381 static inline void gen_op_mov_reg_T0(int ot
, int reg
)
383 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
386 static inline void gen_op_mov_reg_T1(int ot
, int reg
)
388 gen_op_mov_reg_v(ot
, reg
, cpu_T
[1]);
391 static inline void gen_op_mov_reg_A0(int size
, int reg
)
395 tcg_gen_deposit_tl(cpu_regs
[reg
], cpu_regs
[reg
], cpu_A0
, 0, 16);
397 default: /* XXX this shouldn't be reached; abort? */
399 /* For x86_64, this sets the higher half of register to zero.
400 For i386, this is equivalent to a mov. */
401 tcg_gen_ext32u_tl(cpu_regs
[reg
], cpu_A0
);
405 tcg_gen_mov_tl(cpu_regs
[reg
], cpu_A0
);
411 static inline void gen_op_mov_v_reg(int ot
, TCGv t0
, int reg
)
413 if (ot
== OT_BYTE
&& byte_reg_is_xH(reg
)) {
414 tcg_gen_shri_tl(t0
, cpu_regs
[reg
- 4], 8);
415 tcg_gen_ext8u_tl(t0
, t0
);
417 tcg_gen_mov_tl(t0
, cpu_regs
[reg
]);
421 static inline void gen_op_mov_TN_reg(int ot
, int t_index
, int reg
)
423 gen_op_mov_v_reg(ot
, cpu_T
[t_index
], reg
);
426 static inline void gen_op_movl_A0_reg(int reg
)
428 tcg_gen_mov_tl(cpu_A0
, cpu_regs
[reg
]);
431 static inline void gen_op_addl_A0_im(int32_t val
)
433 tcg_gen_addi_tl(cpu_A0
, cpu_A0
, val
);
435 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
440 static inline void gen_op_addq_A0_im(int64_t val
)
442 tcg_gen_addi_tl(cpu_A0
, cpu_A0
, val
);
446 static void gen_add_A0_im(DisasContext
*s
, int val
)
450 gen_op_addq_A0_im(val
);
453 gen_op_addl_A0_im(val
);
456 static inline void gen_op_addl_T0_T1(void)
458 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
461 static inline void gen_op_jmp_T0(void)
463 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, eip
));
466 static inline void gen_op_add_reg_im(int size
, int reg
, int32_t val
)
470 tcg_gen_addi_tl(cpu_tmp0
, cpu_regs
[reg
], val
);
471 tcg_gen_deposit_tl(cpu_regs
[reg
], cpu_regs
[reg
], cpu_tmp0
, 0, 16);
474 tcg_gen_addi_tl(cpu_tmp0
, cpu_regs
[reg
], val
);
475 /* For x86_64, this sets the higher half of register to zero.
476 For i386, this is equivalent to a nop. */
477 tcg_gen_ext32u_tl(cpu_tmp0
, cpu_tmp0
);
478 tcg_gen_mov_tl(cpu_regs
[reg
], cpu_tmp0
);
482 tcg_gen_addi_tl(cpu_regs
[reg
], cpu_regs
[reg
], val
);
488 static inline void gen_op_add_reg_T0(int size
, int reg
)
492 tcg_gen_add_tl(cpu_tmp0
, cpu_regs
[reg
], cpu_T
[0]);
493 tcg_gen_deposit_tl(cpu_regs
[reg
], cpu_regs
[reg
], cpu_tmp0
, 0, 16);
496 tcg_gen_add_tl(cpu_tmp0
, cpu_regs
[reg
], cpu_T
[0]);
497 /* For x86_64, this sets the higher half of register to zero.
498 For i386, this is equivalent to a nop. */
499 tcg_gen_ext32u_tl(cpu_tmp0
, cpu_tmp0
);
500 tcg_gen_mov_tl(cpu_regs
[reg
], cpu_tmp0
);
504 tcg_gen_add_tl(cpu_regs
[reg
], cpu_regs
[reg
], cpu_T
[0]);
510 static inline void gen_op_addl_A0_reg_sN(int shift
, int reg
)
512 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[reg
]);
514 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, shift
);
515 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
516 /* For x86_64, this sets the higher half of register to zero.
517 For i386, this is equivalent to a nop. */
518 tcg_gen_ext32u_tl(cpu_A0
, cpu_A0
);
521 static inline void gen_op_movl_A0_seg(int reg
)
523 tcg_gen_ld32u_tl(cpu_A0
, cpu_env
, offsetof(CPUX86State
, segs
[reg
].base
) + REG_L_OFFSET
);
526 static inline void gen_op_addl_A0_seg(DisasContext
*s
, int reg
)
528 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUX86State
, segs
[reg
].base
));
531 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
532 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
534 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
535 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
538 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
543 static inline void gen_op_movq_A0_seg(int reg
)
545 tcg_gen_ld_tl(cpu_A0
, cpu_env
, offsetof(CPUX86State
, segs
[reg
].base
));
548 static inline void gen_op_addq_A0_seg(int reg
)
550 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUX86State
, segs
[reg
].base
));
551 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
554 static inline void gen_op_movq_A0_reg(int reg
)
556 tcg_gen_mov_tl(cpu_A0
, cpu_regs
[reg
]);
559 static inline void gen_op_addq_A0_reg_sN(int shift
, int reg
)
561 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[reg
]);
563 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, shift
);
564 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
568 static inline void gen_op_lds_T0_A0(int idx
)
570 int mem_index
= (idx
>> 2) - 1;
573 tcg_gen_qemu_ld8s(cpu_T
[0], cpu_A0
, mem_index
);
576 tcg_gen_qemu_ld16s(cpu_T
[0], cpu_A0
, mem_index
);
580 tcg_gen_qemu_ld32s(cpu_T
[0], cpu_A0
, mem_index
);
585 static inline void gen_op_ld_v(int idx
, TCGv t0
, TCGv a0
)
587 int mem_index
= (idx
>> 2) - 1;
590 tcg_gen_qemu_ld8u(t0
, a0
, mem_index
);
593 tcg_gen_qemu_ld16u(t0
, a0
, mem_index
);
596 tcg_gen_qemu_ld32u(t0
, a0
, mem_index
);
600 /* Should never happen on 32-bit targets. */
602 tcg_gen_qemu_ld64(t0
, a0
, mem_index
);
608 /* XXX: always use ldu or lds */
609 static inline void gen_op_ld_T0_A0(int idx
)
611 gen_op_ld_v(idx
, cpu_T
[0], cpu_A0
);
614 static inline void gen_op_ldu_T0_A0(int idx
)
616 gen_op_ld_v(idx
, cpu_T
[0], cpu_A0
);
619 static inline void gen_op_ld_T1_A0(int idx
)
621 gen_op_ld_v(idx
, cpu_T
[1], cpu_A0
);
624 static inline void gen_op_st_v(int idx
, TCGv t0
, TCGv a0
)
626 int mem_index
= (idx
>> 2) - 1;
629 tcg_gen_qemu_st8(t0
, a0
, mem_index
);
632 tcg_gen_qemu_st16(t0
, a0
, mem_index
);
635 tcg_gen_qemu_st32(t0
, a0
, mem_index
);
639 /* Should never happen on 32-bit targets. */
641 tcg_gen_qemu_st64(t0
, a0
, mem_index
);
647 static inline void gen_op_st_T0_A0(int idx
)
649 gen_op_st_v(idx
, cpu_T
[0], cpu_A0
);
652 static inline void gen_op_st_T1_A0(int idx
)
654 gen_op_st_v(idx
, cpu_T
[1], cpu_A0
);
657 static inline void gen_jmp_im(target_ulong pc
)
659 tcg_gen_movi_tl(cpu_tmp0
, pc
);
660 tcg_gen_st_tl(cpu_tmp0
, cpu_env
, offsetof(CPUX86State
, eip
));
663 static inline void gen_string_movl_A0_ESI(DisasContext
*s
)
667 override
= s
->override
;
671 gen_op_movq_A0_seg(override
);
672 gen_op_addq_A0_reg_sN(0, R_ESI
);
674 gen_op_movq_A0_reg(R_ESI
);
680 if (s
->addseg
&& override
< 0)
683 gen_op_movl_A0_seg(override
);
684 gen_op_addl_A0_reg_sN(0, R_ESI
);
686 gen_op_movl_A0_reg(R_ESI
);
689 /* 16 address, always override */
692 gen_op_movl_A0_reg(R_ESI
);
693 gen_op_andl_A0_ffff();
694 gen_op_addl_A0_seg(s
, override
);
698 static inline void gen_string_movl_A0_EDI(DisasContext
*s
)
702 gen_op_movq_A0_reg(R_EDI
);
707 gen_op_movl_A0_seg(R_ES
);
708 gen_op_addl_A0_reg_sN(0, R_EDI
);
710 gen_op_movl_A0_reg(R_EDI
);
713 gen_op_movl_A0_reg(R_EDI
);
714 gen_op_andl_A0_ffff();
715 gen_op_addl_A0_seg(s
, R_ES
);
719 static inline void gen_op_movl_T0_Dshift(int ot
)
721 tcg_gen_ld32s_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, df
));
722 tcg_gen_shli_tl(cpu_T
[0], cpu_T
[0], ot
);
725 static TCGv
gen_ext_tl(TCGv dst
, TCGv src
, int size
, bool sign
)
730 tcg_gen_ext8s_tl(dst
, src
);
732 tcg_gen_ext8u_tl(dst
, src
);
737 tcg_gen_ext16s_tl(dst
, src
);
739 tcg_gen_ext16u_tl(dst
, src
);
745 tcg_gen_ext32s_tl(dst
, src
);
747 tcg_gen_ext32u_tl(dst
, src
);
756 static void gen_extu(int ot
, TCGv reg
)
758 gen_ext_tl(reg
, reg
, ot
, false);
761 static void gen_exts(int ot
, TCGv reg
)
763 gen_ext_tl(reg
, reg
, ot
, true);
766 static inline void gen_op_jnz_ecx(int size
, int label1
)
768 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[R_ECX
]);
769 gen_extu(size
+ 1, cpu_tmp0
);
770 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_tmp0
, 0, label1
);
773 static inline void gen_op_jz_ecx(int size
, int label1
)
775 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[R_ECX
]);
776 gen_extu(size
+ 1, cpu_tmp0
);
777 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_tmp0
, 0, label1
);
780 static void gen_helper_in_func(int ot
, TCGv v
, TCGv_i32 n
)
784 gen_helper_inb(v
, n
);
787 gen_helper_inw(v
, n
);
790 gen_helper_inl(v
, n
);
795 static void gen_helper_out_func(int ot
, TCGv_i32 v
, TCGv_i32 n
)
799 gen_helper_outb(v
, n
);
802 gen_helper_outw(v
, n
);
805 gen_helper_outl(v
, n
);
810 static void gen_check_io(DisasContext
*s
, int ot
, target_ulong cur_eip
,
814 target_ulong next_eip
;
817 if (s
->pe
&& (s
->cpl
> s
->iopl
|| s
->vm86
)) {
821 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
824 gen_helper_check_iob(cpu_env
, cpu_tmp2_i32
);
827 gen_helper_check_iow(cpu_env
, cpu_tmp2_i32
);
830 gen_helper_check_iol(cpu_env
, cpu_tmp2_i32
);
834 if(s
->flags
& HF_SVMI_MASK
) {
839 svm_flags
|= (1 << (4 + ot
));
840 next_eip
= s
->pc
- s
->cs_base
;
841 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
842 gen_helper_svm_check_io(cpu_env
, cpu_tmp2_i32
,
843 tcg_const_i32(svm_flags
),
844 tcg_const_i32(next_eip
- cur_eip
));
848 static inline void gen_movs(DisasContext
*s
, int ot
)
850 gen_string_movl_A0_ESI(s
);
851 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
852 gen_string_movl_A0_EDI(s
);
853 gen_op_st_T0_A0(ot
+ s
->mem_index
);
854 gen_op_movl_T0_Dshift(ot
);
855 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
856 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
859 static void gen_op_update1_cc(void)
861 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
864 static void gen_op_update2_cc(void)
866 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
867 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
870 static inline void gen_op_testl_T0_T1_cc(void)
872 tcg_gen_and_tl(cpu_cc_dst
, cpu_T
[0], cpu_T
[1]);
875 static void gen_op_update_neg_cc(void)
877 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
878 tcg_gen_neg_tl(cpu_cc_src
, cpu_T
[0]);
879 tcg_gen_movi_tl(cpu_cc_srcT
, 0);
882 /* compute all eflags to cc_src */
883 static void gen_compute_eflags(DisasContext
*s
)
885 TCGv zero
, dst
, src1
;
888 if (s
->cc_op
== CC_OP_EFLAGS
) {
896 /* Take care to not read values that are not live. */
897 live
= cc_op_live
[s
->cc_op
] & ~USES_CC_SRCT
;
898 dead
= live
^ (USES_CC_DST
| USES_CC_SRC
);
900 zero
= tcg_const_tl(0);
901 if (dead
& USES_CC_DST
) {
904 if (dead
& USES_CC_SRC
) {
910 gen_helper_cc_compute_all(cpu_cc_src
, dst
, src1
, cpu_cc_op
);
911 set_cc_op(s
, CC_OP_EFLAGS
);
918 typedef struct CCPrepare
{
928 /* compute eflags.C to reg */
929 static CCPrepare
gen_prepare_eflags_c(DisasContext
*s
, TCGv reg
)
935 case CC_OP_SUBB
... CC_OP_SUBQ
:
936 /* (DATA_TYPE)CC_SRCT < (DATA_TYPE)CC_SRC */
937 size
= s
->cc_op
- CC_OP_SUBB
;
938 t1
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, false);
939 /* If no temporary was used, be careful not to alias t1 and t0. */
940 t0
= TCGV_EQUAL(t1
, cpu_cc_src
) ? cpu_tmp0
: reg
;
941 tcg_gen_mov_tl(t0
, cpu_cc_srcT
);
945 case CC_OP_ADDB
... CC_OP_ADDQ
:
946 /* (DATA_TYPE)CC_DST < (DATA_TYPE)CC_SRC */
947 size
= s
->cc_op
- CC_OP_ADDB
;
948 t1
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, false);
949 t0
= gen_ext_tl(reg
, cpu_cc_dst
, size
, false);
951 return (CCPrepare
) { .cond
= TCG_COND_LTU
, .reg
= t0
,
952 .reg2
= t1
, .mask
= -1, .use_reg2
= true };
954 case CC_OP_SBBB
... CC_OP_SBBQ
:
955 /* (DATA_TYPE)(CC_DST + CC_SRC + 1) <= (DATA_TYPE)CC_SRC */
956 size
= s
->cc_op
- CC_OP_SBBB
;
957 t1
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, false);
958 if (TCGV_EQUAL(t1
, reg
) && TCGV_EQUAL(reg
, cpu_cc_src
)) {
959 tcg_gen_mov_tl(cpu_tmp0
, cpu_cc_src
);
963 tcg_gen_add_tl(reg
, cpu_cc_dst
, cpu_cc_src
);
964 tcg_gen_addi_tl(reg
, reg
, 1);
969 case CC_OP_ADCB
... CC_OP_ADCQ
:
970 /* (DATA_TYPE)CC_DST <= (DATA_TYPE)CC_SRC */
971 size
= s
->cc_op
- CC_OP_ADCB
;
972 t1
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, false);
973 t0
= gen_ext_tl(reg
, cpu_cc_dst
, size
, false);
975 return (CCPrepare
) { .cond
= TCG_COND_LEU
, .reg
= t0
,
976 .reg2
= t1
, .mask
= -1, .use_reg2
= true };
978 case CC_OP_LOGICB
... CC_OP_LOGICQ
:
979 return (CCPrepare
) { .cond
= TCG_COND_NEVER
, .mask
= -1 };
981 case CC_OP_INCB
... CC_OP_INCQ
:
982 case CC_OP_DECB
... CC_OP_DECQ
:
983 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
984 .mask
= -1, .no_setcond
= true };
986 case CC_OP_SHLB
... CC_OP_SHLQ
:
987 /* (CC_SRC >> (DATA_BITS - 1)) & 1 */
988 size
= s
->cc_op
- CC_OP_SHLB
;
989 shift
= (8 << size
) - 1;
990 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
991 .mask
= (target_ulong
)1 << shift
};
993 case CC_OP_MULB
... CC_OP_MULQ
:
994 return (CCPrepare
) { .cond
= TCG_COND_NE
,
995 .reg
= cpu_cc_src
, .mask
= -1 };
998 case CC_OP_SARB
... CC_OP_SARQ
:
1000 return (CCPrepare
) { .cond
= TCG_COND_NE
,
1001 .reg
= cpu_cc_src
, .mask
= CC_C
};
1004 /* The need to compute only C from CC_OP_DYNAMIC is important
1005 in efficiently implementing e.g. INC at the start of a TB. */
1006 gen_update_cc_op(s
);
1007 gen_helper_cc_compute_c(reg
, cpu_cc_dst
, cpu_cc_src
, cpu_cc_op
);
1008 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= reg
,
1009 .mask
= -1, .no_setcond
= true };
1013 /* compute eflags.P to reg */
1014 static CCPrepare
gen_prepare_eflags_p(DisasContext
*s
, TCGv reg
)
1016 gen_compute_eflags(s
);
1017 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
1021 /* compute eflags.S to reg */
1022 static CCPrepare
gen_prepare_eflags_s(DisasContext
*s
, TCGv reg
)
1026 gen_compute_eflags(s
);
1029 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
1033 int size
= (s
->cc_op
- CC_OP_ADDB
) & 3;
1034 TCGv t0
= gen_ext_tl(reg
, cpu_cc_dst
, size
, true);
1035 return (CCPrepare
) { .cond
= TCG_COND_LT
, .reg
= t0
, .mask
= -1 };
1040 /* compute eflags.O to reg */
1041 static CCPrepare
gen_prepare_eflags_o(DisasContext
*s
, TCGv reg
)
1043 gen_compute_eflags(s
);
1044 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
1048 /* compute eflags.Z to reg */
1049 static CCPrepare
gen_prepare_eflags_z(DisasContext
*s
, TCGv reg
)
1053 gen_compute_eflags(s
);
1056 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
1060 int size
= (s
->cc_op
- CC_OP_ADDB
) & 3;
1061 TCGv t0
= gen_ext_tl(reg
, cpu_cc_dst
, size
, false);
1062 return (CCPrepare
) { .cond
= TCG_COND_EQ
, .reg
= t0
, .mask
= -1 };
1067 /* perform a conditional store into register 'reg' according to jump opcode
1068 value 'b'. In the fast case, T0 is guaranted not to be used. */
1069 static CCPrepare
gen_prepare_cc(DisasContext
*s
, int b
, TCGv reg
)
1071 int inv
, jcc_op
, size
, cond
;
1076 jcc_op
= (b
>> 1) & 7;
1079 case CC_OP_SUBB
... CC_OP_SUBQ
:
1080 /* We optimize relational operators for the cmp/jcc case. */
1081 size
= s
->cc_op
- CC_OP_SUBB
;
1084 tcg_gen_mov_tl(cpu_tmp4
, cpu_cc_srcT
);
1085 gen_extu(size
, cpu_tmp4
);
1086 t0
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, false);
1087 cc
= (CCPrepare
) { .cond
= TCG_COND_LEU
, .reg
= cpu_tmp4
,
1088 .reg2
= t0
, .mask
= -1, .use_reg2
= true };
1097 tcg_gen_mov_tl(cpu_tmp4
, cpu_cc_srcT
);
1098 gen_exts(size
, cpu_tmp4
);
1099 t0
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, true);
1100 cc
= (CCPrepare
) { .cond
= cond
, .reg
= cpu_tmp4
,
1101 .reg2
= t0
, .mask
= -1, .use_reg2
= true };
1111 /* This actually generates good code for JC, JZ and JS. */
1114 cc
= gen_prepare_eflags_o(s
, reg
);
1117 cc
= gen_prepare_eflags_c(s
, reg
);
1120 cc
= gen_prepare_eflags_z(s
, reg
);
1123 gen_compute_eflags(s
);
1124 cc
= (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
1125 .mask
= CC_Z
| CC_C
};
1128 cc
= gen_prepare_eflags_s(s
, reg
);
1131 cc
= gen_prepare_eflags_p(s
, reg
);
1134 gen_compute_eflags(s
);
1135 if (TCGV_EQUAL(reg
, cpu_cc_src
)) {
1138 tcg_gen_shri_tl(reg
, cpu_cc_src
, 4); /* CC_O -> CC_S */
1139 tcg_gen_xor_tl(reg
, reg
, cpu_cc_src
);
1140 cc
= (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= reg
,
1145 gen_compute_eflags(s
);
1146 if (TCGV_EQUAL(reg
, cpu_cc_src
)) {
1149 tcg_gen_shri_tl(reg
, cpu_cc_src
, 4); /* CC_O -> CC_S */
1150 tcg_gen_xor_tl(reg
, reg
, cpu_cc_src
);
1151 cc
= (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= reg
,
1152 .mask
= CC_S
| CC_Z
};
1159 cc
.cond
= tcg_invert_cond(cc
.cond
);
1164 static void gen_setcc1(DisasContext
*s
, int b
, TCGv reg
)
1166 CCPrepare cc
= gen_prepare_cc(s
, b
, reg
);
1168 if (cc
.no_setcond
) {
1169 if (cc
.cond
== TCG_COND_EQ
) {
1170 tcg_gen_xori_tl(reg
, cc
.reg
, 1);
1172 tcg_gen_mov_tl(reg
, cc
.reg
);
1177 if (cc
.cond
== TCG_COND_NE
&& !cc
.use_reg2
&& cc
.imm
== 0 &&
1178 cc
.mask
!= 0 && (cc
.mask
& (cc
.mask
- 1)) == 0) {
1179 tcg_gen_shri_tl(reg
, cc
.reg
, ctztl(cc
.mask
));
1180 tcg_gen_andi_tl(reg
, reg
, 1);
1183 if (cc
.mask
!= -1) {
1184 tcg_gen_andi_tl(reg
, cc
.reg
, cc
.mask
);
1188 tcg_gen_setcond_tl(cc
.cond
, reg
, cc
.reg
, cc
.reg2
);
1190 tcg_gen_setcondi_tl(cc
.cond
, reg
, cc
.reg
, cc
.imm
);
1194 static inline void gen_compute_eflags_c(DisasContext
*s
, TCGv reg
)
1196 gen_setcc1(s
, JCC_B
<< 1, reg
);
1199 /* generate a conditional jump to label 'l1' according to jump opcode
1200 value 'b'. In the fast case, T0 is guaranted not to be used. */
1201 static inline void gen_jcc1_noeob(DisasContext
*s
, int b
, int l1
)
1203 CCPrepare cc
= gen_prepare_cc(s
, b
, cpu_T
[0]);
1205 if (cc
.mask
!= -1) {
1206 tcg_gen_andi_tl(cpu_T
[0], cc
.reg
, cc
.mask
);
1210 tcg_gen_brcond_tl(cc
.cond
, cc
.reg
, cc
.reg2
, l1
);
1212 tcg_gen_brcondi_tl(cc
.cond
, cc
.reg
, cc
.imm
, l1
);
1216 /* Generate a conditional jump to label 'l1' according to jump opcode
1217 value 'b'. In the fast case, T0 is guaranted not to be used.
1218 A translation block must end soon. */
1219 static inline void gen_jcc1(DisasContext
*s
, int b
, int l1
)
1221 CCPrepare cc
= gen_prepare_cc(s
, b
, cpu_T
[0]);
1223 gen_update_cc_op(s
);
1224 if (cc
.mask
!= -1) {
1225 tcg_gen_andi_tl(cpu_T
[0], cc
.reg
, cc
.mask
);
1228 set_cc_op(s
, CC_OP_DYNAMIC
);
1230 tcg_gen_brcond_tl(cc
.cond
, cc
.reg
, cc
.reg2
, l1
);
1232 tcg_gen_brcondi_tl(cc
.cond
, cc
.reg
, cc
.imm
, l1
);
1236 /* XXX: does not work with gdbstub "ice" single step - not a
1238 static int gen_jz_ecx_string(DisasContext
*s
, target_ulong next_eip
)
1242 l1
= gen_new_label();
1243 l2
= gen_new_label();
1244 gen_op_jnz_ecx(s
->aflag
, l1
);
1246 gen_jmp_tb(s
, next_eip
, 1);
1251 static inline void gen_stos(DisasContext
*s
, int ot
)
1253 gen_op_mov_TN_reg(OT_LONG
, 0, R_EAX
);
1254 gen_string_movl_A0_EDI(s
);
1255 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1256 gen_op_movl_T0_Dshift(ot
);
1257 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1260 static inline void gen_lods(DisasContext
*s
, int ot
)
1262 gen_string_movl_A0_ESI(s
);
1263 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1264 gen_op_mov_reg_T0(ot
, R_EAX
);
1265 gen_op_movl_T0_Dshift(ot
);
1266 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
1269 static inline void gen_scas(DisasContext
*s
, int ot
)
1271 gen_string_movl_A0_EDI(s
);
1272 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
1273 gen_op(s
, OP_CMPL
, ot
, R_EAX
);
1274 gen_op_movl_T0_Dshift(ot
);
1275 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1278 static inline void gen_cmps(DisasContext
*s
, int ot
)
1280 gen_string_movl_A0_EDI(s
);
1281 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
1282 gen_string_movl_A0_ESI(s
);
1283 gen_op(s
, OP_CMPL
, ot
, OR_TMP0
);
1284 gen_op_movl_T0_Dshift(ot
);
1285 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
1286 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1289 static inline void gen_ins(DisasContext
*s
, int ot
)
1293 gen_string_movl_A0_EDI(s
);
1294 /* Note: we must do this dummy write first to be restartable in
1295 case of page fault. */
1297 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1298 gen_op_mov_TN_reg(OT_WORD
, 1, R_EDX
);
1299 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[1]);
1300 tcg_gen_andi_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 0xffff);
1301 gen_helper_in_func(ot
, cpu_T
[0], cpu_tmp2_i32
);
1302 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1303 gen_op_movl_T0_Dshift(ot
);
1304 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1309 static inline void gen_outs(DisasContext
*s
, int ot
)
1313 gen_string_movl_A0_ESI(s
);
1314 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1316 gen_op_mov_TN_reg(OT_WORD
, 1, R_EDX
);
1317 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[1]);
1318 tcg_gen_andi_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 0xffff);
1319 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[0]);
1320 gen_helper_out_func(ot
, cpu_tmp2_i32
, cpu_tmp3_i32
);
1322 gen_op_movl_T0_Dshift(ot
);
1323 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
1328 /* same method as Valgrind : we generate jumps to current or next
1330 #define GEN_REPZ(op) \
1331 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1332 target_ulong cur_eip, target_ulong next_eip) \
1335 gen_update_cc_op(s); \
1336 l2 = gen_jz_ecx_string(s, next_eip); \
1337 gen_ ## op(s, ot); \
1338 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1339 /* a loop would cause two single step exceptions if ECX = 1 \
1340 before rep string_insn */ \
1342 gen_op_jz_ecx(s->aflag, l2); \
1343 gen_jmp(s, cur_eip); \
1346 #define GEN_REPZ2(op) \
1347 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1348 target_ulong cur_eip, \
1349 target_ulong next_eip, \
1353 gen_update_cc_op(s); \
1354 l2 = gen_jz_ecx_string(s, next_eip); \
1355 gen_ ## op(s, ot); \
1356 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1357 gen_update_cc_op(s); \
1358 gen_jcc1(s, (JCC_Z << 1) | (nz ^ 1), l2); \
1360 gen_op_jz_ecx(s->aflag, l2); \
1361 gen_jmp(s, cur_eip); \
1372 static void gen_helper_fp_arith_ST0_FT0(int op
)
1376 gen_helper_fadd_ST0_FT0(cpu_env
);
1379 gen_helper_fmul_ST0_FT0(cpu_env
);
1382 gen_helper_fcom_ST0_FT0(cpu_env
);
1385 gen_helper_fcom_ST0_FT0(cpu_env
);
1388 gen_helper_fsub_ST0_FT0(cpu_env
);
1391 gen_helper_fsubr_ST0_FT0(cpu_env
);
1394 gen_helper_fdiv_ST0_FT0(cpu_env
);
1397 gen_helper_fdivr_ST0_FT0(cpu_env
);
1402 /* NOTE the exception in "r" op ordering */
1403 static void gen_helper_fp_arith_STN_ST0(int op
, int opreg
)
1405 TCGv_i32 tmp
= tcg_const_i32(opreg
);
1408 gen_helper_fadd_STN_ST0(cpu_env
, tmp
);
1411 gen_helper_fmul_STN_ST0(cpu_env
, tmp
);
1414 gen_helper_fsubr_STN_ST0(cpu_env
, tmp
);
1417 gen_helper_fsub_STN_ST0(cpu_env
, tmp
);
1420 gen_helper_fdivr_STN_ST0(cpu_env
, tmp
);
1423 gen_helper_fdiv_STN_ST0(cpu_env
, tmp
);
1428 /* if d == OR_TMP0, it means memory operand (address in A0) */
1429 static void gen_op(DisasContext
*s1
, int op
, int ot
, int d
)
1432 gen_op_mov_TN_reg(ot
, 0, d
);
1434 gen_op_ld_T0_A0(ot
+ s1
->mem_index
);
1438 gen_compute_eflags_c(s1
, cpu_tmp4
);
1439 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1440 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_tmp4
);
1442 gen_op_mov_reg_T0(ot
, d
);
1444 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1445 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
1446 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1447 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_tmp4
);
1448 tcg_gen_shli_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 2);
1449 tcg_gen_addi_i32(cpu_cc_op
, cpu_tmp2_i32
, CC_OP_ADDB
+ ot
);
1450 set_cc_op(s1
, CC_OP_DYNAMIC
);
1454 * No need to store cpu_cc_srcT, because it is used only
1455 * when the cc_op is known.
1457 gen_compute_eflags_c(s1
, cpu_tmp4
);
1458 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1459 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_tmp4
);
1461 gen_op_mov_reg_T0(ot
, d
);
1463 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1464 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
1465 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1466 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_tmp4
);
1467 tcg_gen_shli_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 2);
1468 tcg_gen_addi_i32(cpu_cc_op
, cpu_tmp2_i32
, CC_OP_SUBB
+ ot
);
1469 set_cc_op(s1
, CC_OP_DYNAMIC
);
1472 gen_op_addl_T0_T1();
1474 gen_op_mov_reg_T0(ot
, d
);
1476 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1477 gen_op_update2_cc();
1478 set_cc_op(s1
, CC_OP_ADDB
+ ot
);
1481 tcg_gen_mov_tl(cpu_cc_srcT
, cpu_T
[0]);
1482 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1484 gen_op_mov_reg_T0(ot
, d
);
1486 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1487 gen_op_update2_cc();
1488 set_cc_op(s1
, CC_OP_SUBB
+ ot
);
1492 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1494 gen_op_mov_reg_T0(ot
, d
);
1496 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1497 gen_op_update1_cc();
1498 set_cc_op(s1
, CC_OP_LOGICB
+ ot
);
1501 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1503 gen_op_mov_reg_T0(ot
, d
);
1505 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1506 gen_op_update1_cc();
1507 set_cc_op(s1
, CC_OP_LOGICB
+ ot
);
1510 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1512 gen_op_mov_reg_T0(ot
, d
);
1514 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1515 gen_op_update1_cc();
1516 set_cc_op(s1
, CC_OP_LOGICB
+ ot
);
1519 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
1520 tcg_gen_mov_tl(cpu_cc_srcT
, cpu_T
[0]);
1521 tcg_gen_sub_tl(cpu_cc_dst
, cpu_T
[0], cpu_T
[1]);
1522 set_cc_op(s1
, CC_OP_SUBB
+ ot
);
1527 /* if d == OR_TMP0, it means memory operand (address in A0) */
1528 static void gen_inc(DisasContext
*s1
, int ot
, int d
, int c
)
1531 gen_op_mov_TN_reg(ot
, 0, d
);
1533 gen_op_ld_T0_A0(ot
+ s1
->mem_index
);
1534 gen_compute_eflags_c(s1
, cpu_cc_src
);
1536 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], 1);
1537 set_cc_op(s1
, CC_OP_INCB
+ ot
);
1539 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], -1);
1540 set_cc_op(s1
, CC_OP_DECB
+ ot
);
1543 gen_op_mov_reg_T0(ot
, d
);
1545 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1546 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1549 static void gen_shift_rm_T1(DisasContext
*s
, int ot
, int op1
,
1550 int is_right
, int is_arith
)
1556 if (ot
== OT_QUAD
) {
1563 if (op1
== OR_TMP0
) {
1564 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1566 gen_op_mov_TN_reg(ot
, 0, op1
);
1569 t0
= tcg_temp_local_new();
1570 t1
= tcg_temp_local_new();
1571 t2
= tcg_temp_local_new();
1573 tcg_gen_andi_tl(t2
, cpu_T
[1], mask
);
1577 gen_exts(ot
, cpu_T
[0]);
1578 tcg_gen_mov_tl(t0
, cpu_T
[0]);
1579 tcg_gen_sar_tl(cpu_T
[0], cpu_T
[0], t2
);
1581 gen_extu(ot
, cpu_T
[0]);
1582 tcg_gen_mov_tl(t0
, cpu_T
[0]);
1583 tcg_gen_shr_tl(cpu_T
[0], cpu_T
[0], t2
);
1586 tcg_gen_mov_tl(t0
, cpu_T
[0]);
1587 tcg_gen_shl_tl(cpu_T
[0], cpu_T
[0], t2
);
1591 if (op1
== OR_TMP0
) {
1592 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1594 gen_op_mov_reg_T0(ot
, op1
);
1597 /* Update eflags data because we cannot predict flags afterward. */
1598 gen_update_cc_op(s
);
1599 set_cc_op(s
, CC_OP_DYNAMIC
);
1601 tcg_gen_mov_tl(t1
, cpu_T
[0]);
1603 shift_label
= gen_new_label();
1604 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, shift_label
);
1606 tcg_gen_addi_tl(t2
, t2
, -1);
1607 tcg_gen_mov_tl(cpu_cc_dst
, t1
);
1611 tcg_gen_sar_tl(cpu_cc_src
, t0
, t2
);
1613 tcg_gen_shr_tl(cpu_cc_src
, t0
, t2
);
1616 tcg_gen_shl_tl(cpu_cc_src
, t0
, t2
);
1620 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_SARB
+ ot
);
1622 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_SHLB
+ ot
);
1625 gen_set_label(shift_label
);
1632 static void gen_shift_rm_im(DisasContext
*s
, int ot
, int op1
, int op2
,
1633 int is_right
, int is_arith
)
1644 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1646 gen_op_mov_TN_reg(ot
, 0, op1
);
1652 gen_exts(ot
, cpu_T
[0]);
1653 tcg_gen_sari_tl(cpu_tmp4
, cpu_T
[0], op2
- 1);
1654 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], op2
);
1656 gen_extu(ot
, cpu_T
[0]);
1657 tcg_gen_shri_tl(cpu_tmp4
, cpu_T
[0], op2
- 1);
1658 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], op2
);
1661 tcg_gen_shli_tl(cpu_tmp4
, cpu_T
[0], op2
- 1);
1662 tcg_gen_shli_tl(cpu_T
[0], cpu_T
[0], op2
);
1668 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1670 gen_op_mov_reg_T0(ot
, op1
);
1672 /* update eflags if non zero shift */
1674 tcg_gen_mov_tl(cpu_cc_src
, cpu_tmp4
);
1675 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1676 set_cc_op(s
, (is_right
? CC_OP_SARB
: CC_OP_SHLB
) + ot
);
1680 static inline void tcg_gen_lshift(TCGv ret
, TCGv arg1
, target_long arg2
)
1683 tcg_gen_shli_tl(ret
, arg1
, arg2
);
1685 tcg_gen_shri_tl(ret
, arg1
, -arg2
);
1688 static void gen_rot_rm_T1(DisasContext
*s
, int ot
, int op1
,
1692 int label1
, label2
, data_bits
;
1693 TCGv t0
, t1
, t2
, a0
;
1695 /* XXX: inefficient, but we must use local temps */
1696 t0
= tcg_temp_local_new();
1697 t1
= tcg_temp_local_new();
1698 t2
= tcg_temp_local_new();
1699 a0
= tcg_temp_local_new();
1707 if (op1
== OR_TMP0
) {
1708 tcg_gen_mov_tl(a0
, cpu_A0
);
1709 gen_op_ld_v(ot
+ s
->mem_index
, t0
, a0
);
1711 gen_op_mov_v_reg(ot
, t0
, op1
);
1714 tcg_gen_mov_tl(t1
, cpu_T
[1]);
1716 tcg_gen_andi_tl(t1
, t1
, mask
);
1718 /* Must test zero case to avoid using undefined behaviour in TCG
1720 label1
= gen_new_label();
1721 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, label1
);
1724 tcg_gen_andi_tl(cpu_tmp0
, t1
, (1 << (3 + ot
)) - 1);
1726 tcg_gen_mov_tl(cpu_tmp0
, t1
);
1729 tcg_gen_mov_tl(t2
, t0
);
1731 data_bits
= 8 << ot
;
1732 /* XXX: rely on behaviour of shifts when operand 2 overflows (XXX:
1733 fix TCG definition) */
1735 tcg_gen_shr_tl(cpu_tmp4
, t0
, cpu_tmp0
);
1736 tcg_gen_subfi_tl(cpu_tmp0
, data_bits
, cpu_tmp0
);
1737 tcg_gen_shl_tl(t0
, t0
, cpu_tmp0
);
1739 tcg_gen_shl_tl(cpu_tmp4
, t0
, cpu_tmp0
);
1740 tcg_gen_subfi_tl(cpu_tmp0
, data_bits
, cpu_tmp0
);
1741 tcg_gen_shr_tl(t0
, t0
, cpu_tmp0
);
1743 tcg_gen_or_tl(t0
, t0
, cpu_tmp4
);
1745 gen_set_label(label1
);
1747 if (op1
== OR_TMP0
) {
1748 gen_op_st_v(ot
+ s
->mem_index
, t0
, a0
);
1750 gen_op_mov_reg_v(ot
, op1
, t0
);
1753 /* update eflags. It is needed anyway most of the time, do it always. */
1754 gen_compute_eflags(s
);
1755 assert(s
->cc_op
== CC_OP_EFLAGS
);
1757 label2
= gen_new_label();
1758 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, label2
);
1760 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~(CC_O
| CC_C
));
1761 tcg_gen_xor_tl(cpu_tmp0
, t2
, t0
);
1762 tcg_gen_lshift(cpu_tmp0
, cpu_tmp0
, 11 - (data_bits
- 1));
1763 tcg_gen_andi_tl(cpu_tmp0
, cpu_tmp0
, CC_O
);
1764 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, cpu_tmp0
);
1766 tcg_gen_shri_tl(t0
, t0
, data_bits
- 1);
1768 tcg_gen_andi_tl(t0
, t0
, CC_C
);
1769 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, t0
);
1771 gen_set_label(label2
);
1779 static void gen_rot_rm_im(DisasContext
*s
, int ot
, int op1
, int op2
,
1786 /* XXX: inefficient, but we must use local temps */
1787 t0
= tcg_temp_local_new();
1788 t1
= tcg_temp_local_new();
1789 a0
= tcg_temp_local_new();
1797 if (op1
== OR_TMP0
) {
1798 tcg_gen_mov_tl(a0
, cpu_A0
);
1799 gen_op_ld_v(ot
+ s
->mem_index
, t0
, a0
);
1801 gen_op_mov_v_reg(ot
, t0
, op1
);
1805 tcg_gen_mov_tl(t1
, t0
);
1808 data_bits
= 8 << ot
;
1810 int shift
= op2
& ((1 << (3 + ot
)) - 1);
1812 tcg_gen_shri_tl(cpu_tmp4
, t0
, shift
);
1813 tcg_gen_shli_tl(t0
, t0
, data_bits
- shift
);
1816 tcg_gen_shli_tl(cpu_tmp4
, t0
, shift
);
1817 tcg_gen_shri_tl(t0
, t0
, data_bits
- shift
);
1819 tcg_gen_or_tl(t0
, t0
, cpu_tmp4
);
1823 if (op1
== OR_TMP0
) {
1824 gen_op_st_v(ot
+ s
->mem_index
, t0
, a0
);
1826 gen_op_mov_reg_v(ot
, op1
, t0
);
1831 gen_compute_eflags(s
);
1832 assert(s
->cc_op
== CC_OP_EFLAGS
);
1834 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~(CC_O
| CC_C
));
1835 tcg_gen_xor_tl(cpu_tmp0
, t1
, t0
);
1836 tcg_gen_lshift(cpu_tmp0
, cpu_tmp0
, 11 - (data_bits
- 1));
1837 tcg_gen_andi_tl(cpu_tmp0
, cpu_tmp0
, CC_O
);
1838 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, cpu_tmp0
);
1840 tcg_gen_shri_tl(t0
, t0
, data_bits
- 1);
1842 tcg_gen_andi_tl(t0
, t0
, CC_C
);
1843 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, t0
);
1851 /* XXX: add faster immediate = 1 case */
1852 static void gen_rotc_rm_T1(DisasContext
*s
, int ot
, int op1
,
1855 gen_compute_eflags(s
);
1856 assert(s
->cc_op
== CC_OP_EFLAGS
);
1860 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1862 gen_op_mov_TN_reg(ot
, 0, op1
);
1867 gen_helper_rcrb(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1870 gen_helper_rcrw(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1873 gen_helper_rcrl(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1875 #ifdef TARGET_X86_64
1877 gen_helper_rcrq(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1884 gen_helper_rclb(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1887 gen_helper_rclw(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1890 gen_helper_rcll(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1892 #ifdef TARGET_X86_64
1894 gen_helper_rclq(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1901 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1903 gen_op_mov_reg_T0(ot
, op1
);
1906 /* XXX: add faster immediate case */
1907 static void gen_shiftd_rm_T1(DisasContext
*s
, int ot
, int op1
,
1908 int is_right
, TCGv count
)
1910 int label1
, label2
, data_bits
;
1912 TCGv t0
, t1
, t2
, a0
;
1914 t0
= tcg_temp_local_new();
1915 t1
= tcg_temp_local_new();
1916 t2
= tcg_temp_local_new();
1917 a0
= tcg_temp_local_new();
1925 if (op1
== OR_TMP0
) {
1926 tcg_gen_mov_tl(a0
, cpu_A0
);
1927 gen_op_ld_v(ot
+ s
->mem_index
, t0
, a0
);
1929 gen_op_mov_v_reg(ot
, t0
, op1
);
1932 tcg_gen_andi_tl(t2
, count
, mask
);
1933 tcg_gen_mov_tl(t1
, cpu_T
[1]);
1935 /* Must test zero case to avoid using undefined behaviour in TCG
1937 label1
= gen_new_label();
1938 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, label1
);
1940 tcg_gen_addi_tl(cpu_tmp5
, t2
, -1);
1941 if (ot
== OT_WORD
) {
1942 /* Note: we implement the Intel behaviour for shift count > 16 */
1944 tcg_gen_andi_tl(t0
, t0
, 0xffff);
1945 tcg_gen_shli_tl(cpu_tmp0
, t1
, 16);
1946 tcg_gen_or_tl(t0
, t0
, cpu_tmp0
);
1947 tcg_gen_ext32u_tl(t0
, t0
);
1949 tcg_gen_shr_tl(cpu_tmp4
, t0
, cpu_tmp5
);
1951 /* only needed if count > 16, but a test would complicate */
1952 tcg_gen_subfi_tl(cpu_tmp5
, 32, t2
);
1953 tcg_gen_shl_tl(cpu_tmp0
, t0
, cpu_tmp5
);
1955 tcg_gen_shr_tl(t0
, t0
, t2
);
1957 tcg_gen_or_tl(t0
, t0
, cpu_tmp0
);
1959 /* XXX: not optimal */
1960 tcg_gen_andi_tl(t0
, t0
, 0xffff);
1961 tcg_gen_shli_tl(t1
, t1
, 16);
1962 tcg_gen_or_tl(t1
, t1
, t0
);
1963 tcg_gen_ext32u_tl(t1
, t1
);
1965 tcg_gen_shl_tl(cpu_tmp4
, t0
, cpu_tmp5
);
1966 tcg_gen_subfi_tl(cpu_tmp0
, 32, cpu_tmp5
);
1967 tcg_gen_shr_tl(cpu_tmp5
, t1
, cpu_tmp0
);
1968 tcg_gen_or_tl(cpu_tmp4
, cpu_tmp4
, cpu_tmp5
);
1970 tcg_gen_shl_tl(t0
, t0
, t2
);
1971 tcg_gen_subfi_tl(cpu_tmp5
, 32, t2
);
1972 tcg_gen_shr_tl(t1
, t1
, cpu_tmp5
);
1973 tcg_gen_or_tl(t0
, t0
, t1
);
1976 data_bits
= 8 << ot
;
1979 tcg_gen_ext32u_tl(t0
, t0
);
1981 tcg_gen_shr_tl(cpu_tmp4
, t0
, cpu_tmp5
);
1983 tcg_gen_shr_tl(t0
, t0
, t2
);
1984 tcg_gen_subfi_tl(cpu_tmp5
, data_bits
, t2
);
1985 tcg_gen_shl_tl(t1
, t1
, cpu_tmp5
);
1986 tcg_gen_or_tl(t0
, t0
, t1
);
1990 tcg_gen_ext32u_tl(t1
, t1
);
1992 tcg_gen_shl_tl(cpu_tmp4
, t0
, cpu_tmp5
);
1994 tcg_gen_shl_tl(t0
, t0
, t2
);
1995 tcg_gen_subfi_tl(cpu_tmp5
, data_bits
, t2
);
1996 tcg_gen_shr_tl(t1
, t1
, cpu_tmp5
);
1997 tcg_gen_or_tl(t0
, t0
, t1
);
2000 tcg_gen_mov_tl(t1
, cpu_tmp4
);
2002 gen_set_label(label1
);
2004 if (op1
== OR_TMP0
) {
2005 gen_op_st_v(ot
+ s
->mem_index
, t0
, a0
);
2007 gen_op_mov_reg_v(ot
, op1
, t0
);
2010 /* Update eflags data because we cannot predict flags afterward. */
2011 gen_update_cc_op(s
);
2012 set_cc_op(s
, CC_OP_DYNAMIC
);
2014 label2
= gen_new_label();
2015 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, label2
);
2017 tcg_gen_mov_tl(cpu_cc_src
, t1
);
2018 tcg_gen_mov_tl(cpu_cc_dst
, t0
);
2020 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_SARB
+ ot
);
2022 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_SHLB
+ ot
);
2024 gen_set_label(label2
);
2032 static void gen_shift(DisasContext
*s1
, int op
, int ot
, int d
, int s
)
2035 gen_op_mov_TN_reg(ot
, 1, s
);
2038 gen_rot_rm_T1(s1
, ot
, d
, 0);
2041 gen_rot_rm_T1(s1
, ot
, d
, 1);
2045 gen_shift_rm_T1(s1
, ot
, d
, 0, 0);
2048 gen_shift_rm_T1(s1
, ot
, d
, 1, 0);
2051 gen_shift_rm_T1(s1
, ot
, d
, 1, 1);
2054 gen_rotc_rm_T1(s1
, ot
, d
, 0);
2057 gen_rotc_rm_T1(s1
, ot
, d
, 1);
2062 static void gen_shifti(DisasContext
*s1
, int op
, int ot
, int d
, int c
)
2066 gen_rot_rm_im(s1
, ot
, d
, c
, 0);
2069 gen_rot_rm_im(s1
, ot
, d
, c
, 1);
2073 gen_shift_rm_im(s1
, ot
, d
, c
, 0, 0);
2076 gen_shift_rm_im(s1
, ot
, d
, c
, 1, 0);
2079 gen_shift_rm_im(s1
, ot
, d
, c
, 1, 1);
2082 /* currently not optimized */
2083 gen_op_movl_T1_im(c
);
2084 gen_shift(s1
, op
, ot
, d
, OR_TMP1
);
2089 static void gen_lea_modrm(CPUX86State
*env
, DisasContext
*s
, int modrm
,
2090 int *reg_ptr
, int *offset_ptr
)
2098 int mod
, rm
, code
, override
, must_add_seg
;
2100 override
= s
->override
;
2101 must_add_seg
= s
->addseg
;
2104 mod
= (modrm
>> 6) & 3;
2116 code
= cpu_ldub_code(env
, s
->pc
++);
2117 scale
= (code
>> 6) & 3;
2118 index
= ((code
>> 3) & 7) | REX_X(s
);
2125 if ((base
& 7) == 5) {
2127 disp
= (int32_t)cpu_ldl_code(env
, s
->pc
);
2129 if (CODE64(s
) && !havesib
) {
2130 disp
+= s
->pc
+ s
->rip_offset
;
2137 disp
= (int8_t)cpu_ldub_code(env
, s
->pc
++);
2141 disp
= (int32_t)cpu_ldl_code(env
, s
->pc
);
2147 /* for correct popl handling with esp */
2148 if (base
== 4 && s
->popl_esp_hack
)
2149 disp
+= s
->popl_esp_hack
;
2150 #ifdef TARGET_X86_64
2151 if (s
->aflag
== 2) {
2152 gen_op_movq_A0_reg(base
);
2154 gen_op_addq_A0_im(disp
);
2159 gen_op_movl_A0_reg(base
);
2161 gen_op_addl_A0_im(disp
);
2164 #ifdef TARGET_X86_64
2165 if (s
->aflag
== 2) {
2166 gen_op_movq_A0_im(disp
);
2170 gen_op_movl_A0_im(disp
);
2173 /* index == 4 means no index */
2174 if (havesib
&& (index
!= 4)) {
2175 #ifdef TARGET_X86_64
2176 if (s
->aflag
== 2) {
2177 gen_op_addq_A0_reg_sN(scale
, index
);
2181 gen_op_addl_A0_reg_sN(scale
, index
);
2186 if (base
== R_EBP
|| base
== R_ESP
)
2191 #ifdef TARGET_X86_64
2192 if (s
->aflag
== 2) {
2193 gen_op_addq_A0_seg(override
);
2197 gen_op_addl_A0_seg(s
, override
);
2204 disp
= cpu_lduw_code(env
, s
->pc
);
2206 gen_op_movl_A0_im(disp
);
2207 rm
= 0; /* avoid SS override */
2214 disp
= (int8_t)cpu_ldub_code(env
, s
->pc
++);
2218 disp
= cpu_lduw_code(env
, s
->pc
);
2224 gen_op_movl_A0_reg(R_EBX
);
2225 gen_op_addl_A0_reg_sN(0, R_ESI
);
2228 gen_op_movl_A0_reg(R_EBX
);
2229 gen_op_addl_A0_reg_sN(0, R_EDI
);
2232 gen_op_movl_A0_reg(R_EBP
);
2233 gen_op_addl_A0_reg_sN(0, R_ESI
);
2236 gen_op_movl_A0_reg(R_EBP
);
2237 gen_op_addl_A0_reg_sN(0, R_EDI
);
2240 gen_op_movl_A0_reg(R_ESI
);
2243 gen_op_movl_A0_reg(R_EDI
);
2246 gen_op_movl_A0_reg(R_EBP
);
2250 gen_op_movl_A0_reg(R_EBX
);
2254 gen_op_addl_A0_im(disp
);
2255 gen_op_andl_A0_ffff();
2259 if (rm
== 2 || rm
== 3 || rm
== 6)
2264 gen_op_addl_A0_seg(s
, override
);
2274 static void gen_nop_modrm(CPUX86State
*env
, DisasContext
*s
, int modrm
)
2276 int mod
, rm
, base
, code
;
2278 mod
= (modrm
>> 6) & 3;
2288 code
= cpu_ldub_code(env
, s
->pc
++);
2324 /* used for LEA and MOV AX, mem */
2325 static void gen_add_A0_ds_seg(DisasContext
*s
)
2327 int override
, must_add_seg
;
2328 must_add_seg
= s
->addseg
;
2330 if (s
->override
>= 0) {
2331 override
= s
->override
;
2335 #ifdef TARGET_X86_64
2337 gen_op_addq_A0_seg(override
);
2341 gen_op_addl_A0_seg(s
, override
);
2346 /* generate modrm memory load or store of 'reg'. TMP0 is used if reg ==
2348 static void gen_ldst_modrm(CPUX86State
*env
, DisasContext
*s
, int modrm
,
2349 int ot
, int reg
, int is_store
)
2351 int mod
, rm
, opreg
, disp
;
2353 mod
= (modrm
>> 6) & 3;
2354 rm
= (modrm
& 7) | REX_B(s
);
2358 gen_op_mov_TN_reg(ot
, 0, reg
);
2359 gen_op_mov_reg_T0(ot
, rm
);
2361 gen_op_mov_TN_reg(ot
, 0, rm
);
2363 gen_op_mov_reg_T0(ot
, reg
);
2366 gen_lea_modrm(env
, s
, modrm
, &opreg
, &disp
);
2369 gen_op_mov_TN_reg(ot
, 0, reg
);
2370 gen_op_st_T0_A0(ot
+ s
->mem_index
);
2372 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
2374 gen_op_mov_reg_T0(ot
, reg
);
2379 static inline uint32_t insn_get(CPUX86State
*env
, DisasContext
*s
, int ot
)
2385 ret
= cpu_ldub_code(env
, s
->pc
);
2389 ret
= cpu_lduw_code(env
, s
->pc
);
2394 ret
= cpu_ldl_code(env
, s
->pc
);
2401 static inline int insn_const_size(unsigned int ot
)
2409 static inline void gen_goto_tb(DisasContext
*s
, int tb_num
, target_ulong eip
)
2411 TranslationBlock
*tb
;
2414 pc
= s
->cs_base
+ eip
;
2416 /* NOTE: we handle the case where the TB spans two pages here */
2417 if ((pc
& TARGET_PAGE_MASK
) == (tb
->pc
& TARGET_PAGE_MASK
) ||
2418 (pc
& TARGET_PAGE_MASK
) == ((s
->pc
- 1) & TARGET_PAGE_MASK
)) {
2419 /* jump to same page: we can use a direct jump */
2420 tcg_gen_goto_tb(tb_num
);
2422 tcg_gen_exit_tb((tcg_target_long
)tb
+ tb_num
);
2424 /* jump to another page: currently not optimized */
2430 static inline void gen_jcc(DisasContext
*s
, int b
,
2431 target_ulong val
, target_ulong next_eip
)
2436 l1
= gen_new_label();
2439 gen_goto_tb(s
, 0, next_eip
);
2442 gen_goto_tb(s
, 1, val
);
2443 s
->is_jmp
= DISAS_TB_JUMP
;
2445 l1
= gen_new_label();
2446 l2
= gen_new_label();
2449 gen_jmp_im(next_eip
);
2459 static void gen_cmovcc1(CPUX86State
*env
, DisasContext
*s
, int ot
, int b
,
2464 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
2466 cc
= gen_prepare_cc(s
, b
, cpu_T
[1]);
2467 if (cc
.mask
!= -1) {
2468 TCGv t0
= tcg_temp_new();
2469 tcg_gen_andi_tl(t0
, cc
.reg
, cc
.mask
);
2473 cc
.reg2
= tcg_const_tl(cc
.imm
);
2476 tcg_gen_movcond_tl(cc
.cond
, cpu_T
[0], cc
.reg
, cc
.reg2
,
2477 cpu_T
[0], cpu_regs
[reg
]);
2478 gen_op_mov_reg_T0(ot
, reg
);
2480 if (cc
.mask
!= -1) {
2481 tcg_temp_free(cc
.reg
);
2484 tcg_temp_free(cc
.reg2
);
2488 static inline void gen_op_movl_T0_seg(int seg_reg
)
2490 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
,
2491 offsetof(CPUX86State
,segs
[seg_reg
].selector
));
2494 static inline void gen_op_movl_seg_T0_vm(int seg_reg
)
2496 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xffff);
2497 tcg_gen_st32_tl(cpu_T
[0], cpu_env
,
2498 offsetof(CPUX86State
,segs
[seg_reg
].selector
));
2499 tcg_gen_shli_tl(cpu_T
[0], cpu_T
[0], 4);
2500 tcg_gen_st_tl(cpu_T
[0], cpu_env
,
2501 offsetof(CPUX86State
,segs
[seg_reg
].base
));
2504 /* move T0 to seg_reg and compute if the CPU state may change. Never
2505 call this function with seg_reg == R_CS */
2506 static void gen_movl_seg_T0(DisasContext
*s
, int seg_reg
, target_ulong cur_eip
)
2508 if (s
->pe
&& !s
->vm86
) {
2509 /* XXX: optimize by finding processor state dynamically */
2510 gen_update_cc_op(s
);
2511 gen_jmp_im(cur_eip
);
2512 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
2513 gen_helper_load_seg(cpu_env
, tcg_const_i32(seg_reg
), cpu_tmp2_i32
);
2514 /* abort translation because the addseg value may change or
2515 because ss32 may change. For R_SS, translation must always
2516 stop as a special handling must be done to disable hardware
2517 interrupts for the next instruction */
2518 if (seg_reg
== R_SS
|| (s
->code32
&& seg_reg
< R_FS
))
2519 s
->is_jmp
= DISAS_TB_JUMP
;
2521 gen_op_movl_seg_T0_vm(seg_reg
);
2522 if (seg_reg
== R_SS
)
2523 s
->is_jmp
= DISAS_TB_JUMP
;
2527 static inline int svm_is_rep(int prefixes
)
2529 return ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) ? 8 : 0);
2533 gen_svm_check_intercept_param(DisasContext
*s
, target_ulong pc_start
,
2534 uint32_t type
, uint64_t param
)
2536 /* no SVM activated; fast case */
2537 if (likely(!(s
->flags
& HF_SVMI_MASK
)))
2539 gen_update_cc_op(s
);
2540 gen_jmp_im(pc_start
- s
->cs_base
);
2541 gen_helper_svm_check_intercept_param(cpu_env
, tcg_const_i32(type
),
2542 tcg_const_i64(param
));
2546 gen_svm_check_intercept(DisasContext
*s
, target_ulong pc_start
, uint64_t type
)
2548 gen_svm_check_intercept_param(s
, pc_start
, type
, 0);
2551 static inline void gen_stack_update(DisasContext
*s
, int addend
)
2553 #ifdef TARGET_X86_64
2555 gen_op_add_reg_im(2, R_ESP
, addend
);
2559 gen_op_add_reg_im(1, R_ESP
, addend
);
2561 gen_op_add_reg_im(0, R_ESP
, addend
);
2565 /* generate a push. It depends on ss32, addseg and dflag */
2566 static void gen_push_T0(DisasContext
*s
)
2568 #ifdef TARGET_X86_64
2570 gen_op_movq_A0_reg(R_ESP
);
2572 gen_op_addq_A0_im(-8);
2573 gen_op_st_T0_A0(OT_QUAD
+ s
->mem_index
);
2575 gen_op_addq_A0_im(-2);
2576 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
2578 gen_op_mov_reg_A0(2, R_ESP
);
2582 gen_op_movl_A0_reg(R_ESP
);
2584 gen_op_addl_A0_im(-2);
2586 gen_op_addl_A0_im(-4);
2589 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2590 gen_op_addl_A0_seg(s
, R_SS
);
2593 gen_op_andl_A0_ffff();
2594 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2595 gen_op_addl_A0_seg(s
, R_SS
);
2597 gen_op_st_T0_A0(s
->dflag
+ 1 + s
->mem_index
);
2598 if (s
->ss32
&& !s
->addseg
)
2599 gen_op_mov_reg_A0(1, R_ESP
);
2601 gen_op_mov_reg_T1(s
->ss32
+ 1, R_ESP
);
2605 /* generate a push. It depends on ss32, addseg and dflag */
2606 /* slower version for T1, only used for call Ev */
2607 static void gen_push_T1(DisasContext
*s
)
2609 #ifdef TARGET_X86_64
2611 gen_op_movq_A0_reg(R_ESP
);
2613 gen_op_addq_A0_im(-8);
2614 gen_op_st_T1_A0(OT_QUAD
+ s
->mem_index
);
2616 gen_op_addq_A0_im(-2);
2617 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
2619 gen_op_mov_reg_A0(2, R_ESP
);
2623 gen_op_movl_A0_reg(R_ESP
);
2625 gen_op_addl_A0_im(-2);
2627 gen_op_addl_A0_im(-4);
2630 gen_op_addl_A0_seg(s
, R_SS
);
2633 gen_op_andl_A0_ffff();
2634 gen_op_addl_A0_seg(s
, R_SS
);
2636 gen_op_st_T1_A0(s
->dflag
+ 1 + s
->mem_index
);
2638 if (s
->ss32
&& !s
->addseg
)
2639 gen_op_mov_reg_A0(1, R_ESP
);
2641 gen_stack_update(s
, (-2) << s
->dflag
);
2645 /* two step pop is necessary for precise exceptions */
2646 static void gen_pop_T0(DisasContext
*s
)
2648 #ifdef TARGET_X86_64
2650 gen_op_movq_A0_reg(R_ESP
);
2651 gen_op_ld_T0_A0((s
->dflag
? OT_QUAD
: OT_WORD
) + s
->mem_index
);
2655 gen_op_movl_A0_reg(R_ESP
);
2658 gen_op_addl_A0_seg(s
, R_SS
);
2660 gen_op_andl_A0_ffff();
2661 gen_op_addl_A0_seg(s
, R_SS
);
2663 gen_op_ld_T0_A0(s
->dflag
+ 1 + s
->mem_index
);
2667 static void gen_pop_update(DisasContext
*s
)
2669 #ifdef TARGET_X86_64
2670 if (CODE64(s
) && s
->dflag
) {
2671 gen_stack_update(s
, 8);
2675 gen_stack_update(s
, 2 << s
->dflag
);
2679 static void gen_stack_A0(DisasContext
*s
)
2681 gen_op_movl_A0_reg(R_ESP
);
2683 gen_op_andl_A0_ffff();
2684 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2686 gen_op_addl_A0_seg(s
, R_SS
);
2689 /* NOTE: wrap around in 16 bit not fully handled */
2690 static void gen_pusha(DisasContext
*s
)
2693 gen_op_movl_A0_reg(R_ESP
);
2694 gen_op_addl_A0_im(-16 << s
->dflag
);
2696 gen_op_andl_A0_ffff();
2697 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2699 gen_op_addl_A0_seg(s
, R_SS
);
2700 for(i
= 0;i
< 8; i
++) {
2701 gen_op_mov_TN_reg(OT_LONG
, 0, 7 - i
);
2702 gen_op_st_T0_A0(OT_WORD
+ s
->dflag
+ s
->mem_index
);
2703 gen_op_addl_A0_im(2 << s
->dflag
);
2705 gen_op_mov_reg_T1(OT_WORD
+ s
->ss32
, R_ESP
);
2708 /* NOTE: wrap around in 16 bit not fully handled */
2709 static void gen_popa(DisasContext
*s
)
2712 gen_op_movl_A0_reg(R_ESP
);
2714 gen_op_andl_A0_ffff();
2715 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2716 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], 16 << s
->dflag
);
2718 gen_op_addl_A0_seg(s
, R_SS
);
2719 for(i
= 0;i
< 8; i
++) {
2720 /* ESP is not reloaded */
2722 gen_op_ld_T0_A0(OT_WORD
+ s
->dflag
+ s
->mem_index
);
2723 gen_op_mov_reg_T0(OT_WORD
+ s
->dflag
, 7 - i
);
2725 gen_op_addl_A0_im(2 << s
->dflag
);
2727 gen_op_mov_reg_T1(OT_WORD
+ s
->ss32
, R_ESP
);
2730 static void gen_enter(DisasContext
*s
, int esp_addend
, int level
)
2735 #ifdef TARGET_X86_64
2737 ot
= s
->dflag
? OT_QUAD
: OT_WORD
;
2740 gen_op_movl_A0_reg(R_ESP
);
2741 gen_op_addq_A0_im(-opsize
);
2742 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2745 gen_op_mov_TN_reg(OT_LONG
, 0, R_EBP
);
2746 gen_op_st_T0_A0(ot
+ s
->mem_index
);
2748 /* XXX: must save state */
2749 gen_helper_enter64_level(cpu_env
, tcg_const_i32(level
),
2750 tcg_const_i32((ot
== OT_QUAD
)),
2753 gen_op_mov_reg_T1(ot
, R_EBP
);
2754 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], -esp_addend
+ (-opsize
* level
));
2755 gen_op_mov_reg_T1(OT_QUAD
, R_ESP
);
2759 ot
= s
->dflag
+ OT_WORD
;
2760 opsize
= 2 << s
->dflag
;
2762 gen_op_movl_A0_reg(R_ESP
);
2763 gen_op_addl_A0_im(-opsize
);
2765 gen_op_andl_A0_ffff();
2766 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2768 gen_op_addl_A0_seg(s
, R_SS
);
2770 gen_op_mov_TN_reg(OT_LONG
, 0, R_EBP
);
2771 gen_op_st_T0_A0(ot
+ s
->mem_index
);
2773 /* XXX: must save state */
2774 gen_helper_enter_level(cpu_env
, tcg_const_i32(level
),
2775 tcg_const_i32(s
->dflag
),
2778 gen_op_mov_reg_T1(ot
, R_EBP
);
2779 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], -esp_addend
+ (-opsize
* level
));
2780 gen_op_mov_reg_T1(OT_WORD
+ s
->ss32
, R_ESP
);
2784 static void gen_exception(DisasContext
*s
, int trapno
, target_ulong cur_eip
)
2786 gen_update_cc_op(s
);
2787 gen_jmp_im(cur_eip
);
2788 gen_helper_raise_exception(cpu_env
, tcg_const_i32(trapno
));
2789 s
->is_jmp
= DISAS_TB_JUMP
;
2792 /* an interrupt is different from an exception because of the
2794 static void gen_interrupt(DisasContext
*s
, int intno
,
2795 target_ulong cur_eip
, target_ulong next_eip
)
2797 gen_update_cc_op(s
);
2798 gen_jmp_im(cur_eip
);
2799 gen_helper_raise_interrupt(cpu_env
, tcg_const_i32(intno
),
2800 tcg_const_i32(next_eip
- cur_eip
));
2801 s
->is_jmp
= DISAS_TB_JUMP
;
2804 static void gen_debug(DisasContext
*s
, target_ulong cur_eip
)
2806 gen_update_cc_op(s
);
2807 gen_jmp_im(cur_eip
);
2808 gen_helper_debug(cpu_env
);
2809 s
->is_jmp
= DISAS_TB_JUMP
;
2812 /* generate a generic end of block. Trace exception is also generated
2814 static void gen_eob(DisasContext
*s
)
2816 gen_update_cc_op(s
);
2817 if (s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
) {
2818 gen_helper_reset_inhibit_irq(cpu_env
);
2820 if (s
->tb
->flags
& HF_RF_MASK
) {
2821 gen_helper_reset_rf(cpu_env
);
2823 if (s
->singlestep_enabled
) {
2824 gen_helper_debug(cpu_env
);
2826 gen_helper_single_step(cpu_env
);
2830 s
->is_jmp
= DISAS_TB_JUMP
;
2833 /* generate a jump to eip. No segment change must happen before as a
2834 direct call to the next block may occur */
2835 static void gen_jmp_tb(DisasContext
*s
, target_ulong eip
, int tb_num
)
2837 gen_update_cc_op(s
);
2838 set_cc_op(s
, CC_OP_DYNAMIC
);
2840 gen_goto_tb(s
, tb_num
, eip
);
2841 s
->is_jmp
= DISAS_TB_JUMP
;
2848 static void gen_jmp(DisasContext
*s
, target_ulong eip
)
2850 gen_jmp_tb(s
, eip
, 0);
2853 static inline void gen_ldq_env_A0(int idx
, int offset
)
2855 int mem_index
= (idx
>> 2) - 1;
2856 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
, mem_index
);
2857 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, offset
);
2860 static inline void gen_stq_env_A0(int idx
, int offset
)
2862 int mem_index
= (idx
>> 2) - 1;
2863 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, offset
);
2864 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
, mem_index
);
2867 static inline void gen_ldo_env_A0(int idx
, int offset
)
2869 int mem_index
= (idx
>> 2) - 1;
2870 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
, mem_index
);
2871 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(0)));
2872 tcg_gen_addi_tl(cpu_tmp0
, cpu_A0
, 8);
2873 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_tmp0
, mem_index
);
2874 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(1)));
2877 static inline void gen_sto_env_A0(int idx
, int offset
)
2879 int mem_index
= (idx
>> 2) - 1;
2880 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(0)));
2881 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
, mem_index
);
2882 tcg_gen_addi_tl(cpu_tmp0
, cpu_A0
, 8);
2883 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(1)));
2884 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_tmp0
, mem_index
);
2887 static inline void gen_op_movo(int d_offset
, int s_offset
)
2889 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, s_offset
);
2890 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
);
2891 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, s_offset
+ 8);
2892 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
+ 8);
2895 static inline void gen_op_movq(int d_offset
, int s_offset
)
2897 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, s_offset
);
2898 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
);
2901 static inline void gen_op_movl(int d_offset
, int s_offset
)
2903 tcg_gen_ld_i32(cpu_tmp2_i32
, cpu_env
, s_offset
);
2904 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, d_offset
);
2907 static inline void gen_op_movq_env_0(int d_offset
)
2909 tcg_gen_movi_i64(cpu_tmp1_i64
, 0);
2910 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
);
2913 typedef void (*SSEFunc_i_ep
)(TCGv_i32 val
, TCGv_ptr env
, TCGv_ptr reg
);
2914 typedef void (*SSEFunc_l_ep
)(TCGv_i64 val
, TCGv_ptr env
, TCGv_ptr reg
);
2915 typedef void (*SSEFunc_0_epi
)(TCGv_ptr env
, TCGv_ptr reg
, TCGv_i32 val
);
2916 typedef void (*SSEFunc_0_epl
)(TCGv_ptr env
, TCGv_ptr reg
, TCGv_i64 val
);
2917 typedef void (*SSEFunc_0_epp
)(TCGv_ptr env
, TCGv_ptr reg_a
, TCGv_ptr reg_b
);
2918 typedef void (*SSEFunc_0_eppi
)(TCGv_ptr env
, TCGv_ptr reg_a
, TCGv_ptr reg_b
,
2920 typedef void (*SSEFunc_0_ppi
)(TCGv_ptr reg_a
, TCGv_ptr reg_b
, TCGv_i32 val
);
2921 typedef void (*SSEFunc_0_eppt
)(TCGv_ptr env
, TCGv_ptr reg_a
, TCGv_ptr reg_b
,
2924 #define SSE_SPECIAL ((void *)1)
2925 #define SSE_DUMMY ((void *)2)
2927 #define MMX_OP2(x) { gen_helper_ ## x ## _mmx, gen_helper_ ## x ## _xmm }
2928 #define SSE_FOP(x) { gen_helper_ ## x ## ps, gen_helper_ ## x ## pd, \
2929 gen_helper_ ## x ## ss, gen_helper_ ## x ## sd, }
2931 static const SSEFunc_0_epp sse_op_table1
[256][4] = {
2932 /* 3DNow! extensions */
2933 [0x0e] = { SSE_DUMMY
}, /* femms */
2934 [0x0f] = { SSE_DUMMY
}, /* pf... */
2935 /* pure SSE operations */
2936 [0x10] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movups, movupd, movss, movsd */
2937 [0x11] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movups, movupd, movss, movsd */
2938 [0x12] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movlps, movlpd, movsldup, movddup */
2939 [0x13] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movlps, movlpd */
2940 [0x14] = { gen_helper_punpckldq_xmm
, gen_helper_punpcklqdq_xmm
},
2941 [0x15] = { gen_helper_punpckhdq_xmm
, gen_helper_punpckhqdq_xmm
},
2942 [0x16] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movhps, movhpd, movshdup */
2943 [0x17] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movhps, movhpd */
2945 [0x28] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movaps, movapd */
2946 [0x29] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movaps, movapd */
2947 [0x2a] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */
2948 [0x2b] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movntps, movntpd, movntss, movntsd */
2949 [0x2c] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */
2950 [0x2d] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */
2951 [0x2e] = { gen_helper_ucomiss
, gen_helper_ucomisd
},
2952 [0x2f] = { gen_helper_comiss
, gen_helper_comisd
},
2953 [0x50] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movmskps, movmskpd */
2954 [0x51] = SSE_FOP(sqrt
),
2955 [0x52] = { gen_helper_rsqrtps
, NULL
, gen_helper_rsqrtss
, NULL
},
2956 [0x53] = { gen_helper_rcpps
, NULL
, gen_helper_rcpss
, NULL
},
2957 [0x54] = { gen_helper_pand_xmm
, gen_helper_pand_xmm
}, /* andps, andpd */
2958 [0x55] = { gen_helper_pandn_xmm
, gen_helper_pandn_xmm
}, /* andnps, andnpd */
2959 [0x56] = { gen_helper_por_xmm
, gen_helper_por_xmm
}, /* orps, orpd */
2960 [0x57] = { gen_helper_pxor_xmm
, gen_helper_pxor_xmm
}, /* xorps, xorpd */
2961 [0x58] = SSE_FOP(add
),
2962 [0x59] = SSE_FOP(mul
),
2963 [0x5a] = { gen_helper_cvtps2pd
, gen_helper_cvtpd2ps
,
2964 gen_helper_cvtss2sd
, gen_helper_cvtsd2ss
},
2965 [0x5b] = { gen_helper_cvtdq2ps
, gen_helper_cvtps2dq
, gen_helper_cvttps2dq
},
2966 [0x5c] = SSE_FOP(sub
),
2967 [0x5d] = SSE_FOP(min
),
2968 [0x5e] = SSE_FOP(div
),
2969 [0x5f] = SSE_FOP(max
),
2971 [0xc2] = SSE_FOP(cmpeq
),
2972 [0xc6] = { (SSEFunc_0_epp
)gen_helper_shufps
,
2973 (SSEFunc_0_epp
)gen_helper_shufpd
}, /* XXX: casts */
2975 [0x38] = { SSE_SPECIAL
, SSE_SPECIAL
, NULL
, SSE_SPECIAL
}, /* SSSE3/SSE4 */
2976 [0x3a] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* SSSE3/SSE4 */
2978 /* MMX ops and their SSE extensions */
2979 [0x60] = MMX_OP2(punpcklbw
),
2980 [0x61] = MMX_OP2(punpcklwd
),
2981 [0x62] = MMX_OP2(punpckldq
),
2982 [0x63] = MMX_OP2(packsswb
),
2983 [0x64] = MMX_OP2(pcmpgtb
),
2984 [0x65] = MMX_OP2(pcmpgtw
),
2985 [0x66] = MMX_OP2(pcmpgtl
),
2986 [0x67] = MMX_OP2(packuswb
),
2987 [0x68] = MMX_OP2(punpckhbw
),
2988 [0x69] = MMX_OP2(punpckhwd
),
2989 [0x6a] = MMX_OP2(punpckhdq
),
2990 [0x6b] = MMX_OP2(packssdw
),
2991 [0x6c] = { NULL
, gen_helper_punpcklqdq_xmm
},
2992 [0x6d] = { NULL
, gen_helper_punpckhqdq_xmm
},
2993 [0x6e] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movd mm, ea */
2994 [0x6f] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movq, movdqa, , movqdu */
2995 [0x70] = { (SSEFunc_0_epp
)gen_helper_pshufw_mmx
,
2996 (SSEFunc_0_epp
)gen_helper_pshufd_xmm
,
2997 (SSEFunc_0_epp
)gen_helper_pshufhw_xmm
,
2998 (SSEFunc_0_epp
)gen_helper_pshuflw_xmm
}, /* XXX: casts */
2999 [0x71] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* shiftw */
3000 [0x72] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* shiftd */
3001 [0x73] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* shiftq */
3002 [0x74] = MMX_OP2(pcmpeqb
),
3003 [0x75] = MMX_OP2(pcmpeqw
),
3004 [0x76] = MMX_OP2(pcmpeql
),
3005 [0x77] = { SSE_DUMMY
}, /* emms */
3006 [0x78] = { NULL
, SSE_SPECIAL
, NULL
, SSE_SPECIAL
}, /* extrq_i, insertq_i */
3007 [0x79] = { NULL
, gen_helper_extrq_r
, NULL
, gen_helper_insertq_r
},
3008 [0x7c] = { NULL
, gen_helper_haddpd
, NULL
, gen_helper_haddps
},
3009 [0x7d] = { NULL
, gen_helper_hsubpd
, NULL
, gen_helper_hsubps
},
3010 [0x7e] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movd, movd, , movq */
3011 [0x7f] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movq, movdqa, movdqu */
3012 [0xc4] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* pinsrw */
3013 [0xc5] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* pextrw */
3014 [0xd0] = { NULL
, gen_helper_addsubpd
, NULL
, gen_helper_addsubps
},
3015 [0xd1] = MMX_OP2(psrlw
),
3016 [0xd2] = MMX_OP2(psrld
),
3017 [0xd3] = MMX_OP2(psrlq
),
3018 [0xd4] = MMX_OP2(paddq
),
3019 [0xd5] = MMX_OP2(pmullw
),
3020 [0xd6] = { NULL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
},
3021 [0xd7] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* pmovmskb */
3022 [0xd8] = MMX_OP2(psubusb
),
3023 [0xd9] = MMX_OP2(psubusw
),
3024 [0xda] = MMX_OP2(pminub
),
3025 [0xdb] = MMX_OP2(pand
),
3026 [0xdc] = MMX_OP2(paddusb
),
3027 [0xdd] = MMX_OP2(paddusw
),
3028 [0xde] = MMX_OP2(pmaxub
),
3029 [0xdf] = MMX_OP2(pandn
),
3030 [0xe0] = MMX_OP2(pavgb
),
3031 [0xe1] = MMX_OP2(psraw
),
3032 [0xe2] = MMX_OP2(psrad
),
3033 [0xe3] = MMX_OP2(pavgw
),
3034 [0xe4] = MMX_OP2(pmulhuw
),
3035 [0xe5] = MMX_OP2(pmulhw
),
3036 [0xe6] = { NULL
, gen_helper_cvttpd2dq
, gen_helper_cvtdq2pd
, gen_helper_cvtpd2dq
},
3037 [0xe7] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movntq, movntq */
3038 [0xe8] = MMX_OP2(psubsb
),
3039 [0xe9] = MMX_OP2(psubsw
),
3040 [0xea] = MMX_OP2(pminsw
),
3041 [0xeb] = MMX_OP2(por
),
3042 [0xec] = MMX_OP2(paddsb
),
3043 [0xed] = MMX_OP2(paddsw
),
3044 [0xee] = MMX_OP2(pmaxsw
),
3045 [0xef] = MMX_OP2(pxor
),
3046 [0xf0] = { NULL
, NULL
, NULL
, SSE_SPECIAL
}, /* lddqu */
3047 [0xf1] = MMX_OP2(psllw
),
3048 [0xf2] = MMX_OP2(pslld
),
3049 [0xf3] = MMX_OP2(psllq
),
3050 [0xf4] = MMX_OP2(pmuludq
),
3051 [0xf5] = MMX_OP2(pmaddwd
),
3052 [0xf6] = MMX_OP2(psadbw
),
3053 [0xf7] = { (SSEFunc_0_epp
)gen_helper_maskmov_mmx
,
3054 (SSEFunc_0_epp
)gen_helper_maskmov_xmm
}, /* XXX: casts */
3055 [0xf8] = MMX_OP2(psubb
),
3056 [0xf9] = MMX_OP2(psubw
),
3057 [0xfa] = MMX_OP2(psubl
),
3058 [0xfb] = MMX_OP2(psubq
),
3059 [0xfc] = MMX_OP2(paddb
),
3060 [0xfd] = MMX_OP2(paddw
),
3061 [0xfe] = MMX_OP2(paddl
),
3064 static const SSEFunc_0_epp sse_op_table2
[3 * 8][2] = {
3065 [0 + 2] = MMX_OP2(psrlw
),
3066 [0 + 4] = MMX_OP2(psraw
),
3067 [0 + 6] = MMX_OP2(psllw
),
3068 [8 + 2] = MMX_OP2(psrld
),
3069 [8 + 4] = MMX_OP2(psrad
),
3070 [8 + 6] = MMX_OP2(pslld
),
3071 [16 + 2] = MMX_OP2(psrlq
),
3072 [16 + 3] = { NULL
, gen_helper_psrldq_xmm
},
3073 [16 + 6] = MMX_OP2(psllq
),
3074 [16 + 7] = { NULL
, gen_helper_pslldq_xmm
},
3077 static const SSEFunc_0_epi sse_op_table3ai
[] = {
3078 gen_helper_cvtsi2ss
,
3082 #ifdef TARGET_X86_64
3083 static const SSEFunc_0_epl sse_op_table3aq
[] = {
3084 gen_helper_cvtsq2ss
,
3089 static const SSEFunc_i_ep sse_op_table3bi
[] = {
3090 gen_helper_cvttss2si
,
3091 gen_helper_cvtss2si
,
3092 gen_helper_cvttsd2si
,
3096 #ifdef TARGET_X86_64
3097 static const SSEFunc_l_ep sse_op_table3bq
[] = {
3098 gen_helper_cvttss2sq
,
3099 gen_helper_cvtss2sq
,
3100 gen_helper_cvttsd2sq
,
3105 static const SSEFunc_0_epp sse_op_table4
[8][4] = {
3116 static const SSEFunc_0_epp sse_op_table5
[256] = {
3117 [0x0c] = gen_helper_pi2fw
,
3118 [0x0d] = gen_helper_pi2fd
,
3119 [0x1c] = gen_helper_pf2iw
,
3120 [0x1d] = gen_helper_pf2id
,
3121 [0x8a] = gen_helper_pfnacc
,
3122 [0x8e] = gen_helper_pfpnacc
,
3123 [0x90] = gen_helper_pfcmpge
,
3124 [0x94] = gen_helper_pfmin
,
3125 [0x96] = gen_helper_pfrcp
,
3126 [0x97] = gen_helper_pfrsqrt
,
3127 [0x9a] = gen_helper_pfsub
,
3128 [0x9e] = gen_helper_pfadd
,
3129 [0xa0] = gen_helper_pfcmpgt
,
3130 [0xa4] = gen_helper_pfmax
,
3131 [0xa6] = gen_helper_movq
, /* pfrcpit1; no need to actually increase precision */
3132 [0xa7] = gen_helper_movq
, /* pfrsqit1 */
3133 [0xaa] = gen_helper_pfsubr
,
3134 [0xae] = gen_helper_pfacc
,
3135 [0xb0] = gen_helper_pfcmpeq
,
3136 [0xb4] = gen_helper_pfmul
,
3137 [0xb6] = gen_helper_movq
, /* pfrcpit2 */
3138 [0xb7] = gen_helper_pmulhrw_mmx
,
3139 [0xbb] = gen_helper_pswapd
,
3140 [0xbf] = gen_helper_pavgb_mmx
/* pavgusb */
3143 struct SSEOpHelper_epp
{
3144 SSEFunc_0_epp op
[2];
3148 struct SSEOpHelper_eppi
{
3149 SSEFunc_0_eppi op
[2];
3153 #define SSSE3_OP(x) { MMX_OP2(x), CPUID_EXT_SSSE3 }
3154 #define SSE41_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE41 }
3155 #define SSE42_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE42 }
3156 #define SSE41_SPECIAL { { NULL, SSE_SPECIAL }, CPUID_EXT_SSE41 }
3158 static const struct SSEOpHelper_epp sse_op_table6
[256] = {
3159 [0x00] = SSSE3_OP(pshufb
),
3160 [0x01] = SSSE3_OP(phaddw
),
3161 [0x02] = SSSE3_OP(phaddd
),
3162 [0x03] = SSSE3_OP(phaddsw
),
3163 [0x04] = SSSE3_OP(pmaddubsw
),
3164 [0x05] = SSSE3_OP(phsubw
),
3165 [0x06] = SSSE3_OP(phsubd
),
3166 [0x07] = SSSE3_OP(phsubsw
),
3167 [0x08] = SSSE3_OP(psignb
),
3168 [0x09] = SSSE3_OP(psignw
),
3169 [0x0a] = SSSE3_OP(psignd
),
3170 [0x0b] = SSSE3_OP(pmulhrsw
),
3171 [0x10] = SSE41_OP(pblendvb
),
3172 [0x14] = SSE41_OP(blendvps
),
3173 [0x15] = SSE41_OP(blendvpd
),
3174 [0x17] = SSE41_OP(ptest
),
3175 [0x1c] = SSSE3_OP(pabsb
),
3176 [0x1d] = SSSE3_OP(pabsw
),
3177 [0x1e] = SSSE3_OP(pabsd
),
3178 [0x20] = SSE41_OP(pmovsxbw
),
3179 [0x21] = SSE41_OP(pmovsxbd
),
3180 [0x22] = SSE41_OP(pmovsxbq
),
3181 [0x23] = SSE41_OP(pmovsxwd
),
3182 [0x24] = SSE41_OP(pmovsxwq
),
3183 [0x25] = SSE41_OP(pmovsxdq
),
3184 [0x28] = SSE41_OP(pmuldq
),
3185 [0x29] = SSE41_OP(pcmpeqq
),
3186 [0x2a] = SSE41_SPECIAL
, /* movntqda */
3187 [0x2b] = SSE41_OP(packusdw
),
3188 [0x30] = SSE41_OP(pmovzxbw
),
3189 [0x31] = SSE41_OP(pmovzxbd
),
3190 [0x32] = SSE41_OP(pmovzxbq
),
3191 [0x33] = SSE41_OP(pmovzxwd
),
3192 [0x34] = SSE41_OP(pmovzxwq
),
3193 [0x35] = SSE41_OP(pmovzxdq
),
3194 [0x37] = SSE42_OP(pcmpgtq
),
3195 [0x38] = SSE41_OP(pminsb
),
3196 [0x39] = SSE41_OP(pminsd
),
3197 [0x3a] = SSE41_OP(pminuw
),
3198 [0x3b] = SSE41_OP(pminud
),
3199 [0x3c] = SSE41_OP(pmaxsb
),
3200 [0x3d] = SSE41_OP(pmaxsd
),
3201 [0x3e] = SSE41_OP(pmaxuw
),
3202 [0x3f] = SSE41_OP(pmaxud
),
3203 [0x40] = SSE41_OP(pmulld
),
3204 [0x41] = SSE41_OP(phminposuw
),
3207 static const struct SSEOpHelper_eppi sse_op_table7
[256] = {
3208 [0x08] = SSE41_OP(roundps
),
3209 [0x09] = SSE41_OP(roundpd
),
3210 [0x0a] = SSE41_OP(roundss
),
3211 [0x0b] = SSE41_OP(roundsd
),
3212 [0x0c] = SSE41_OP(blendps
),
3213 [0x0d] = SSE41_OP(blendpd
),
3214 [0x0e] = SSE41_OP(pblendw
),
3215 [0x0f] = SSSE3_OP(palignr
),
3216 [0x14] = SSE41_SPECIAL
, /* pextrb */
3217 [0x15] = SSE41_SPECIAL
, /* pextrw */
3218 [0x16] = SSE41_SPECIAL
, /* pextrd/pextrq */
3219 [0x17] = SSE41_SPECIAL
, /* extractps */
3220 [0x20] = SSE41_SPECIAL
, /* pinsrb */
3221 [0x21] = SSE41_SPECIAL
, /* insertps */
3222 [0x22] = SSE41_SPECIAL
, /* pinsrd/pinsrq */
3223 [0x40] = SSE41_OP(dpps
),
3224 [0x41] = SSE41_OP(dppd
),
3225 [0x42] = SSE41_OP(mpsadbw
),
3226 [0x60] = SSE42_OP(pcmpestrm
),
3227 [0x61] = SSE42_OP(pcmpestri
),
3228 [0x62] = SSE42_OP(pcmpistrm
),
3229 [0x63] = SSE42_OP(pcmpistri
),
3232 static void gen_sse(CPUX86State
*env
, DisasContext
*s
, int b
,
3233 target_ulong pc_start
, int rex_r
)
3235 int b1
, op1_offset
, op2_offset
, is_xmm
, val
, ot
;
3236 int modrm
, mod
, rm
, reg
, reg_addr
, offset_addr
;
3237 SSEFunc_0_epp sse_fn_epp
;
3238 SSEFunc_0_eppi sse_fn_eppi
;
3239 SSEFunc_0_ppi sse_fn_ppi
;
3240 SSEFunc_0_eppt sse_fn_eppt
;
3243 if (s
->prefix
& PREFIX_DATA
)
3245 else if (s
->prefix
& PREFIX_REPZ
)
3247 else if (s
->prefix
& PREFIX_REPNZ
)
3251 sse_fn_epp
= sse_op_table1
[b
][b1
];
3255 if ((b
<= 0x5f && b
>= 0x10) || b
== 0xc6 || b
== 0xc2) {
3265 /* simple MMX/SSE operation */
3266 if (s
->flags
& HF_TS_MASK
) {
3267 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
3270 if (s
->flags
& HF_EM_MASK
) {
3272 gen_exception(s
, EXCP06_ILLOP
, pc_start
- s
->cs_base
);
3275 if (is_xmm
&& !(s
->flags
& HF_OSFXSR_MASK
))
3276 if ((b
!= 0x38 && b
!= 0x3a) || (s
->prefix
& PREFIX_DATA
))
3279 if (!(s
->cpuid_ext2_features
& CPUID_EXT2_3DNOW
))
3282 gen_helper_emms(cpu_env
);
3287 gen_helper_emms(cpu_env
);
3290 /* prepare MMX state (XXX: optimize by storing fptt and fptags in
3291 the static cpu state) */
3293 gen_helper_enter_mmx(cpu_env
);
3296 modrm
= cpu_ldub_code(env
, s
->pc
++);
3297 reg
= ((modrm
>> 3) & 7);
3300 mod
= (modrm
>> 6) & 3;
3301 if (sse_fn_epp
== SSE_SPECIAL
) {
3304 case 0x0e7: /* movntq */
3307 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3308 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3310 case 0x1e7: /* movntdq */
3311 case 0x02b: /* movntps */
3312 case 0x12b: /* movntps */
3315 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3316 gen_sto_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3318 case 0x3f0: /* lddqu */
3321 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3322 gen_ldo_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3324 case 0x22b: /* movntss */
3325 case 0x32b: /* movntsd */
3328 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3330 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,
3333 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
3334 xmm_regs
[reg
].XMM_L(0)));
3335 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
3338 case 0x6e: /* movd mm, ea */
3339 #ifdef TARGET_X86_64
3340 if (s
->dflag
== 2) {
3341 gen_ldst_modrm(env
, s
, modrm
, OT_QUAD
, OR_TMP0
, 0);
3342 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3346 gen_ldst_modrm(env
, s
, modrm
, OT_LONG
, OR_TMP0
, 0);
3347 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3348 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3349 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3350 gen_helper_movl_mm_T0_mmx(cpu_ptr0
, cpu_tmp2_i32
);
3353 case 0x16e: /* movd xmm, ea */
3354 #ifdef TARGET_X86_64
3355 if (s
->dflag
== 2) {
3356 gen_ldst_modrm(env
, s
, modrm
, OT_QUAD
, OR_TMP0
, 0);
3357 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3358 offsetof(CPUX86State
,xmm_regs
[reg
]));
3359 gen_helper_movq_mm_T0_xmm(cpu_ptr0
, cpu_T
[0]);
3363 gen_ldst_modrm(env
, s
, modrm
, OT_LONG
, OR_TMP0
, 0);
3364 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3365 offsetof(CPUX86State
,xmm_regs
[reg
]));
3366 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3367 gen_helper_movl_mm_T0_xmm(cpu_ptr0
, cpu_tmp2_i32
);
3370 case 0x6f: /* movq mm, ea */
3372 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3373 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3376 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
,
3377 offsetof(CPUX86State
,fpregs
[rm
].mmx
));
3378 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
,
3379 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3382 case 0x010: /* movups */
3383 case 0x110: /* movupd */
3384 case 0x028: /* movaps */
3385 case 0x128: /* movapd */
3386 case 0x16f: /* movdqa xmm, ea */
3387 case 0x26f: /* movdqu xmm, ea */
3389 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3390 gen_ldo_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3392 rm
= (modrm
& 7) | REX_B(s
);
3393 gen_op_movo(offsetof(CPUX86State
,xmm_regs
[reg
]),
3394 offsetof(CPUX86State
,xmm_regs
[rm
]));
3397 case 0x210: /* movss xmm, ea */
3399 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3400 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
3401 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3403 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)));
3404 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)));
3405 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)));
3407 rm
= (modrm
& 7) | REX_B(s
);
3408 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)),
3409 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(0)));
3412 case 0x310: /* movsd xmm, ea */
3414 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3415 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3417 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)));
3418 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)));
3420 rm
= (modrm
& 7) | REX_B(s
);
3421 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3422 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3425 case 0x012: /* movlps */
3426 case 0x112: /* movlpd */
3428 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3429 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3432 rm
= (modrm
& 7) | REX_B(s
);
3433 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3434 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(1)));
3437 case 0x212: /* movsldup */
3439 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3440 gen_ldo_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3442 rm
= (modrm
& 7) | REX_B(s
);
3443 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)),
3444 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(0)));
3445 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)),
3446 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(2)));
3448 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)),
3449 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3450 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)),
3451 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)));
3453 case 0x312: /* movddup */
3455 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3456 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3458 rm
= (modrm
& 7) | REX_B(s
);
3459 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3460 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3462 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)),
3463 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3465 case 0x016: /* movhps */
3466 case 0x116: /* movhpd */
3468 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3469 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3472 rm
= (modrm
& 7) | REX_B(s
);
3473 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)),
3474 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3477 case 0x216: /* movshdup */
3479 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3480 gen_ldo_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3482 rm
= (modrm
& 7) | REX_B(s
);
3483 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)),
3484 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(1)));
3485 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)),
3486 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(3)));
3488 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)),
3489 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)));
3490 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)),
3491 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)));
3496 int bit_index
, field_length
;
3498 if (b1
== 1 && reg
!= 0)
3500 field_length
= cpu_ldub_code(env
, s
->pc
++) & 0x3F;
3501 bit_index
= cpu_ldub_code(env
, s
->pc
++) & 0x3F;
3502 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3503 offsetof(CPUX86State
,xmm_regs
[reg
]));
3505 gen_helper_extrq_i(cpu_env
, cpu_ptr0
,
3506 tcg_const_i32(bit_index
),
3507 tcg_const_i32(field_length
));
3509 gen_helper_insertq_i(cpu_env
, cpu_ptr0
,
3510 tcg_const_i32(bit_index
),
3511 tcg_const_i32(field_length
));
3514 case 0x7e: /* movd ea, mm */
3515 #ifdef TARGET_X86_64
3516 if (s
->dflag
== 2) {
3517 tcg_gen_ld_i64(cpu_T
[0], cpu_env
,
3518 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3519 gen_ldst_modrm(env
, s
, modrm
, OT_QUAD
, OR_TMP0
, 1);
3523 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
,
3524 offsetof(CPUX86State
,fpregs
[reg
].mmx
.MMX_L(0)));
3525 gen_ldst_modrm(env
, s
, modrm
, OT_LONG
, OR_TMP0
, 1);
3528 case 0x17e: /* movd ea, xmm */
3529 #ifdef TARGET_X86_64
3530 if (s
->dflag
== 2) {
3531 tcg_gen_ld_i64(cpu_T
[0], cpu_env
,
3532 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3533 gen_ldst_modrm(env
, s
, modrm
, OT_QUAD
, OR_TMP0
, 1);
3537 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
,
3538 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3539 gen_ldst_modrm(env
, s
, modrm
, OT_LONG
, OR_TMP0
, 1);
3542 case 0x27e: /* movq xmm, ea */
3544 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3545 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3547 rm
= (modrm
& 7) | REX_B(s
);
3548 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3549 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3551 gen_op_movq_env_0(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3553 case 0x7f: /* movq ea, mm */
3555 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3556 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3559 gen_op_movq(offsetof(CPUX86State
,fpregs
[rm
].mmx
),
3560 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3563 case 0x011: /* movups */
3564 case 0x111: /* movupd */
3565 case 0x029: /* movaps */
3566 case 0x129: /* movapd */
3567 case 0x17f: /* movdqa ea, xmm */
3568 case 0x27f: /* movdqu ea, xmm */
3570 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3571 gen_sto_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3573 rm
= (modrm
& 7) | REX_B(s
);
3574 gen_op_movo(offsetof(CPUX86State
,xmm_regs
[rm
]),
3575 offsetof(CPUX86State
,xmm_regs
[reg
]));
3578 case 0x211: /* movss ea, xmm */
3580 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3581 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3582 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
3584 rm
= (modrm
& 7) | REX_B(s
);
3585 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(0)),
3586 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3589 case 0x311: /* movsd ea, xmm */
3591 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3592 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3594 rm
= (modrm
& 7) | REX_B(s
);
3595 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)),
3596 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3599 case 0x013: /* movlps */
3600 case 0x113: /* movlpd */
3602 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3603 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3608 case 0x017: /* movhps */
3609 case 0x117: /* movhpd */
3611 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3612 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3617 case 0x71: /* shift mm, im */
3620 case 0x171: /* shift xmm, im */
3626 val
= cpu_ldub_code(env
, s
->pc
++);
3628 gen_op_movl_T0_im(val
);
3629 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(0)));
3631 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(1)));
3632 op1_offset
= offsetof(CPUX86State
,xmm_t0
);
3634 gen_op_movl_T0_im(val
);
3635 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,mmx_t0
.MMX_L(0)));
3637 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,mmx_t0
.MMX_L(1)));
3638 op1_offset
= offsetof(CPUX86State
,mmx_t0
);
3640 sse_fn_epp
= sse_op_table2
[((b
- 1) & 3) * 8 +
3641 (((modrm
>> 3)) & 7)][b1
];
3646 rm
= (modrm
& 7) | REX_B(s
);
3647 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3650 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3652 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op2_offset
);
3653 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op1_offset
);
3654 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3656 case 0x050: /* movmskps */
3657 rm
= (modrm
& 7) | REX_B(s
);
3658 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3659 offsetof(CPUX86State
,xmm_regs
[rm
]));
3660 gen_helper_movmskps(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3661 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3662 gen_op_mov_reg_T0(OT_LONG
, reg
);
3664 case 0x150: /* movmskpd */
3665 rm
= (modrm
& 7) | REX_B(s
);
3666 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3667 offsetof(CPUX86State
,xmm_regs
[rm
]));
3668 gen_helper_movmskpd(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3669 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3670 gen_op_mov_reg_T0(OT_LONG
, reg
);
3672 case 0x02a: /* cvtpi2ps */
3673 case 0x12a: /* cvtpi2pd */
3674 gen_helper_enter_mmx(cpu_env
);
3676 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3677 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
3678 gen_ldq_env_A0(s
->mem_index
, op2_offset
);
3681 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3683 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3684 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3685 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3688 gen_helper_cvtpi2ps(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3692 gen_helper_cvtpi2pd(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3696 case 0x22a: /* cvtsi2ss */
3697 case 0x32a: /* cvtsi2sd */
3698 ot
= (s
->dflag
== 2) ? OT_QUAD
: OT_LONG
;
3699 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3700 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3701 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3702 if (ot
== OT_LONG
) {
3703 SSEFunc_0_epi sse_fn_epi
= sse_op_table3ai
[(b
>> 8) & 1];
3704 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3705 sse_fn_epi(cpu_env
, cpu_ptr0
, cpu_tmp2_i32
);
3707 #ifdef TARGET_X86_64
3708 SSEFunc_0_epl sse_fn_epl
= sse_op_table3aq
[(b
>> 8) & 1];
3709 sse_fn_epl(cpu_env
, cpu_ptr0
, cpu_T
[0]);
3715 case 0x02c: /* cvttps2pi */
3716 case 0x12c: /* cvttpd2pi */
3717 case 0x02d: /* cvtps2pi */
3718 case 0x12d: /* cvtpd2pi */
3719 gen_helper_enter_mmx(cpu_env
);
3721 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3722 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3723 gen_ldo_env_A0(s
->mem_index
, op2_offset
);
3725 rm
= (modrm
& 7) | REX_B(s
);
3726 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3728 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
& 7].mmx
);
3729 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3730 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3733 gen_helper_cvttps2pi(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3736 gen_helper_cvttpd2pi(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3739 gen_helper_cvtps2pi(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3742 gen_helper_cvtpd2pi(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3746 case 0x22c: /* cvttss2si */
3747 case 0x32c: /* cvttsd2si */
3748 case 0x22d: /* cvtss2si */
3749 case 0x32d: /* cvtsd2si */
3750 ot
= (s
->dflag
== 2) ? OT_QUAD
: OT_LONG
;
3752 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3754 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_t0
.XMM_Q(0)));
3756 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
3757 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(0)));
3759 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3761 rm
= (modrm
& 7) | REX_B(s
);
3762 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3764 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op2_offset
);
3765 if (ot
== OT_LONG
) {
3766 SSEFunc_i_ep sse_fn_i_ep
=
3767 sse_op_table3bi
[((b
>> 7) & 2) | (b
& 1)];
3768 sse_fn_i_ep(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3769 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3771 #ifdef TARGET_X86_64
3772 SSEFunc_l_ep sse_fn_l_ep
=
3773 sse_op_table3bq
[((b
>> 7) & 2) | (b
& 1)];
3774 sse_fn_l_ep(cpu_T
[0], cpu_env
, cpu_ptr0
);
3779 gen_op_mov_reg_T0(ot
, reg
);
3781 case 0xc4: /* pinsrw */
3784 gen_ldst_modrm(env
, s
, modrm
, OT_WORD
, OR_TMP0
, 0);
3785 val
= cpu_ldub_code(env
, s
->pc
++);
3788 tcg_gen_st16_tl(cpu_T
[0], cpu_env
,
3789 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_W(val
)));
3792 tcg_gen_st16_tl(cpu_T
[0], cpu_env
,
3793 offsetof(CPUX86State
,fpregs
[reg
].mmx
.MMX_W(val
)));
3796 case 0xc5: /* pextrw */
3800 ot
= (s
->dflag
== 2) ? OT_QUAD
: OT_LONG
;
3801 val
= cpu_ldub_code(env
, s
->pc
++);
3804 rm
= (modrm
& 7) | REX_B(s
);
3805 tcg_gen_ld16u_tl(cpu_T
[0], cpu_env
,
3806 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_W(val
)));
3810 tcg_gen_ld16u_tl(cpu_T
[0], cpu_env
,
3811 offsetof(CPUX86State
,fpregs
[rm
].mmx
.MMX_W(val
)));
3813 reg
= ((modrm
>> 3) & 7) | rex_r
;
3814 gen_op_mov_reg_T0(ot
, reg
);
3816 case 0x1d6: /* movq ea, xmm */
3818 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3819 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3821 rm
= (modrm
& 7) | REX_B(s
);
3822 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)),
3823 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3824 gen_op_movq_env_0(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(1)));
3827 case 0x2d6: /* movq2dq */
3828 gen_helper_enter_mmx(cpu_env
);
3830 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3831 offsetof(CPUX86State
,fpregs
[rm
].mmx
));
3832 gen_op_movq_env_0(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3834 case 0x3d6: /* movdq2q */
3835 gen_helper_enter_mmx(cpu_env
);
3836 rm
= (modrm
& 7) | REX_B(s
);
3837 gen_op_movq(offsetof(CPUX86State
,fpregs
[reg
& 7].mmx
),
3838 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3840 case 0xd7: /* pmovmskb */
3845 rm
= (modrm
& 7) | REX_B(s
);
3846 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, offsetof(CPUX86State
,xmm_regs
[rm
]));
3847 gen_helper_pmovmskb_xmm(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3850 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, offsetof(CPUX86State
,fpregs
[rm
].mmx
));
3851 gen_helper_pmovmskb_mmx(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3853 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3854 reg
= ((modrm
>> 3) & 7) | rex_r
;
3855 gen_op_mov_reg_T0(OT_LONG
, reg
);
3858 if (s
->prefix
& PREFIX_REPNZ
)
3862 modrm
= cpu_ldub_code(env
, s
->pc
++);
3864 reg
= ((modrm
>> 3) & 7) | rex_r
;
3865 mod
= (modrm
>> 6) & 3;
3870 sse_fn_epp
= sse_op_table6
[b
].op
[b1
];
3874 if (!(s
->cpuid_ext_features
& sse_op_table6
[b
].ext_mask
))
3878 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3880 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
| REX_B(s
)]);
3882 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3883 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3885 case 0x20: case 0x30: /* pmovsxbw, pmovzxbw */
3886 case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */
3887 case 0x25: case 0x35: /* pmovsxdq, pmovzxdq */
3888 gen_ldq_env_A0(s
->mem_index
, op2_offset
+
3889 offsetof(XMMReg
, XMM_Q(0)));
3891 case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */
3892 case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */
3893 tcg_gen_qemu_ld32u(cpu_tmp0
, cpu_A0
,
3894 (s
->mem_index
>> 2) - 1);
3895 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_tmp0
);
3896 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, op2_offset
+
3897 offsetof(XMMReg
, XMM_L(0)));
3899 case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */
3900 tcg_gen_qemu_ld16u(cpu_tmp0
, cpu_A0
,
3901 (s
->mem_index
>> 2) - 1);
3902 tcg_gen_st16_tl(cpu_tmp0
, cpu_env
, op2_offset
+
3903 offsetof(XMMReg
, XMM_W(0)));
3905 case 0x2a: /* movntqda */
3906 gen_ldo_env_A0(s
->mem_index
, op1_offset
);
3909 gen_ldo_env_A0(s
->mem_index
, op2_offset
);
3913 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
].mmx
);
3915 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3917 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
3918 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3919 gen_ldq_env_A0(s
->mem_index
, op2_offset
);
3922 if (sse_fn_epp
== SSE_SPECIAL
) {
3926 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3927 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3928 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3931 set_cc_op(s
, CC_OP_EFLAGS
);
3934 case 0x338: /* crc32 */
3937 modrm
= cpu_ldub_code(env
, s
->pc
++);
3938 reg
= ((modrm
>> 3) & 7) | rex_r
;
3940 if (b
!= 0xf0 && b
!= 0xf1)
3942 if (!(s
->cpuid_ext_features
& CPUID_EXT_SSE42
))
3947 else if (b
== 0xf1 && s
->dflag
!= 2)
3948 if (s
->prefix
& PREFIX_DATA
)
3955 gen_op_mov_TN_reg(OT_LONG
, 0, reg
);
3956 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3957 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3958 gen_helper_crc32(cpu_T
[0], cpu_tmp2_i32
,
3959 cpu_T
[0], tcg_const_i32(8 << ot
));
3961 ot
= (s
->dflag
== 2) ? OT_QUAD
: OT_LONG
;
3962 gen_op_mov_reg_T0(ot
, reg
);
3967 modrm
= cpu_ldub_code(env
, s
->pc
++);
3969 reg
= ((modrm
>> 3) & 7) | rex_r
;
3970 mod
= (modrm
>> 6) & 3;
3975 sse_fn_eppi
= sse_op_table7
[b
].op
[b1
];
3979 if (!(s
->cpuid_ext_features
& sse_op_table7
[b
].ext_mask
))
3982 if (sse_fn_eppi
== SSE_SPECIAL
) {
3983 ot
= (s
->dflag
== 2) ? OT_QUAD
: OT_LONG
;
3984 rm
= (modrm
& 7) | REX_B(s
);
3986 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3987 reg
= ((modrm
>> 3) & 7) | rex_r
;
3988 val
= cpu_ldub_code(env
, s
->pc
++);
3990 case 0x14: /* pextrb */
3991 tcg_gen_ld8u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
3992 xmm_regs
[reg
].XMM_B(val
& 15)));
3994 gen_op_mov_reg_T0(ot
, rm
);
3996 tcg_gen_qemu_st8(cpu_T
[0], cpu_A0
,
3997 (s
->mem_index
>> 2) - 1);
3999 case 0x15: /* pextrw */
4000 tcg_gen_ld16u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
4001 xmm_regs
[reg
].XMM_W(val
& 7)));
4003 gen_op_mov_reg_T0(ot
, rm
);
4005 tcg_gen_qemu_st16(cpu_T
[0], cpu_A0
,
4006 (s
->mem_index
>> 2) - 1);
4009 if (ot
== OT_LONG
) { /* pextrd */
4010 tcg_gen_ld_i32(cpu_tmp2_i32
, cpu_env
,
4011 offsetof(CPUX86State
,
4012 xmm_regs
[reg
].XMM_L(val
& 3)));
4013 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
4015 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
4017 tcg_gen_qemu_st32(cpu_T
[0], cpu_A0
,
4018 (s
->mem_index
>> 2) - 1);
4019 } else { /* pextrq */
4020 #ifdef TARGET_X86_64
4021 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
,
4022 offsetof(CPUX86State
,
4023 xmm_regs
[reg
].XMM_Q(val
& 1)));
4025 gen_op_mov_reg_v(ot
, rm
, cpu_tmp1_i64
);
4027 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
,
4028 (s
->mem_index
>> 2) - 1);
4034 case 0x17: /* extractps */
4035 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
4036 xmm_regs
[reg
].XMM_L(val
& 3)));
4038 gen_op_mov_reg_T0(ot
, rm
);
4040 tcg_gen_qemu_st32(cpu_T
[0], cpu_A0
,
4041 (s
->mem_index
>> 2) - 1);
4043 case 0x20: /* pinsrb */
4045 gen_op_mov_TN_reg(OT_LONG
, 0, rm
);
4047 tcg_gen_qemu_ld8u(cpu_tmp0
, cpu_A0
,
4048 (s
->mem_index
>> 2) - 1);
4049 tcg_gen_st8_tl(cpu_tmp0
, cpu_env
, offsetof(CPUX86State
,
4050 xmm_regs
[reg
].XMM_B(val
& 15)));
4052 case 0x21: /* insertps */
4054 tcg_gen_ld_i32(cpu_tmp2_i32
, cpu_env
,
4055 offsetof(CPUX86State
,xmm_regs
[rm
]
4056 .XMM_L((val
>> 6) & 3)));
4058 tcg_gen_qemu_ld32u(cpu_tmp0
, cpu_A0
,
4059 (s
->mem_index
>> 2) - 1);
4060 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_tmp0
);
4062 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
,
4063 offsetof(CPUX86State
,xmm_regs
[reg
]
4064 .XMM_L((val
>> 4) & 3)));
4066 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4067 cpu_env
, offsetof(CPUX86State
,
4068 xmm_regs
[reg
].XMM_L(0)));
4070 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4071 cpu_env
, offsetof(CPUX86State
,
4072 xmm_regs
[reg
].XMM_L(1)));
4074 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4075 cpu_env
, offsetof(CPUX86State
,
4076 xmm_regs
[reg
].XMM_L(2)));
4078 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4079 cpu_env
, offsetof(CPUX86State
,
4080 xmm_regs
[reg
].XMM_L(3)));
4083 if (ot
== OT_LONG
) { /* pinsrd */
4085 gen_op_mov_v_reg(ot
, cpu_tmp0
, rm
);
4087 tcg_gen_qemu_ld32u(cpu_tmp0
, cpu_A0
,
4088 (s
->mem_index
>> 2) - 1);
4089 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_tmp0
);
4090 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
,
4091 offsetof(CPUX86State
,
4092 xmm_regs
[reg
].XMM_L(val
& 3)));
4093 } else { /* pinsrq */
4094 #ifdef TARGET_X86_64
4096 gen_op_mov_v_reg(ot
, cpu_tmp1_i64
, rm
);
4098 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
,
4099 (s
->mem_index
>> 2) - 1);
4100 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
,
4101 offsetof(CPUX86State
,
4102 xmm_regs
[reg
].XMM_Q(val
& 1)));
4113 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
4115 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
| REX_B(s
)]);
4117 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
4118 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4119 gen_ldo_env_A0(s
->mem_index
, op2_offset
);
4122 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
].mmx
);
4124 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
4126 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
4127 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4128 gen_ldq_env_A0(s
->mem_index
, op2_offset
);
4131 val
= cpu_ldub_code(env
, s
->pc
++);
4133 if ((b
& 0xfc) == 0x60) { /* pcmpXstrX */
4134 set_cc_op(s
, CC_OP_EFLAGS
);
4137 /* The helper must use entire 64-bit gp registers */
4141 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4142 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4143 sse_fn_eppi(cpu_env
, cpu_ptr0
, cpu_ptr1
, tcg_const_i32(val
));
4149 /* generic MMX or SSE operation */
4151 case 0x70: /* pshufx insn */
4152 case 0xc6: /* pshufx insn */
4153 case 0xc2: /* compare insns */
4160 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
4162 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4163 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
4164 if (b1
>= 2 && ((b
>= 0x50 && b
<= 0x5f && b
!= 0x5b) ||
4166 /* specific case for SSE single instructions */
4169 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
4170 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(0)));
4173 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_t0
.XMM_D(0)));
4176 gen_ldo_env_A0(s
->mem_index
, op2_offset
);
4179 rm
= (modrm
& 7) | REX_B(s
);
4180 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
4183 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
].mmx
);
4185 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4186 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
4187 gen_ldq_env_A0(s
->mem_index
, op2_offset
);
4190 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
4194 case 0x0f: /* 3DNow! data insns */
4195 if (!(s
->cpuid_ext2_features
& CPUID_EXT2_3DNOW
))
4197 val
= cpu_ldub_code(env
, s
->pc
++);
4198 sse_fn_epp
= sse_op_table5
[val
];
4202 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4203 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4204 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
4206 case 0x70: /* pshufx insn */
4207 case 0xc6: /* pshufx insn */
4208 val
= cpu_ldub_code(env
, s
->pc
++);
4209 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4210 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4211 /* XXX: introduce a new table? */
4212 sse_fn_ppi
= (SSEFunc_0_ppi
)sse_fn_epp
;
4213 sse_fn_ppi(cpu_ptr0
, cpu_ptr1
, tcg_const_i32(val
));
4217 val
= cpu_ldub_code(env
, s
->pc
++);
4220 sse_fn_epp
= sse_op_table4
[val
][b1
];
4222 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4223 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4224 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
4227 /* maskmov : we must prepare A0 */
4230 #ifdef TARGET_X86_64
4231 if (s
->aflag
== 2) {
4232 gen_op_movq_A0_reg(R_EDI
);
4236 gen_op_movl_A0_reg(R_EDI
);
4238 gen_op_andl_A0_ffff();
4240 gen_add_A0_ds_seg(s
);
4242 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4243 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4244 /* XXX: introduce a new table? */
4245 sse_fn_eppt
= (SSEFunc_0_eppt
)sse_fn_epp
;
4246 sse_fn_eppt(cpu_env
, cpu_ptr0
, cpu_ptr1
, cpu_A0
);
4249 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4250 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4251 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
4254 if (b
== 0x2e || b
== 0x2f) {
4255 set_cc_op(s
, CC_OP_EFLAGS
);
4260 /* convert one instruction. s->is_jmp is set if the translation must
4261 be stopped. Return the next pc value */
4262 static target_ulong
disas_insn(CPUX86State
*env
, DisasContext
*s
,
4263 target_ulong pc_start
)
4265 int b
, prefixes
, aflag
, dflag
;
4267 int modrm
, reg
, rm
, mod
, reg_addr
, op
, opreg
, offset_addr
, val
;
4268 target_ulong next_eip
, tval
;
4271 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
| CPU_LOG_TB_OP_OPT
))) {
4272 tcg_gen_debug_insn_start(pc_start
);
4281 #ifdef TARGET_X86_64
4286 s
->rip_offset
= 0; /* for relative ip address */
4288 b
= cpu_ldub_code(env
, s
->pc
);
4290 /* check prefixes */
4291 #ifdef TARGET_X86_64
4295 prefixes
|= PREFIX_REPZ
;
4298 prefixes
|= PREFIX_REPNZ
;
4301 prefixes
|= PREFIX_LOCK
;
4322 prefixes
|= PREFIX_DATA
;
4325 prefixes
|= PREFIX_ADR
;
4329 rex_w
= (b
>> 3) & 1;
4330 rex_r
= (b
& 0x4) << 1;
4331 s
->rex_x
= (b
& 0x2) << 2;
4332 REX_B(s
) = (b
& 0x1) << 3;
4333 x86_64_hregs
= 1; /* select uniform byte register addressing */
4337 /* 0x66 is ignored if rex.w is set */
4340 if (prefixes
& PREFIX_DATA
)
4343 if (!(prefixes
& PREFIX_ADR
))
4350 prefixes
|= PREFIX_REPZ
;
4353 prefixes
|= PREFIX_REPNZ
;
4356 prefixes
|= PREFIX_LOCK
;
4377 prefixes
|= PREFIX_DATA
;
4380 prefixes
|= PREFIX_ADR
;
4383 if (prefixes
& PREFIX_DATA
)
4385 if (prefixes
& PREFIX_ADR
)
4389 s
->prefix
= prefixes
;
4393 /* lock generation */
4394 if (prefixes
& PREFIX_LOCK
)
4397 /* now check op code */
4401 /**************************/
4402 /* extended op code */
4403 b
= cpu_ldub_code(env
, s
->pc
++) | 0x100;
4406 /**************************/
4424 ot
= dflag
+ OT_WORD
;
4427 case 0: /* OP Ev, Gv */
4428 modrm
= cpu_ldub_code(env
, s
->pc
++);
4429 reg
= ((modrm
>> 3) & 7) | rex_r
;
4430 mod
= (modrm
>> 6) & 3;
4431 rm
= (modrm
& 7) | REX_B(s
);
4433 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4435 } else if (op
== OP_XORL
&& rm
== reg
) {
4437 /* xor reg, reg optimisation */
4439 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
4440 gen_op_mov_reg_T0(ot
, reg
);
4441 gen_op_update1_cc();
4446 gen_op_mov_TN_reg(ot
, 1, reg
);
4447 gen_op(s
, op
, ot
, opreg
);
4449 case 1: /* OP Gv, Ev */
4450 modrm
= cpu_ldub_code(env
, s
->pc
++);
4451 mod
= (modrm
>> 6) & 3;
4452 reg
= ((modrm
>> 3) & 7) | rex_r
;
4453 rm
= (modrm
& 7) | REX_B(s
);
4455 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4456 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
4457 } else if (op
== OP_XORL
&& rm
== reg
) {
4460 gen_op_mov_TN_reg(ot
, 1, rm
);
4462 gen_op(s
, op
, ot
, reg
);
4464 case 2: /* OP A, Iv */
4465 val
= insn_get(env
, s
, ot
);
4466 gen_op_movl_T1_im(val
);
4467 gen_op(s
, op
, ot
, OR_EAX
);
4476 case 0x80: /* GRP1 */
4485 ot
= dflag
+ OT_WORD
;
4487 modrm
= cpu_ldub_code(env
, s
->pc
++);
4488 mod
= (modrm
>> 6) & 3;
4489 rm
= (modrm
& 7) | REX_B(s
);
4490 op
= (modrm
>> 3) & 7;
4496 s
->rip_offset
= insn_const_size(ot
);
4497 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4508 val
= insn_get(env
, s
, ot
);
4511 val
= (int8_t)insn_get(env
, s
, OT_BYTE
);
4514 gen_op_movl_T1_im(val
);
4515 gen_op(s
, op
, ot
, opreg
);
4519 /**************************/
4520 /* inc, dec, and other misc arith */
4521 case 0x40 ... 0x47: /* inc Gv */
4522 ot
= dflag
? OT_LONG
: OT_WORD
;
4523 gen_inc(s
, ot
, OR_EAX
+ (b
& 7), 1);
4525 case 0x48 ... 0x4f: /* dec Gv */
4526 ot
= dflag
? OT_LONG
: OT_WORD
;
4527 gen_inc(s
, ot
, OR_EAX
+ (b
& 7), -1);
4529 case 0xf6: /* GRP3 */
4534 ot
= dflag
+ OT_WORD
;
4536 modrm
= cpu_ldub_code(env
, s
->pc
++);
4537 mod
= (modrm
>> 6) & 3;
4538 rm
= (modrm
& 7) | REX_B(s
);
4539 op
= (modrm
>> 3) & 7;
4542 s
->rip_offset
= insn_const_size(ot
);
4543 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4544 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
4546 gen_op_mov_TN_reg(ot
, 0, rm
);
4551 val
= insn_get(env
, s
, ot
);
4552 gen_op_movl_T1_im(val
);
4553 gen_op_testl_T0_T1_cc();
4554 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
4557 tcg_gen_not_tl(cpu_T
[0], cpu_T
[0]);
4559 gen_op_st_T0_A0(ot
+ s
->mem_index
);
4561 gen_op_mov_reg_T0(ot
, rm
);
4565 tcg_gen_neg_tl(cpu_T
[0], cpu_T
[0]);
4567 gen_op_st_T0_A0(ot
+ s
->mem_index
);
4569 gen_op_mov_reg_T0(ot
, rm
);
4571 gen_op_update_neg_cc();
4572 set_cc_op(s
, CC_OP_SUBB
+ ot
);
4577 gen_op_mov_TN_reg(OT_BYTE
, 1, R_EAX
);
4578 tcg_gen_ext8u_tl(cpu_T
[0], cpu_T
[0]);
4579 tcg_gen_ext8u_tl(cpu_T
[1], cpu_T
[1]);
4580 /* XXX: use 32 bit mul which could be faster */
4581 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4582 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
4583 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4584 tcg_gen_andi_tl(cpu_cc_src
, cpu_T
[0], 0xff00);
4585 set_cc_op(s
, CC_OP_MULB
);
4588 gen_op_mov_TN_reg(OT_WORD
, 1, R_EAX
);
4589 tcg_gen_ext16u_tl(cpu_T
[0], cpu_T
[0]);
4590 tcg_gen_ext16u_tl(cpu_T
[1], cpu_T
[1]);
4591 /* XXX: use 32 bit mul which could be faster */
4592 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4593 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
4594 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4595 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 16);
4596 gen_op_mov_reg_T0(OT_WORD
, R_EDX
);
4597 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
4598 set_cc_op(s
, CC_OP_MULW
);
4602 #ifdef TARGET_X86_64
4603 gen_op_mov_TN_reg(OT_LONG
, 1, R_EAX
);
4604 tcg_gen_ext32u_tl(cpu_T
[0], cpu_T
[0]);
4605 tcg_gen_ext32u_tl(cpu_T
[1], cpu_T
[1]);
4606 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4607 gen_op_mov_reg_T0(OT_LONG
, R_EAX
);
4608 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4609 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 32);
4610 gen_op_mov_reg_T0(OT_LONG
, R_EDX
);
4611 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
4615 t0
= tcg_temp_new_i64();
4616 t1
= tcg_temp_new_i64();
4617 gen_op_mov_TN_reg(OT_LONG
, 1, R_EAX
);
4618 tcg_gen_extu_i32_i64(t0
, cpu_T
[0]);
4619 tcg_gen_extu_i32_i64(t1
, cpu_T
[1]);
4620 tcg_gen_mul_i64(t0
, t0
, t1
);
4621 tcg_gen_trunc_i64_i32(cpu_T
[0], t0
);
4622 gen_op_mov_reg_T0(OT_LONG
, R_EAX
);
4623 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4624 tcg_gen_shri_i64(t0
, t0
, 32);
4625 tcg_gen_trunc_i64_i32(cpu_T
[0], t0
);
4626 gen_op_mov_reg_T0(OT_LONG
, R_EDX
);
4627 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
4630 set_cc_op(s
, CC_OP_MULL
);
4632 #ifdef TARGET_X86_64
4634 gen_helper_mulq_EAX_T0(cpu_env
, cpu_T
[0]);
4635 set_cc_op(s
, CC_OP_MULQ
);
4643 gen_op_mov_TN_reg(OT_BYTE
, 1, R_EAX
);
4644 tcg_gen_ext8s_tl(cpu_T
[0], cpu_T
[0]);
4645 tcg_gen_ext8s_tl(cpu_T
[1], cpu_T
[1]);
4646 /* XXX: use 32 bit mul which could be faster */
4647 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4648 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
4649 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4650 tcg_gen_ext8s_tl(cpu_tmp0
, cpu_T
[0]);
4651 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4652 set_cc_op(s
, CC_OP_MULB
);
4655 gen_op_mov_TN_reg(OT_WORD
, 1, R_EAX
);
4656 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
4657 tcg_gen_ext16s_tl(cpu_T
[1], cpu_T
[1]);
4658 /* XXX: use 32 bit mul which could be faster */
4659 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4660 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
4661 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4662 tcg_gen_ext16s_tl(cpu_tmp0
, cpu_T
[0]);
4663 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4664 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 16);
4665 gen_op_mov_reg_T0(OT_WORD
, R_EDX
);
4666 set_cc_op(s
, CC_OP_MULW
);
4670 #ifdef TARGET_X86_64
4671 gen_op_mov_TN_reg(OT_LONG
, 1, R_EAX
);
4672 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
4673 tcg_gen_ext32s_tl(cpu_T
[1], cpu_T
[1]);
4674 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4675 gen_op_mov_reg_T0(OT_LONG
, R_EAX
);
4676 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4677 tcg_gen_ext32s_tl(cpu_tmp0
, cpu_T
[0]);
4678 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4679 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 32);
4680 gen_op_mov_reg_T0(OT_LONG
, R_EDX
);
4684 t0
= tcg_temp_new_i64();
4685 t1
= tcg_temp_new_i64();
4686 gen_op_mov_TN_reg(OT_LONG
, 1, R_EAX
);
4687 tcg_gen_ext_i32_i64(t0
, cpu_T
[0]);
4688 tcg_gen_ext_i32_i64(t1
, cpu_T
[1]);
4689 tcg_gen_mul_i64(t0
, t0
, t1
);
4690 tcg_gen_trunc_i64_i32(cpu_T
[0], t0
);
4691 gen_op_mov_reg_T0(OT_LONG
, R_EAX
);
4692 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4693 tcg_gen_sari_tl(cpu_tmp0
, cpu_T
[0], 31);
4694 tcg_gen_shri_i64(t0
, t0
, 32);
4695 tcg_gen_trunc_i64_i32(cpu_T
[0], t0
);
4696 gen_op_mov_reg_T0(OT_LONG
, R_EDX
);
4697 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4700 set_cc_op(s
, CC_OP_MULL
);
4702 #ifdef TARGET_X86_64
4704 gen_helper_imulq_EAX_T0(cpu_env
, cpu_T
[0]);
4705 set_cc_op(s
, CC_OP_MULQ
);
4713 gen_jmp_im(pc_start
- s
->cs_base
);
4714 gen_helper_divb_AL(cpu_env
, cpu_T
[0]);
4717 gen_jmp_im(pc_start
- s
->cs_base
);
4718 gen_helper_divw_AX(cpu_env
, cpu_T
[0]);
4722 gen_jmp_im(pc_start
- s
->cs_base
);
4723 gen_helper_divl_EAX(cpu_env
, cpu_T
[0]);
4725 #ifdef TARGET_X86_64
4727 gen_jmp_im(pc_start
- s
->cs_base
);
4728 gen_helper_divq_EAX(cpu_env
, cpu_T
[0]);
4736 gen_jmp_im(pc_start
- s
->cs_base
);
4737 gen_helper_idivb_AL(cpu_env
, cpu_T
[0]);
4740 gen_jmp_im(pc_start
- s
->cs_base
);
4741 gen_helper_idivw_AX(cpu_env
, cpu_T
[0]);
4745 gen_jmp_im(pc_start
- s
->cs_base
);
4746 gen_helper_idivl_EAX(cpu_env
, cpu_T
[0]);
4748 #ifdef TARGET_X86_64
4750 gen_jmp_im(pc_start
- s
->cs_base
);
4751 gen_helper_idivq_EAX(cpu_env
, cpu_T
[0]);
4761 case 0xfe: /* GRP4 */
4762 case 0xff: /* GRP5 */
4766 ot
= dflag
+ OT_WORD
;
4768 modrm
= cpu_ldub_code(env
, s
->pc
++);
4769 mod
= (modrm
>> 6) & 3;
4770 rm
= (modrm
& 7) | REX_B(s
);
4771 op
= (modrm
>> 3) & 7;
4772 if (op
>= 2 && b
== 0xfe) {
4776 if (op
== 2 || op
== 4) {
4777 /* operand size for jumps is 64 bit */
4779 } else if (op
== 3 || op
== 5) {
4780 ot
= dflag
? OT_LONG
+ (rex_w
== 1) : OT_WORD
;
4781 } else if (op
== 6) {
4782 /* default push size is 64 bit */
4783 ot
= dflag
? OT_QUAD
: OT_WORD
;
4787 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4788 if (op
>= 2 && op
!= 3 && op
!= 5)
4789 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
4791 gen_op_mov_TN_reg(ot
, 0, rm
);
4795 case 0: /* inc Ev */
4800 gen_inc(s
, ot
, opreg
, 1);
4802 case 1: /* dec Ev */
4807 gen_inc(s
, ot
, opreg
, -1);
4809 case 2: /* call Ev */
4810 /* XXX: optimize if memory (no 'and' is necessary) */
4812 gen_op_andl_T0_ffff();
4813 next_eip
= s
->pc
- s
->cs_base
;
4814 gen_movtl_T1_im(next_eip
);
4819 case 3: /* lcall Ev */
4820 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
4821 gen_add_A0_im(s
, 1 << (ot
- OT_WORD
+ 1));
4822 gen_op_ldu_T0_A0(OT_WORD
+ s
->mem_index
);
4824 if (s
->pe
&& !s
->vm86
) {
4825 gen_update_cc_op(s
);
4826 gen_jmp_im(pc_start
- s
->cs_base
);
4827 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4828 gen_helper_lcall_protected(cpu_env
, cpu_tmp2_i32
, cpu_T
[1],
4829 tcg_const_i32(dflag
),
4830 tcg_const_i32(s
->pc
- pc_start
));
4832 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4833 gen_helper_lcall_real(cpu_env
, cpu_tmp2_i32
, cpu_T
[1],
4834 tcg_const_i32(dflag
),
4835 tcg_const_i32(s
->pc
- s
->cs_base
));
4839 case 4: /* jmp Ev */
4841 gen_op_andl_T0_ffff();
4845 case 5: /* ljmp Ev */
4846 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
4847 gen_add_A0_im(s
, 1 << (ot
- OT_WORD
+ 1));
4848 gen_op_ldu_T0_A0(OT_WORD
+ s
->mem_index
);
4850 if (s
->pe
&& !s
->vm86
) {
4851 gen_update_cc_op(s
);
4852 gen_jmp_im(pc_start
- s
->cs_base
);
4853 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4854 gen_helper_ljmp_protected(cpu_env
, cpu_tmp2_i32
, cpu_T
[1],
4855 tcg_const_i32(s
->pc
- pc_start
));
4857 gen_op_movl_seg_T0_vm(R_CS
);
4858 gen_op_movl_T0_T1();
4863 case 6: /* push Ev */
4871 case 0x84: /* test Ev, Gv */
4876 ot
= dflag
+ OT_WORD
;
4878 modrm
= cpu_ldub_code(env
, s
->pc
++);
4879 reg
= ((modrm
>> 3) & 7) | rex_r
;
4881 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
4882 gen_op_mov_TN_reg(ot
, 1, reg
);
4883 gen_op_testl_T0_T1_cc();
4884 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
4887 case 0xa8: /* test eAX, Iv */
4892 ot
= dflag
+ OT_WORD
;
4893 val
= insn_get(env
, s
, ot
);
4895 gen_op_mov_TN_reg(ot
, 0, OR_EAX
);
4896 gen_op_movl_T1_im(val
);
4897 gen_op_testl_T0_T1_cc();
4898 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
4901 case 0x98: /* CWDE/CBW */
4902 #ifdef TARGET_X86_64
4904 gen_op_mov_TN_reg(OT_LONG
, 0, R_EAX
);
4905 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
4906 gen_op_mov_reg_T0(OT_QUAD
, R_EAX
);
4910 gen_op_mov_TN_reg(OT_WORD
, 0, R_EAX
);
4911 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
4912 gen_op_mov_reg_T0(OT_LONG
, R_EAX
);
4914 gen_op_mov_TN_reg(OT_BYTE
, 0, R_EAX
);
4915 tcg_gen_ext8s_tl(cpu_T
[0], cpu_T
[0]);
4916 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
4919 case 0x99: /* CDQ/CWD */
4920 #ifdef TARGET_X86_64
4922 gen_op_mov_TN_reg(OT_QUAD
, 0, R_EAX
);
4923 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], 63);
4924 gen_op_mov_reg_T0(OT_QUAD
, R_EDX
);
4928 gen_op_mov_TN_reg(OT_LONG
, 0, R_EAX
);
4929 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
4930 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], 31);
4931 gen_op_mov_reg_T0(OT_LONG
, R_EDX
);
4933 gen_op_mov_TN_reg(OT_WORD
, 0, R_EAX
);
4934 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
4935 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], 15);
4936 gen_op_mov_reg_T0(OT_WORD
, R_EDX
);
4939 case 0x1af: /* imul Gv, Ev */
4940 case 0x69: /* imul Gv, Ev, I */
4942 ot
= dflag
+ OT_WORD
;
4943 modrm
= cpu_ldub_code(env
, s
->pc
++);
4944 reg
= ((modrm
>> 3) & 7) | rex_r
;
4946 s
->rip_offset
= insn_const_size(ot
);
4949 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
4951 val
= insn_get(env
, s
, ot
);
4952 gen_op_movl_T1_im(val
);
4953 } else if (b
== 0x6b) {
4954 val
= (int8_t)insn_get(env
, s
, OT_BYTE
);
4955 gen_op_movl_T1_im(val
);
4957 gen_op_mov_TN_reg(ot
, 1, reg
);
4960 #ifdef TARGET_X86_64
4961 if (ot
== OT_QUAD
) {
4962 gen_helper_imulq_T0_T1(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
4965 if (ot
== OT_LONG
) {
4966 #ifdef TARGET_X86_64
4967 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
4968 tcg_gen_ext32s_tl(cpu_T
[1], cpu_T
[1]);
4969 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4970 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4971 tcg_gen_ext32s_tl(cpu_tmp0
, cpu_T
[0]);
4972 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4976 t0
= tcg_temp_new_i64();
4977 t1
= tcg_temp_new_i64();
4978 tcg_gen_ext_i32_i64(t0
, cpu_T
[0]);
4979 tcg_gen_ext_i32_i64(t1
, cpu_T
[1]);
4980 tcg_gen_mul_i64(t0
, t0
, t1
);
4981 tcg_gen_trunc_i64_i32(cpu_T
[0], t0
);
4982 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4983 tcg_gen_sari_tl(cpu_tmp0
, cpu_T
[0], 31);
4984 tcg_gen_shri_i64(t0
, t0
, 32);
4985 tcg_gen_trunc_i64_i32(cpu_T
[1], t0
);
4986 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[1], cpu_tmp0
);
4990 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
4991 tcg_gen_ext16s_tl(cpu_T
[1], cpu_T
[1]);
4992 /* XXX: use 32 bit mul which could be faster */
4993 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4994 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4995 tcg_gen_ext16s_tl(cpu_tmp0
, cpu_T
[0]);
4996 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4998 gen_op_mov_reg_T0(ot
, reg
);
4999 set_cc_op(s
, CC_OP_MULB
+ ot
);
5002 case 0x1c1: /* xadd Ev, Gv */
5006 ot
= dflag
+ OT_WORD
;
5007 modrm
= cpu_ldub_code(env
, s
->pc
++);
5008 reg
= ((modrm
>> 3) & 7) | rex_r
;
5009 mod
= (modrm
>> 6) & 3;
5011 rm
= (modrm
& 7) | REX_B(s
);
5012 gen_op_mov_TN_reg(ot
, 0, reg
);
5013 gen_op_mov_TN_reg(ot
, 1, rm
);
5014 gen_op_addl_T0_T1();
5015 gen_op_mov_reg_T1(ot
, reg
);
5016 gen_op_mov_reg_T0(ot
, rm
);
5018 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5019 gen_op_mov_TN_reg(ot
, 0, reg
);
5020 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
5021 gen_op_addl_T0_T1();
5022 gen_op_st_T0_A0(ot
+ s
->mem_index
);
5023 gen_op_mov_reg_T1(ot
, reg
);
5025 gen_op_update2_cc();
5026 set_cc_op(s
, CC_OP_ADDB
+ ot
);
5029 case 0x1b1: /* cmpxchg Ev, Gv */
5032 TCGv t0
, t1
, t2
, a0
;
5037 ot
= dflag
+ OT_WORD
;
5038 modrm
= cpu_ldub_code(env
, s
->pc
++);
5039 reg
= ((modrm
>> 3) & 7) | rex_r
;
5040 mod
= (modrm
>> 6) & 3;
5041 t0
= tcg_temp_local_new();
5042 t1
= tcg_temp_local_new();
5043 t2
= tcg_temp_local_new();
5044 a0
= tcg_temp_local_new();
5045 gen_op_mov_v_reg(ot
, t1
, reg
);
5047 rm
= (modrm
& 7) | REX_B(s
);
5048 gen_op_mov_v_reg(ot
, t0
, rm
);
5050 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5051 tcg_gen_mov_tl(a0
, cpu_A0
);
5052 gen_op_ld_v(ot
+ s
->mem_index
, t0
, a0
);
5053 rm
= 0; /* avoid warning */
5055 label1
= gen_new_label();
5056 tcg_gen_mov_tl(t2
, cpu_regs
[R_EAX
]);
5059 tcg_gen_brcond_tl(TCG_COND_EQ
, t2
, t0
, label1
);
5060 label2
= gen_new_label();
5062 gen_op_mov_reg_v(ot
, R_EAX
, t0
);
5064 gen_set_label(label1
);
5065 gen_op_mov_reg_v(ot
, rm
, t1
);
5067 /* perform no-op store cycle like physical cpu; must be
5068 before changing accumulator to ensure idempotency if
5069 the store faults and the instruction is restarted */
5070 gen_op_st_v(ot
+ s
->mem_index
, t0
, a0
);
5071 gen_op_mov_reg_v(ot
, R_EAX
, t0
);
5073 gen_set_label(label1
);
5074 gen_op_st_v(ot
+ s
->mem_index
, t1
, a0
);
5076 gen_set_label(label2
);
5077 tcg_gen_mov_tl(cpu_cc_src
, t0
);
5078 tcg_gen_mov_tl(cpu_cc_srcT
, t2
);
5079 tcg_gen_sub_tl(cpu_cc_dst
, t2
, t0
);
5080 set_cc_op(s
, CC_OP_SUBB
+ ot
);
5087 case 0x1c7: /* cmpxchg8b */
5088 modrm
= cpu_ldub_code(env
, s
->pc
++);
5089 mod
= (modrm
>> 6) & 3;
5090 if ((mod
== 3) || ((modrm
& 0x38) != 0x8))
5092 #ifdef TARGET_X86_64
5094 if (!(s
->cpuid_ext_features
& CPUID_EXT_CX16
))
5096 gen_jmp_im(pc_start
- s
->cs_base
);
5097 gen_update_cc_op(s
);
5098 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5099 gen_helper_cmpxchg16b(cpu_env
, cpu_A0
);
5103 if (!(s
->cpuid_features
& CPUID_CX8
))
5105 gen_jmp_im(pc_start
- s
->cs_base
);
5106 gen_update_cc_op(s
);
5107 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5108 gen_helper_cmpxchg8b(cpu_env
, cpu_A0
);
5110 set_cc_op(s
, CC_OP_EFLAGS
);
5113 /**************************/
5115 case 0x50 ... 0x57: /* push */
5116 gen_op_mov_TN_reg(OT_LONG
, 0, (b
& 7) | REX_B(s
));
5119 case 0x58 ... 0x5f: /* pop */
5121 ot
= dflag
? OT_QUAD
: OT_WORD
;
5123 ot
= dflag
+ OT_WORD
;
5126 /* NOTE: order is important for pop %sp */
5128 gen_op_mov_reg_T0(ot
, (b
& 7) | REX_B(s
));
5130 case 0x60: /* pusha */
5135 case 0x61: /* popa */
5140 case 0x68: /* push Iv */
5143 ot
= dflag
? OT_QUAD
: OT_WORD
;
5145 ot
= dflag
+ OT_WORD
;
5148 val
= insn_get(env
, s
, ot
);
5150 val
= (int8_t)insn_get(env
, s
, OT_BYTE
);
5151 gen_op_movl_T0_im(val
);
5154 case 0x8f: /* pop Ev */
5156 ot
= dflag
? OT_QUAD
: OT_WORD
;
5158 ot
= dflag
+ OT_WORD
;
5160 modrm
= cpu_ldub_code(env
, s
->pc
++);
5161 mod
= (modrm
>> 6) & 3;
5164 /* NOTE: order is important for pop %sp */
5166 rm
= (modrm
& 7) | REX_B(s
);
5167 gen_op_mov_reg_T0(ot
, rm
);
5169 /* NOTE: order is important too for MMU exceptions */
5170 s
->popl_esp_hack
= 1 << ot
;
5171 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 1);
5172 s
->popl_esp_hack
= 0;
5176 case 0xc8: /* enter */
5179 val
= cpu_lduw_code(env
, s
->pc
);
5181 level
= cpu_ldub_code(env
, s
->pc
++);
5182 gen_enter(s
, val
, level
);
5185 case 0xc9: /* leave */
5186 /* XXX: exception not precise (ESP is updated before potential exception) */
5188 gen_op_mov_TN_reg(OT_QUAD
, 0, R_EBP
);
5189 gen_op_mov_reg_T0(OT_QUAD
, R_ESP
);
5190 } else if (s
->ss32
) {
5191 gen_op_mov_TN_reg(OT_LONG
, 0, R_EBP
);
5192 gen_op_mov_reg_T0(OT_LONG
, R_ESP
);
5194 gen_op_mov_TN_reg(OT_WORD
, 0, R_EBP
);
5195 gen_op_mov_reg_T0(OT_WORD
, R_ESP
);
5199 ot
= dflag
? OT_QUAD
: OT_WORD
;
5201 ot
= dflag
+ OT_WORD
;
5203 gen_op_mov_reg_T0(ot
, R_EBP
);
5206 case 0x06: /* push es */
5207 case 0x0e: /* push cs */
5208 case 0x16: /* push ss */
5209 case 0x1e: /* push ds */
5212 gen_op_movl_T0_seg(b
>> 3);
5215 case 0x1a0: /* push fs */
5216 case 0x1a8: /* push gs */
5217 gen_op_movl_T0_seg((b
>> 3) & 7);
5220 case 0x07: /* pop es */
5221 case 0x17: /* pop ss */
5222 case 0x1f: /* pop ds */
5227 gen_movl_seg_T0(s
, reg
, pc_start
- s
->cs_base
);
5230 /* if reg == SS, inhibit interrupts/trace. */
5231 /* If several instructions disable interrupts, only the
5233 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
5234 gen_helper_set_inhibit_irq(cpu_env
);
5238 gen_jmp_im(s
->pc
- s
->cs_base
);
5242 case 0x1a1: /* pop fs */
5243 case 0x1a9: /* pop gs */
5245 gen_movl_seg_T0(s
, (b
>> 3) & 7, pc_start
- s
->cs_base
);
5248 gen_jmp_im(s
->pc
- s
->cs_base
);
5253 /**************************/
5256 case 0x89: /* mov Gv, Ev */
5260 ot
= dflag
+ OT_WORD
;
5261 modrm
= cpu_ldub_code(env
, s
->pc
++);
5262 reg
= ((modrm
>> 3) & 7) | rex_r
;
5264 /* generate a generic store */
5265 gen_ldst_modrm(env
, s
, modrm
, ot
, reg
, 1);
5268 case 0xc7: /* mov Ev, Iv */
5272 ot
= dflag
+ OT_WORD
;
5273 modrm
= cpu_ldub_code(env
, s
->pc
++);
5274 mod
= (modrm
>> 6) & 3;
5276 s
->rip_offset
= insn_const_size(ot
);
5277 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5279 val
= insn_get(env
, s
, ot
);
5280 gen_op_movl_T0_im(val
);
5282 gen_op_st_T0_A0(ot
+ s
->mem_index
);
5284 gen_op_mov_reg_T0(ot
, (modrm
& 7) | REX_B(s
));
5287 case 0x8b: /* mov Ev, Gv */
5291 ot
= OT_WORD
+ dflag
;
5292 modrm
= cpu_ldub_code(env
, s
->pc
++);
5293 reg
= ((modrm
>> 3) & 7) | rex_r
;
5295 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
5296 gen_op_mov_reg_T0(ot
, reg
);
5298 case 0x8e: /* mov seg, Gv */
5299 modrm
= cpu_ldub_code(env
, s
->pc
++);
5300 reg
= (modrm
>> 3) & 7;
5301 if (reg
>= 6 || reg
== R_CS
)
5303 gen_ldst_modrm(env
, s
, modrm
, OT_WORD
, OR_TMP0
, 0);
5304 gen_movl_seg_T0(s
, reg
, pc_start
- s
->cs_base
);
5306 /* if reg == SS, inhibit interrupts/trace */
5307 /* If several instructions disable interrupts, only the
5309 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
5310 gen_helper_set_inhibit_irq(cpu_env
);
5314 gen_jmp_im(s
->pc
- s
->cs_base
);
5318 case 0x8c: /* mov Gv, seg */
5319 modrm
= cpu_ldub_code(env
, s
->pc
++);
5320 reg
= (modrm
>> 3) & 7;
5321 mod
= (modrm
>> 6) & 3;
5324 gen_op_movl_T0_seg(reg
);
5326 ot
= OT_WORD
+ dflag
;
5329 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 1);
5332 case 0x1b6: /* movzbS Gv, Eb */
5333 case 0x1b7: /* movzwS Gv, Eb */
5334 case 0x1be: /* movsbS Gv, Eb */
5335 case 0x1bf: /* movswS Gv, Eb */
5338 /* d_ot is the size of destination */
5339 d_ot
= dflag
+ OT_WORD
;
5340 /* ot is the size of source */
5341 ot
= (b
& 1) + OT_BYTE
;
5342 modrm
= cpu_ldub_code(env
, s
->pc
++);
5343 reg
= ((modrm
>> 3) & 7) | rex_r
;
5344 mod
= (modrm
>> 6) & 3;
5345 rm
= (modrm
& 7) | REX_B(s
);
5348 gen_op_mov_TN_reg(ot
, 0, rm
);
5349 switch(ot
| (b
& 8)) {
5351 tcg_gen_ext8u_tl(cpu_T
[0], cpu_T
[0]);
5354 tcg_gen_ext8s_tl(cpu_T
[0], cpu_T
[0]);
5357 tcg_gen_ext16u_tl(cpu_T
[0], cpu_T
[0]);
5361 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
5364 gen_op_mov_reg_T0(d_ot
, reg
);
5366 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5368 gen_op_lds_T0_A0(ot
+ s
->mem_index
);
5370 gen_op_ldu_T0_A0(ot
+ s
->mem_index
);
5372 gen_op_mov_reg_T0(d_ot
, reg
);
5377 case 0x8d: /* lea */
5378 ot
= dflag
+ OT_WORD
;
5379 modrm
= cpu_ldub_code(env
, s
->pc
++);
5380 mod
= (modrm
>> 6) & 3;
5383 reg
= ((modrm
>> 3) & 7) | rex_r
;
5384 /* we must ensure that no segment is added */
5388 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5390 gen_op_mov_reg_A0(ot
- OT_WORD
, reg
);
5393 case 0xa0: /* mov EAX, Ov */
5395 case 0xa2: /* mov Ov, EAX */
5398 target_ulong offset_addr
;
5403 ot
= dflag
+ OT_WORD
;
5404 #ifdef TARGET_X86_64
5405 if (s
->aflag
== 2) {
5406 offset_addr
= cpu_ldq_code(env
, s
->pc
);
5408 gen_op_movq_A0_im(offset_addr
);
5413 offset_addr
= insn_get(env
, s
, OT_LONG
);
5415 offset_addr
= insn_get(env
, s
, OT_WORD
);
5417 gen_op_movl_A0_im(offset_addr
);
5419 gen_add_A0_ds_seg(s
);
5421 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
5422 gen_op_mov_reg_T0(ot
, R_EAX
);
5424 gen_op_mov_TN_reg(ot
, 0, R_EAX
);
5425 gen_op_st_T0_A0(ot
+ s
->mem_index
);
5429 case 0xd7: /* xlat */
5430 #ifdef TARGET_X86_64
5431 if (s
->aflag
== 2) {
5432 gen_op_movq_A0_reg(R_EBX
);
5433 gen_op_mov_TN_reg(OT_QUAD
, 0, R_EAX
);
5434 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xff);
5435 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_T
[0]);
5439 gen_op_movl_A0_reg(R_EBX
);
5440 gen_op_mov_TN_reg(OT_LONG
, 0, R_EAX
);
5441 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xff);
5442 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_T
[0]);
5444 gen_op_andl_A0_ffff();
5446 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
5448 gen_add_A0_ds_seg(s
);
5449 gen_op_ldu_T0_A0(OT_BYTE
+ s
->mem_index
);
5450 gen_op_mov_reg_T0(OT_BYTE
, R_EAX
);
5452 case 0xb0 ... 0xb7: /* mov R, Ib */
5453 val
= insn_get(env
, s
, OT_BYTE
);
5454 gen_op_movl_T0_im(val
);
5455 gen_op_mov_reg_T0(OT_BYTE
, (b
& 7) | REX_B(s
));
5457 case 0xb8 ... 0xbf: /* mov R, Iv */
5458 #ifdef TARGET_X86_64
5462 tmp
= cpu_ldq_code(env
, s
->pc
);
5464 reg
= (b
& 7) | REX_B(s
);
5465 gen_movtl_T0_im(tmp
);
5466 gen_op_mov_reg_T0(OT_QUAD
, reg
);
5470 ot
= dflag
? OT_LONG
: OT_WORD
;
5471 val
= insn_get(env
, s
, ot
);
5472 reg
= (b
& 7) | REX_B(s
);
5473 gen_op_movl_T0_im(val
);
5474 gen_op_mov_reg_T0(ot
, reg
);
5478 case 0x91 ... 0x97: /* xchg R, EAX */
5480 ot
= dflag
+ OT_WORD
;
5481 reg
= (b
& 7) | REX_B(s
);
5485 case 0x87: /* xchg Ev, Gv */
5489 ot
= dflag
+ OT_WORD
;
5490 modrm
= cpu_ldub_code(env
, s
->pc
++);
5491 reg
= ((modrm
>> 3) & 7) | rex_r
;
5492 mod
= (modrm
>> 6) & 3;
5494 rm
= (modrm
& 7) | REX_B(s
);
5496 gen_op_mov_TN_reg(ot
, 0, reg
);
5497 gen_op_mov_TN_reg(ot
, 1, rm
);
5498 gen_op_mov_reg_T0(ot
, rm
);
5499 gen_op_mov_reg_T1(ot
, reg
);
5501 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5502 gen_op_mov_TN_reg(ot
, 0, reg
);
5503 /* for xchg, lock is implicit */
5504 if (!(prefixes
& PREFIX_LOCK
))
5506 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
5507 gen_op_st_T0_A0(ot
+ s
->mem_index
);
5508 if (!(prefixes
& PREFIX_LOCK
))
5509 gen_helper_unlock();
5510 gen_op_mov_reg_T1(ot
, reg
);
5513 case 0xc4: /* les Gv */
5518 case 0xc5: /* lds Gv */
5523 case 0x1b2: /* lss Gv */
5526 case 0x1b4: /* lfs Gv */
5529 case 0x1b5: /* lgs Gv */
5532 ot
= dflag
? OT_LONG
: OT_WORD
;
5533 modrm
= cpu_ldub_code(env
, s
->pc
++);
5534 reg
= ((modrm
>> 3) & 7) | rex_r
;
5535 mod
= (modrm
>> 6) & 3;
5538 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5539 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
5540 gen_add_A0_im(s
, 1 << (ot
- OT_WORD
+ 1));
5541 /* load the segment first to handle exceptions properly */
5542 gen_op_ldu_T0_A0(OT_WORD
+ s
->mem_index
);
5543 gen_movl_seg_T0(s
, op
, pc_start
- s
->cs_base
);
5544 /* then put the data */
5545 gen_op_mov_reg_T1(ot
, reg
);
5547 gen_jmp_im(s
->pc
- s
->cs_base
);
5552 /************************/
5563 ot
= dflag
+ OT_WORD
;
5565 modrm
= cpu_ldub_code(env
, s
->pc
++);
5566 mod
= (modrm
>> 6) & 3;
5567 op
= (modrm
>> 3) & 7;
5573 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5576 opreg
= (modrm
& 7) | REX_B(s
);
5581 gen_shift(s
, op
, ot
, opreg
, OR_ECX
);
5584 shift
= cpu_ldub_code(env
, s
->pc
++);
5586 gen_shifti(s
, op
, ot
, opreg
, shift
);
5601 case 0x1a4: /* shld imm */
5605 case 0x1a5: /* shld cl */
5609 case 0x1ac: /* shrd imm */
5613 case 0x1ad: /* shrd cl */
5617 ot
= dflag
+ OT_WORD
;
5618 modrm
= cpu_ldub_code(env
, s
->pc
++);
5619 mod
= (modrm
>> 6) & 3;
5620 rm
= (modrm
& 7) | REX_B(s
);
5621 reg
= ((modrm
>> 3) & 7) | rex_r
;
5623 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5628 gen_op_mov_TN_reg(ot
, 1, reg
);
5631 TCGv imm
= tcg_const_tl(cpu_ldub_code(env
, s
->pc
++));
5632 gen_shiftd_rm_T1(s
, ot
, opreg
, op
, imm
);
5635 gen_shiftd_rm_T1(s
, ot
, opreg
, op
, cpu_regs
[R_ECX
]);
5639 /************************/
5642 if (s
->flags
& (HF_EM_MASK
| HF_TS_MASK
)) {
5643 /* if CR0.EM or CR0.TS are set, generate an FPU exception */
5644 /* XXX: what to do if illegal op ? */
5645 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
5648 modrm
= cpu_ldub_code(env
, s
->pc
++);
5649 mod
= (modrm
>> 6) & 3;
5651 op
= ((b
& 7) << 3) | ((modrm
>> 3) & 7);
5654 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5656 case 0x00 ... 0x07: /* fxxxs */
5657 case 0x10 ... 0x17: /* fixxxl */
5658 case 0x20 ... 0x27: /* fxxxl */
5659 case 0x30 ... 0x37: /* fixxx */
5666 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
5667 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5668 gen_helper_flds_FT0(cpu_env
, cpu_tmp2_i32
);
5671 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
5672 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5673 gen_helper_fildl_FT0(cpu_env
, cpu_tmp2_i32
);
5676 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
,
5677 (s
->mem_index
>> 2) - 1);
5678 gen_helper_fldl_FT0(cpu_env
, cpu_tmp1_i64
);
5682 gen_op_lds_T0_A0(OT_WORD
+ s
->mem_index
);
5683 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5684 gen_helper_fildl_FT0(cpu_env
, cpu_tmp2_i32
);
5688 gen_helper_fp_arith_ST0_FT0(op1
);
5690 /* fcomp needs pop */
5691 gen_helper_fpop(cpu_env
);
5695 case 0x08: /* flds */
5696 case 0x0a: /* fsts */
5697 case 0x0b: /* fstps */
5698 case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */
5699 case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */
5700 case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */
5705 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
5706 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5707 gen_helper_flds_ST0(cpu_env
, cpu_tmp2_i32
);
5710 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
5711 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5712 gen_helper_fildl_ST0(cpu_env
, cpu_tmp2_i32
);
5715 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
,
5716 (s
->mem_index
>> 2) - 1);
5717 gen_helper_fldl_ST0(cpu_env
, cpu_tmp1_i64
);
5721 gen_op_lds_T0_A0(OT_WORD
+ s
->mem_index
);
5722 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5723 gen_helper_fildl_ST0(cpu_env
, cpu_tmp2_i32
);
5728 /* XXX: the corresponding CPUID bit must be tested ! */
5731 gen_helper_fisttl_ST0(cpu_tmp2_i32
, cpu_env
);
5732 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5733 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
5736 gen_helper_fisttll_ST0(cpu_tmp1_i64
, cpu_env
);
5737 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
,
5738 (s
->mem_index
>> 2) - 1);
5742 gen_helper_fistt_ST0(cpu_tmp2_i32
, cpu_env
);
5743 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5744 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
5747 gen_helper_fpop(cpu_env
);
5752 gen_helper_fsts_ST0(cpu_tmp2_i32
, cpu_env
);
5753 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5754 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
5757 gen_helper_fistl_ST0(cpu_tmp2_i32
, cpu_env
);
5758 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5759 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
5762 gen_helper_fstl_ST0(cpu_tmp1_i64
, cpu_env
);
5763 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
,
5764 (s
->mem_index
>> 2) - 1);
5768 gen_helper_fist_ST0(cpu_tmp2_i32
, cpu_env
);
5769 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5770 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
5774 gen_helper_fpop(cpu_env
);
5778 case 0x0c: /* fldenv mem */
5779 gen_update_cc_op(s
);
5780 gen_jmp_im(pc_start
- s
->cs_base
);
5781 gen_helper_fldenv(cpu_env
, cpu_A0
, tcg_const_i32(s
->dflag
));
5783 case 0x0d: /* fldcw mem */
5784 gen_op_ld_T0_A0(OT_WORD
+ s
->mem_index
);
5785 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5786 gen_helper_fldcw(cpu_env
, cpu_tmp2_i32
);
5788 case 0x0e: /* fnstenv mem */
5789 gen_update_cc_op(s
);
5790 gen_jmp_im(pc_start
- s
->cs_base
);
5791 gen_helper_fstenv(cpu_env
, cpu_A0
, tcg_const_i32(s
->dflag
));
5793 case 0x0f: /* fnstcw mem */
5794 gen_helper_fnstcw(cpu_tmp2_i32
, cpu_env
);
5795 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5796 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
5798 case 0x1d: /* fldt mem */
5799 gen_update_cc_op(s
);
5800 gen_jmp_im(pc_start
- s
->cs_base
);
5801 gen_helper_fldt_ST0(cpu_env
, cpu_A0
);
5803 case 0x1f: /* fstpt mem */
5804 gen_update_cc_op(s
);
5805 gen_jmp_im(pc_start
- s
->cs_base
);
5806 gen_helper_fstt_ST0(cpu_env
, cpu_A0
);
5807 gen_helper_fpop(cpu_env
);
5809 case 0x2c: /* frstor mem */
5810 gen_update_cc_op(s
);
5811 gen_jmp_im(pc_start
- s
->cs_base
);
5812 gen_helper_frstor(cpu_env
, cpu_A0
, tcg_const_i32(s
->dflag
));
5814 case 0x2e: /* fnsave mem */
5815 gen_update_cc_op(s
);
5816 gen_jmp_im(pc_start
- s
->cs_base
);
5817 gen_helper_fsave(cpu_env
, cpu_A0
, tcg_const_i32(s
->dflag
));
5819 case 0x2f: /* fnstsw mem */
5820 gen_helper_fnstsw(cpu_tmp2_i32
, cpu_env
);
5821 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5822 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
5824 case 0x3c: /* fbld */
5825 gen_update_cc_op(s
);
5826 gen_jmp_im(pc_start
- s
->cs_base
);
5827 gen_helper_fbld_ST0(cpu_env
, cpu_A0
);
5829 case 0x3e: /* fbstp */
5830 gen_update_cc_op(s
);
5831 gen_jmp_im(pc_start
- s
->cs_base
);
5832 gen_helper_fbst_ST0(cpu_env
, cpu_A0
);
5833 gen_helper_fpop(cpu_env
);
5835 case 0x3d: /* fildll */
5836 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
,
5837 (s
->mem_index
>> 2) - 1);
5838 gen_helper_fildll_ST0(cpu_env
, cpu_tmp1_i64
);
5840 case 0x3f: /* fistpll */
5841 gen_helper_fistll_ST0(cpu_tmp1_i64
, cpu_env
);
5842 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
,
5843 (s
->mem_index
>> 2) - 1);
5844 gen_helper_fpop(cpu_env
);
5850 /* register float ops */
5854 case 0x08: /* fld sti */
5855 gen_helper_fpush(cpu_env
);
5856 gen_helper_fmov_ST0_STN(cpu_env
,
5857 tcg_const_i32((opreg
+ 1) & 7));
5859 case 0x09: /* fxchg sti */
5860 case 0x29: /* fxchg4 sti, undocumented op */
5861 case 0x39: /* fxchg7 sti, undocumented op */
5862 gen_helper_fxchg_ST0_STN(cpu_env
, tcg_const_i32(opreg
));
5864 case 0x0a: /* grp d9/2 */
5867 /* check exceptions (FreeBSD FPU probe) */
5868 gen_update_cc_op(s
);
5869 gen_jmp_im(pc_start
- s
->cs_base
);
5870 gen_helper_fwait(cpu_env
);
5876 case 0x0c: /* grp d9/4 */
5879 gen_helper_fchs_ST0(cpu_env
);
5882 gen_helper_fabs_ST0(cpu_env
);
5885 gen_helper_fldz_FT0(cpu_env
);
5886 gen_helper_fcom_ST0_FT0(cpu_env
);
5889 gen_helper_fxam_ST0(cpu_env
);
5895 case 0x0d: /* grp d9/5 */
5899 gen_helper_fpush(cpu_env
);
5900 gen_helper_fld1_ST0(cpu_env
);
5903 gen_helper_fpush(cpu_env
);
5904 gen_helper_fldl2t_ST0(cpu_env
);
5907 gen_helper_fpush(cpu_env
);
5908 gen_helper_fldl2e_ST0(cpu_env
);
5911 gen_helper_fpush(cpu_env
);
5912 gen_helper_fldpi_ST0(cpu_env
);
5915 gen_helper_fpush(cpu_env
);
5916 gen_helper_fldlg2_ST0(cpu_env
);
5919 gen_helper_fpush(cpu_env
);
5920 gen_helper_fldln2_ST0(cpu_env
);
5923 gen_helper_fpush(cpu_env
);
5924 gen_helper_fldz_ST0(cpu_env
);
5931 case 0x0e: /* grp d9/6 */
5934 gen_helper_f2xm1(cpu_env
);
5937 gen_helper_fyl2x(cpu_env
);
5940 gen_helper_fptan(cpu_env
);
5942 case 3: /* fpatan */
5943 gen_helper_fpatan(cpu_env
);
5945 case 4: /* fxtract */
5946 gen_helper_fxtract(cpu_env
);
5948 case 5: /* fprem1 */
5949 gen_helper_fprem1(cpu_env
);
5951 case 6: /* fdecstp */
5952 gen_helper_fdecstp(cpu_env
);
5955 case 7: /* fincstp */
5956 gen_helper_fincstp(cpu_env
);
5960 case 0x0f: /* grp d9/7 */
5963 gen_helper_fprem(cpu_env
);
5965 case 1: /* fyl2xp1 */
5966 gen_helper_fyl2xp1(cpu_env
);
5969 gen_helper_fsqrt(cpu_env
);
5971 case 3: /* fsincos */
5972 gen_helper_fsincos(cpu_env
);
5974 case 5: /* fscale */
5975 gen_helper_fscale(cpu_env
);
5977 case 4: /* frndint */
5978 gen_helper_frndint(cpu_env
);
5981 gen_helper_fsin(cpu_env
);
5985 gen_helper_fcos(cpu_env
);
5989 case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
5990 case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
5991 case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
5997 gen_helper_fp_arith_STN_ST0(op1
, opreg
);
5999 gen_helper_fpop(cpu_env
);
6001 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6002 gen_helper_fp_arith_ST0_FT0(op1
);
6006 case 0x02: /* fcom */
6007 case 0x22: /* fcom2, undocumented op */
6008 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6009 gen_helper_fcom_ST0_FT0(cpu_env
);
6011 case 0x03: /* fcomp */
6012 case 0x23: /* fcomp3, undocumented op */
6013 case 0x32: /* fcomp5, undocumented op */
6014 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6015 gen_helper_fcom_ST0_FT0(cpu_env
);
6016 gen_helper_fpop(cpu_env
);
6018 case 0x15: /* da/5 */
6020 case 1: /* fucompp */
6021 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(1));
6022 gen_helper_fucom_ST0_FT0(cpu_env
);
6023 gen_helper_fpop(cpu_env
);
6024 gen_helper_fpop(cpu_env
);
6032 case 0: /* feni (287 only, just do nop here) */
6034 case 1: /* fdisi (287 only, just do nop here) */
6037 gen_helper_fclex(cpu_env
);
6039 case 3: /* fninit */
6040 gen_helper_fninit(cpu_env
);
6042 case 4: /* fsetpm (287 only, just do nop here) */
6048 case 0x1d: /* fucomi */
6049 gen_update_cc_op(s
);
6050 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6051 gen_helper_fucomi_ST0_FT0(cpu_env
);
6052 set_cc_op(s
, CC_OP_EFLAGS
);
6054 case 0x1e: /* fcomi */
6055 gen_update_cc_op(s
);
6056 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6057 gen_helper_fcomi_ST0_FT0(cpu_env
);
6058 set_cc_op(s
, CC_OP_EFLAGS
);
6060 case 0x28: /* ffree sti */
6061 gen_helper_ffree_STN(cpu_env
, tcg_const_i32(opreg
));
6063 case 0x2a: /* fst sti */
6064 gen_helper_fmov_STN_ST0(cpu_env
, tcg_const_i32(opreg
));
6066 case 0x2b: /* fstp sti */
6067 case 0x0b: /* fstp1 sti, undocumented op */
6068 case 0x3a: /* fstp8 sti, undocumented op */
6069 case 0x3b: /* fstp9 sti, undocumented op */
6070 gen_helper_fmov_STN_ST0(cpu_env
, tcg_const_i32(opreg
));
6071 gen_helper_fpop(cpu_env
);
6073 case 0x2c: /* fucom st(i) */
6074 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6075 gen_helper_fucom_ST0_FT0(cpu_env
);
6077 case 0x2d: /* fucomp st(i) */
6078 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6079 gen_helper_fucom_ST0_FT0(cpu_env
);
6080 gen_helper_fpop(cpu_env
);
6082 case 0x33: /* de/3 */
6084 case 1: /* fcompp */
6085 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(1));
6086 gen_helper_fcom_ST0_FT0(cpu_env
);
6087 gen_helper_fpop(cpu_env
);
6088 gen_helper_fpop(cpu_env
);
6094 case 0x38: /* ffreep sti, undocumented op */
6095 gen_helper_ffree_STN(cpu_env
, tcg_const_i32(opreg
));
6096 gen_helper_fpop(cpu_env
);
6098 case 0x3c: /* df/4 */
6101 gen_helper_fnstsw(cpu_tmp2_i32
, cpu_env
);
6102 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
6103 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
6109 case 0x3d: /* fucomip */
6110 gen_update_cc_op(s
);
6111 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6112 gen_helper_fucomi_ST0_FT0(cpu_env
);
6113 gen_helper_fpop(cpu_env
);
6114 set_cc_op(s
, CC_OP_EFLAGS
);
6116 case 0x3e: /* fcomip */
6117 gen_update_cc_op(s
);
6118 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6119 gen_helper_fcomi_ST0_FT0(cpu_env
);
6120 gen_helper_fpop(cpu_env
);
6121 set_cc_op(s
, CC_OP_EFLAGS
);
6123 case 0x10 ... 0x13: /* fcmovxx */
6127 static const uint8_t fcmov_cc
[8] = {
6133 op1
= fcmov_cc
[op
& 3] | (((op
>> 3) & 1) ^ 1);
6134 l1
= gen_new_label();
6135 gen_jcc1_noeob(s
, op1
, l1
);
6136 gen_helper_fmov_ST0_STN(cpu_env
, tcg_const_i32(opreg
));
6145 /************************/
6148 case 0xa4: /* movsS */
6153 ot
= dflag
+ OT_WORD
;
6155 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6156 gen_repz_movs(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6162 case 0xaa: /* stosS */
6167 ot
= dflag
+ OT_WORD
;
6169 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6170 gen_repz_stos(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6175 case 0xac: /* lodsS */
6180 ot
= dflag
+ OT_WORD
;
6181 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6182 gen_repz_lods(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6187 case 0xae: /* scasS */
6192 ot
= dflag
+ OT_WORD
;
6193 if (prefixes
& PREFIX_REPNZ
) {
6194 gen_repz_scas(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 1);
6195 } else if (prefixes
& PREFIX_REPZ
) {
6196 gen_repz_scas(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 0);
6202 case 0xa6: /* cmpsS */
6207 ot
= dflag
+ OT_WORD
;
6208 if (prefixes
& PREFIX_REPNZ
) {
6209 gen_repz_cmps(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 1);
6210 } else if (prefixes
& PREFIX_REPZ
) {
6211 gen_repz_cmps(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 0);
6216 case 0x6c: /* insS */
6221 ot
= dflag
? OT_LONG
: OT_WORD
;
6222 gen_op_mov_TN_reg(OT_WORD
, 0, R_EDX
);
6223 gen_op_andl_T0_ffff();
6224 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6225 SVM_IOIO_TYPE_MASK
| svm_is_rep(prefixes
) | 4);
6226 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6227 gen_repz_ins(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6231 gen_jmp(s
, s
->pc
- s
->cs_base
);
6235 case 0x6e: /* outsS */
6240 ot
= dflag
? OT_LONG
: OT_WORD
;
6241 gen_op_mov_TN_reg(OT_WORD
, 0, R_EDX
);
6242 gen_op_andl_T0_ffff();
6243 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6244 svm_is_rep(prefixes
) | 4);
6245 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6246 gen_repz_outs(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6250 gen_jmp(s
, s
->pc
- s
->cs_base
);
6255 /************************/
6263 ot
= dflag
? OT_LONG
: OT_WORD
;
6264 val
= cpu_ldub_code(env
, s
->pc
++);
6265 gen_op_movl_T0_im(val
);
6266 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6267 SVM_IOIO_TYPE_MASK
| svm_is_rep(prefixes
));
6270 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6271 gen_helper_in_func(ot
, cpu_T
[1], cpu_tmp2_i32
);
6272 gen_op_mov_reg_T1(ot
, R_EAX
);
6275 gen_jmp(s
, s
->pc
- s
->cs_base
);
6283 ot
= dflag
? OT_LONG
: OT_WORD
;
6284 val
= cpu_ldub_code(env
, s
->pc
++);
6285 gen_op_movl_T0_im(val
);
6286 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6287 svm_is_rep(prefixes
));
6288 gen_op_mov_TN_reg(ot
, 1, R_EAX
);
6292 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6293 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[1]);
6294 gen_helper_out_func(ot
, cpu_tmp2_i32
, cpu_tmp3_i32
);
6297 gen_jmp(s
, s
->pc
- s
->cs_base
);
6305 ot
= dflag
? OT_LONG
: OT_WORD
;
6306 gen_op_mov_TN_reg(OT_WORD
, 0, R_EDX
);
6307 gen_op_andl_T0_ffff();
6308 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6309 SVM_IOIO_TYPE_MASK
| svm_is_rep(prefixes
));
6312 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6313 gen_helper_in_func(ot
, cpu_T
[1], cpu_tmp2_i32
);
6314 gen_op_mov_reg_T1(ot
, R_EAX
);
6317 gen_jmp(s
, s
->pc
- s
->cs_base
);
6325 ot
= dflag
? OT_LONG
: OT_WORD
;
6326 gen_op_mov_TN_reg(OT_WORD
, 0, R_EDX
);
6327 gen_op_andl_T0_ffff();
6328 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6329 svm_is_rep(prefixes
));
6330 gen_op_mov_TN_reg(ot
, 1, R_EAX
);
6334 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6335 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[1]);
6336 gen_helper_out_func(ot
, cpu_tmp2_i32
, cpu_tmp3_i32
);
6339 gen_jmp(s
, s
->pc
- s
->cs_base
);
6343 /************************/
6345 case 0xc2: /* ret im */
6346 val
= cpu_ldsw_code(env
, s
->pc
);
6349 if (CODE64(s
) && s
->dflag
)
6351 gen_stack_update(s
, val
+ (2 << s
->dflag
));
6353 gen_op_andl_T0_ffff();
6357 case 0xc3: /* ret */
6361 gen_op_andl_T0_ffff();
6365 case 0xca: /* lret im */
6366 val
= cpu_ldsw_code(env
, s
->pc
);
6369 if (s
->pe
&& !s
->vm86
) {
6370 gen_update_cc_op(s
);
6371 gen_jmp_im(pc_start
- s
->cs_base
);
6372 gen_helper_lret_protected(cpu_env
, tcg_const_i32(s
->dflag
),
6373 tcg_const_i32(val
));
6377 gen_op_ld_T0_A0(1 + s
->dflag
+ s
->mem_index
);
6379 gen_op_andl_T0_ffff();
6380 /* NOTE: keeping EIP updated is not a problem in case of
6384 gen_op_addl_A0_im(2 << s
->dflag
);
6385 gen_op_ld_T0_A0(1 + s
->dflag
+ s
->mem_index
);
6386 gen_op_movl_seg_T0_vm(R_CS
);
6387 /* add stack offset */
6388 gen_stack_update(s
, val
+ (4 << s
->dflag
));
6392 case 0xcb: /* lret */
6395 case 0xcf: /* iret */
6396 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_IRET
);
6399 gen_helper_iret_real(cpu_env
, tcg_const_i32(s
->dflag
));
6400 set_cc_op(s
, CC_OP_EFLAGS
);
6401 } else if (s
->vm86
) {
6403 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6405 gen_helper_iret_real(cpu_env
, tcg_const_i32(s
->dflag
));
6406 set_cc_op(s
, CC_OP_EFLAGS
);
6409 gen_update_cc_op(s
);
6410 gen_jmp_im(pc_start
- s
->cs_base
);
6411 gen_helper_iret_protected(cpu_env
, tcg_const_i32(s
->dflag
),
6412 tcg_const_i32(s
->pc
- s
->cs_base
));
6413 set_cc_op(s
, CC_OP_EFLAGS
);
6417 case 0xe8: /* call im */
6420 tval
= (int32_t)insn_get(env
, s
, OT_LONG
);
6422 tval
= (int16_t)insn_get(env
, s
, OT_WORD
);
6423 next_eip
= s
->pc
- s
->cs_base
;
6429 gen_movtl_T0_im(next_eip
);
6434 case 0x9a: /* lcall im */
6436 unsigned int selector
, offset
;
6440 ot
= dflag
? OT_LONG
: OT_WORD
;
6441 offset
= insn_get(env
, s
, ot
);
6442 selector
= insn_get(env
, s
, OT_WORD
);
6444 gen_op_movl_T0_im(selector
);
6445 gen_op_movl_T1_imu(offset
);
6448 case 0xe9: /* jmp im */
6450 tval
= (int32_t)insn_get(env
, s
, OT_LONG
);
6452 tval
= (int16_t)insn_get(env
, s
, OT_WORD
);
6453 tval
+= s
->pc
- s
->cs_base
;
6460 case 0xea: /* ljmp im */
6462 unsigned int selector
, offset
;
6466 ot
= dflag
? OT_LONG
: OT_WORD
;
6467 offset
= insn_get(env
, s
, ot
);
6468 selector
= insn_get(env
, s
, OT_WORD
);
6470 gen_op_movl_T0_im(selector
);
6471 gen_op_movl_T1_imu(offset
);
6474 case 0xeb: /* jmp Jb */
6475 tval
= (int8_t)insn_get(env
, s
, OT_BYTE
);
6476 tval
+= s
->pc
- s
->cs_base
;
6481 case 0x70 ... 0x7f: /* jcc Jb */
6482 tval
= (int8_t)insn_get(env
, s
, OT_BYTE
);
6484 case 0x180 ... 0x18f: /* jcc Jv */
6486 tval
= (int32_t)insn_get(env
, s
, OT_LONG
);
6488 tval
= (int16_t)insn_get(env
, s
, OT_WORD
);
6491 next_eip
= s
->pc
- s
->cs_base
;
6495 gen_jcc(s
, b
, tval
, next_eip
);
6498 case 0x190 ... 0x19f: /* setcc Gv */
6499 modrm
= cpu_ldub_code(env
, s
->pc
++);
6500 gen_setcc1(s
, b
, cpu_T
[0]);
6501 gen_ldst_modrm(env
, s
, modrm
, OT_BYTE
, OR_TMP0
, 1);
6503 case 0x140 ... 0x14f: /* cmov Gv, Ev */
6504 ot
= dflag
+ OT_WORD
;
6505 modrm
= cpu_ldub_code(env
, s
->pc
++);
6506 reg
= ((modrm
>> 3) & 7) | rex_r
;
6507 gen_cmovcc1(env
, s
, ot
, b
, modrm
, reg
);
6510 /************************/
6512 case 0x9c: /* pushf */
6513 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_PUSHF
);
6514 if (s
->vm86
&& s
->iopl
!= 3) {
6515 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6517 gen_update_cc_op(s
);
6518 gen_helper_read_eflags(cpu_T
[0], cpu_env
);
6522 case 0x9d: /* popf */
6523 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_POPF
);
6524 if (s
->vm86
&& s
->iopl
!= 3) {
6525 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6530 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6531 tcg_const_i32((TF_MASK
| AC_MASK
|
6536 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6537 tcg_const_i32((TF_MASK
| AC_MASK
|
6539 IF_MASK
| IOPL_MASK
)
6543 if (s
->cpl
<= s
->iopl
) {
6545 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6546 tcg_const_i32((TF_MASK
|
6552 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6553 tcg_const_i32((TF_MASK
|
6562 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6563 tcg_const_i32((TF_MASK
| AC_MASK
|
6564 ID_MASK
| NT_MASK
)));
6566 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6567 tcg_const_i32((TF_MASK
| AC_MASK
|
6574 set_cc_op(s
, CC_OP_EFLAGS
);
6575 /* abort translation because TF/AC flag may change */
6576 gen_jmp_im(s
->pc
- s
->cs_base
);
6580 case 0x9e: /* sahf */
6581 if (CODE64(s
) && !(s
->cpuid_ext3_features
& CPUID_EXT3_LAHF_LM
))
6583 gen_op_mov_TN_reg(OT_BYTE
, 0, R_AH
);
6584 gen_compute_eflags(s
);
6585 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, CC_O
);
6586 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
6587 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, cpu_T
[0]);
6589 case 0x9f: /* lahf */
6590 if (CODE64(s
) && !(s
->cpuid_ext3_features
& CPUID_EXT3_LAHF_LM
))
6592 gen_compute_eflags(s
);
6593 /* Note: gen_compute_eflags() only gives the condition codes */
6594 tcg_gen_ori_tl(cpu_T
[0], cpu_cc_src
, 0x02);
6595 gen_op_mov_reg_T0(OT_BYTE
, R_AH
);
6597 case 0xf5: /* cmc */
6598 gen_compute_eflags(s
);
6599 tcg_gen_xori_tl(cpu_cc_src
, cpu_cc_src
, CC_C
);
6601 case 0xf8: /* clc */
6602 gen_compute_eflags(s
);
6603 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~CC_C
);
6605 case 0xf9: /* stc */
6606 gen_compute_eflags(s
);
6607 tcg_gen_ori_tl(cpu_cc_src
, cpu_cc_src
, CC_C
);
6609 case 0xfc: /* cld */
6610 tcg_gen_movi_i32(cpu_tmp2_i32
, 1);
6611 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, offsetof(CPUX86State
, df
));
6613 case 0xfd: /* std */
6614 tcg_gen_movi_i32(cpu_tmp2_i32
, -1);
6615 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, offsetof(CPUX86State
, df
));
6618 /************************/
6619 /* bit operations */
6620 case 0x1ba: /* bt/bts/btr/btc Gv, im */
6621 ot
= dflag
+ OT_WORD
;
6622 modrm
= cpu_ldub_code(env
, s
->pc
++);
6623 op
= (modrm
>> 3) & 7;
6624 mod
= (modrm
>> 6) & 3;
6625 rm
= (modrm
& 7) | REX_B(s
);
6628 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
6629 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
6631 gen_op_mov_TN_reg(ot
, 0, rm
);
6634 val
= cpu_ldub_code(env
, s
->pc
++);
6635 gen_op_movl_T1_im(val
);
6640 case 0x1a3: /* bt Gv, Ev */
6643 case 0x1ab: /* bts */
6646 case 0x1b3: /* btr */
6649 case 0x1bb: /* btc */
6652 ot
= dflag
+ OT_WORD
;
6653 modrm
= cpu_ldub_code(env
, s
->pc
++);
6654 reg
= ((modrm
>> 3) & 7) | rex_r
;
6655 mod
= (modrm
>> 6) & 3;
6656 rm
= (modrm
& 7) | REX_B(s
);
6657 gen_op_mov_TN_reg(OT_LONG
, 1, reg
);
6659 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
6660 /* specific case: we need to add a displacement */
6661 gen_exts(ot
, cpu_T
[1]);
6662 tcg_gen_sari_tl(cpu_tmp0
, cpu_T
[1], 3 + ot
);
6663 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, ot
);
6664 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
6665 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
6667 gen_op_mov_TN_reg(ot
, 0, rm
);
6670 tcg_gen_andi_tl(cpu_T
[1], cpu_T
[1], (1 << (3 + ot
)) - 1);
6673 tcg_gen_shr_tl(cpu_cc_src
, cpu_T
[0], cpu_T
[1]);
6674 tcg_gen_movi_tl(cpu_cc_dst
, 0);
6677 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[0], cpu_T
[1]);
6678 tcg_gen_movi_tl(cpu_tmp0
, 1);
6679 tcg_gen_shl_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[1]);
6680 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
6683 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[0], cpu_T
[1]);
6684 tcg_gen_movi_tl(cpu_tmp0
, 1);
6685 tcg_gen_shl_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[1]);
6686 tcg_gen_not_tl(cpu_tmp0
, cpu_tmp0
);
6687 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
6691 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[0], cpu_T
[1]);
6692 tcg_gen_movi_tl(cpu_tmp0
, 1);
6693 tcg_gen_shl_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[1]);
6694 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
6697 set_cc_op(s
, CC_OP_SARB
+ ot
);
6700 gen_op_st_T0_A0(ot
+ s
->mem_index
);
6702 gen_op_mov_reg_T0(ot
, rm
);
6703 tcg_gen_mov_tl(cpu_cc_src
, cpu_tmp4
);
6704 tcg_gen_movi_tl(cpu_cc_dst
, 0);
6707 case 0x1bc: /* bsf */
6708 case 0x1bd: /* bsr */
6713 ot
= dflag
+ OT_WORD
;
6714 modrm
= cpu_ldub_code(env
, s
->pc
++);
6715 reg
= ((modrm
>> 3) & 7) | rex_r
;
6716 gen_ldst_modrm(env
, s
,modrm
, ot
, OR_TMP0
, 0);
6717 gen_extu(ot
, cpu_T
[0]);
6718 t0
= tcg_temp_local_new();
6719 tcg_gen_mov_tl(t0
, cpu_T
[0]);
6720 if ((b
& 1) && (prefixes
& PREFIX_REPZ
) &&
6721 (s
->cpuid_ext3_features
& CPUID_EXT3_ABM
)) {
6723 case OT_WORD
: gen_helper_lzcnt(cpu_T
[0], t0
,
6724 tcg_const_i32(16)); break;
6725 case OT_LONG
: gen_helper_lzcnt(cpu_T
[0], t0
,
6726 tcg_const_i32(32)); break;
6727 case OT_QUAD
: gen_helper_lzcnt(cpu_T
[0], t0
,
6728 tcg_const_i32(64)); break;
6730 gen_op_mov_reg_T0(ot
, reg
);
6732 label1
= gen_new_label();
6733 tcg_gen_movi_tl(cpu_cc_dst
, 0);
6734 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, label1
);
6736 gen_helper_bsr(cpu_T
[0], t0
);
6738 gen_helper_bsf(cpu_T
[0], t0
);
6740 gen_op_mov_reg_T0(ot
, reg
);
6741 tcg_gen_movi_tl(cpu_cc_dst
, 1);
6742 gen_set_label(label1
);
6743 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
6748 /************************/
6750 case 0x27: /* daa */
6753 gen_update_cc_op(s
);
6754 gen_helper_daa(cpu_env
);
6755 set_cc_op(s
, CC_OP_EFLAGS
);
6757 case 0x2f: /* das */
6760 gen_update_cc_op(s
);
6761 gen_helper_das(cpu_env
);
6762 set_cc_op(s
, CC_OP_EFLAGS
);
6764 case 0x37: /* aaa */
6767 gen_update_cc_op(s
);
6768 gen_helper_aaa(cpu_env
);
6769 set_cc_op(s
, CC_OP_EFLAGS
);
6771 case 0x3f: /* aas */
6774 gen_update_cc_op(s
);
6775 gen_helper_aas(cpu_env
);
6776 set_cc_op(s
, CC_OP_EFLAGS
);
6778 case 0xd4: /* aam */
6781 val
= cpu_ldub_code(env
, s
->pc
++);
6783 gen_exception(s
, EXCP00_DIVZ
, pc_start
- s
->cs_base
);
6785 gen_helper_aam(cpu_env
, tcg_const_i32(val
));
6786 set_cc_op(s
, CC_OP_LOGICB
);
6789 case 0xd5: /* aad */
6792 val
= cpu_ldub_code(env
, s
->pc
++);
6793 gen_helper_aad(cpu_env
, tcg_const_i32(val
));
6794 set_cc_op(s
, CC_OP_LOGICB
);
6796 /************************/
6798 case 0x90: /* nop */
6799 /* XXX: correct lock test for all insn */
6800 if (prefixes
& PREFIX_LOCK
) {
6803 /* If REX_B is set, then this is xchg eax, r8d, not a nop. */
6805 goto do_xchg_reg_eax
;
6807 if (prefixes
& PREFIX_REPZ
) {
6808 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_PAUSE
);
6811 case 0x9b: /* fwait */
6812 if ((s
->flags
& (HF_MP_MASK
| HF_TS_MASK
)) ==
6813 (HF_MP_MASK
| HF_TS_MASK
)) {
6814 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
6816 gen_update_cc_op(s
);
6817 gen_jmp_im(pc_start
- s
->cs_base
);
6818 gen_helper_fwait(cpu_env
);
6821 case 0xcc: /* int3 */
6822 gen_interrupt(s
, EXCP03_INT3
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6824 case 0xcd: /* int N */
6825 val
= cpu_ldub_code(env
, s
->pc
++);
6826 if (s
->vm86
&& s
->iopl
!= 3) {
6827 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6829 gen_interrupt(s
, val
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6832 case 0xce: /* into */
6835 gen_update_cc_op(s
);
6836 gen_jmp_im(pc_start
- s
->cs_base
);
6837 gen_helper_into(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
6840 case 0xf1: /* icebp (undocumented, exits to external debugger) */
6841 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_ICEBP
);
6843 gen_debug(s
, pc_start
- s
->cs_base
);
6847 qemu_set_log(CPU_LOG_INT
| CPU_LOG_TB_IN_ASM
);
6851 case 0xfa: /* cli */
6853 if (s
->cpl
<= s
->iopl
) {
6854 gen_helper_cli(cpu_env
);
6856 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6860 gen_helper_cli(cpu_env
);
6862 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6866 case 0xfb: /* sti */
6868 if (s
->cpl
<= s
->iopl
) {
6870 gen_helper_sti(cpu_env
);
6871 /* interruptions are enabled only the first insn after sti */
6872 /* If several instructions disable interrupts, only the
6874 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
6875 gen_helper_set_inhibit_irq(cpu_env
);
6876 /* give a chance to handle pending irqs */
6877 gen_jmp_im(s
->pc
- s
->cs_base
);
6880 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6886 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6890 case 0x62: /* bound */
6893 ot
= dflag
? OT_LONG
: OT_WORD
;
6894 modrm
= cpu_ldub_code(env
, s
->pc
++);
6895 reg
= (modrm
>> 3) & 7;
6896 mod
= (modrm
>> 6) & 3;
6899 gen_op_mov_TN_reg(ot
, 0, reg
);
6900 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
6901 gen_jmp_im(pc_start
- s
->cs_base
);
6902 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6903 if (ot
== OT_WORD
) {
6904 gen_helper_boundw(cpu_env
, cpu_A0
, cpu_tmp2_i32
);
6906 gen_helper_boundl(cpu_env
, cpu_A0
, cpu_tmp2_i32
);
6909 case 0x1c8 ... 0x1cf: /* bswap reg */
6910 reg
= (b
& 7) | REX_B(s
);
6911 #ifdef TARGET_X86_64
6913 gen_op_mov_TN_reg(OT_QUAD
, 0, reg
);
6914 tcg_gen_bswap64_i64(cpu_T
[0], cpu_T
[0]);
6915 gen_op_mov_reg_T0(OT_QUAD
, reg
);
6919 gen_op_mov_TN_reg(OT_LONG
, 0, reg
);
6920 tcg_gen_ext32u_tl(cpu_T
[0], cpu_T
[0]);
6921 tcg_gen_bswap32_tl(cpu_T
[0], cpu_T
[0]);
6922 gen_op_mov_reg_T0(OT_LONG
, reg
);
6925 case 0xd6: /* salc */
6928 gen_compute_eflags_c(s
, cpu_T
[0]);
6929 tcg_gen_neg_tl(cpu_T
[0], cpu_T
[0]);
6930 gen_op_mov_reg_T0(OT_BYTE
, R_EAX
);
6932 case 0xe0: /* loopnz */
6933 case 0xe1: /* loopz */
6934 case 0xe2: /* loop */
6935 case 0xe3: /* jecxz */
6939 tval
= (int8_t)insn_get(env
, s
, OT_BYTE
);
6940 next_eip
= s
->pc
- s
->cs_base
;
6945 l1
= gen_new_label();
6946 l2
= gen_new_label();
6947 l3
= gen_new_label();
6950 case 0: /* loopnz */
6952 gen_op_add_reg_im(s
->aflag
, R_ECX
, -1);
6953 gen_op_jz_ecx(s
->aflag
, l3
);
6954 gen_jcc1(s
, (JCC_Z
<< 1) | (b
^ 1), l1
);
6957 gen_op_add_reg_im(s
->aflag
, R_ECX
, -1);
6958 gen_op_jnz_ecx(s
->aflag
, l1
);
6962 gen_op_jz_ecx(s
->aflag
, l1
);
6967 gen_jmp_im(next_eip
);
6976 case 0x130: /* wrmsr */
6977 case 0x132: /* rdmsr */
6979 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6981 gen_update_cc_op(s
);
6982 gen_jmp_im(pc_start
- s
->cs_base
);
6984 gen_helper_rdmsr(cpu_env
);
6986 gen_helper_wrmsr(cpu_env
);
6990 case 0x131: /* rdtsc */
6991 gen_update_cc_op(s
);
6992 gen_jmp_im(pc_start
- s
->cs_base
);
6995 gen_helper_rdtsc(cpu_env
);
6998 gen_jmp(s
, s
->pc
- s
->cs_base
);
7001 case 0x133: /* rdpmc */
7002 gen_update_cc_op(s
);
7003 gen_jmp_im(pc_start
- s
->cs_base
);
7004 gen_helper_rdpmc(cpu_env
);
7006 case 0x134: /* sysenter */
7007 /* For Intel SYSENTER is valid on 64-bit */
7008 if (CODE64(s
) && env
->cpuid_vendor1
!= CPUID_VENDOR_INTEL_1
)
7011 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7013 gen_update_cc_op(s
);
7014 gen_jmp_im(pc_start
- s
->cs_base
);
7015 gen_helper_sysenter(cpu_env
);
7019 case 0x135: /* sysexit */
7020 /* For Intel SYSEXIT is valid on 64-bit */
7021 if (CODE64(s
) && env
->cpuid_vendor1
!= CPUID_VENDOR_INTEL_1
)
7024 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7026 gen_update_cc_op(s
);
7027 gen_jmp_im(pc_start
- s
->cs_base
);
7028 gen_helper_sysexit(cpu_env
, tcg_const_i32(dflag
));
7032 #ifdef TARGET_X86_64
7033 case 0x105: /* syscall */
7034 /* XXX: is it usable in real mode ? */
7035 gen_update_cc_op(s
);
7036 gen_jmp_im(pc_start
- s
->cs_base
);
7037 gen_helper_syscall(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
7040 case 0x107: /* sysret */
7042 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7044 gen_update_cc_op(s
);
7045 gen_jmp_im(pc_start
- s
->cs_base
);
7046 gen_helper_sysret(cpu_env
, tcg_const_i32(s
->dflag
));
7047 /* condition codes are modified only in long mode */
7049 set_cc_op(s
, CC_OP_EFLAGS
);
7055 case 0x1a2: /* cpuid */
7056 gen_update_cc_op(s
);
7057 gen_jmp_im(pc_start
- s
->cs_base
);
7058 gen_helper_cpuid(cpu_env
);
7060 case 0xf4: /* hlt */
7062 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7064 gen_update_cc_op(s
);
7065 gen_jmp_im(pc_start
- s
->cs_base
);
7066 gen_helper_hlt(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
7067 s
->is_jmp
= DISAS_TB_JUMP
;
7071 modrm
= cpu_ldub_code(env
, s
->pc
++);
7072 mod
= (modrm
>> 6) & 3;
7073 op
= (modrm
>> 3) & 7;
7076 if (!s
->pe
|| s
->vm86
)
7078 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_LDTR_READ
);
7079 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,ldt
.selector
));
7083 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 1);
7086 if (!s
->pe
|| s
->vm86
)
7089 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7091 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_LDTR_WRITE
);
7092 gen_ldst_modrm(env
, s
, modrm
, OT_WORD
, OR_TMP0
, 0);
7093 gen_jmp_im(pc_start
- s
->cs_base
);
7094 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
7095 gen_helper_lldt(cpu_env
, cpu_tmp2_i32
);
7099 if (!s
->pe
|| s
->vm86
)
7101 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_TR_READ
);
7102 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,tr
.selector
));
7106 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 1);
7109 if (!s
->pe
|| s
->vm86
)
7112 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7114 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_TR_WRITE
);
7115 gen_ldst_modrm(env
, s
, modrm
, OT_WORD
, OR_TMP0
, 0);
7116 gen_jmp_im(pc_start
- s
->cs_base
);
7117 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
7118 gen_helper_ltr(cpu_env
, cpu_tmp2_i32
);
7123 if (!s
->pe
|| s
->vm86
)
7125 gen_ldst_modrm(env
, s
, modrm
, OT_WORD
, OR_TMP0
, 0);
7126 gen_update_cc_op(s
);
7128 gen_helper_verr(cpu_env
, cpu_T
[0]);
7130 gen_helper_verw(cpu_env
, cpu_T
[0]);
7132 set_cc_op(s
, CC_OP_EFLAGS
);
7139 modrm
= cpu_ldub_code(env
, s
->pc
++);
7140 mod
= (modrm
>> 6) & 3;
7141 op
= (modrm
>> 3) & 7;
7147 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_GDTR_READ
);
7148 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7149 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, gdt
.limit
));
7150 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
7151 gen_add_A0_im(s
, 2);
7152 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, gdt
.base
));
7154 gen_op_andl_T0_im(0xffffff);
7155 gen_op_st_T0_A0(CODE64(s
) + OT_LONG
+ s
->mem_index
);
7160 case 0: /* monitor */
7161 if (!(s
->cpuid_ext_features
& CPUID_EXT_MONITOR
) ||
7164 gen_update_cc_op(s
);
7165 gen_jmp_im(pc_start
- s
->cs_base
);
7166 #ifdef TARGET_X86_64
7167 if (s
->aflag
== 2) {
7168 gen_op_movq_A0_reg(R_EAX
);
7172 gen_op_movl_A0_reg(R_EAX
);
7174 gen_op_andl_A0_ffff();
7176 gen_add_A0_ds_seg(s
);
7177 gen_helper_monitor(cpu_env
, cpu_A0
);
7180 if (!(s
->cpuid_ext_features
& CPUID_EXT_MONITOR
) ||
7183 gen_update_cc_op(s
);
7184 gen_jmp_im(pc_start
- s
->cs_base
);
7185 gen_helper_mwait(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
7189 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_SMAP
) ||
7193 gen_helper_clac(cpu_env
);
7194 gen_jmp_im(s
->pc
- s
->cs_base
);
7198 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_SMAP
) ||
7202 gen_helper_stac(cpu_env
);
7203 gen_jmp_im(s
->pc
- s
->cs_base
);
7210 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_IDTR_READ
);
7211 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7212 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, idt
.limit
));
7213 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
7214 gen_add_A0_im(s
, 2);
7215 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, idt
.base
));
7217 gen_op_andl_T0_im(0xffffff);
7218 gen_op_st_T0_A0(CODE64(s
) + OT_LONG
+ s
->mem_index
);
7224 gen_update_cc_op(s
);
7225 gen_jmp_im(pc_start
- s
->cs_base
);
7228 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7231 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7234 gen_helper_vmrun(cpu_env
, tcg_const_i32(s
->aflag
),
7235 tcg_const_i32(s
->pc
- pc_start
));
7237 s
->is_jmp
= DISAS_TB_JUMP
;
7240 case 1: /* VMMCALL */
7241 if (!(s
->flags
& HF_SVME_MASK
))
7243 gen_helper_vmmcall(cpu_env
);
7245 case 2: /* VMLOAD */
7246 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7249 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7252 gen_helper_vmload(cpu_env
, tcg_const_i32(s
->aflag
));
7255 case 3: /* VMSAVE */
7256 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7259 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7262 gen_helper_vmsave(cpu_env
, tcg_const_i32(s
->aflag
));
7266 if ((!(s
->flags
& HF_SVME_MASK
) &&
7267 !(s
->cpuid_ext3_features
& CPUID_EXT3_SKINIT
)) ||
7271 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7274 gen_helper_stgi(cpu_env
);
7278 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7281 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7284 gen_helper_clgi(cpu_env
);
7287 case 6: /* SKINIT */
7288 if ((!(s
->flags
& HF_SVME_MASK
) &&
7289 !(s
->cpuid_ext3_features
& CPUID_EXT3_SKINIT
)) ||
7292 gen_helper_skinit(cpu_env
);
7294 case 7: /* INVLPGA */
7295 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7298 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7301 gen_helper_invlpga(cpu_env
, tcg_const_i32(s
->aflag
));
7307 } else if (s
->cpl
!= 0) {
7308 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7310 gen_svm_check_intercept(s
, pc_start
,
7311 op
==2 ? SVM_EXIT_GDTR_WRITE
: SVM_EXIT_IDTR_WRITE
);
7312 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7313 gen_op_ld_T1_A0(OT_WORD
+ s
->mem_index
);
7314 gen_add_A0_im(s
, 2);
7315 gen_op_ld_T0_A0(CODE64(s
) + OT_LONG
+ s
->mem_index
);
7317 gen_op_andl_T0_im(0xffffff);
7319 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,gdt
.base
));
7320 tcg_gen_st32_tl(cpu_T
[1], cpu_env
, offsetof(CPUX86State
,gdt
.limit
));
7322 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,idt
.base
));
7323 tcg_gen_st32_tl(cpu_T
[1], cpu_env
, offsetof(CPUX86State
,idt
.limit
));
7328 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_READ_CR0
);
7329 #if defined TARGET_X86_64 && defined HOST_WORDS_BIGENDIAN
7330 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,cr
[0]) + 4);
7332 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,cr
[0]));
7334 gen_ldst_modrm(env
, s
, modrm
, OT_WORD
, OR_TMP0
, 1);
7338 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7340 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_WRITE_CR0
);
7341 gen_ldst_modrm(env
, s
, modrm
, OT_WORD
, OR_TMP0
, 0);
7342 gen_helper_lmsw(cpu_env
, cpu_T
[0]);
7343 gen_jmp_im(s
->pc
- s
->cs_base
);
7348 if (mod
!= 3) { /* invlpg */
7350 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7352 gen_update_cc_op(s
);
7353 gen_jmp_im(pc_start
- s
->cs_base
);
7354 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7355 gen_helper_invlpg(cpu_env
, cpu_A0
);
7356 gen_jmp_im(s
->pc
- s
->cs_base
);
7361 case 0: /* swapgs */
7362 #ifdef TARGET_X86_64
7365 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7367 tcg_gen_ld_tl(cpu_T
[0], cpu_env
,
7368 offsetof(CPUX86State
,segs
[R_GS
].base
));
7369 tcg_gen_ld_tl(cpu_T
[1], cpu_env
,
7370 offsetof(CPUX86State
,kernelgsbase
));
7371 tcg_gen_st_tl(cpu_T
[1], cpu_env
,
7372 offsetof(CPUX86State
,segs
[R_GS
].base
));
7373 tcg_gen_st_tl(cpu_T
[0], cpu_env
,
7374 offsetof(CPUX86State
,kernelgsbase
));
7382 case 1: /* rdtscp */
7383 if (!(s
->cpuid_ext2_features
& CPUID_EXT2_RDTSCP
))
7385 gen_update_cc_op(s
);
7386 gen_jmp_im(pc_start
- s
->cs_base
);
7389 gen_helper_rdtscp(cpu_env
);
7392 gen_jmp(s
, s
->pc
- s
->cs_base
);
7404 case 0x108: /* invd */
7405 case 0x109: /* wbinvd */
7407 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7409 gen_svm_check_intercept(s
, pc_start
, (b
& 2) ? SVM_EXIT_INVD
: SVM_EXIT_WBINVD
);
7413 case 0x63: /* arpl or movslS (x86_64) */
7414 #ifdef TARGET_X86_64
7417 /* d_ot is the size of destination */
7418 d_ot
= dflag
+ OT_WORD
;
7420 modrm
= cpu_ldub_code(env
, s
->pc
++);
7421 reg
= ((modrm
>> 3) & 7) | rex_r
;
7422 mod
= (modrm
>> 6) & 3;
7423 rm
= (modrm
& 7) | REX_B(s
);
7426 gen_op_mov_TN_reg(OT_LONG
, 0, rm
);
7428 if (d_ot
== OT_QUAD
)
7429 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
7430 gen_op_mov_reg_T0(d_ot
, reg
);
7432 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7433 if (d_ot
== OT_QUAD
) {
7434 gen_op_lds_T0_A0(OT_LONG
+ s
->mem_index
);
7436 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
7438 gen_op_mov_reg_T0(d_ot
, reg
);
7444 TCGv t0
, t1
, t2
, a0
;
7446 if (!s
->pe
|| s
->vm86
)
7448 t0
= tcg_temp_local_new();
7449 t1
= tcg_temp_local_new();
7450 t2
= tcg_temp_local_new();
7452 modrm
= cpu_ldub_code(env
, s
->pc
++);
7453 reg
= (modrm
>> 3) & 7;
7454 mod
= (modrm
>> 6) & 3;
7457 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7458 gen_op_ld_v(ot
+ s
->mem_index
, t0
, cpu_A0
);
7459 a0
= tcg_temp_local_new();
7460 tcg_gen_mov_tl(a0
, cpu_A0
);
7462 gen_op_mov_v_reg(ot
, t0
, rm
);
7465 gen_op_mov_v_reg(ot
, t1
, reg
);
7466 tcg_gen_andi_tl(cpu_tmp0
, t0
, 3);
7467 tcg_gen_andi_tl(t1
, t1
, 3);
7468 tcg_gen_movi_tl(t2
, 0);
7469 label1
= gen_new_label();
7470 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_tmp0
, t1
, label1
);
7471 tcg_gen_andi_tl(t0
, t0
, ~3);
7472 tcg_gen_or_tl(t0
, t0
, t1
);
7473 tcg_gen_movi_tl(t2
, CC_Z
);
7474 gen_set_label(label1
);
7476 gen_op_st_v(ot
+ s
->mem_index
, t0
, a0
);
7479 gen_op_mov_reg_v(ot
, rm
, t0
);
7481 gen_compute_eflags(s
);
7482 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~CC_Z
);
7483 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, t2
);
7489 case 0x102: /* lar */
7490 case 0x103: /* lsl */
7494 if (!s
->pe
|| s
->vm86
)
7496 ot
= dflag
? OT_LONG
: OT_WORD
;
7497 modrm
= cpu_ldub_code(env
, s
->pc
++);
7498 reg
= ((modrm
>> 3) & 7) | rex_r
;
7499 gen_ldst_modrm(env
, s
, modrm
, OT_WORD
, OR_TMP0
, 0);
7500 t0
= tcg_temp_local_new();
7501 gen_update_cc_op(s
);
7503 gen_helper_lar(t0
, cpu_env
, cpu_T
[0]);
7505 gen_helper_lsl(t0
, cpu_env
, cpu_T
[0]);
7507 tcg_gen_andi_tl(cpu_tmp0
, cpu_cc_src
, CC_Z
);
7508 label1
= gen_new_label();
7509 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_tmp0
, 0, label1
);
7510 gen_op_mov_reg_v(ot
, reg
, t0
);
7511 gen_set_label(label1
);
7512 set_cc_op(s
, CC_OP_EFLAGS
);
7517 modrm
= cpu_ldub_code(env
, s
->pc
++);
7518 mod
= (modrm
>> 6) & 3;
7519 op
= (modrm
>> 3) & 7;
7521 case 0: /* prefetchnta */
7522 case 1: /* prefetchnt0 */
7523 case 2: /* prefetchnt0 */
7524 case 3: /* prefetchnt0 */
7527 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7528 /* nothing more to do */
7530 default: /* nop (multi byte) */
7531 gen_nop_modrm(env
, s
, modrm
);
7535 case 0x119 ... 0x11f: /* nop (multi byte) */
7536 modrm
= cpu_ldub_code(env
, s
->pc
++);
7537 gen_nop_modrm(env
, s
, modrm
);
7539 case 0x120: /* mov reg, crN */
7540 case 0x122: /* mov crN, reg */
7542 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7544 modrm
= cpu_ldub_code(env
, s
->pc
++);
7545 /* Ignore the mod bits (assume (modrm&0xc0)==0xc0).
7546 * AMD documentation (24594.pdf) and testing of
7547 * intel 386 and 486 processors all show that the mod bits
7548 * are assumed to be 1's, regardless of actual values.
7550 rm
= (modrm
& 7) | REX_B(s
);
7551 reg
= ((modrm
>> 3) & 7) | rex_r
;
7556 if ((prefixes
& PREFIX_LOCK
) && (reg
== 0) &&
7557 (s
->cpuid_ext3_features
& CPUID_EXT3_CR8LEG
)) {
7566 gen_update_cc_op(s
);
7567 gen_jmp_im(pc_start
- s
->cs_base
);
7569 gen_op_mov_TN_reg(ot
, 0, rm
);
7570 gen_helper_write_crN(cpu_env
, tcg_const_i32(reg
),
7572 gen_jmp_im(s
->pc
- s
->cs_base
);
7575 gen_helper_read_crN(cpu_T
[0], cpu_env
, tcg_const_i32(reg
));
7576 gen_op_mov_reg_T0(ot
, rm
);
7584 case 0x121: /* mov reg, drN */
7585 case 0x123: /* mov drN, reg */
7587 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7589 modrm
= cpu_ldub_code(env
, s
->pc
++);
7590 /* Ignore the mod bits (assume (modrm&0xc0)==0xc0).
7591 * AMD documentation (24594.pdf) and testing of
7592 * intel 386 and 486 processors all show that the mod bits
7593 * are assumed to be 1's, regardless of actual values.
7595 rm
= (modrm
& 7) | REX_B(s
);
7596 reg
= ((modrm
>> 3) & 7) | rex_r
;
7601 /* XXX: do it dynamically with CR4.DE bit */
7602 if (reg
== 4 || reg
== 5 || reg
>= 8)
7605 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_WRITE_DR0
+ reg
);
7606 gen_op_mov_TN_reg(ot
, 0, rm
);
7607 gen_helper_movl_drN_T0(cpu_env
, tcg_const_i32(reg
), cpu_T
[0]);
7608 gen_jmp_im(s
->pc
- s
->cs_base
);
7611 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_READ_DR0
+ reg
);
7612 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,dr
[reg
]));
7613 gen_op_mov_reg_T0(ot
, rm
);
7617 case 0x106: /* clts */
7619 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7621 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_WRITE_CR0
);
7622 gen_helper_clts(cpu_env
);
7623 /* abort block because static cpu state changed */
7624 gen_jmp_im(s
->pc
- s
->cs_base
);
7628 /* MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4 support */
7629 case 0x1c3: /* MOVNTI reg, mem */
7630 if (!(s
->cpuid_features
& CPUID_SSE2
))
7632 ot
= s
->dflag
== 2 ? OT_QUAD
: OT_LONG
;
7633 modrm
= cpu_ldub_code(env
, s
->pc
++);
7634 mod
= (modrm
>> 6) & 3;
7637 reg
= ((modrm
>> 3) & 7) | rex_r
;
7638 /* generate a generic store */
7639 gen_ldst_modrm(env
, s
, modrm
, ot
, reg
, 1);
7642 modrm
= cpu_ldub_code(env
, s
->pc
++);
7643 mod
= (modrm
>> 6) & 3;
7644 op
= (modrm
>> 3) & 7;
7646 case 0: /* fxsave */
7647 if (mod
== 3 || !(s
->cpuid_features
& CPUID_FXSR
) ||
7648 (s
->prefix
& PREFIX_LOCK
))
7650 if ((s
->flags
& HF_EM_MASK
) || (s
->flags
& HF_TS_MASK
)) {
7651 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7654 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7655 gen_update_cc_op(s
);
7656 gen_jmp_im(pc_start
- s
->cs_base
);
7657 gen_helper_fxsave(cpu_env
, cpu_A0
, tcg_const_i32((s
->dflag
== 2)));
7659 case 1: /* fxrstor */
7660 if (mod
== 3 || !(s
->cpuid_features
& CPUID_FXSR
) ||
7661 (s
->prefix
& PREFIX_LOCK
))
7663 if ((s
->flags
& HF_EM_MASK
) || (s
->flags
& HF_TS_MASK
)) {
7664 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7667 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7668 gen_update_cc_op(s
);
7669 gen_jmp_im(pc_start
- s
->cs_base
);
7670 gen_helper_fxrstor(cpu_env
, cpu_A0
,
7671 tcg_const_i32((s
->dflag
== 2)));
7673 case 2: /* ldmxcsr */
7674 case 3: /* stmxcsr */
7675 if (s
->flags
& HF_TS_MASK
) {
7676 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7679 if ((s
->flags
& HF_EM_MASK
) || !(s
->flags
& HF_OSFXSR_MASK
) ||
7682 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7684 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
7685 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
7686 gen_helper_ldmxcsr(cpu_env
, cpu_tmp2_i32
);
7688 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, mxcsr
));
7689 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
7692 case 5: /* lfence */
7693 case 6: /* mfence */
7694 if ((modrm
& 0xc7) != 0xc0 || !(s
->cpuid_features
& CPUID_SSE2
))
7697 case 7: /* sfence / clflush */
7698 if ((modrm
& 0xc7) == 0xc0) {
7700 /* XXX: also check for cpuid_ext2_features & CPUID_EXT2_EMMX */
7701 if (!(s
->cpuid_features
& CPUID_SSE
))
7705 if (!(s
->cpuid_features
& CPUID_CLFLUSH
))
7707 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7714 case 0x10d: /* 3DNow! prefetch(w) */
7715 modrm
= cpu_ldub_code(env
, s
->pc
++);
7716 mod
= (modrm
>> 6) & 3;
7719 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7720 /* ignore for now */
7722 case 0x1aa: /* rsm */
7723 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_RSM
);
7724 if (!(s
->flags
& HF_SMM_MASK
))
7726 gen_update_cc_op(s
);
7727 gen_jmp_im(s
->pc
- s
->cs_base
);
7728 gen_helper_rsm(cpu_env
);
7731 case 0x1b8: /* SSE4.2 popcnt */
7732 if ((prefixes
& (PREFIX_REPZ
| PREFIX_LOCK
| PREFIX_REPNZ
)) !=
7735 if (!(s
->cpuid_ext_features
& CPUID_EXT_POPCNT
))
7738 modrm
= cpu_ldub_code(env
, s
->pc
++);
7739 reg
= ((modrm
>> 3) & 7) | rex_r
;
7741 if (s
->prefix
& PREFIX_DATA
)
7743 else if (s
->dflag
!= 2)
7748 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
7749 gen_helper_popcnt(cpu_T
[0], cpu_env
, cpu_T
[0], tcg_const_i32(ot
));
7750 gen_op_mov_reg_T0(ot
, reg
);
7752 set_cc_op(s
, CC_OP_EFLAGS
);
7754 case 0x10e ... 0x10f:
7755 /* 3DNow! instructions, ignore prefixes */
7756 s
->prefix
&= ~(PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
);
7757 case 0x110 ... 0x117:
7758 case 0x128 ... 0x12f:
7759 case 0x138 ... 0x13a:
7760 case 0x150 ... 0x179:
7761 case 0x17c ... 0x17f:
7763 case 0x1c4 ... 0x1c6:
7764 case 0x1d0 ... 0x1fe:
7765 gen_sse(env
, s
, b
, pc_start
, rex_r
);
7770 /* lock generation */
7771 if (s
->prefix
& PREFIX_LOCK
)
7772 gen_helper_unlock();
7775 if (s
->prefix
& PREFIX_LOCK
)
7776 gen_helper_unlock();
7777 /* XXX: ensure that no lock was generated */
7778 gen_exception(s
, EXCP06_ILLOP
, pc_start
- s
->cs_base
);
7782 void optimize_flags_init(void)
7784 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
7785 cpu_cc_op
= tcg_global_mem_new_i32(TCG_AREG0
,
7786 offsetof(CPUX86State
, cc_op
), "cc_op");
7787 cpu_cc_dst
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUX86State
, cc_dst
),
7789 cpu_cc_src
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUX86State
, cc_src
),
7792 #ifdef TARGET_X86_64
7793 cpu_regs
[R_EAX
] = tcg_global_mem_new_i64(TCG_AREG0
,
7794 offsetof(CPUX86State
, regs
[R_EAX
]), "rax");
7795 cpu_regs
[R_ECX
] = tcg_global_mem_new_i64(TCG_AREG0
,
7796 offsetof(CPUX86State
, regs
[R_ECX
]), "rcx");
7797 cpu_regs
[R_EDX
] = tcg_global_mem_new_i64(TCG_AREG0
,
7798 offsetof(CPUX86State
, regs
[R_EDX
]), "rdx");
7799 cpu_regs
[R_EBX
] = tcg_global_mem_new_i64(TCG_AREG0
,
7800 offsetof(CPUX86State
, regs
[R_EBX
]), "rbx");
7801 cpu_regs
[R_ESP
] = tcg_global_mem_new_i64(TCG_AREG0
,
7802 offsetof(CPUX86State
, regs
[R_ESP
]), "rsp");
7803 cpu_regs
[R_EBP
] = tcg_global_mem_new_i64(TCG_AREG0
,
7804 offsetof(CPUX86State
, regs
[R_EBP
]), "rbp");
7805 cpu_regs
[R_ESI
] = tcg_global_mem_new_i64(TCG_AREG0
,
7806 offsetof(CPUX86State
, regs
[R_ESI
]), "rsi");
7807 cpu_regs
[R_EDI
] = tcg_global_mem_new_i64(TCG_AREG0
,
7808 offsetof(CPUX86State
, regs
[R_EDI
]), "rdi");
7809 cpu_regs
[8] = tcg_global_mem_new_i64(TCG_AREG0
,
7810 offsetof(CPUX86State
, regs
[8]), "r8");
7811 cpu_regs
[9] = tcg_global_mem_new_i64(TCG_AREG0
,
7812 offsetof(CPUX86State
, regs
[9]), "r9");
7813 cpu_regs
[10] = tcg_global_mem_new_i64(TCG_AREG0
,
7814 offsetof(CPUX86State
, regs
[10]), "r10");
7815 cpu_regs
[11] = tcg_global_mem_new_i64(TCG_AREG0
,
7816 offsetof(CPUX86State
, regs
[11]), "r11");
7817 cpu_regs
[12] = tcg_global_mem_new_i64(TCG_AREG0
,
7818 offsetof(CPUX86State
, regs
[12]), "r12");
7819 cpu_regs
[13] = tcg_global_mem_new_i64(TCG_AREG0
,
7820 offsetof(CPUX86State
, regs
[13]), "r13");
7821 cpu_regs
[14] = tcg_global_mem_new_i64(TCG_AREG0
,
7822 offsetof(CPUX86State
, regs
[14]), "r14");
7823 cpu_regs
[15] = tcg_global_mem_new_i64(TCG_AREG0
,
7824 offsetof(CPUX86State
, regs
[15]), "r15");
7826 cpu_regs
[R_EAX
] = tcg_global_mem_new_i32(TCG_AREG0
,
7827 offsetof(CPUX86State
, regs
[R_EAX
]), "eax");
7828 cpu_regs
[R_ECX
] = tcg_global_mem_new_i32(TCG_AREG0
,
7829 offsetof(CPUX86State
, regs
[R_ECX
]), "ecx");
7830 cpu_regs
[R_EDX
] = tcg_global_mem_new_i32(TCG_AREG0
,
7831 offsetof(CPUX86State
, regs
[R_EDX
]), "edx");
7832 cpu_regs
[R_EBX
] = tcg_global_mem_new_i32(TCG_AREG0
,
7833 offsetof(CPUX86State
, regs
[R_EBX
]), "ebx");
7834 cpu_regs
[R_ESP
] = tcg_global_mem_new_i32(TCG_AREG0
,
7835 offsetof(CPUX86State
, regs
[R_ESP
]), "esp");
7836 cpu_regs
[R_EBP
] = tcg_global_mem_new_i32(TCG_AREG0
,
7837 offsetof(CPUX86State
, regs
[R_EBP
]), "ebp");
7838 cpu_regs
[R_ESI
] = tcg_global_mem_new_i32(TCG_AREG0
,
7839 offsetof(CPUX86State
, regs
[R_ESI
]), "esi");
7840 cpu_regs
[R_EDI
] = tcg_global_mem_new_i32(TCG_AREG0
,
7841 offsetof(CPUX86State
, regs
[R_EDI
]), "edi");
7844 /* register helpers */
7845 #define GEN_HELPER 2
7849 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
7850 basic block 'tb'. If search_pc is TRUE, also generate PC
7851 information for each intermediate instruction. */
7852 static inline void gen_intermediate_code_internal(CPUX86State
*env
,
7853 TranslationBlock
*tb
,
7856 DisasContext dc1
, *dc
= &dc1
;
7857 target_ulong pc_ptr
;
7858 uint16_t *gen_opc_end
;
7862 target_ulong pc_start
;
7863 target_ulong cs_base
;
7867 /* generate intermediate code */
7869 cs_base
= tb
->cs_base
;
7872 dc
->pe
= (flags
>> HF_PE_SHIFT
) & 1;
7873 dc
->code32
= (flags
>> HF_CS32_SHIFT
) & 1;
7874 dc
->ss32
= (flags
>> HF_SS32_SHIFT
) & 1;
7875 dc
->addseg
= (flags
>> HF_ADDSEG_SHIFT
) & 1;
7877 dc
->vm86
= (flags
>> VM_SHIFT
) & 1;
7878 dc
->cpl
= (flags
>> HF_CPL_SHIFT
) & 3;
7879 dc
->iopl
= (flags
>> IOPL_SHIFT
) & 3;
7880 dc
->tf
= (flags
>> TF_SHIFT
) & 1;
7881 dc
->singlestep_enabled
= env
->singlestep_enabled
;
7882 dc
->cc_op
= CC_OP_DYNAMIC
;
7883 dc
->cc_op_dirty
= false;
7884 dc
->cs_base
= cs_base
;
7886 dc
->popl_esp_hack
= 0;
7887 /* select memory access functions */
7889 if (flags
& HF_SOFTMMU_MASK
) {
7890 dc
->mem_index
= (cpu_mmu_index(env
) + 1) << 2;
7892 dc
->cpuid_features
= env
->cpuid_features
;
7893 dc
->cpuid_ext_features
= env
->cpuid_ext_features
;
7894 dc
->cpuid_ext2_features
= env
->cpuid_ext2_features
;
7895 dc
->cpuid_ext3_features
= env
->cpuid_ext3_features
;
7896 dc
->cpuid_7_0_ebx_features
= env
->cpuid_7_0_ebx_features
;
7897 #ifdef TARGET_X86_64
7898 dc
->lma
= (flags
>> HF_LMA_SHIFT
) & 1;
7899 dc
->code64
= (flags
>> HF_CS64_SHIFT
) & 1;
7902 dc
->jmp_opt
= !(dc
->tf
|| env
->singlestep_enabled
||
7903 (flags
& HF_INHIBIT_IRQ_MASK
)
7904 #ifndef CONFIG_SOFTMMU
7905 || (flags
& HF_SOFTMMU_MASK
)
7909 /* check addseg logic */
7910 if (!dc
->addseg
&& (dc
->vm86
|| !dc
->pe
|| !dc
->code32
))
7911 printf("ERROR addseg\n");
7914 cpu_T
[0] = tcg_temp_new();
7915 cpu_T
[1] = tcg_temp_new();
7916 cpu_A0
= tcg_temp_new();
7918 cpu_tmp0
= tcg_temp_new();
7919 cpu_tmp1_i64
= tcg_temp_new_i64();
7920 cpu_tmp2_i32
= tcg_temp_new_i32();
7921 cpu_tmp3_i32
= tcg_temp_new_i32();
7922 cpu_tmp4
= tcg_temp_new();
7923 cpu_tmp5
= tcg_temp_new();
7924 cpu_ptr0
= tcg_temp_new_ptr();
7925 cpu_ptr1
= tcg_temp_new_ptr();
7926 cpu_cc_srcT
= tcg_temp_local_new();
7928 gen_opc_end
= tcg_ctx
.gen_opc_buf
+ OPC_MAX_SIZE
;
7930 dc
->is_jmp
= DISAS_NEXT
;
7934 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
7936 max_insns
= CF_COUNT_MASK
;
7940 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
7941 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
7942 if (bp
->pc
== pc_ptr
&&
7943 !((bp
->flags
& BP_CPU
) && (tb
->flags
& HF_RF_MASK
))) {
7944 gen_debug(dc
, pc_ptr
- dc
->cs_base
);
7950 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
7954 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
7956 tcg_ctx
.gen_opc_pc
[lj
] = pc_ptr
;
7957 gen_opc_cc_op
[lj
] = dc
->cc_op
;
7958 tcg_ctx
.gen_opc_instr_start
[lj
] = 1;
7959 tcg_ctx
.gen_opc_icount
[lj
] = num_insns
;
7961 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
7964 pc_ptr
= disas_insn(env
, dc
, pc_ptr
);
7966 /* stop translation if indicated */
7969 /* if single step mode, we generate only one instruction and
7970 generate an exception */
7971 /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
7972 the flag and abort the translation to give the irqs a
7973 change to be happen */
7974 if (dc
->tf
|| dc
->singlestep_enabled
||
7975 (flags
& HF_INHIBIT_IRQ_MASK
)) {
7976 gen_jmp_im(pc_ptr
- dc
->cs_base
);
7980 /* if too long translation, stop generation too */
7981 if (tcg_ctx
.gen_opc_ptr
>= gen_opc_end
||
7982 (pc_ptr
- pc_start
) >= (TARGET_PAGE_SIZE
- 32) ||
7983 num_insns
>= max_insns
) {
7984 gen_jmp_im(pc_ptr
- dc
->cs_base
);
7989 gen_jmp_im(pc_ptr
- dc
->cs_base
);
7994 if (tb
->cflags
& CF_LAST_IO
)
7996 gen_icount_end(tb
, num_insns
);
7997 *tcg_ctx
.gen_opc_ptr
= INDEX_op_end
;
7998 /* we don't forget to fill the last values */
8000 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
8003 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
8007 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
8009 qemu_log("----------------\n");
8010 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
8011 #ifdef TARGET_X86_64
8016 disas_flags
= !dc
->code32
;
8017 log_target_disas(env
, pc_start
, pc_ptr
- pc_start
, disas_flags
);
8023 tb
->size
= pc_ptr
- pc_start
;
8024 tb
->icount
= num_insns
;
8028 void gen_intermediate_code(CPUX86State
*env
, TranslationBlock
*tb
)
8030 gen_intermediate_code_internal(env
, tb
, 0);
8033 void gen_intermediate_code_pc(CPUX86State
*env
, TranslationBlock
*tb
)
8035 gen_intermediate_code_internal(env
, tb
, 1);
8038 void restore_state_to_opc(CPUX86State
*env
, TranslationBlock
*tb
, int pc_pos
)
8042 if (qemu_loglevel_mask(CPU_LOG_TB_OP
)) {
8044 qemu_log("RESTORE:\n");
8045 for(i
= 0;i
<= pc_pos
; i
++) {
8046 if (tcg_ctx
.gen_opc_instr_start
[i
]) {
8047 qemu_log("0x%04x: " TARGET_FMT_lx
"\n", i
,
8048 tcg_ctx
.gen_opc_pc
[i
]);
8051 qemu_log("pc_pos=0x%x eip=" TARGET_FMT_lx
" cs_base=%x\n",
8052 pc_pos
, tcg_ctx
.gen_opc_pc
[pc_pos
] - tb
->cs_base
,
8053 (uint32_t)tb
->cs_base
);
8056 env
->eip
= tcg_ctx
.gen_opc_pc
[pc_pos
] - tb
->cs_base
;
8057 cc_op
= gen_opc_cc_op
[pc_pos
];
8058 if (cc_op
!= CC_OP_DYNAMIC
)