target-microblaze/op_helper.c

   1 /*
   2  *  Microblaze helper routines.
   3  *
   4  *  Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>.
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <assert.h>
  21 #include "cpu.h"
  22 #include "dyngen-exec.h"
  23 #include "helper.h"
  24 #include "host-utils.h"
  25
  26 #define D(x)
  27
  28 #if !defined(CONFIG_USER_ONLY)
  29 #include "softmmu_exec.h"
  30
  31 #define MMUSUFFIX _mmu
  32 #define SHIFT 0
  33 #include "softmmu_template.h"
  34 #define SHIFT 1
  35 #include "softmmu_template.h"
  36 #define SHIFT 2
  37 #include "softmmu_template.h"
  38 #define SHIFT 3
  39 #include "softmmu_template.h"
  40
  41 /* Try to fill the TLB and return an exception if error. If retaddr is
  42    NULL, it means that the function was called in C code (i.e. not
  43    from generated code or from helper.c) */
  44 /* XXX: fix it to restore all registers */
  45 void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx,
  46               void *retaddr)
  47 {
  48     TranslationBlock *tb;
  49     CPUState *saved_env;
  50     unsigned long pc;
  51     int ret;
  52
  53     saved_env = env;
  54     env = env1;
  55
  56     ret = cpu_mb_handle_mmu_fault(env, addr, is_write, mmu_idx);
  57     if (unlikely(ret)) {
  58         if (retaddr) {
  59             /* now we have a real cpu fault */
  60             pc = (unsigned long)retaddr;
  61             tb = tb_find_pc(pc);
  62             if (tb) {
  63                 /* the PC is inside the translated code. It means that we have
  64                    a virtual CPU fault */
  65                 cpu_restore_state(tb, env, pc);
  66             }
  67         }
  68         cpu_loop_exit(env);
  69     }
  70     env = saved_env;
  71 }
  72 #endif
  73
  74 void helper_put(uint32_t id, uint32_t ctrl, uint32_t data)
  75 {
  76     int test = ctrl & STREAM_TEST;
  77     int atomic = ctrl & STREAM_ATOMIC;
  78     int control = ctrl & STREAM_CONTROL;
  79     int nonblock = ctrl & STREAM_NONBLOCK;
  80     int exception = ctrl & STREAM_EXCEPTION;
  81
  82     qemu_log("Unhandled stream put to stream-id=%d data=%x %s%s%s%s%s\n",
  83              id, data,
  84              test ? "t" : "",
  85              nonblock ? "n" : "",
  86              exception ? "e" : "",
  87              control ? "c" : "",
  88              atomic ? "a" : "");
  89 }
  90
  91 uint32_t helper_get(uint32_t id, uint32_t ctrl)
  92 {
  93     int test = ctrl & STREAM_TEST;
  94     int atomic = ctrl & STREAM_ATOMIC;
  95     int control = ctrl & STREAM_CONTROL;
  96     int nonblock = ctrl & STREAM_NONBLOCK;
  97     int exception = ctrl & STREAM_EXCEPTION;
  98
  99     qemu_log("Unhandled stream get from stream-id=%d %s%s%s%s%s\n",
 100              id,
 101              test ? "t" : "",
 102              nonblock ? "n" : "",
 103              exception ? "e" : "",
 104              control ? "c" : "",
 105              atomic ? "a" : "");
 106     return 0xdead0000 | id;
 107 }
 108
 109 void helper_raise_exception(uint32_t index)
 110 {
 111     env->exception_index = index;
 112     cpu_loop_exit(env);
 113 }
 114
 115 void helper_debug(void)
 116 {
 117     int i;
 118
 119     qemu_log("PC=%8.8x\n", env->sregs[SR_PC]);
 120     qemu_log("rmsr=%x resr=%x rear=%x debug[%x] imm=%x iflags=%x\n",
 121              env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
 122              env->debug, env->imm, env->iflags);
 123     qemu_log("btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
 124              env->btaken, env->btarget,
 125              (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
 126              (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
 127              (env->sregs[SR_MSR] & MSR_EIP),
 128              (env->sregs[SR_MSR] & MSR_IE));
 129     for (i = 0; i < 32; i++) {
 130         qemu_log("r%2.2d=%8.8x ", i, env->regs[i]);
 131         if ((i + 1) % 4 == 0)
 132             qemu_log("\n");
 133     }
 134     qemu_log("\n\n");
 135 }
 136
 137 static inline uint32_t compute_carry(uint32_t a, uint32_t b, uint32_t cin)
 138 {
 139     uint32_t cout = 0;
 140
 141     if ((b == ~0) && cin)
 142         cout = 1;
 143     else if ((~0 - a) < (b + cin))
 144         cout = 1;
 145     return cout;
 146 }
 147
 148 uint32_t helper_cmp(uint32_t a, uint32_t b)
 149 {
 150     uint32_t t;
 151
 152     t = b + ~a + 1;
 153     if ((b & 0x80000000) ^ (a & 0x80000000))
 154         t = (t & 0x7fffffff) | (b & 0x80000000);
 155     return t;
 156 }
 157
 158 uint32_t helper_cmpu(uint32_t a, uint32_t b)
 159 {
 160     uint32_t t;
 161
 162     t = b + ~a + 1;
 163     if ((b & 0x80000000) ^ (a & 0x80000000))
 164         t = (t & 0x7fffffff) | (a & 0x80000000);
 165     return t;
 166 }
 167
 168 uint32_t helper_clz(uint32_t t0)
 169 {
 170     return clz32(t0);
 171 }
 172
 173 uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf)
 174 {
 175     uint32_t ncf;
 176     ncf = compute_carry(a, b, cf);
 177     return ncf;
 178 }
 179
 180 static inline int div_prepare(uint32_t a, uint32_t b)
 181 {
 182     if (b == 0) {
 183         env->sregs[SR_MSR] |= MSR_DZ;
 184
 185         if ((env->sregs[SR_MSR] & MSR_EE)
 186             && !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
 187             env->sregs[SR_ESR] = ESR_EC_DIVZERO;
 188             helper_raise_exception(EXCP_HW_EXCP);
 189         }
 190         return 0;
 191     }
 192     env->sregs[SR_MSR] &= ~MSR_DZ;
 193     return 1;
 194 }
 195
 196 uint32_t helper_divs(uint32_t a, uint32_t b)
 197 {
 198     if (!div_prepare(a, b))
 199         return 0;
 200     return (int32_t)a / (int32_t)b;
 201 }
 202
 203 uint32_t helper_divu(uint32_t a, uint32_t b)
 204 {
 205     if (!div_prepare(a, b))
 206         return 0;
 207     return a / b;
 208 }
 209
 210 /* raise FPU exception.  */
 211 static void raise_fpu_exception(void)
 212 {
 213     env->sregs[SR_ESR] = ESR_EC_FPU;
 214     helper_raise_exception(EXCP_HW_EXCP);
 215 }
 216
 217 static void update_fpu_flags(int flags)
 218 {
 219     int raise = 0;
 220
 221     if (flags & float_flag_invalid) {
 222         env->sregs[SR_FSR] |= FSR_IO;
 223         raise = 1;
 224     }
 225     if (flags & float_flag_divbyzero) {
 226         env->sregs[SR_FSR] |= FSR_DZ;
 227         raise = 1;
 228     }
 229     if (flags & float_flag_overflow) {
 230         env->sregs[SR_FSR] |= FSR_OF;
 231         raise = 1;
 232     }
 233     if (flags & float_flag_underflow) {
 234         env->sregs[SR_FSR] |= FSR_UF;
 235         raise = 1;
 236     }
 237     if (raise
 238         && (env->pvr.regs[2] & PVR2_FPU_EXC_MASK)
 239         && (env->sregs[SR_MSR] & MSR_EE)) {
 240         raise_fpu_exception();
 241     }
 242 }
 243
 244 uint32_t helper_fadd(uint32_t a, uint32_t b)
 245 {
 246     CPU_FloatU fd, fa, fb;
 247     int flags;
 248
 249     set_float_exception_flags(0, &env->fp_status);
 250     fa.l = a;
 251     fb.l = b;
 252     fd.f = float32_add(fa.f, fb.f, &env->fp_status);
 253
 254     flags = get_float_exception_flags(&env->fp_status);
 255     update_fpu_flags(flags);
 256     return fd.l;
 257 }
 258
 259 uint32_t helper_frsub(uint32_t a, uint32_t b)
 260 {
 261     CPU_FloatU fd, fa, fb;
 262     int flags;
 263
 264     set_float_exception_flags(0, &env->fp_status);
 265     fa.l = a;
 266     fb.l = b;
 267     fd.f = float32_sub(fb.f, fa.f, &env->fp_status);
 268     flags = get_float_exception_flags(&env->fp_status);
 269     update_fpu_flags(flags);
 270     return fd.l;
 271 }
 272
 273 uint32_t helper_fmul(uint32_t a, uint32_t b)
 274 {
 275     CPU_FloatU fd, fa, fb;
 276     int flags;
 277
 278     set_float_exception_flags(0, &env->fp_status);
 279     fa.l = a;
 280     fb.l = b;
 281     fd.f = float32_mul(fa.f, fb.f, &env->fp_status);
 282     flags = get_float_exception_flags(&env->fp_status);
 283     update_fpu_flags(flags);
 284
 285     return fd.l;
 286 }
 287
 288 uint32_t helper_fdiv(uint32_t a, uint32_t b)
 289 {
 290     CPU_FloatU fd, fa, fb;
 291     int flags;
 292
 293     set_float_exception_flags(0, &env->fp_status);
 294     fa.l = a;
 295     fb.l = b;
 296     fd.f = float32_div(fb.f, fa.f, &env->fp_status);
 297     flags = get_float_exception_flags(&env->fp_status);
 298     update_fpu_flags(flags);
 299
 300     return fd.l;
 301 }
 302
 303 uint32_t helper_fcmp_un(uint32_t a, uint32_t b)
 304 {
 305     CPU_FloatU fa, fb;
 306     uint32_t r = 0;
 307
 308     fa.l = a;
 309     fb.l = b;
 310
 311     if (float32_is_signaling_nan(fa.f) || float32_is_signaling_nan(fb.f)) {
 312         update_fpu_flags(float_flag_invalid);
 313         r = 1;
 314     }
 315
 316     if (float32_is_quiet_nan(fa.f) || float32_is_quiet_nan(fb.f)) {
 317         r = 1;
 318     }
 319
 320     return r;
 321 }
 322
 323 uint32_t helper_fcmp_lt(uint32_t a, uint32_t b)
 324 {
 325     CPU_FloatU fa, fb;
 326     int r;
 327     int flags;
 328
 329     set_float_exception_flags(0, &env->fp_status);
 330     fa.l = a;
 331     fb.l = b;
 332     r = float32_lt(fb.f, fa.f, &env->fp_status);
 333     flags = get_float_exception_flags(&env->fp_status);
 334     update_fpu_flags(flags & float_flag_invalid);
 335
 336     return r;
 337 }
 338
 339 uint32_t helper_fcmp_eq(uint32_t a, uint32_t b)
 340 {
 341     CPU_FloatU fa, fb;
 342     int flags;
 343     int r;
 344
 345     set_float_exception_flags(0, &env->fp_status);
 346     fa.l = a;
 347     fb.l = b;
 348     r = float32_eq_quiet(fa.f, fb.f, &env->fp_status);
 349     flags = get_float_exception_flags(&env->fp_status);
 350     update_fpu_flags(flags & float_flag_invalid);
 351
 352     return r;
 353 }
 354
 355 uint32_t helper_fcmp_le(uint32_t a, uint32_t b)
 356 {
 357     CPU_FloatU fa, fb;
 358     int flags;
 359     int r;
 360
 361     fa.l = a;
 362     fb.l = b;
 363     set_float_exception_flags(0, &env->fp_status);
 364     r = float32_le(fa.f, fb.f, &env->fp_status);
 365     flags = get_float_exception_flags(&env->fp_status);
 366     update_fpu_flags(flags & float_flag_invalid);
 367
 368
 369     return r;
 370 }
 371
 372 uint32_t helper_fcmp_gt(uint32_t a, uint32_t b)
 373 {
 374     CPU_FloatU fa, fb;
 375     int flags, r;
 376
 377     fa.l = a;
 378     fb.l = b;
 379     set_float_exception_flags(0, &env->fp_status);
 380     r = float32_lt(fa.f, fb.f, &env->fp_status);
 381     flags = get_float_exception_flags(&env->fp_status);
 382     update_fpu_flags(flags & float_flag_invalid);
 383     return r;
 384 }
 385
 386 uint32_t helper_fcmp_ne(uint32_t a, uint32_t b)
 387 {
 388     CPU_FloatU fa, fb;
 389     int flags, r;
 390
 391     fa.l = a;
 392     fb.l = b;
 393     set_float_exception_flags(0, &env->fp_status);
 394     r = !float32_eq_quiet(fa.f, fb.f, &env->fp_status);
 395     flags = get_float_exception_flags(&env->fp_status);
 396     update_fpu_flags(flags & float_flag_invalid);
 397
 398     return r;
 399 }
 400
 401 uint32_t helper_fcmp_ge(uint32_t a, uint32_t b)
 402 {
 403     CPU_FloatU fa, fb;
 404     int flags, r;
 405
 406     fa.l = a;
 407     fb.l = b;
 408     set_float_exception_flags(0, &env->fp_status);
 409     r = !float32_lt(fa.f, fb.f, &env->fp_status);
 410     flags = get_float_exception_flags(&env->fp_status);
 411     update_fpu_flags(flags & float_flag_invalid);
 412
 413     return r;
 414 }
 415
 416 uint32_t helper_flt(uint32_t a)
 417 {
 418     CPU_FloatU fd, fa;
 419
 420     fa.l = a;
 421     fd.f = int32_to_float32(fa.l, &env->fp_status);
 422     return fd.l;
 423 }
 424
 425 uint32_t helper_fint(uint32_t a)
 426 {
 427     CPU_FloatU fa;
 428     uint32_t r;
 429     int flags;
 430
 431     set_float_exception_flags(0, &env->fp_status);
 432     fa.l = a;
 433     r = float32_to_int32(fa.f, &env->fp_status);
 434     flags = get_float_exception_flags(&env->fp_status);
 435     update_fpu_flags(flags);
 436
 437     return r;
 438 }
 439
 440 uint32_t helper_fsqrt(uint32_t a)
 441 {
 442     CPU_FloatU fd, fa;
 443     int flags;
 444
 445     set_float_exception_flags(0, &env->fp_status);
 446     fa.l = a;
 447     fd.l = float32_sqrt(fa.f, &env->fp_status);
 448     flags = get_float_exception_flags(&env->fp_status);
 449     update_fpu_flags(flags);
 450
 451     return fd.l;
 452 }
 453
 454 uint32_t helper_pcmpbf(uint32_t a, uint32_t b)
 455 {
 456     unsigned int i;
 457     uint32_t mask = 0xff000000;
 458
 459     for (i = 0; i < 4; i++) {
 460         if ((a & mask) == (b & mask))
 461             return i + 1;
 462         mask >>= 8;
 463     }
 464     return 0;
 465 }
 466
 467 void helper_memalign(uint32_t addr, uint32_t dr, uint32_t wr, uint32_t mask)
 468 {
 469     if (addr & mask) {
 470             qemu_log_mask(CPU_LOG_INT,
 471                           "unaligned access addr=%x mask=%x, wr=%d dr=r%d\n",
 472                           addr, mask, wr, dr);
 473             env->sregs[SR_EAR] = addr;
 474             env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA | (wr << 10) \
 475                                  | (dr & 31) << 5;
 476             if (mask == 3) {
 477                 env->sregs[SR_ESR] |= 1 << 11;
 478             }
 479             if (!(env->sregs[SR_MSR] & MSR_EE)) {
 480                 return;
 481             }
 482             helper_raise_exception(EXCP_HW_EXCP);
 483     }
 484 }
 485
 486 void helper_stackprot(uint32_t addr)
 487 {
 488     if (addr < env->slr || addr > env->shr) {
 489             qemu_log("Stack protector violation at %x %x %x\n",
 490                      addr, env->slr, env->shr);
 491             env->sregs[SR_EAR] = addr;
 492             env->sregs[SR_ESR] = ESR_EC_STACKPROT;
 493             helper_raise_exception(EXCP_HW_EXCP);
 494     }
 495 }
 496
 497 #if !defined(CONFIG_USER_ONLY)
 498 /* Writes/reads to the MMU's special regs end up here.  */
 499 uint32_t helper_mmu_read(uint32_t rn)
 500 {
 501     return mmu_read(env, rn);
 502 }
 503
 504 void helper_mmu_write(uint32_t rn, uint32_t v)
 505 {
 506     mmu_write(env, rn, v);
 507 }
 508
 509 void cpu_unassigned_access(CPUState *env1, target_phys_addr_t addr,
 510                            int is_write, int is_exec, int is_asi, int size)
 511 {
 512     CPUState *saved_env;
 513
 514     saved_env = env;
 515     env = env1;
 516
 517     qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n",
 518              addr, is_write, is_exec);
 519     if (!(env->sregs[SR_MSR] & MSR_EE)) {
 520         env = saved_env;
 521         return;
 522     }
 523
 524     env->sregs[SR_EAR] = addr;
 525     if (is_exec) {
 526         if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) {
 527             env->sregs[SR_ESR] = ESR_EC_INSN_BUS;
 528             helper_raise_exception(EXCP_HW_EXCP);
 529         }
 530     } else {
 531         if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) {
 532             env->sregs[SR_ESR] = ESR_EC_DATA_BUS;
 533             helper_raise_exception(EXCP_HW_EXCP);
 534         }
 535     }
 536     env = saved_env;
 537 }
 538 #endif