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Merge branch 'target-arm.next' of git://git.linaro.org/people/pmaydell/qemu-arm
[qemu.git] / target-mips / dsp_helper.c
1 /*
2 * MIPS ASE DSP Instruction emulation helpers for QEMU.
3 *
4 * Copyright (c) 2012 Jia Liu <proljc@gmail.com>
5 * Dongxue Zhang <elta.era@gmail.com>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "cpu.h"
21 #include "helper.h"
22
23 /* As the byte ordering doesn't matter, i.e. all columns are treated
24 identically, these unions can be used directly. */
25 typedef union {
26 uint8_t ub[4];
27 int8_t sb[4];
28 uint16_t uh[2];
29 int16_t sh[2];
30 uint32_t uw[1];
31 int32_t sw[1];
32 } DSP32Value;
33
34 typedef union {
35 uint8_t ub[8];
36 int8_t sb[8];
37 uint16_t uh[4];
38 int16_t sh[4];
39 uint32_t uw[2];
40 int32_t sw[2];
41 uint64_t ul[1];
42 int64_t sl[1];
43 } DSP64Value;
44
45 /*** MIPS DSP internal functions begin ***/
46 #define MIPSDSP_ABS(x) (((x) >= 0) ? x : -x)
47 #define MIPSDSP_OVERFLOW_ADD(a, b, c, d) (~(a ^ b) & (a ^ c) & d)
48 #define MIPSDSP_OVERFLOW_SUB(a, b, c, d) ((a ^ b) & (a ^ c) & d)
49
50 static inline void set_DSPControl_overflow_flag(uint32_t flag, int position,
51 CPUMIPSState *env)
52 {
53 env->active_tc.DSPControl |= (target_ulong)flag << position;
54 }
55
56 static inline void set_DSPControl_carryflag(uint32_t flag, CPUMIPSState *env)
57 {
58 env->active_tc.DSPControl |= (target_ulong)flag << 13;
59 }
60
61 static inline uint32_t get_DSPControl_carryflag(CPUMIPSState *env)
62 {
63 return (env->active_tc.DSPControl >> 13) & 0x01;
64 }
65
66 static inline void set_DSPControl_24(uint32_t flag, int len, CPUMIPSState *env)
67 {
68 uint32_t filter;
69
70 filter = ((0x01 << len) - 1) << 24;
71 filter = ~filter;
72
73 env->active_tc.DSPControl &= filter;
74 env->active_tc.DSPControl |= (target_ulong)flag << 24;
75 }
76
77 static inline uint32_t get_DSPControl_24(int len, CPUMIPSState *env)
78 {
79 uint32_t filter;
80
81 filter = (0x01 << len) - 1;
82
83 return (env->active_tc.DSPControl >> 24) & filter;
84 }
85
86 static inline void set_DSPControl_pos(uint32_t pos, CPUMIPSState *env)
87 {
88 target_ulong dspc;
89
90 dspc = env->active_tc.DSPControl;
91 #ifndef TARGET_MIPS64
92 dspc = dspc & 0xFFFFFFC0;
93 dspc |= pos;
94 #else
95 dspc = dspc & 0xFFFFFF80;
96 dspc |= pos;
97 #endif
98 env->active_tc.DSPControl = dspc;
99 }
100
101 static inline uint32_t get_DSPControl_pos(CPUMIPSState *env)
102 {
103 target_ulong dspc;
104 uint32_t pos;
105
106 dspc = env->active_tc.DSPControl;
107
108 #ifndef TARGET_MIPS64
109 pos = dspc & 0x3F;
110 #else
111 pos = dspc & 0x7F;
112 #endif
113
114 return pos;
115 }
116
117 static inline void set_DSPControl_efi(uint32_t flag, CPUMIPSState *env)
118 {
119 env->active_tc.DSPControl &= 0xFFFFBFFF;
120 env->active_tc.DSPControl |= (target_ulong)flag << 14;
121 }
122
123 #define DO_MIPS_SAT_ABS(size) \
124 static inline int##size##_t mipsdsp_sat_abs##size(int##size##_t a, \
125 CPUMIPSState *env) \
126 { \
127 if (a == INT##size##_MIN) { \
128 set_DSPControl_overflow_flag(1, 20, env); \
129 return INT##size##_MAX; \
130 } else { \
131 return MIPSDSP_ABS(a); \
132 } \
133 }
134 DO_MIPS_SAT_ABS(8)
135 DO_MIPS_SAT_ABS(16)
136 DO_MIPS_SAT_ABS(32)
137 #undef DO_MIPS_SAT_ABS
138
139 /* get sum value */
140 static inline int16_t mipsdsp_add_i16(int16_t a, int16_t b, CPUMIPSState *env)
141 {
142 int16_t tempI;
143
144 tempI = a + b;
145
146 if (MIPSDSP_OVERFLOW_ADD(a, b, tempI, 0x8000)) {
147 set_DSPControl_overflow_flag(1, 20, env);
148 }
149
150 return tempI;
151 }
152
153 static inline int16_t mipsdsp_sat_add_i16(int16_t a, int16_t b,
154 CPUMIPSState *env)
155 {
156 int16_t tempS;
157
158 tempS = a + b;
159
160 if (MIPSDSP_OVERFLOW_ADD(a, b, tempS, 0x8000)) {
161 if (a > 0) {
162 tempS = 0x7FFF;
163 } else {
164 tempS = 0x8000;
165 }
166 set_DSPControl_overflow_flag(1, 20, env);
167 }
168
169 return tempS;
170 }
171
172 static inline int32_t mipsdsp_sat_add_i32(int32_t a, int32_t b,
173 CPUMIPSState *env)
174 {
175 int32_t tempI;
176
177 tempI = a + b;
178
179 if (MIPSDSP_OVERFLOW_ADD(a, b, tempI, 0x80000000)) {
180 if (a > 0) {
181 tempI = 0x7FFFFFFF;
182 } else {
183 tempI = 0x80000000;
184 }
185 set_DSPControl_overflow_flag(1, 20, env);
186 }
187
188 return tempI;
189 }
190
191 static inline uint8_t mipsdsp_add_u8(uint8_t a, uint8_t b, CPUMIPSState *env)
192 {
193 uint16_t temp;
194
195 temp = (uint16_t)a + (uint16_t)b;
196
197 if (temp & 0x0100) {
198 set_DSPControl_overflow_flag(1, 20, env);
199 }
200
201 return temp & 0xFF;
202 }
203
204 static inline uint16_t mipsdsp_add_u16(uint16_t a, uint16_t b,
205 CPUMIPSState *env)
206 {
207 uint32_t temp;
208
209 temp = (uint32_t)a + (uint32_t)b;
210
211 if (temp & 0x00010000) {
212 set_DSPControl_overflow_flag(1, 20, env);
213 }
214
215 return temp & 0xFFFF;
216 }
217
218 static inline uint8_t mipsdsp_sat_add_u8(uint8_t a, uint8_t b,
219 CPUMIPSState *env)
220 {
221 uint8_t result;
222 uint16_t temp;
223
224 temp = (uint16_t)a + (uint16_t)b;
225 result = temp & 0xFF;
226
227 if (0x0100 & temp) {
228 result = 0xFF;
229 set_DSPControl_overflow_flag(1, 20, env);
230 }
231
232 return result;
233 }
234
235 static inline uint16_t mipsdsp_sat_add_u16(uint16_t a, uint16_t b,
236 CPUMIPSState *env)
237 {
238 uint16_t result;
239 uint32_t temp;
240
241 temp = (uint32_t)a + (uint32_t)b;
242 result = temp & 0xFFFF;
243
244 if (0x00010000 & temp) {
245 result = 0xFFFF;
246 set_DSPControl_overflow_flag(1, 20, env);
247 }
248
249 return result;
250 }
251
252 static inline int32_t mipsdsp_sat32_acc_q31(int32_t acc, int32_t a,
253 CPUMIPSState *env)
254 {
255 int64_t temp;
256 int32_t temp32, temp31, result;
257 int64_t temp_sum;
258
259 #ifndef TARGET_MIPS64
260 temp = ((uint64_t)env->active_tc.HI[acc] << 32) |
261 (uint64_t)env->active_tc.LO[acc];
262 #else
263 temp = (uint64_t)env->active_tc.LO[acc];
264 #endif
265
266 temp_sum = (int64_t)a + temp;
267
268 temp32 = (temp_sum >> 32) & 0x01;
269 temp31 = (temp_sum >> 31) & 0x01;
270 result = temp_sum & 0xFFFFFFFF;
271
272 /* FIXME
273 This sat function may wrong, because user manual wrote:
274 temp127..0 ← temp + ( (signA) || a31..0
275 if ( temp32 ≠ temp31 ) then
276 if ( temp32 = 0 ) then
277 temp31..0 ← 0x80000000
278 else
279 temp31..0 ← 0x7FFFFFFF
280 endif
281 DSPControlouflag:16+acc ← 1
282 endif
283 */
284 if (temp32 != temp31) {
285 if (temp32 == 0) {
286 result = 0x7FFFFFFF;
287 } else {
288 result = 0x80000000;
289 }
290 set_DSPControl_overflow_flag(1, 16 + acc, env);
291 }
292
293 return result;
294 }
295
296 /* a[0] is LO, a[1] is HI. */
297 static inline void mipsdsp_sat64_acc_add_q63(int64_t *ret,
298 int32_t ac,
299 int64_t *a,
300 CPUMIPSState *env)
301 {
302 bool temp64;
303
304 ret[0] = env->active_tc.LO[ac] + a[0];
305 ret[1] = env->active_tc.HI[ac] + a[1];
306
307 if (((uint64_t)ret[0] < (uint64_t)env->active_tc.LO[ac]) &&
308 ((uint64_t)ret[0] < (uint64_t)a[0])) {
309 ret[1] += 1;
310 }
311 temp64 = ret[1] & 1;
312 if (temp64 != ((ret[0] >> 63) & 0x01)) {
313 if (temp64) {
314 ret[0] = (0x01ull << 63);
315 ret[1] = ~0ull;
316 } else {
317 ret[0] = (0x01ull << 63) - 1;
318 ret[1] = 0x00;
319 }
320 set_DSPControl_overflow_flag(1, 16 + ac, env);
321 }
322 }
323
324 static inline void mipsdsp_sat64_acc_sub_q63(int64_t *ret,
325 int32_t ac,
326 int64_t *a,
327 CPUMIPSState *env)
328 {
329 bool temp64;
330
331 ret[0] = env->active_tc.LO[ac] - a[0];
332 ret[1] = env->active_tc.HI[ac] - a[1];
333
334 if ((uint64_t)ret[0] > (uint64_t)env->active_tc.LO[ac]) {
335 ret[1] -= 1;
336 }
337 temp64 = ret[1] & 1;
338 if (temp64 != ((ret[0] >> 63) & 0x01)) {
339 if (temp64) {
340 ret[0] = (0x01ull << 63);
341 ret[1] = ~0ull;
342 } else {
343 ret[0] = (0x01ull << 63) - 1;
344 ret[1] = 0x00;
345 }
346 set_DSPControl_overflow_flag(1, 16 + ac, env);
347 }
348 }
349
350 static inline int32_t mipsdsp_mul_i16_i16(int16_t a, int16_t b,
351 CPUMIPSState *env)
352 {
353 int32_t temp;
354
355 temp = (int32_t)a * (int32_t)b;
356
357 if ((temp > (int)0x7FFF) || (temp < (int)0xFFFF8000)) {
358 set_DSPControl_overflow_flag(1, 21, env);
359 }
360 temp &= 0x0000FFFF;
361
362 return temp;
363 }
364
365 static inline int32_t mipsdsp_mul_u16_u16(int32_t a, int32_t b)
366 {
367 return a * b;
368 }
369
370 static inline int32_t mipsdsp_mul_i32_i32(int32_t a, int32_t b)
371 {
372 return a * b;
373 }
374
375 static inline int32_t mipsdsp_sat16_mul_i16_i16(int16_t a, int16_t b,
376 CPUMIPSState *env)
377 {
378 int32_t temp;
379
380 temp = (int32_t)a * (int32_t)b;
381
382 if (temp > (int)0x7FFF) {
383 temp = 0x00007FFF;
384 set_DSPControl_overflow_flag(1, 21, env);
385 } else if (temp < (int)0xffff8000) {
386 temp = 0xFFFF8000;
387 set_DSPControl_overflow_flag(1, 21, env);
388 }
389 temp &= 0x0000FFFF;
390
391 return temp;
392 }
393
394 static inline int32_t mipsdsp_mul_q15_q15_overflowflag21(uint16_t a, uint16_t b,
395 CPUMIPSState *env)
396 {
397 int32_t temp;
398
399 if ((a == 0x8000) && (b == 0x8000)) {
400 temp = 0x7FFFFFFF;
401 set_DSPControl_overflow_flag(1, 21, env);
402 } else {
403 temp = ((int32_t)(int16_t)a * (int32_t)(int16_t)b) << 1;
404 }
405
406 return temp;
407 }
408
409 /* right shift */
410 static inline uint8_t mipsdsp_rshift_u8(uint8_t a, target_ulong mov)
411 {
412 return a >> mov;
413 }
414
415 static inline uint16_t mipsdsp_rshift_u16(uint16_t a, target_ulong mov)
416 {
417 return a >> mov;
418 }
419
420 static inline int8_t mipsdsp_rashift8(int8_t a, target_ulong mov)
421 {
422 return a >> mov;
423 }
424
425 static inline int16_t mipsdsp_rashift16(int16_t a, target_ulong mov)
426 {
427 return a >> mov;
428 }
429
430 static inline int32_t mipsdsp_rashift32(int32_t a, target_ulong mov)
431 {
432 return a >> mov;
433 }
434
435 static inline int16_t mipsdsp_rshift1_add_q16(int16_t a, int16_t b)
436 {
437 int32_t temp;
438
439 temp = (int32_t)a + (int32_t)b;
440
441 return (temp >> 1) & 0xFFFF;
442 }
443
444 /* round right shift */
445 static inline int16_t mipsdsp_rrshift1_add_q16(int16_t a, int16_t b)
446 {
447 int32_t temp;
448
449 temp = (int32_t)a + (int32_t)b;
450 temp += 1;
451
452 return (temp >> 1) & 0xFFFF;
453 }
454
455 static inline int32_t mipsdsp_rshift1_add_q32(int32_t a, int32_t b)
456 {
457 int64_t temp;
458
459 temp = (int64_t)a + (int64_t)b;
460
461 return (temp >> 1) & 0xFFFFFFFF;
462 }
463
464 static inline int32_t mipsdsp_rrshift1_add_q32(int32_t a, int32_t b)
465 {
466 int64_t temp;
467
468 temp = (int64_t)a + (int64_t)b;
469 temp += 1;
470
471 return (temp >> 1) & 0xFFFFFFFF;
472 }
473
474 static inline uint8_t mipsdsp_rshift1_add_u8(uint8_t a, uint8_t b)
475 {
476 uint16_t temp;
477
478 temp = (uint16_t)a + (uint16_t)b;
479
480 return (temp >> 1) & 0x00FF;
481 }
482
483 static inline uint8_t mipsdsp_rrshift1_add_u8(uint8_t a, uint8_t b)
484 {
485 uint16_t temp;
486
487 temp = (uint16_t)a + (uint16_t)b + 1;
488
489 return (temp >> 1) & 0x00FF;
490 }
491
492 static inline uint8_t mipsdsp_rshift1_sub_u8(uint8_t a, uint8_t b)
493 {
494 uint16_t temp;
495
496 temp = (uint16_t)a - (uint16_t)b;
497
498 return (temp >> 1) & 0x00FF;
499 }
500
501 static inline uint8_t mipsdsp_rrshift1_sub_u8(uint8_t a, uint8_t b)
502 {
503 uint16_t temp;
504
505 temp = (uint16_t)a - (uint16_t)b + 1;
506
507 return (temp >> 1) & 0x00FF;
508 }
509
510 /* 128 bits long. p[0] is LO, p[1] is HI. */
511 static inline void mipsdsp_rndrashift_short_acc(int64_t *p,
512 int32_t ac,
513 int32_t shift,
514 CPUMIPSState *env)
515 {
516 int64_t acc;
517
518 acc = ((int64_t)env->active_tc.HI[ac] << 32) |
519 ((int64_t)env->active_tc.LO[ac] & 0xFFFFFFFF);
520 if (shift == 0) {
521 p[0] = acc << 1;
522 p[1] = (acc >> 63) & 0x01;
523 } else {
524 p[0] = acc >> (shift - 1);
525 p[1] = 0;
526 }
527 }
528
529 /* 128 bits long. p[0] is LO, p[1] is HI */
530 static inline void mipsdsp_rashift_acc(uint64_t *p,
531 uint32_t ac,
532 uint32_t shift,
533 CPUMIPSState *env)
534 {
535 uint64_t tempB, tempA;
536
537 tempB = env->active_tc.HI[ac];
538 tempA = env->active_tc.LO[ac];
539 shift = shift & 0x1F;
540
541 if (shift == 0) {
542 p[1] = tempB;
543 p[0] = tempA;
544 } else {
545 p[0] = (tempB << (64 - shift)) | (tempA >> shift);
546 p[1] = (int64_t)tempB >> shift;
547 }
548 }
549
550 /* 128 bits long. p[0] is LO, p[1] is HI , p[2] is sign of HI.*/
551 static inline void mipsdsp_rndrashift_acc(uint64_t *p,
552 uint32_t ac,
553 uint32_t shift,
554 CPUMIPSState *env)
555 {
556 int64_t tempB, tempA;
557
558 tempB = env->active_tc.HI[ac];
559 tempA = env->active_tc.LO[ac];
560 shift = shift & 0x3F;
561
562 if (shift == 0) {
563 p[2] = tempB >> 63;
564 p[1] = (tempB << 1) | (tempA >> 63);
565 p[0] = tempA << 1;
566 } else {
567 p[0] = (tempB << (65 - shift)) | (tempA >> (shift - 1));
568 p[1] = (int64_t)tempB >> (shift - 1);
569 if (tempB >= 0) {
570 p[2] = 0x0;
571 } else {
572 p[2] = ~0ull;
573 }
574 }
575 }
576
577 static inline int32_t mipsdsp_mul_q15_q15(int32_t ac, uint16_t a, uint16_t b,
578 CPUMIPSState *env)
579 {
580 int32_t temp;
581
582 if ((a == 0x8000) && (b == 0x8000)) {
583 temp = 0x7FFFFFFF;
584 set_DSPControl_overflow_flag(1, 16 + ac, env);
585 } else {
586 temp = ((uint32_t)a * (uint32_t)b) << 1;
587 }
588
589 return temp;
590 }
591
592 static inline int64_t mipsdsp_mul_q31_q31(int32_t ac, uint32_t a, uint32_t b,
593 CPUMIPSState *env)
594 {
595 uint64_t temp;
596
597 if ((a == 0x80000000) && (b == 0x80000000)) {
598 temp = (0x01ull << 63) - 1;
599 set_DSPControl_overflow_flag(1, 16 + ac, env);
600 } else {
601 temp = ((uint64_t)a * (uint64_t)b) << 1;
602 }
603
604 return temp;
605 }
606
607 static inline uint16_t mipsdsp_mul_u8_u8(uint8_t a, uint8_t b)
608 {
609 return (uint16_t)a * (uint16_t)b;
610 }
611
612 static inline uint16_t mipsdsp_mul_u8_u16(uint8_t a, uint16_t b,
613 CPUMIPSState *env)
614 {
615 uint32_t tempI;
616
617 tempI = (uint32_t)a * (uint32_t)b;
618 if (tempI > 0x0000FFFF) {
619 tempI = 0x0000FFFF;
620 set_DSPControl_overflow_flag(1, 21, env);
621 }
622
623 return tempI & 0x0000FFFF;
624 }
625
626 static inline uint64_t mipsdsp_mul_u32_u32(uint32_t a, uint32_t b)
627 {
628 return (uint64_t)a * (uint64_t)b;
629 }
630
631 static inline int16_t mipsdsp_rndq15_mul_q15_q15(uint16_t a, uint16_t b,
632 CPUMIPSState *env)
633 {
634 uint32_t temp;
635
636 if ((a == 0x8000) && (b == 0x8000)) {
637 temp = 0x7FFF0000;
638 set_DSPControl_overflow_flag(1, 21, env);
639 } else {
640 temp = (a * b) << 1;
641 temp = temp + 0x00008000;
642 }
643
644 return (temp & 0xFFFF0000) >> 16;
645 }
646
647 static inline int32_t mipsdsp_sat16_mul_q15_q15(uint16_t a, uint16_t b,
648 CPUMIPSState *env)
649 {
650 int32_t temp;
651
652 if ((a == 0x8000) && (b == 0x8000)) {
653 temp = 0x7FFF0000;
654 set_DSPControl_overflow_flag(1, 21, env);
655 } else {
656 temp = (int16_t)a * (int16_t)b;
657 temp = temp << 1;
658 }
659
660 return (temp >> 16) & 0x0000FFFF;
661 }
662
663 static inline uint16_t mipsdsp_trunc16_sat16_round(int32_t a,
664 CPUMIPSState *env)
665 {
666 int64_t temp;
667
668 temp = (int32_t)a + 0x00008000;
669
670 if (a > (int)0x7fff8000) {
671 temp = 0x7FFFFFFF;
672 set_DSPControl_overflow_flag(1, 22, env);
673 }
674
675 return (temp >> 16) & 0xFFFF;
676 }
677
678 static inline uint8_t mipsdsp_sat8_reduce_precision(uint16_t a,
679 CPUMIPSState *env)
680 {
681 uint16_t mag;
682 uint32_t sign;
683
684 sign = (a >> 15) & 0x01;
685 mag = a & 0x7FFF;
686
687 if (sign == 0) {
688 if (mag > 0x7F80) {
689 set_DSPControl_overflow_flag(1, 22, env);
690 return 0xFF;
691 } else {
692 return (mag >> 7) & 0xFFFF;
693 }
694 } else {
695 set_DSPControl_overflow_flag(1, 22, env);
696 return 0x00;
697 }
698 }
699
700 static inline uint8_t mipsdsp_lshift8(uint8_t a, uint8_t s, CPUMIPSState *env)
701 {
702 uint8_t sign;
703 uint8_t discard;
704
705 if (s == 0) {
706 return a;
707 } else {
708 sign = (a >> 7) & 0x01;
709 if (sign != 0) {
710 discard = (((0x01 << (8 - s)) - 1) << s) |
711 ((a >> (6 - (s - 1))) & ((0x01 << s) - 1));
712 } else {
713 discard = a >> (6 - (s - 1));
714 }
715
716 if (discard != 0x00) {
717 set_DSPControl_overflow_flag(1, 22, env);
718 }
719 return a << s;
720 }
721 }
722
723 static inline uint16_t mipsdsp_lshift16(uint16_t a, uint8_t s,
724 CPUMIPSState *env)
725 {
726 uint8_t sign;
727 uint16_t discard;
728
729 if (s == 0) {
730 return a;
731 } else {
732 sign = (a >> 15) & 0x01;
733 if (sign != 0) {
734 discard = (((0x01 << (16 - s)) - 1) << s) |
735 ((a >> (14 - (s - 1))) & ((0x01 << s) - 1));
736 } else {
737 discard = a >> (14 - (s - 1));
738 }
739
740 if ((discard != 0x0000) && (discard != 0xFFFF)) {
741 set_DSPControl_overflow_flag(1, 22, env);
742 }
743 return a << s;
744 }
745 }
746
747
748 static inline uint32_t mipsdsp_lshift32(uint32_t a, uint8_t s,
749 CPUMIPSState *env)
750 {
751 uint32_t discard;
752
753 if (s == 0) {
754 return a;
755 } else {
756 discard = (int32_t)a >> (31 - (s - 1));
757
758 if ((discard != 0x00000000) && (discard != 0xFFFFFFFF)) {
759 set_DSPControl_overflow_flag(1, 22, env);
760 }
761 return a << s;
762 }
763 }
764
765 static inline uint16_t mipsdsp_sat16_lshift(uint16_t a, uint8_t s,
766 CPUMIPSState *env)
767 {
768 uint8_t sign;
769 uint16_t discard;
770
771 if (s == 0) {
772 return a;
773 } else {
774 sign = (a >> 15) & 0x01;
775 if (sign != 0) {
776 discard = (((0x01 << (16 - s)) - 1) << s) |
777 ((a >> (14 - (s - 1))) & ((0x01 << s) - 1));
778 } else {
779 discard = a >> (14 - (s - 1));
780 }
781
782 if ((discard != 0x0000) && (discard != 0xFFFF)) {
783 set_DSPControl_overflow_flag(1, 22, env);
784 return (sign == 0) ? 0x7FFF : 0x8000;
785 } else {
786 return a << s;
787 }
788 }
789 }
790
791 static inline uint32_t mipsdsp_sat32_lshift(uint32_t a, uint8_t s,
792 CPUMIPSState *env)
793 {
794 uint8_t sign;
795 uint32_t discard;
796
797 if (s == 0) {
798 return a;
799 } else {
800 sign = (a >> 31) & 0x01;
801 if (sign != 0) {
802 discard = (((0x01 << (32 - s)) - 1) << s) |
803 ((a >> (30 - (s - 1))) & ((0x01 << s) - 1));
804 } else {
805 discard = a >> (30 - (s - 1));
806 }
807
808 if ((discard != 0x00000000) && (discard != 0xFFFFFFFF)) {
809 set_DSPControl_overflow_flag(1, 22, env);
810 return (sign == 0) ? 0x7FFFFFFF : 0x80000000;
811 } else {
812 return a << s;
813 }
814 }
815 }
816
817 static inline uint8_t mipsdsp_rnd8_rashift(uint8_t a, uint8_t s)
818 {
819 uint32_t temp;
820
821 if (s == 0) {
822 temp = (uint32_t)a << 1;
823 } else {
824 temp = (int32_t)(int8_t)a >> (s - 1);
825 }
826
827 return (temp + 1) >> 1;
828 }
829
830 static inline uint16_t mipsdsp_rnd16_rashift(uint16_t a, uint8_t s)
831 {
832 uint32_t temp;
833
834 if (s == 0) {
835 temp = (uint32_t)a << 1;
836 } else {
837 temp = (int32_t)(int16_t)a >> (s - 1);
838 }
839
840 return (temp + 1) >> 1;
841 }
842
843 static inline uint32_t mipsdsp_rnd32_rashift(uint32_t a, uint8_t s)
844 {
845 int64_t temp;
846
847 if (s == 0) {
848 temp = (uint64_t)a << 1;
849 } else {
850 temp = (int64_t)(int32_t)a >> (s - 1);
851 }
852 temp += 1;
853
854 return (temp >> 1) & 0xFFFFFFFFull;
855 }
856
857 static inline uint16_t mipsdsp_sub_i16(int16_t a, int16_t b, CPUMIPSState *env)
858 {
859 int16_t temp;
860
861 temp = a - b;
862 if (MIPSDSP_OVERFLOW_SUB(a, b, temp, 0x8000)) {
863 set_DSPControl_overflow_flag(1, 20, env);
864 }
865
866 return temp;
867 }
868
869 static inline uint16_t mipsdsp_sat16_sub(int16_t a, int16_t b,
870 CPUMIPSState *env)
871 {
872 int16_t temp;
873
874 temp = a - b;
875 if (MIPSDSP_OVERFLOW_SUB(a, b, temp, 0x8000)) {
876 if (a >= 0) {
877 temp = 0x7FFF;
878 } else {
879 temp = 0x8000;
880 }
881 set_DSPControl_overflow_flag(1, 20, env);
882 }
883
884 return temp;
885 }
886
887 static inline uint32_t mipsdsp_sat32_sub(int32_t a, int32_t b,
888 CPUMIPSState *env)
889 {
890 int32_t temp;
891
892 temp = a - b;
893 if (MIPSDSP_OVERFLOW_SUB(a, b, temp, 0x80000000)) {
894 if (a >= 0) {
895 temp = 0x7FFFFFFF;
896 } else {
897 temp = 0x80000000;
898 }
899 set_DSPControl_overflow_flag(1, 20, env);
900 }
901
902 return temp & 0xFFFFFFFFull;
903 }
904
905 static inline uint16_t mipsdsp_rshift1_sub_q16(int16_t a, int16_t b)
906 {
907 int32_t temp;
908
909 temp = (int32_t)a - (int32_t)b;
910
911 return (temp >> 1) & 0x0000FFFF;
912 }
913
914 static inline uint16_t mipsdsp_rrshift1_sub_q16(int16_t a, int16_t b)
915 {
916 int32_t temp;
917
918 temp = (int32_t)a - (int32_t)b;
919 temp += 1;
920
921 return (temp >> 1) & 0x0000FFFF;
922 }
923
924 static inline uint32_t mipsdsp_rshift1_sub_q32(int32_t a, int32_t b)
925 {
926 int64_t temp;
927
928 temp = (int64_t)a - (int64_t)b;
929
930 return (temp >> 1) & 0xFFFFFFFFull;
931 }
932
933 static inline uint32_t mipsdsp_rrshift1_sub_q32(int32_t a, int32_t b)
934 {
935 int64_t temp;
936
937 temp = (int64_t)a - (int64_t)b;
938 temp += 1;
939
940 return (temp >> 1) & 0xFFFFFFFFull;
941 }
942
943 static inline uint16_t mipsdsp_sub_u16_u16(uint16_t a, uint16_t b,
944 CPUMIPSState *env)
945 {
946 uint8_t temp16;
947 uint32_t temp;
948
949 temp = (uint32_t)a - (uint32_t)b;
950 temp16 = (temp >> 16) & 0x01;
951 if (temp16 == 1) {
952 set_DSPControl_overflow_flag(1, 20, env);
953 }
954 return temp & 0x0000FFFF;
955 }
956
957 static inline uint16_t mipsdsp_satu16_sub_u16_u16(uint16_t a, uint16_t b,
958 CPUMIPSState *env)
959 {
960 uint8_t temp16;
961 uint32_t temp;
962
963 temp = (uint32_t)a - (uint32_t)b;
964 temp16 = (temp >> 16) & 0x01;
965
966 if (temp16 == 1) {
967 temp = 0x0000;
968 set_DSPControl_overflow_flag(1, 20, env);
969 }
970
971 return temp & 0x0000FFFF;
972 }
973
974 static inline uint8_t mipsdsp_sub_u8(uint8_t a, uint8_t b, CPUMIPSState *env)
975 {
976 uint8_t temp8;
977 uint16_t temp;
978
979 temp = (uint16_t)a - (uint16_t)b;
980 temp8 = (temp >> 8) & 0x01;
981 if (temp8 == 1) {
982 set_DSPControl_overflow_flag(1, 20, env);
983 }
984
985 return temp & 0x00FF;
986 }
987
988 static inline uint8_t mipsdsp_satu8_sub(uint8_t a, uint8_t b, CPUMIPSState *env)
989 {
990 uint8_t temp8;
991 uint16_t temp;
992
993 temp = (uint16_t)a - (uint16_t)b;
994 temp8 = (temp >> 8) & 0x01;
995 if (temp8 == 1) {
996 temp = 0x00;
997 set_DSPControl_overflow_flag(1, 20, env);
998 }
999
1000 return temp & 0x00FF;
1001 }
1002
1003 static inline uint32_t mipsdsp_sub32(int32_t a, int32_t b, CPUMIPSState *env)
1004 {
1005 int32_t temp;
1006
1007 temp = a - b;
1008 if (MIPSDSP_OVERFLOW_SUB(a, b, temp, 0x80000000)) {
1009 set_DSPControl_overflow_flag(1, 20, env);
1010 }
1011
1012 return temp;
1013 }
1014
1015 static inline int32_t mipsdsp_add_i32(int32_t a, int32_t b, CPUMIPSState *env)
1016 {
1017 int32_t temp;
1018
1019 temp = a + b;
1020
1021 if (MIPSDSP_OVERFLOW_ADD(a, b, temp, 0x80000000)) {
1022 set_DSPControl_overflow_flag(1, 20, env);
1023 }
1024
1025 return temp;
1026 }
1027
1028 static inline int32_t mipsdsp_cmp_eq(int32_t a, int32_t b)
1029 {
1030 return a == b;
1031 }
1032
1033 static inline int32_t mipsdsp_cmp_le(int32_t a, int32_t b)
1034 {
1035 return a <= b;
1036 }
1037
1038 static inline int32_t mipsdsp_cmp_lt(int32_t a, int32_t b)
1039 {
1040 return a < b;
1041 }
1042
1043 static inline int32_t mipsdsp_cmpu_eq(uint32_t a, uint32_t b)
1044 {
1045 return a == b;
1046 }
1047
1048 static inline int32_t mipsdsp_cmpu_le(uint32_t a, uint32_t b)
1049 {
1050 return a <= b;
1051 }
1052
1053 static inline int32_t mipsdsp_cmpu_lt(uint32_t a, uint32_t b)
1054 {
1055 return a < b;
1056 }
1057 /*** MIPS DSP internal functions end ***/
1058
1059 #define MIPSDSP_LHI 0xFFFFFFFF00000000ull
1060 #define MIPSDSP_LLO 0x00000000FFFFFFFFull
1061 #define MIPSDSP_HI 0xFFFF0000
1062 #define MIPSDSP_LO 0x0000FFFF
1063 #define MIPSDSP_Q3 0xFF000000
1064 #define MIPSDSP_Q2 0x00FF0000
1065 #define MIPSDSP_Q1 0x0000FF00
1066 #define MIPSDSP_Q0 0x000000FF
1067
1068 #define MIPSDSP_SPLIT32_8(num, a, b, c, d) \
1069 do { \
1070 a = (num >> 24) & MIPSDSP_Q0; \
1071 b = (num >> 16) & MIPSDSP_Q0; \
1072 c = (num >> 8) & MIPSDSP_Q0; \
1073 d = num & MIPSDSP_Q0; \
1074 } while (0)
1075
1076 #define MIPSDSP_SPLIT32_16(num, a, b) \
1077 do { \
1078 a = (num >> 16) & MIPSDSP_LO; \
1079 b = num & MIPSDSP_LO; \
1080 } while (0)
1081
1082 #define MIPSDSP_RETURN32_8(a, b, c, d) ((target_long)(int32_t) \
1083 (((uint32_t)a << 24) | \
1084 (((uint32_t)b << 16) | \
1085 (((uint32_t)c << 8) | \
1086 ((uint32_t)d & 0xFF)))))
1087 #define MIPSDSP_RETURN32_16(a, b) ((target_long)(int32_t) \
1088 (((uint32_t)a << 16) | \
1089 ((uint32_t)b & 0xFFFF)))
1090
1091 #ifdef TARGET_MIPS64
1092 #define MIPSDSP_SPLIT64_16(num, a, b, c, d) \
1093 do { \
1094 a = (num >> 48) & MIPSDSP_LO; \
1095 b = (num >> 32) & MIPSDSP_LO; \
1096 c = (num >> 16) & MIPSDSP_LO; \
1097 d = num & MIPSDSP_LO; \
1098 } while (0)
1099
1100 #define MIPSDSP_SPLIT64_32(num, a, b) \
1101 do { \
1102 a = (num >> 32) & MIPSDSP_LLO; \
1103 b = num & MIPSDSP_LLO; \
1104 } while (0)
1105
1106 #define MIPSDSP_RETURN64_16(a, b, c, d) (((uint64_t)a << 48) | \
1107 ((uint64_t)b << 32) | \
1108 ((uint64_t)c << 16) | \
1109 (uint64_t)d)
1110 #define MIPSDSP_RETURN64_32(a, b) (((uint64_t)a << 32) | (uint64_t)b)
1111 #endif
1112
1113 /** DSP Arithmetic Sub-class insns **/
1114 #define MIPSDSP32_UNOP_ENV(name, func, element) \
1115 target_ulong helper_##name(target_ulong rt, CPUMIPSState *env) \
1116 { \
1117 DSP32Value dt; \
1118 unsigned int i, n; \
1119 \
1120 n = sizeof(DSP32Value) / sizeof(dt.element[0]); \
1121 dt.sw[0] = rt; \
1122 \
1123 for (i = 0; i < n; i++) { \
1124 dt.element[i] = mipsdsp_##func(dt.element[i], env); \
1125 } \
1126 \
1127 return (target_long)dt.sw[0]; \
1128 }
1129 MIPSDSP32_UNOP_ENV(absq_s_ph, sat_abs16, sh)
1130 MIPSDSP32_UNOP_ENV(absq_s_qb, sat_abs8, sb)
1131 MIPSDSP32_UNOP_ENV(absq_s_w, sat_abs32, sw)
1132 #undef MIPSDSP32_UNOP_ENV
1133
1134 #if defined(TARGET_MIPS64)
1135 #define MIPSDSP64_UNOP_ENV(name, func, element) \
1136 target_ulong helper_##name(target_ulong rt, CPUMIPSState *env) \
1137 { \
1138 DSP64Value dt; \
1139 unsigned int i, n; \
1140 \
1141 n = sizeof(DSP64Value) / sizeof(dt.element[0]); \
1142 dt.sl[0] = rt; \
1143 \
1144 for (i = 0; i < n; i++) { \
1145 dt.element[i] = mipsdsp_##func(dt.element[i], env); \
1146 } \
1147 \
1148 return dt.sl[0]; \
1149 }
1150 MIPSDSP64_UNOP_ENV(absq_s_ob, sat_abs8, sb)
1151 MIPSDSP64_UNOP_ENV(absq_s_qh, sat_abs16, sh)
1152 MIPSDSP64_UNOP_ENV(absq_s_pw, sat_abs32, sw)
1153 #undef MIPSDSP64_UNOP_ENV
1154 #endif
1155
1156 #define MIPSDSP32_BINOP(name, func, element) \
1157 target_ulong helper_##name(target_ulong rs, target_ulong rt) \
1158 { \
1159 DSP32Value ds, dt; \
1160 unsigned int i, n; \
1161 \
1162 n = sizeof(DSP32Value) / sizeof(ds.element[0]); \
1163 ds.sw[0] = rs; \
1164 dt.sw[0] = rt; \
1165 \
1166 for (i = 0; i < n; i++) { \
1167 ds.element[i] = mipsdsp_##func(ds.element[i], dt.element[i]); \
1168 } \
1169 \
1170 return (target_long)ds.sw[0]; \
1171 }
1172 MIPSDSP32_BINOP(addqh_ph, rshift1_add_q16, sh);
1173 MIPSDSP32_BINOP(addqh_r_ph, rrshift1_add_q16, sh);
1174 MIPSDSP32_BINOP(addqh_r_w, rrshift1_add_q32, sw);
1175 MIPSDSP32_BINOP(addqh_w, rshift1_add_q32, sw);
1176 MIPSDSP32_BINOP(adduh_qb, rshift1_add_u8, ub);
1177 MIPSDSP32_BINOP(adduh_r_qb, rrshift1_add_u8, ub);
1178 MIPSDSP32_BINOP(subqh_ph, rshift1_sub_q16, sh);
1179 MIPSDSP32_BINOP(subqh_r_ph, rrshift1_sub_q16, sh);
1180 MIPSDSP32_BINOP(subqh_r_w, rrshift1_sub_q32, sw);
1181 MIPSDSP32_BINOP(subqh_w, rshift1_sub_q32, sw);
1182 #undef MIPSDSP32_BINOP
1183
1184 #define MIPSDSP32_BINOP_ENV(name, func, element) \
1185 target_ulong helper_##name(target_ulong rs, target_ulong rt, \
1186 CPUMIPSState *env) \
1187 { \
1188 DSP32Value ds, dt; \
1189 unsigned int i, n; \
1190 \
1191 n = sizeof(DSP32Value) / sizeof(ds.element[0]); \
1192 ds.sw[0] = rs; \
1193 dt.sw[0] = rt; \
1194 \
1195 for (i = 0 ; i < n ; i++) { \
1196 ds.element[i] = mipsdsp_##func(ds.element[i], dt.element[i], env); \
1197 } \
1198 \
1199 return (target_long)ds.sw[0]; \
1200 }
1201 MIPSDSP32_BINOP_ENV(addq_ph, add_i16, sh)
1202 MIPSDSP32_BINOP_ENV(addq_s_ph, sat_add_i16, sh)
1203 MIPSDSP32_BINOP_ENV(addq_s_w, sat_add_i32, sw);
1204 MIPSDSP32_BINOP_ENV(addu_ph, add_u16, sh)
1205 MIPSDSP32_BINOP_ENV(addu_qb, add_u8, ub);
1206 MIPSDSP32_BINOP_ENV(addu_s_ph, sat_add_u16, sh)
1207 MIPSDSP32_BINOP_ENV(addu_s_qb, sat_add_u8, ub);
1208 MIPSDSP32_BINOP_ENV(subq_ph, sub_i16, sh);
1209 MIPSDSP32_BINOP_ENV(subq_s_ph, sat16_sub, sh);
1210 MIPSDSP32_BINOP_ENV(subq_s_w, sat32_sub, sw);
1211 MIPSDSP32_BINOP_ENV(subu_ph, sub_u16_u16, sh);
1212 MIPSDSP32_BINOP_ENV(subu_qb, sub_u8, ub);
1213 MIPSDSP32_BINOP_ENV(subu_s_ph, satu16_sub_u16_u16, sh);
1214 MIPSDSP32_BINOP_ENV(subu_s_qb, satu8_sub, ub);
1215 #undef MIPSDSP32_BINOP_ENV
1216
1217 #ifdef TARGET_MIPS64
1218 #define MIPSDSP64_BINOP(name, func, element) \
1219 target_ulong helper_##name(target_ulong rs, target_ulong rt) \
1220 { \
1221 DSP64Value ds, dt; \
1222 unsigned int i, n; \
1223 \
1224 n = sizeof(DSP64Value) / sizeof(ds.element[0]); \
1225 ds.sl[0] = rs; \
1226 dt.sl[0] = rt; \
1227 \
1228 for (i = 0 ; i < n ; i++) { \
1229 ds.element[i] = mipsdsp_##func(ds.element[i], dt.element[i]); \
1230 } \
1231 \
1232 return ds.sl[0]; \
1233 }
1234 MIPSDSP64_BINOP(adduh_ob, rshift1_add_u8, ub);
1235 MIPSDSP64_BINOP(adduh_r_ob, rrshift1_add_u8, ub);
1236 MIPSDSP64_BINOP(subuh_ob, rshift1_sub_u8, ub);
1237 MIPSDSP64_BINOP(subuh_r_ob, rrshift1_sub_u8, ub);
1238 #undef MIPSDSP64_BINOP
1239
1240 #define MIPSDSP64_BINOP_ENV(name, func, element) \
1241 target_ulong helper_##name(target_ulong rs, target_ulong rt, \
1242 CPUMIPSState *env) \
1243 { \
1244 DSP64Value ds, dt; \
1245 unsigned int i, n; \
1246 \
1247 n = sizeof(DSP64Value) / sizeof(ds.element[0]); \
1248 ds.sl[0] = rs; \
1249 dt.sl[0] = rt; \
1250 \
1251 for (i = 0 ; i < n ; i++) { \
1252 ds.element[i] = mipsdsp_##func(ds.element[i], dt.element[i], env); \
1253 } \
1254 \
1255 return ds.sl[0]; \
1256 }
1257 MIPSDSP64_BINOP_ENV(addq_pw, add_i32, sw);
1258 MIPSDSP64_BINOP_ENV(addq_qh, add_i16, sh);
1259 MIPSDSP64_BINOP_ENV(addq_s_pw, sat_add_i32, sw);
1260 MIPSDSP64_BINOP_ENV(addq_s_qh, sat_add_i16, sh);
1261 MIPSDSP64_BINOP_ENV(addu_ob, add_u8, uh);
1262 MIPSDSP64_BINOP_ENV(addu_qh, add_u16, uh);
1263 MIPSDSP64_BINOP_ENV(addu_s_ob, sat_add_u8, uh);
1264 MIPSDSP64_BINOP_ENV(addu_s_qh, sat_add_u16, uh);
1265 MIPSDSP64_BINOP_ENV(subq_pw, sub32, sw);
1266 MIPSDSP64_BINOP_ENV(subq_qh, sub_i16, sh);
1267 MIPSDSP64_BINOP_ENV(subq_s_pw, sat32_sub, sw);
1268 MIPSDSP64_BINOP_ENV(subq_s_qh, sat16_sub, sh);
1269 MIPSDSP64_BINOP_ENV(subu_ob, sub_u8, uh);
1270 MIPSDSP64_BINOP_ENV(subu_qh, sub_u16_u16, uh);
1271 MIPSDSP64_BINOP_ENV(subu_s_ob, satu8_sub, uh);
1272 MIPSDSP64_BINOP_ENV(subu_s_qh, satu16_sub_u16_u16, uh);
1273 #undef MIPSDSP64_BINOP_ENV
1274
1275 #endif
1276
1277 #define SUBUH_QB(name, var) \
1278 target_ulong helper_##name##_qb(target_ulong rs, target_ulong rt) \
1279 { \
1280 uint8_t rs3, rs2, rs1, rs0; \
1281 uint8_t rt3, rt2, rt1, rt0; \
1282 uint8_t tempD, tempC, tempB, tempA; \
1283 \
1284 MIPSDSP_SPLIT32_8(rs, rs3, rs2, rs1, rs0); \
1285 MIPSDSP_SPLIT32_8(rt, rt3, rt2, rt1, rt0); \
1286 \
1287 tempD = ((uint16_t)rs3 - (uint16_t)rt3 + var) >> 1; \
1288 tempC = ((uint16_t)rs2 - (uint16_t)rt2 + var) >> 1; \
1289 tempB = ((uint16_t)rs1 - (uint16_t)rt1 + var) >> 1; \
1290 tempA = ((uint16_t)rs0 - (uint16_t)rt0 + var) >> 1; \
1291 \
1292 return ((uint32_t)tempD << 24) | ((uint32_t)tempC << 16) | \
1293 ((uint32_t)tempB << 8) | ((uint32_t)tempA); \
1294 }
1295
1296 SUBUH_QB(subuh, 0);
1297 SUBUH_QB(subuh_r, 1);
1298
1299 #undef SUBUH_QB
1300
1301 target_ulong helper_addsc(target_ulong rs, target_ulong rt, CPUMIPSState *env)
1302 {
1303 uint64_t temp, tempRs, tempRt;
1304 int32_t flag;
1305
1306 tempRs = (uint64_t)rs & MIPSDSP_LLO;
1307 tempRt = (uint64_t)rt & MIPSDSP_LLO;
1308
1309 temp = tempRs + tempRt;
1310 flag = (temp & 0x0100000000ull) >> 32;
1311 set_DSPControl_carryflag(flag, env);
1312
1313 return (target_long)(int32_t)(temp & MIPSDSP_LLO);
1314 }
1315
1316 target_ulong helper_addwc(target_ulong rs, target_ulong rt, CPUMIPSState *env)
1317 {
1318 uint32_t rd;
1319 int32_t temp32, temp31;
1320 int64_t tempL;
1321
1322 tempL = (int64_t)(int32_t)rs + (int64_t)(int32_t)rt +
1323 get_DSPControl_carryflag(env);
1324 temp31 = (tempL >> 31) & 0x01;
1325 temp32 = (tempL >> 32) & 0x01;
1326
1327 if (temp31 != temp32) {
1328 set_DSPControl_overflow_flag(1, 20, env);
1329 }
1330
1331 rd = tempL & MIPSDSP_LLO;
1332
1333 return (target_long)(int32_t)rd;
1334 }
1335
1336 target_ulong helper_modsub(target_ulong rs, target_ulong rt)
1337 {
1338 int32_t decr;
1339 uint16_t lastindex;
1340 target_ulong rd;
1341
1342 decr = rt & MIPSDSP_Q0;
1343 lastindex = (rt >> 8) & MIPSDSP_LO;
1344
1345 if ((rs & MIPSDSP_LLO) == 0x00000000) {
1346 rd = (target_ulong)lastindex;
1347 } else {
1348 rd = rs - decr;
1349 }
1350
1351 return rd;
1352 }
1353
1354 target_ulong helper_raddu_w_qb(target_ulong rs)
1355 {
1356 target_ulong ret = 0;
1357 DSP32Value ds;
1358 unsigned int i;
1359
1360 ds.uw[0] = rs;
1361 for (i = 0; i < 4; i++) {
1362 ret += ds.ub[i];
1363 }
1364 return ret;
1365 }
1366
1367 #if defined(TARGET_MIPS64)
1368 target_ulong helper_raddu_l_ob(target_ulong rs)
1369 {
1370 target_ulong ret = 0;
1371 DSP64Value ds;
1372 unsigned int i;
1373
1374 ds.ul[0] = rs;
1375 for (i = 0; i < 8; i++) {
1376 ret += ds.ub[i];
1377 }
1378 return ret;
1379 }
1380 #endif
1381
1382 #define PRECR_QB_PH(name, a, b)\
1383 target_ulong helper_##name##_qb_ph(target_ulong rs, target_ulong rt) \
1384 { \
1385 uint8_t tempD, tempC, tempB, tempA; \
1386 \
1387 tempD = (rs >> a) & MIPSDSP_Q0; \
1388 tempC = (rs >> b) & MIPSDSP_Q0; \
1389 tempB = (rt >> a) & MIPSDSP_Q0; \
1390 tempA = (rt >> b) & MIPSDSP_Q0; \
1391 \
1392 return MIPSDSP_RETURN32_8(tempD, tempC, tempB, tempA); \
1393 }
1394
1395 PRECR_QB_PH(precr, 16, 0);
1396 PRECR_QB_PH(precrq, 24, 8);
1397
1398 #undef PRECR_QB_OH
1399
1400 target_ulong helper_precr_sra_ph_w(uint32_t sa, target_ulong rs,
1401 target_ulong rt)
1402 {
1403 uint16_t tempB, tempA;
1404
1405 tempB = ((int32_t)rt >> sa) & MIPSDSP_LO;
1406 tempA = ((int32_t)rs >> sa) & MIPSDSP_LO;
1407
1408 return MIPSDSP_RETURN32_16(tempB, tempA);
1409 }
1410
1411 target_ulong helper_precr_sra_r_ph_w(uint32_t sa,
1412 target_ulong rs, target_ulong rt)
1413 {
1414 uint64_t tempB, tempA;
1415
1416 /* If sa = 0, then (sa - 1) = -1 will case shift error, so we need else. */
1417 if (sa == 0) {
1418 tempB = (rt & MIPSDSP_LO) << 1;
1419 tempA = (rs & MIPSDSP_LO) << 1;
1420 } else {
1421 tempB = ((int32_t)rt >> (sa - 1)) + 1;
1422 tempA = ((int32_t)rs >> (sa - 1)) + 1;
1423 }
1424 rt = (((tempB >> 1) & MIPSDSP_LO) << 16) | ((tempA >> 1) & MIPSDSP_LO);
1425
1426 return (target_long)(int32_t)rt;
1427 }
1428
1429 target_ulong helper_precrq_ph_w(target_ulong rs, target_ulong rt)
1430 {
1431 uint16_t tempB, tempA;
1432
1433 tempB = (rs & MIPSDSP_HI) >> 16;
1434 tempA = (rt & MIPSDSP_HI) >> 16;
1435
1436 return MIPSDSP_RETURN32_16(tempB, tempA);
1437 }
1438
1439 target_ulong helper_precrq_rs_ph_w(target_ulong rs, target_ulong rt,
1440 CPUMIPSState *env)
1441 {
1442 uint16_t tempB, tempA;
1443
1444 tempB = mipsdsp_trunc16_sat16_round(rs, env);
1445 tempA = mipsdsp_trunc16_sat16_round(rt, env);
1446
1447 return MIPSDSP_RETURN32_16(tempB, tempA);
1448 }
1449
1450 #if defined(TARGET_MIPS64)
1451 target_ulong helper_precr_ob_qh(target_ulong rs, target_ulong rt)
1452 {
1453 uint8_t rs6, rs4, rs2, rs0;
1454 uint8_t rt6, rt4, rt2, rt0;
1455 uint64_t temp;
1456
1457 rs6 = (rs >> 48) & MIPSDSP_Q0;
1458 rs4 = (rs >> 32) & MIPSDSP_Q0;
1459 rs2 = (rs >> 16) & MIPSDSP_Q0;
1460 rs0 = rs & MIPSDSP_Q0;
1461 rt6 = (rt >> 48) & MIPSDSP_Q0;
1462 rt4 = (rt >> 32) & MIPSDSP_Q0;
1463 rt2 = (rt >> 16) & MIPSDSP_Q0;
1464 rt0 = rt & MIPSDSP_Q0;
1465
1466 temp = ((uint64_t)rs6 << 56) | ((uint64_t)rs4 << 48) |
1467 ((uint64_t)rs2 << 40) | ((uint64_t)rs0 << 32) |
1468 ((uint64_t)rt6 << 24) | ((uint64_t)rt4 << 16) |
1469 ((uint64_t)rt2 << 8) | (uint64_t)rt0;
1470
1471 return temp;
1472 }
1473
1474 #define PRECR_QH_PW(name, var) \
1475 target_ulong helper_precr_##name##_qh_pw(target_ulong rs, target_ulong rt, \
1476 uint32_t sa) \
1477 { \
1478 uint16_t rs3, rs2, rs1, rs0; \
1479 uint16_t rt3, rt2, rt1, rt0; \
1480 uint16_t tempD, tempC, tempB, tempA; \
1481 \
1482 MIPSDSP_SPLIT64_16(rs, rs3, rs2, rs1, rs0); \
1483 MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0); \
1484 \
1485 /* When sa = 0, we use rt2, rt0, rs2, rs0; \
1486 * when sa != 0, we use rt3, rt1, rs3, rs1. */ \
1487 if (sa == 0) { \
1488 tempD = rt2 << var; \
1489 tempC = rt0 << var; \
1490 tempB = rs2 << var; \
1491 tempA = rs0 << var; \
1492 } else { \
1493 tempD = (((int16_t)rt3 >> sa) + var) >> var; \
1494 tempC = (((int16_t)rt1 >> sa) + var) >> var; \
1495 tempB = (((int16_t)rs3 >> sa) + var) >> var; \
1496 tempA = (((int16_t)rs1 >> sa) + var) >> var; \
1497 } \
1498 \
1499 return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA); \
1500 }
1501
1502 PRECR_QH_PW(sra, 0);
1503 PRECR_QH_PW(sra_r, 1);
1504
1505 #undef PRECR_QH_PW
1506
1507 target_ulong helper_precrq_ob_qh(target_ulong rs, target_ulong rt)
1508 {
1509 uint8_t rs6, rs4, rs2, rs0;
1510 uint8_t rt6, rt4, rt2, rt0;
1511 uint64_t temp;
1512
1513 rs6 = (rs >> 56) & MIPSDSP_Q0;
1514 rs4 = (rs >> 40) & MIPSDSP_Q0;
1515 rs2 = (rs >> 24) & MIPSDSP_Q0;
1516 rs0 = (rs >> 8) & MIPSDSP_Q0;
1517 rt6 = (rt >> 56) & MIPSDSP_Q0;
1518 rt4 = (rt >> 40) & MIPSDSP_Q0;
1519 rt2 = (rt >> 24) & MIPSDSP_Q0;
1520 rt0 = (rt >> 8) & MIPSDSP_Q0;
1521
1522 temp = ((uint64_t)rs6 << 56) | ((uint64_t)rs4 << 48) |
1523 ((uint64_t)rs2 << 40) | ((uint64_t)rs0 << 32) |
1524 ((uint64_t)rt6 << 24) | ((uint64_t)rt4 << 16) |
1525 ((uint64_t)rt2 << 8) | (uint64_t)rt0;
1526
1527 return temp;
1528 }
1529
1530 target_ulong helper_precrq_qh_pw(target_ulong rs, target_ulong rt)
1531 {
1532 uint16_t tempD, tempC, tempB, tempA;
1533
1534 tempD = (rs >> 48) & MIPSDSP_LO;
1535 tempC = (rs >> 16) & MIPSDSP_LO;
1536 tempB = (rt >> 48) & MIPSDSP_LO;
1537 tempA = (rt >> 16) & MIPSDSP_LO;
1538
1539 return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA);
1540 }
1541
1542 target_ulong helper_precrq_rs_qh_pw(target_ulong rs, target_ulong rt,
1543 CPUMIPSState *env)
1544 {
1545 uint32_t rs2, rs0;
1546 uint32_t rt2, rt0;
1547 uint16_t tempD, tempC, tempB, tempA;
1548
1549 rs2 = (rs >> 32) & MIPSDSP_LLO;
1550 rs0 = rs & MIPSDSP_LLO;
1551 rt2 = (rt >> 32) & MIPSDSP_LLO;
1552 rt0 = rt & MIPSDSP_LLO;
1553
1554 tempD = mipsdsp_trunc16_sat16_round(rs2, env);
1555 tempC = mipsdsp_trunc16_sat16_round(rs0, env);
1556 tempB = mipsdsp_trunc16_sat16_round(rt2, env);
1557 tempA = mipsdsp_trunc16_sat16_round(rt0, env);
1558
1559 return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA);
1560 }
1561
1562 target_ulong helper_precrq_pw_l(target_ulong rs, target_ulong rt)
1563 {
1564 uint32_t tempB, tempA;
1565
1566 tempB = (rs >> 32) & MIPSDSP_LLO;
1567 tempA = (rt >> 32) & MIPSDSP_LLO;
1568
1569 return MIPSDSP_RETURN64_32(tempB, tempA);
1570 }
1571 #endif
1572
1573 target_ulong helper_precrqu_s_qb_ph(target_ulong rs, target_ulong rt,
1574 CPUMIPSState *env)
1575 {
1576 uint8_t tempD, tempC, tempB, tempA;
1577 uint16_t rsh, rsl, rth, rtl;
1578
1579 rsh = (rs & MIPSDSP_HI) >> 16;
1580 rsl = rs & MIPSDSP_LO;
1581 rth = (rt & MIPSDSP_HI) >> 16;
1582 rtl = rt & MIPSDSP_LO;
1583
1584 tempD = mipsdsp_sat8_reduce_precision(rsh, env);
1585 tempC = mipsdsp_sat8_reduce_precision(rsl, env);
1586 tempB = mipsdsp_sat8_reduce_precision(rth, env);
1587 tempA = mipsdsp_sat8_reduce_precision(rtl, env);
1588
1589 return MIPSDSP_RETURN32_8(tempD, tempC, tempB, tempA);
1590 }
1591
1592 #if defined(TARGET_MIPS64)
1593 target_ulong helper_precrqu_s_ob_qh(target_ulong rs, target_ulong rt,
1594 CPUMIPSState *env)
1595 {
1596 int i;
1597 uint16_t rs3, rs2, rs1, rs0;
1598 uint16_t rt3, rt2, rt1, rt0;
1599 uint8_t temp[8];
1600 uint64_t result;
1601
1602 result = 0;
1603
1604 MIPSDSP_SPLIT64_16(rs, rs3, rs2, rs1, rs0);
1605 MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0);
1606
1607 temp[7] = mipsdsp_sat8_reduce_precision(rs3, env);
1608 temp[6] = mipsdsp_sat8_reduce_precision(rs2, env);
1609 temp[5] = mipsdsp_sat8_reduce_precision(rs1, env);
1610 temp[4] = mipsdsp_sat8_reduce_precision(rs0, env);
1611 temp[3] = mipsdsp_sat8_reduce_precision(rt3, env);
1612 temp[2] = mipsdsp_sat8_reduce_precision(rt2, env);
1613 temp[1] = mipsdsp_sat8_reduce_precision(rt1, env);
1614 temp[0] = mipsdsp_sat8_reduce_precision(rt0, env);
1615
1616 for (i = 0; i < 8; i++) {
1617 result |= (uint64_t)temp[i] << (8 * i);
1618 }
1619
1620 return result;
1621 }
1622
1623 #define PRECEQ_PW(name, a, b) \
1624 target_ulong helper_preceq_pw_##name(target_ulong rt) \
1625 { \
1626 uint16_t tempB, tempA; \
1627 uint32_t tempBI, tempAI; \
1628 \
1629 tempB = (rt >> a) & MIPSDSP_LO; \
1630 tempA = (rt >> b) & MIPSDSP_LO; \
1631 \
1632 tempBI = (uint32_t)tempB << 16; \
1633 tempAI = (uint32_t)tempA << 16; \
1634 \
1635 return MIPSDSP_RETURN64_32(tempBI, tempAI); \
1636 }
1637
1638 PRECEQ_PW(qhl, 48, 32);
1639 PRECEQ_PW(qhr, 16, 0);
1640 PRECEQ_PW(qhla, 48, 16);
1641 PRECEQ_PW(qhra, 32, 0);
1642
1643 #undef PRECEQ_PW
1644
1645 #endif
1646
1647 #define PRECEQU_PH(name, a, b) \
1648 target_ulong helper_precequ_ph_##name(target_ulong rt) \
1649 { \
1650 uint16_t tempB, tempA; \
1651 \
1652 tempB = (rt >> a) & MIPSDSP_Q0; \
1653 tempA = (rt >> b) & MIPSDSP_Q0; \
1654 \
1655 tempB = tempB << 7; \
1656 tempA = tempA << 7; \
1657 \
1658 return MIPSDSP_RETURN32_16(tempB, tempA); \
1659 }
1660
1661 PRECEQU_PH(qbl, 24, 16);
1662 PRECEQU_PH(qbr, 8, 0);
1663 PRECEQU_PH(qbla, 24, 8);
1664 PRECEQU_PH(qbra, 16, 0);
1665
1666 #undef PRECEQU_PH
1667
1668 #if defined(TARGET_MIPS64)
1669 #define PRECEQU_QH(name, a, b, c, d) \
1670 target_ulong helper_precequ_qh_##name(target_ulong rt) \
1671 { \
1672 uint16_t tempD, tempC, tempB, tempA; \
1673 \
1674 tempD = (rt >> a) & MIPSDSP_Q0; \
1675 tempC = (rt >> b) & MIPSDSP_Q0; \
1676 tempB = (rt >> c) & MIPSDSP_Q0; \
1677 tempA = (rt >> d) & MIPSDSP_Q0; \
1678 \
1679 tempD = tempD << 7; \
1680 tempC = tempC << 7; \
1681 tempB = tempB << 7; \
1682 tempA = tempA << 7; \
1683 \
1684 return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA); \
1685 }
1686
1687 PRECEQU_QH(obl, 56, 48, 40, 32);
1688 PRECEQU_QH(obr, 24, 16, 8, 0);
1689 PRECEQU_QH(obla, 56, 40, 24, 8);
1690 PRECEQU_QH(obra, 48, 32, 16, 0);
1691
1692 #undef PRECEQU_QH
1693
1694 #endif
1695
1696 #define PRECEU_PH(name, a, b) \
1697 target_ulong helper_preceu_ph_##name(target_ulong rt) \
1698 { \
1699 uint16_t tempB, tempA; \
1700 \
1701 tempB = (rt >> a) & MIPSDSP_Q0; \
1702 tempA = (rt >> b) & MIPSDSP_Q0; \
1703 \
1704 return MIPSDSP_RETURN32_16(tempB, tempA); \
1705 }
1706
1707 PRECEU_PH(qbl, 24, 16);
1708 PRECEU_PH(qbr, 8, 0);
1709 PRECEU_PH(qbla, 24, 8);
1710 PRECEU_PH(qbra, 16, 0);
1711
1712 #undef PRECEU_PH
1713
1714 #if defined(TARGET_MIPS64)
1715 #define PRECEU_QH(name, a, b, c, d) \
1716 target_ulong helper_preceu_qh_##name(target_ulong rt) \
1717 { \
1718 uint16_t tempD, tempC, tempB, tempA; \
1719 \
1720 tempD = (rt >> a) & MIPSDSP_Q0; \
1721 tempC = (rt >> b) & MIPSDSP_Q0; \
1722 tempB = (rt >> c) & MIPSDSP_Q0; \
1723 tempA = (rt >> d) & MIPSDSP_Q0; \
1724 \
1725 return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA); \
1726 }
1727
1728 PRECEU_QH(obl, 56, 48, 40, 32);
1729 PRECEU_QH(obr, 24, 16, 8, 0);
1730 PRECEU_QH(obla, 56, 40, 24, 8);
1731 PRECEU_QH(obra, 48, 32, 16, 0);
1732
1733 #undef PRECEU_QH
1734
1735 #endif
1736
1737 /** DSP GPR-Based Shift Sub-class insns **/
1738 #define SHIFT_QB(name, func) \
1739 target_ulong helper_##name##_qb(target_ulong sa, target_ulong rt) \
1740 { \
1741 uint8_t rt3, rt2, rt1, rt0; \
1742 \
1743 sa = sa & 0x07; \
1744 \
1745 MIPSDSP_SPLIT32_8(rt, rt3, rt2, rt1, rt0); \
1746 \
1747 rt3 = mipsdsp_##func(rt3, sa); \
1748 rt2 = mipsdsp_##func(rt2, sa); \
1749 rt1 = mipsdsp_##func(rt1, sa); \
1750 rt0 = mipsdsp_##func(rt0, sa); \
1751 \
1752 return MIPSDSP_RETURN32_8(rt3, rt2, rt1, rt0); \
1753 }
1754
1755 #define SHIFT_QB_ENV(name, func) \
1756 target_ulong helper_##name##_qb(target_ulong sa, target_ulong rt,\
1757 CPUMIPSState *env) \
1758 { \
1759 uint8_t rt3, rt2, rt1, rt0; \
1760 \
1761 sa = sa & 0x07; \
1762 \
1763 MIPSDSP_SPLIT32_8(rt, rt3, rt2, rt1, rt0); \
1764 \
1765 rt3 = mipsdsp_##func(rt3, sa, env); \
1766 rt2 = mipsdsp_##func(rt2, sa, env); \
1767 rt1 = mipsdsp_##func(rt1, sa, env); \
1768 rt0 = mipsdsp_##func(rt0, sa, env); \
1769 \
1770 return MIPSDSP_RETURN32_8(rt3, rt2, rt1, rt0); \
1771 }
1772
1773 SHIFT_QB_ENV(shll, lshift8);
1774 SHIFT_QB(shrl, rshift_u8);
1775
1776 SHIFT_QB(shra, rashift8);
1777 SHIFT_QB(shra_r, rnd8_rashift);
1778
1779 #undef SHIFT_QB
1780 #undef SHIFT_QB_ENV
1781
1782 #if defined(TARGET_MIPS64)
1783 #define SHIFT_OB(name, func) \
1784 target_ulong helper_##name##_ob(target_ulong rt, target_ulong sa) \
1785 { \
1786 int i; \
1787 uint8_t rt_t[8]; \
1788 uint64_t temp; \
1789 \
1790 sa = sa & 0x07; \
1791 temp = 0; \
1792 \
1793 for (i = 0; i < 8; i++) { \
1794 rt_t[i] = (rt >> (8 * i)) & MIPSDSP_Q0; \
1795 rt_t[i] = mipsdsp_##func(rt_t[i], sa); \
1796 temp |= (uint64_t)rt_t[i] << (8 * i); \
1797 } \
1798 \
1799 return temp; \
1800 }
1801
1802 #define SHIFT_OB_ENV(name, func) \
1803 target_ulong helper_##name##_ob(target_ulong rt, target_ulong sa, \
1804 CPUMIPSState *env) \
1805 { \
1806 int i; \
1807 uint8_t rt_t[8]; \
1808 uint64_t temp; \
1809 \
1810 sa = sa & 0x07; \
1811 temp = 0; \
1812 \
1813 for (i = 0; i < 8; i++) { \
1814 rt_t[i] = (rt >> (8 * i)) & MIPSDSP_Q0; \
1815 rt_t[i] = mipsdsp_##func(rt_t[i], sa, env); \
1816 temp |= (uint64_t)rt_t[i] << (8 * i); \
1817 } \
1818 \
1819 return temp; \
1820 }
1821
1822 SHIFT_OB_ENV(shll, lshift8);
1823 SHIFT_OB(shrl, rshift_u8);
1824
1825 SHIFT_OB(shra, rashift8);
1826 SHIFT_OB(shra_r, rnd8_rashift);
1827
1828 #undef SHIFT_OB
1829 #undef SHIFT_OB_ENV
1830
1831 #endif
1832
1833 #define SHIFT_PH(name, func) \
1834 target_ulong helper_##name##_ph(target_ulong sa, target_ulong rt, \
1835 CPUMIPSState *env) \
1836 { \
1837 uint16_t rth, rtl; \
1838 \
1839 sa = sa & 0x0F; \
1840 \
1841 MIPSDSP_SPLIT32_16(rt, rth, rtl); \
1842 \
1843 rth = mipsdsp_##func(rth, sa, env); \
1844 rtl = mipsdsp_##func(rtl, sa, env); \
1845 \
1846 return MIPSDSP_RETURN32_16(rth, rtl); \
1847 }
1848
1849 SHIFT_PH(shll, lshift16);
1850 SHIFT_PH(shll_s, sat16_lshift);
1851
1852 #undef SHIFT_PH
1853
1854 #if defined(TARGET_MIPS64)
1855 #define SHIFT_QH(name, func) \
1856 target_ulong helper_##name##_qh(target_ulong rt, target_ulong sa) \
1857 { \
1858 uint16_t rt3, rt2, rt1, rt0; \
1859 \
1860 sa = sa & 0x0F; \
1861 \
1862 MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0); \
1863 \
1864 rt3 = mipsdsp_##func(rt3, sa); \
1865 rt2 = mipsdsp_##func(rt2, sa); \
1866 rt1 = mipsdsp_##func(rt1, sa); \
1867 rt0 = mipsdsp_##func(rt0, sa); \
1868 \
1869 return MIPSDSP_RETURN64_16(rt3, rt2, rt1, rt0); \
1870 }
1871
1872 #define SHIFT_QH_ENV(name, func) \
1873 target_ulong helper_##name##_qh(target_ulong rt, target_ulong sa, \
1874 CPUMIPSState *env) \
1875 { \
1876 uint16_t rt3, rt2, rt1, rt0; \
1877 \
1878 sa = sa & 0x0F; \
1879 \
1880 MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0); \
1881 \
1882 rt3 = mipsdsp_##func(rt3, sa, env); \
1883 rt2 = mipsdsp_##func(rt2, sa, env); \
1884 rt1 = mipsdsp_##func(rt1, sa, env); \
1885 rt0 = mipsdsp_##func(rt0, sa, env); \
1886 \
1887 return MIPSDSP_RETURN64_16(rt3, rt2, rt1, rt0); \
1888 }
1889
1890 SHIFT_QH_ENV(shll, lshift16);
1891 SHIFT_QH_ENV(shll_s, sat16_lshift);
1892
1893 SHIFT_QH(shrl, rshift_u16);
1894 SHIFT_QH(shra, rashift16);
1895 SHIFT_QH(shra_r, rnd16_rashift);
1896
1897 #undef SHIFT_QH
1898 #undef SHIFT_QH_ENV
1899
1900 #endif
1901
1902 #define SHIFT_W(name, func) \
1903 target_ulong helper_##name##_w(target_ulong sa, target_ulong rt) \
1904 { \
1905 uint32_t temp; \
1906 \
1907 sa = sa & 0x1F; \
1908 temp = mipsdsp_##func(rt, sa); \
1909 \
1910 return (target_long)(int32_t)temp; \
1911 }
1912
1913 #define SHIFT_W_ENV(name, func) \
1914 target_ulong helper_##name##_w(target_ulong sa, target_ulong rt, \
1915 CPUMIPSState *env) \
1916 { \
1917 uint32_t temp; \
1918 \
1919 sa = sa & 0x1F; \
1920 temp = mipsdsp_##func(rt, sa, env); \
1921 \
1922 return (target_long)(int32_t)temp; \
1923 }
1924
1925 SHIFT_W_ENV(shll_s, sat32_lshift);
1926 SHIFT_W(shra_r, rnd32_rashift);
1927
1928 #undef SHIFT_W
1929 #undef SHIFT_W_ENV
1930
1931 #if defined(TARGET_MIPS64)
1932 #define SHIFT_PW(name, func) \
1933 target_ulong helper_##name##_pw(target_ulong rt, target_ulong sa) \
1934 { \
1935 uint32_t rt1, rt0; \
1936 \
1937 sa = sa & 0x1F; \
1938 MIPSDSP_SPLIT64_32(rt, rt1, rt0); \
1939 \
1940 rt1 = mipsdsp_##func(rt1, sa); \
1941 rt0 = mipsdsp_##func(rt0, sa); \
1942 \
1943 return MIPSDSP_RETURN64_32(rt1, rt0); \
1944 }
1945
1946 #define SHIFT_PW_ENV(name, func) \
1947 target_ulong helper_##name##_pw(target_ulong rt, target_ulong sa, \
1948 CPUMIPSState *env) \
1949 { \
1950 uint32_t rt1, rt0; \
1951 \
1952 sa = sa & 0x1F; \
1953 MIPSDSP_SPLIT64_32(rt, rt1, rt0); \
1954 \
1955 rt1 = mipsdsp_##func(rt1, sa, env); \
1956 rt0 = mipsdsp_##func(rt0, sa, env); \
1957 \
1958 return MIPSDSP_RETURN64_32(rt1, rt0); \
1959 }
1960
1961 SHIFT_PW_ENV(shll, lshift32);
1962 SHIFT_PW_ENV(shll_s, sat32_lshift);
1963
1964 SHIFT_PW(shra, rashift32);
1965 SHIFT_PW(shra_r, rnd32_rashift);
1966
1967 #undef SHIFT_PW
1968 #undef SHIFT_PW_ENV
1969
1970 #endif
1971
1972 #define SHIFT_PH(name, func) \
1973 target_ulong helper_##name##_ph(target_ulong sa, target_ulong rt) \
1974 { \
1975 uint16_t rth, rtl; \
1976 \
1977 sa = sa & 0x0F; \
1978 \
1979 MIPSDSP_SPLIT32_16(rt, rth, rtl); \
1980 \
1981 rth = mipsdsp_##func(rth, sa); \
1982 rtl = mipsdsp_##func(rtl, sa); \
1983 \
1984 return MIPSDSP_RETURN32_16(rth, rtl); \
1985 }
1986
1987 SHIFT_PH(shrl, rshift_u16);
1988 SHIFT_PH(shra, rashift16);
1989 SHIFT_PH(shra_r, rnd16_rashift);
1990
1991 #undef SHIFT_PH
1992
1993 /** DSP Multiply Sub-class insns **/
1994 /* Return value made up by two 16bits value.
1995 * FIXME give the macro a better name.
1996 */
1997 #define MUL_RETURN32_16_PH(name, func, \
1998 rsmov1, rsmov2, rsfilter, \
1999 rtmov1, rtmov2, rtfilter) \
2000 target_ulong helper_##name(target_ulong rs, target_ulong rt, \
2001 CPUMIPSState *env) \
2002 { \
2003 uint16_t rsB, rsA, rtB, rtA; \
2004 \
2005 rsB = (rs >> rsmov1) & rsfilter; \
2006 rsA = (rs >> rsmov2) & rsfilter; \
2007 rtB = (rt >> rtmov1) & rtfilter; \
2008 rtA = (rt >> rtmov2) & rtfilter; \
2009 \
2010 rsB = mipsdsp_##func(rsB, rtB, env); \
2011 rsA = mipsdsp_##func(rsA, rtA, env); \
2012 \
2013 return MIPSDSP_RETURN32_16(rsB, rsA); \
2014 }
2015
2016 MUL_RETURN32_16_PH(muleu_s_ph_qbl, mul_u8_u16, \
2017 24, 16, MIPSDSP_Q0, \
2018 16, 0, MIPSDSP_LO);
2019 MUL_RETURN32_16_PH(muleu_s_ph_qbr, mul_u8_u16, \
2020 8, 0, MIPSDSP_Q0, \
2021 16, 0, MIPSDSP_LO);
2022 MUL_RETURN32_16_PH(mulq_rs_ph, rndq15_mul_q15_q15, \
2023 16, 0, MIPSDSP_LO, \
2024 16, 0, MIPSDSP_LO);
2025 MUL_RETURN32_16_PH(mul_ph, mul_i16_i16, \
2026 16, 0, MIPSDSP_LO, \
2027 16, 0, MIPSDSP_LO);
2028 MUL_RETURN32_16_PH(mul_s_ph, sat16_mul_i16_i16, \
2029 16, 0, MIPSDSP_LO, \
2030 16, 0, MIPSDSP_LO);
2031 MUL_RETURN32_16_PH(mulq_s_ph, sat16_mul_q15_q15, \
2032 16, 0, MIPSDSP_LO, \
2033 16, 0, MIPSDSP_LO);
2034
2035 #undef MUL_RETURN32_16_PH
2036
2037 #define MUL_RETURN32_32_ph(name, func, movbits) \
2038 target_ulong helper_##name(target_ulong rs, target_ulong rt, \
2039 CPUMIPSState *env) \
2040 { \
2041 int16_t rsh, rth; \
2042 int32_t temp; \
2043 \
2044 rsh = (rs >> movbits) & MIPSDSP_LO; \
2045 rth = (rt >> movbits) & MIPSDSP_LO; \
2046 temp = mipsdsp_##func(rsh, rth, env); \
2047 \
2048 return (target_long)(int32_t)temp; \
2049 }
2050
2051 MUL_RETURN32_32_ph(muleq_s_w_phl, mul_q15_q15_overflowflag21, 16);
2052 MUL_RETURN32_32_ph(muleq_s_w_phr, mul_q15_q15_overflowflag21, 0);
2053
2054 #undef MUL_RETURN32_32_ph
2055
2056 #define MUL_VOID_PH(name, use_ac_env) \
2057 void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt, \
2058 CPUMIPSState *env) \
2059 { \
2060 int16_t rsh, rsl, rth, rtl; \
2061 int32_t tempB, tempA; \
2062 int64_t acc, dotp; \
2063 \
2064 MIPSDSP_SPLIT32_16(rs, rsh, rsl); \
2065 MIPSDSP_SPLIT32_16(rt, rth, rtl); \
2066 \
2067 if (use_ac_env == 1) { \
2068 tempB = mipsdsp_mul_q15_q15(ac, rsh, rth, env); \
2069 tempA = mipsdsp_mul_q15_q15(ac, rsl, rtl, env); \
2070 } else { \
2071 tempB = mipsdsp_mul_u16_u16(rsh, rth); \
2072 tempA = mipsdsp_mul_u16_u16(rsl, rtl); \
2073 } \
2074 \
2075 dotp = (int64_t)tempB - (int64_t)tempA; \
2076 acc = ((uint64_t)env->active_tc.HI[ac] << 32) | \
2077 ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO); \
2078 dotp = dotp + acc; \
2079 env->active_tc.HI[ac] = (target_long)(int32_t) \
2080 ((dotp & MIPSDSP_LHI) >> 32); \
2081 env->active_tc.LO[ac] = (target_long)(int32_t)(dotp & MIPSDSP_LLO); \
2082 }
2083
2084 MUL_VOID_PH(mulsaq_s_w_ph, 1);
2085 MUL_VOID_PH(mulsa_w_ph, 0);
2086
2087 #undef MUL_VOID_PH
2088
2089 #if defined(TARGET_MIPS64)
2090 #define MUL_RETURN64_16_QH(name, func, \
2091 rsmov1, rsmov2, rsmov3, rsmov4, rsfilter, \
2092 rtmov1, rtmov2, rtmov3, rtmov4, rtfilter) \
2093 target_ulong helper_##name(target_ulong rs, target_ulong rt, \
2094 CPUMIPSState *env) \
2095 { \
2096 uint16_t rs3, rs2, rs1, rs0; \
2097 uint16_t rt3, rt2, rt1, rt0; \
2098 uint16_t tempD, tempC, tempB, tempA; \
2099 \
2100 rs3 = (rs >> rsmov1) & rsfilter; \
2101 rs2 = (rs >> rsmov2) & rsfilter; \
2102 rs1 = (rs >> rsmov3) & rsfilter; \
2103 rs0 = (rs >> rsmov4) & rsfilter; \
2104 rt3 = (rt >> rtmov1) & rtfilter; \
2105 rt2 = (rt >> rtmov2) & rtfilter; \
2106 rt1 = (rt >> rtmov3) & rtfilter; \
2107 rt0 = (rt >> rtmov4) & rtfilter; \
2108 \
2109 tempD = mipsdsp_##func(rs3, rt3, env); \
2110 tempC = mipsdsp_##func(rs2, rt2, env); \
2111 tempB = mipsdsp_##func(rs1, rt1, env); \
2112 tempA = mipsdsp_##func(rs0, rt0, env); \
2113 \
2114 return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA); \
2115 }
2116
2117 MUL_RETURN64_16_QH(muleu_s_qh_obl, mul_u8_u16, \
2118 56, 48, 40, 32, MIPSDSP_Q0, \
2119 48, 32, 16, 0, MIPSDSP_LO);
2120 MUL_RETURN64_16_QH(muleu_s_qh_obr, mul_u8_u16, \
2121 24, 16, 8, 0, MIPSDSP_Q0, \
2122 48, 32, 16, 0, MIPSDSP_LO);
2123 MUL_RETURN64_16_QH(mulq_rs_qh, rndq15_mul_q15_q15, \
2124 48, 32, 16, 0, MIPSDSP_LO, \
2125 48, 32, 16, 0, MIPSDSP_LO);
2126
2127 #undef MUL_RETURN64_16_QH
2128
2129 #define MUL_RETURN64_32_QH(name, \
2130 rsmov1, rsmov2, \
2131 rtmov1, rtmov2) \
2132 target_ulong helper_##name(target_ulong rs, target_ulong rt, \
2133 CPUMIPSState *env) \
2134 { \
2135 uint16_t rsB, rsA; \
2136 uint16_t rtB, rtA; \
2137 uint32_t tempB, tempA; \
2138 \
2139 rsB = (rs >> rsmov1) & MIPSDSP_LO; \
2140 rsA = (rs >> rsmov2) & MIPSDSP_LO; \
2141 rtB = (rt >> rtmov1) & MIPSDSP_LO; \
2142 rtA = (rt >> rtmov2) & MIPSDSP_LO; \
2143 \
2144 tempB = mipsdsp_mul_q15_q15(5, rsB, rtB, env); \
2145 tempA = mipsdsp_mul_q15_q15(5, rsA, rtA, env); \
2146 \
2147 return ((uint64_t)tempB << 32) | (uint64_t)tempA; \
2148 }
2149
2150 MUL_RETURN64_32_QH(muleq_s_pw_qhl, 48, 32, 48, 32);
2151 MUL_RETURN64_32_QH(muleq_s_pw_qhr, 16, 0, 16, 0);
2152
2153 #undef MUL_RETURN64_32_QH
2154
2155 void helper_mulsaq_s_w_qh(target_ulong rs, target_ulong rt, uint32_t ac,
2156 CPUMIPSState *env)
2157 {
2158 int16_t rs3, rs2, rs1, rs0;
2159 int16_t rt3, rt2, rt1, rt0;
2160 int32_t tempD, tempC, tempB, tempA;
2161 int64_t acc[2];
2162 int64_t temp[2];
2163 int64_t temp_sum;
2164
2165 MIPSDSP_SPLIT64_16(rs, rs3, rs2, rs1, rs0);
2166 MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0);
2167
2168 tempD = mipsdsp_mul_q15_q15(ac, rs3, rt3, env);
2169 tempC = mipsdsp_mul_q15_q15(ac, rs2, rt2, env);
2170 tempB = mipsdsp_mul_q15_q15(ac, rs1, rt1, env);
2171 tempA = mipsdsp_mul_q15_q15(ac, rs0, rt0, env);
2172
2173 temp[0] = ((int32_t)tempD - (int32_t)tempC) +
2174 ((int32_t)tempB - (int32_t)tempA);
2175 temp[0] = (int64_t)(temp[0] << 30) >> 30;
2176 if (((temp[0] >> 33) & 0x01) == 0) {
2177 temp[1] = 0x00;
2178 } else {
2179 temp[1] = ~0ull;
2180 }
2181
2182 acc[0] = env->active_tc.LO[ac];
2183 acc[1] = env->active_tc.HI[ac];
2184
2185 temp_sum = acc[0] + temp[0];
2186 if (((uint64_t)temp_sum < (uint64_t)acc[0]) &&
2187 ((uint64_t)temp_sum < (uint64_t)temp[0])) {
2188 acc[1] += 1;
2189 }
2190 acc[0] = temp_sum;
2191 acc[1] += temp[1];
2192
2193 env->active_tc.HI[ac] = acc[1];
2194 env->active_tc.LO[ac] = acc[0];
2195 }
2196 #endif
2197
2198 #define DP_QB(name, func, is_add, rsmov1, rsmov2, rtmov1, rtmov2) \
2199 void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt, \
2200 CPUMIPSState *env) \
2201 { \
2202 uint8_t rs3, rs2; \
2203 uint8_t rt3, rt2; \
2204 uint16_t tempB, tempA; \
2205 uint64_t tempC, dotp; \
2206 \
2207 rs3 = (rs >> rsmov1) & MIPSDSP_Q0; \
2208 rs2 = (rs >> rsmov2) & MIPSDSP_Q0; \
2209 rt3 = (rt >> rtmov1) & MIPSDSP_Q0; \
2210 rt2 = (rt >> rtmov2) & MIPSDSP_Q0; \
2211 tempB = mipsdsp_##func(rs3, rt3); \
2212 tempA = mipsdsp_##func(rs2, rt2); \
2213 dotp = (int64_t)tempB + (int64_t)tempA; \
2214 if (is_add) { \
2215 tempC = (((uint64_t)env->active_tc.HI[ac] << 32) | \
2216 ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO)) \
2217 + dotp; \
2218 } else { \
2219 tempC = (((uint64_t)env->active_tc.HI[ac] << 32) | \
2220 ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO)) \
2221 - dotp; \
2222 } \
2223 \
2224 env->active_tc.HI[ac] = (target_long)(int32_t) \
2225 ((tempC & MIPSDSP_LHI) >> 32); \
2226 env->active_tc.LO[ac] = (target_long)(int32_t)(tempC & MIPSDSP_LLO); \
2227 }
2228
2229 DP_QB(dpau_h_qbl, mul_u8_u8, 1, 24, 16, 24, 16);
2230 DP_QB(dpau_h_qbr, mul_u8_u8, 1, 8, 0, 8, 0);
2231 DP_QB(dpsu_h_qbl, mul_u8_u8, 0, 24, 16, 24, 16);
2232 DP_QB(dpsu_h_qbr, mul_u8_u8, 0, 8, 0, 8, 0);
2233
2234 #undef DP_QB
2235
2236 #if defined(TARGET_MIPS64)
2237 #define DP_OB(name, add_sub, \
2238 rsmov1, rsmov2, rsmov3, rsmov4, \
2239 rtmov1, rtmov2, rtmov3, rtmov4) \
2240 void helper_##name(target_ulong rs, target_ulong rt, uint32_t ac, \
2241 CPUMIPSState *env) \
2242 { \
2243 uint8_t rsD, rsC, rsB, rsA; \
2244 uint8_t rtD, rtC, rtB, rtA; \
2245 uint16_t tempD, tempC, tempB, tempA; \
2246 uint64_t temp[2]; \
2247 uint64_t acc[2]; \
2248 uint64_t temp_sum; \
2249 \
2250 temp[0] = 0; \
2251 temp[1] = 0; \
2252 \
2253 rsD = (rs >> rsmov1) & MIPSDSP_Q0; \
2254 rsC = (rs >> rsmov2) & MIPSDSP_Q0; \
2255 rsB = (rs >> rsmov3) & MIPSDSP_Q0; \
2256 rsA = (rs >> rsmov4) & MIPSDSP_Q0; \
2257 rtD = (rt >> rtmov1) & MIPSDSP_Q0; \
2258 rtC = (rt >> rtmov2) & MIPSDSP_Q0; \
2259 rtB = (rt >> rtmov3) & MIPSDSP_Q0; \
2260 rtA = (rt >> rtmov4) & MIPSDSP_Q0; \
2261 \
2262 tempD = mipsdsp_mul_u8_u8(rsD, rtD); \
2263 tempC = mipsdsp_mul_u8_u8(rsC, rtC); \
2264 tempB = mipsdsp_mul_u8_u8(rsB, rtB); \
2265 tempA = mipsdsp_mul_u8_u8(rsA, rtA); \
2266 \
2267 temp[0] = (uint64_t)tempD + (uint64_t)tempC + \
2268 (uint64_t)tempB + (uint64_t)tempA; \
2269 \
2270 acc[0] = env->active_tc.LO[ac]; \
2271 acc[1] = env->active_tc.HI[ac]; \
2272 \
2273 if (add_sub) { \
2274 temp_sum = acc[0] + temp[0]; \
2275 if (((uint64_t)temp_sum < (uint64_t)acc[0]) && \
2276 ((uint64_t)temp_sum < (uint64_t)temp[0])) { \
2277 acc[1] += 1; \
2278 } \
2279 temp[0] = temp_sum; \
2280 temp[1] = acc[1] + temp[1]; \
2281 } else { \
2282 temp_sum = acc[0] - temp[0]; \
2283 if ((uint64_t)temp_sum > (uint64_t)acc[0]) { \
2284 acc[1] -= 1; \
2285 } \
2286 temp[0] = temp_sum; \
2287 temp[1] = acc[1] - temp[1]; \
2288 } \
2289 \
2290 env->active_tc.HI[ac] = temp[1]; \
2291 env->active_tc.LO[ac] = temp[0]; \
2292 }
2293
2294 DP_OB(dpau_h_obl, 1, 56, 48, 40, 32, 56, 48, 40, 32);
2295 DP_OB(dpau_h_obr, 1, 24, 16, 8, 0, 24, 16, 8, 0);
2296 DP_OB(dpsu_h_obl, 0, 56, 48, 40, 32, 56, 48, 40, 32);
2297 DP_OB(dpsu_h_obr, 0, 24, 16, 8, 0, 24, 16, 8, 0);
2298
2299 #undef DP_OB
2300 #endif
2301
2302 #define DP_NOFUNC_PH(name, is_add, rsmov1, rsmov2, rtmov1, rtmov2) \
2303 void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt, \
2304 CPUMIPSState *env) \
2305 { \
2306 int16_t rsB, rsA, rtB, rtA; \
2307 int32_t tempA, tempB; \
2308 int64_t acc; \
2309 \
2310 rsB = (rs >> rsmov1) & MIPSDSP_LO; \
2311 rsA = (rs >> rsmov2) & MIPSDSP_LO; \
2312 rtB = (rt >> rtmov1) & MIPSDSP_LO; \
2313 rtA = (rt >> rtmov2) & MIPSDSP_LO; \
2314 \
2315 tempB = (int32_t)rsB * (int32_t)rtB; \
2316 tempA = (int32_t)rsA * (int32_t)rtA; \
2317 \
2318 acc = ((uint64_t)env->active_tc.HI[ac] << 32) | \
2319 ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO); \
2320 \
2321 if (is_add) { \
2322 acc = acc + ((int64_t)tempB + (int64_t)tempA); \
2323 } else { \
2324 acc = acc - ((int64_t)tempB + (int64_t)tempA); \
2325 } \
2326 \
2327 env->active_tc.HI[ac] = (target_long)(int32_t)((acc & MIPSDSP_LHI) >> 32); \
2328 env->active_tc.LO[ac] = (target_long)(int32_t)(acc & MIPSDSP_LLO); \
2329 }
2330
2331 DP_NOFUNC_PH(dpa_w_ph, 1, 16, 0, 16, 0);
2332 DP_NOFUNC_PH(dpax_w_ph, 1, 16, 0, 0, 16);
2333 DP_NOFUNC_PH(dps_w_ph, 0, 16, 0, 16, 0);
2334 DP_NOFUNC_PH(dpsx_w_ph, 0, 16, 0, 0, 16);
2335 #undef DP_NOFUNC_PH
2336
2337 #define DP_HASFUNC_PH(name, is_add, rsmov1, rsmov2, rtmov1, rtmov2) \
2338 void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt, \
2339 CPUMIPSState *env) \
2340 { \
2341 int16_t rsB, rsA, rtB, rtA; \
2342 int32_t tempB, tempA; \
2343 int64_t acc, dotp; \
2344 \
2345 rsB = (rs >> rsmov1) & MIPSDSP_LO; \
2346 rsA = (rs >> rsmov2) & MIPSDSP_LO; \
2347 rtB = (rt >> rtmov1) & MIPSDSP_LO; \
2348 rtA = (rt >> rtmov2) & MIPSDSP_LO; \
2349 \
2350 tempB = mipsdsp_mul_q15_q15(ac, rsB, rtB, env); \
2351 tempA = mipsdsp_mul_q15_q15(ac, rsA, rtA, env); \
2352 \
2353 dotp = (int64_t)tempB + (int64_t)tempA; \
2354 acc = ((uint64_t)env->active_tc.HI[ac] << 32) | \
2355 ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO); \
2356 \
2357 if (is_add) { \
2358 acc = acc + dotp; \
2359 } else { \
2360 acc = acc - dotp; \
2361 } \
2362 \
2363 env->active_tc.HI[ac] = (target_long)(int32_t) \
2364 ((acc & MIPSDSP_LHI) >> 32); \
2365 env->active_tc.LO[ac] = (target_long)(int32_t) \
2366 (acc & MIPSDSP_LLO); \
2367 }
2368
2369 DP_HASFUNC_PH(dpaq_s_w_ph, 1, 16, 0, 16, 0);
2370 DP_HASFUNC_PH(dpaqx_s_w_ph, 1, 16, 0, 0, 16);
2371 DP_HASFUNC_PH(dpsq_s_w_ph, 0, 16, 0, 16, 0);
2372 DP_HASFUNC_PH(dpsqx_s_w_ph, 0, 16, 0, 0, 16);
2373
2374 #undef DP_HASFUNC_PH
2375
2376 #define DP_128OPERATION_PH(name, is_add) \
2377 void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt, \
2378 CPUMIPSState *env) \
2379 { \
2380 int16_t rsh, rsl, rth, rtl; \
2381 int32_t tempB, tempA, tempC62_31, tempC63; \
2382 int64_t acc, dotp, tempC; \
2383 \
2384 MIPSDSP_SPLIT32_16(rs, rsh, rsl); \
2385 MIPSDSP_SPLIT32_16(rt, rth, rtl); \
2386 \
2387 tempB = mipsdsp_mul_q15_q15(ac, rsh, rtl, env); \
2388 tempA = mipsdsp_mul_q15_q15(ac, rsl, rth, env); \
2389 \
2390 dotp = (int64_t)tempB + (int64_t)tempA; \
2391 acc = ((uint64_t)env->active_tc.HI[ac] << 32) | \
2392 ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO); \
2393 if (is_add) { \
2394 tempC = acc + dotp; \
2395 } else { \
2396 tempC = acc - dotp; \
2397 } \
2398 tempC63 = (tempC >> 63) & 0x01; \
2399 tempC62_31 = (tempC >> 31) & 0xFFFFFFFF; \
2400 \
2401 if ((tempC63 == 0) && (tempC62_31 != 0x00000000)) { \
2402 tempC = 0x7FFFFFFF; \
2403 set_DSPControl_overflow_flag(1, 16 + ac, env); \
2404 } \
2405 \
2406 if ((tempC63 == 1) && (tempC62_31 != 0xFFFFFFFF)) { \
2407 tempC = (int64_t)(int32_t)0x80000000; \
2408 set_DSPControl_overflow_flag(1, 16 + ac, env); \
2409 } \
2410 \
2411 env->active_tc.HI[ac] = (target_long)(int32_t) \
2412 ((tempC & MIPSDSP_LHI) >> 32); \
2413 env->active_tc.LO[ac] = (target_long)(int32_t) \
2414 (tempC & MIPSDSP_LLO); \
2415 }
2416
2417 DP_128OPERATION_PH(dpaqx_sa_w_ph, 1);
2418 DP_128OPERATION_PH(dpsqx_sa_w_ph, 0);
2419
2420 #undef DP_128OPERATION_HP
2421
2422 #if defined(TARGET_MIPS64)
2423 #define DP_QH(name, is_add, use_ac_env) \
2424 void helper_##name(target_ulong rs, target_ulong rt, uint32_t ac, \
2425 CPUMIPSState *env) \
2426 { \
2427 int32_t rs3, rs2, rs1, rs0; \
2428 int32_t rt3, rt2, rt1, rt0; \
2429 int32_t tempD, tempC, tempB, tempA; \
2430 int64_t acc[2]; \
2431 int64_t temp[2]; \
2432 int64_t temp_sum; \
2433 \
2434 MIPSDSP_SPLIT64_16(rs, rs3, rs2, rs1, rs0); \
2435 MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0); \
2436 \
2437 if (use_ac_env) { \
2438 tempD = mipsdsp_mul_q15_q15(ac, rs3, rt3, env); \
2439 tempC = mipsdsp_mul_q15_q15(ac, rs2, rt2, env); \
2440 tempB = mipsdsp_mul_q15_q15(ac, rs1, rt1, env); \
2441 tempA = mipsdsp_mul_q15_q15(ac, rs0, rt0, env); \
2442 } else { \
2443 tempD = mipsdsp_mul_u16_u16(rs3, rt3); \
2444 tempC = mipsdsp_mul_u16_u16(rs2, rt2); \
2445 tempB = mipsdsp_mul_u16_u16(rs1, rt1); \
2446 tempA = mipsdsp_mul_u16_u16(rs0, rt0); \
2447 } \
2448 \
2449 temp[0] = (int64_t)tempD + (int64_t)tempC + \
2450 (int64_t)tempB + (int64_t)tempA; \
2451 \
2452 if (temp[0] >= 0) { \
2453 temp[1] = 0; \
2454 } else { \
2455 temp[1] = ~0ull; \
2456 } \
2457 \
2458 acc[1] = env->active_tc.HI[ac]; \
2459 acc[0] = env->active_tc.LO[ac]; \
2460 \
2461 if (is_add) { \
2462 temp_sum = acc[0] + temp[0]; \
2463 if (((uint64_t)temp_sum < (uint64_t)acc[0]) && \
2464 ((uint64_t)temp_sum < (uint64_t)temp[0])) { \
2465 acc[1] = acc[1] + 1; \
2466 } \
2467 temp[0] = temp_sum; \
2468 temp[1] = acc[1] + temp[1]; \
2469 } else { \
2470 temp_sum = acc[0] - temp[0]; \
2471 if ((uint64_t)temp_sum > (uint64_t)acc[0]) { \
2472 acc[1] = acc[1] - 1; \
2473 } \
2474 temp[0] = temp_sum; \
2475 temp[1] = acc[1] - temp[1]; \
2476 } \
2477 \
2478 env->active_tc.HI[ac] = temp[1]; \
2479 env->active_tc.LO[ac] = temp[0]; \
2480 }
2481
2482 DP_QH(dpa_w_qh, 1, 0);
2483 DP_QH(dpaq_s_w_qh, 1, 1);
2484 DP_QH(dps_w_qh, 0, 0);
2485 DP_QH(dpsq_s_w_qh, 0, 1);
2486
2487 #undef DP_QH
2488
2489 #endif
2490
2491 #define DP_L_W(name, is_add) \
2492 void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt, \
2493 CPUMIPSState *env) \
2494 { \
2495 int32_t temp63; \
2496 int64_t dotp, acc; \
2497 uint64_t temp; \
2498 bool overflow; \
2499 \
2500 dotp = mipsdsp_mul_q31_q31(ac, rs, rt, env); \
2501 acc = ((uint64_t)env->active_tc.HI[ac] << 32) | \
2502 ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO); \
2503 if (is_add) { \
2504 temp = acc + dotp; \
2505 overflow = MIPSDSP_OVERFLOW_ADD((uint64_t)acc, (uint64_t)dotp, \
2506 temp, (0x01ull << 63)); \
2507 } else { \
2508 temp = acc - dotp; \
2509 overflow = MIPSDSP_OVERFLOW_SUB((uint64_t)acc, (uint64_t)dotp, \
2510 temp, (0x01ull << 63)); \
2511 } \
2512 \
2513 if (overflow) { \
2514 temp63 = (temp >> 63) & 0x01; \
2515 if (temp63 == 1) { \
2516 temp = (0x01ull << 63) - 1; \
2517 } else { \
2518 temp = 0x01ull << 63; \
2519 } \
2520 \
2521 set_DSPControl_overflow_flag(1, 16 + ac, env); \
2522 } \
2523 \
2524 env->active_tc.HI[ac] = (target_long)(int32_t) \
2525 ((temp & MIPSDSP_LHI) >> 32); \
2526 env->active_tc.LO[ac] = (target_long)(int32_t) \
2527 (temp & MIPSDSP_LLO); \
2528 }
2529
2530 DP_L_W(dpaq_sa_l_w, 1);
2531 DP_L_W(dpsq_sa_l_w, 0);
2532
2533 #undef DP_L_W
2534
2535 #if defined(TARGET_MIPS64)
2536 #define DP_L_PW(name, func) \
2537 void helper_##name(target_ulong rs, target_ulong rt, uint32_t ac, \
2538 CPUMIPSState *env) \
2539 { \
2540 int32_t rs1, rs0; \
2541 int32_t rt1, rt0; \
2542 int64_t tempB[2], tempA[2]; \
2543 int64_t temp[2]; \
2544 int64_t acc[2]; \
2545 int64_t temp_sum; \
2546 \
2547 temp[0] = 0; \
2548 temp[1] = 0; \
2549 \
2550 MIPSDSP_SPLIT64_32(rs, rs1, rs0); \
2551 MIPSDSP_SPLIT64_32(rt, rt1, rt0); \
2552 \
2553 tempB[0] = mipsdsp_mul_q31_q31(ac, rs1, rt1, env); \
2554 tempA[0] = mipsdsp_mul_q31_q31(ac, rs0, rt0, env); \
2555 \
2556 if (tempB[0] >= 0) { \
2557 tempB[1] = 0x00; \
2558 } else { \
2559 tempB[1] = ~0ull; \
2560 } \
2561 \
2562 if (tempA[0] >= 0) { \
2563 tempA[1] = 0x00; \
2564 } else { \
2565 tempA[1] = ~0ull; \
2566 } \
2567 \
2568 temp_sum = tempB[0] + tempA[0]; \
2569 if (((uint64_t)temp_sum < (uint64_t)tempB[0]) && \
2570 ((uint64_t)temp_sum < (uint64_t)tempA[0])) { \
2571 temp[1] += 1; \
2572 } \
2573 temp[0] = temp_sum; \
2574 temp[1] += tempB[1] + tempA[1]; \
2575 \
2576 mipsdsp_##func(acc, ac, temp, env); \
2577 \
2578 env->active_tc.HI[ac] = acc[1]; \
2579 env->active_tc.LO[ac] = acc[0]; \
2580 }
2581
2582 DP_L_PW(dpaq_sa_l_pw, sat64_acc_add_q63);
2583 DP_L_PW(dpsq_sa_l_pw, sat64_acc_sub_q63);
2584
2585 #undef DP_L_PW
2586
2587 void helper_mulsaq_s_l_pw(target_ulong rs, target_ulong rt, uint32_t ac,
2588 CPUMIPSState *env)
2589 {
2590 int32_t rs1, rs0;
2591 int32_t rt1, rt0;
2592 int64_t tempB[2], tempA[2];
2593 int64_t temp[2];
2594 int64_t acc[2];
2595 int64_t temp_sum;
2596
2597 rs1 = (rs >> 32) & MIPSDSP_LLO;
2598 rs0 = rs & MIPSDSP_LLO;
2599 rt1 = (rt >> 32) & MIPSDSP_LLO;
2600 rt0 = rt & MIPSDSP_LLO;
2601
2602 tempB[0] = mipsdsp_mul_q31_q31(ac, rs1, rt1, env);
2603 tempA[0] = mipsdsp_mul_q31_q31(ac, rs0, rt0, env);
2604
2605 if (tempB[0] >= 0) {
2606 tempB[1] = 0x00;
2607 } else {
2608 tempB[1] = ~0ull;
2609 }
2610
2611 if (tempA[0] >= 0) {
2612 tempA[1] = 0x00;
2613 } else {
2614 tempA[1] = ~0ull;
2615 }
2616
2617 acc[0] = env->active_tc.LO[ac];
2618 acc[1] = env->active_tc.HI[ac];
2619
2620 temp_sum = tempB[0] - tempA[0];
2621 if ((uint64_t)temp_sum > (uint64_t)tempB[0]) {
2622 tempB[1] -= 1;
2623 }
2624 temp[0] = temp_sum;
2625 temp[1] = tempB[1] - tempA[1];
2626
2627 if ((temp[1] & 0x01) == 0) {
2628 temp[1] = 0x00;
2629 } else {
2630 temp[1] = ~0ull;
2631 }
2632
2633 temp_sum = acc[0] + temp[0];
2634 if (((uint64_t)temp_sum < (uint64_t)acc[0]) &&
2635 ((uint64_t)temp_sum < (uint64_t)temp[0])) {
2636 acc[1] += 1;
2637 }
2638 acc[0] = temp_sum;
2639 acc[1] += temp[1];
2640
2641 env->active_tc.HI[ac] = acc[1];
2642 env->active_tc.LO[ac] = acc[0];
2643 }
2644 #endif
2645
2646 #define MAQ_S_W(name, mov) \
2647 void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt, \
2648 CPUMIPSState *env) \
2649 { \
2650 int16_t rsh, rth; \
2651 int32_t tempA; \
2652 int64_t tempL, acc; \
2653 \
2654 rsh = (rs >> mov) & MIPSDSP_LO; \
2655 rth = (rt >> mov) & MIPSDSP_LO; \
2656 tempA = mipsdsp_mul_q15_q15(ac, rsh, rth, env); \
2657 acc = ((uint64_t)env->active_tc.HI[ac] << 32) | \
2658 ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO); \
2659 tempL = (int64_t)tempA + acc; \
2660 env->active_tc.HI[ac] = (target_long)(int32_t) \
2661 ((tempL & MIPSDSP_LHI) >> 32); \
2662 env->active_tc.LO[ac] = (target_long)(int32_t) \
2663 (tempL & MIPSDSP_LLO); \
2664 }
2665
2666 MAQ_S_W(maq_s_w_phl, 16);
2667 MAQ_S_W(maq_s_w_phr, 0);
2668
2669 #undef MAQ_S_W
2670
2671 #define MAQ_SA_W(name, mov) \
2672 void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt, \
2673 CPUMIPSState *env) \
2674 { \
2675 int16_t rsh, rth; \
2676 int32_t tempA; \
2677 \
2678 rsh = (rs >> mov) & MIPSDSP_LO; \
2679 rth = (rt >> mov) & MIPSDSP_LO; \
2680 tempA = mipsdsp_mul_q15_q15(ac, rsh, rth, env); \
2681 tempA = mipsdsp_sat32_acc_q31(ac, tempA, env); \
2682 \
2683 env->active_tc.HI[ac] = (target_long)(int32_t)(((int64_t)tempA & \
2684 MIPSDSP_LHI) >> 32); \
2685 env->active_tc.LO[ac] = (target_long)(int32_t)((int64_t)tempA & \
2686 MIPSDSP_LLO); \
2687 }
2688
2689 MAQ_SA_W(maq_sa_w_phl, 16);
2690 MAQ_SA_W(maq_sa_w_phr, 0);
2691
2692 #undef MAQ_SA_W
2693
2694 #define MULQ_W(name, addvar) \
2695 target_ulong helper_##name(target_ulong rs, target_ulong rt, \
2696 CPUMIPSState *env) \
2697 { \
2698 int32_t rs_t, rt_t; \
2699 int32_t tempI; \
2700 int64_t tempL; \
2701 \
2702 rs_t = rs & MIPSDSP_LLO; \
2703 rt_t = rt & MIPSDSP_LLO; \
2704 \
2705 if ((rs_t == 0x80000000) && (rt_t == 0x80000000)) { \
2706 tempL = 0x7FFFFFFF00000000ull; \
2707 set_DSPControl_overflow_flag(1, 21, env); \
2708 } else { \
2709 tempL = ((int64_t)rs_t * (int64_t)rt_t) << 1; \
2710 tempL += addvar; \
2711 } \
2712 tempI = (tempL & MIPSDSP_LHI) >> 32; \
2713 \
2714 return (target_long)(int32_t)tempI; \
2715 }
2716
2717 MULQ_W(mulq_s_w, 0);
2718 MULQ_W(mulq_rs_w, 0x80000000ull);
2719
2720 #undef MULQ_W
2721
2722 #if defined(TARGET_MIPS64)
2723
2724 #define MAQ_S_W_QH(name, mov) \
2725 void helper_##name(target_ulong rs, target_ulong rt, uint32_t ac, \
2726 CPUMIPSState *env) \
2727 { \
2728 int16_t rs_t, rt_t; \
2729 int32_t temp_mul; \
2730 int64_t temp[2]; \
2731 int64_t acc[2]; \
2732 int64_t temp_sum; \
2733 \
2734 temp[0] = 0; \
2735 temp[1] = 0; \
2736 \
2737 rs_t = (rs >> mov) & MIPSDSP_LO; \
2738 rt_t = (rt >> mov) & MIPSDSP_LO; \
2739 temp_mul = mipsdsp_mul_q15_q15(ac, rs_t, rt_t, env); \
2740 \
2741 temp[0] = (int64_t)temp_mul; \
2742 if (temp[0] >= 0) { \
2743 temp[1] = 0x00; \
2744 } else { \
2745 temp[1] = ~0ull; \
2746 } \
2747 \
2748 acc[0] = env->active_tc.LO[ac]; \
2749 acc[1] = env->active_tc.HI[ac]; \
2750 \
2751 temp_sum = acc[0] + temp[0]; \
2752 if (((uint64_t)temp_sum < (uint64_t)acc[0]) && \
2753 ((uint64_t)temp_sum < (uint64_t)temp[0])) { \
2754 acc[1] += 1; \
2755 } \
2756 acc[0] = temp_sum; \
2757 acc[1] += temp[1]; \
2758 \
2759 env->active_tc.HI[ac] = acc[1]; \
2760 env->active_tc.LO[ac] = acc[0]; \
2761 }
2762
2763 MAQ_S_W_QH(maq_s_w_qhll, 48);
2764 MAQ_S_W_QH(maq_s_w_qhlr, 32);
2765 MAQ_S_W_QH(maq_s_w_qhrl, 16);
2766 MAQ_S_W_QH(maq_s_w_qhrr, 0);
2767
2768 #undef MAQ_S_W_QH
2769
2770 #define MAQ_SA_W(name, mov) \
2771 void helper_##name(target_ulong rs, target_ulong rt, uint32_t ac, \
2772 CPUMIPSState *env) \
2773 { \
2774 int16_t rs_t, rt_t; \
2775 int32_t temp; \
2776 int64_t acc[2]; \
2777 \
2778 rs_t = (rs >> mov) & MIPSDSP_LO; \
2779 rt_t = (rt >> mov) & MIPSDSP_LO; \
2780 temp = mipsdsp_mul_q15_q15(ac, rs_t, rt_t, env); \
2781 temp = mipsdsp_sat32_acc_q31(ac, temp, env); \
2782 \
2783 acc[0] = (int64_t)(int32_t)temp; \
2784 if (acc[0] >= 0) { \
2785 acc[1] = 0x00; \
2786 } else { \
2787 acc[1] = ~0ull; \
2788 } \
2789 \
2790 env->active_tc.HI[ac] = acc[1]; \
2791 env->active_tc.LO[ac] = acc[0]; \
2792 }
2793
2794 MAQ_SA_W(maq_sa_w_qhll, 48);
2795 MAQ_SA_W(maq_sa_w_qhlr, 32);
2796 MAQ_SA_W(maq_sa_w_qhrl, 16);
2797 MAQ_SA_W(maq_sa_w_qhrr, 0);
2798
2799 #undef MAQ_SA_W
2800
2801 #define MAQ_S_L_PW(name, mov) \
2802 void helper_##name(target_ulong rs, target_ulong rt, uint32_t ac, \
2803 CPUMIPSState *env) \
2804 { \
2805 int32_t rs_t, rt_t; \
2806 int64_t temp[2]; \
2807 int64_t acc[2]; \
2808 int64_t temp_sum; \
2809 \
2810 temp[0] = 0; \
2811 temp[1] = 0; \
2812 \
2813 rs_t = (rs >> mov) & MIPSDSP_LLO; \
2814 rt_t = (rt >> mov) & MIPSDSP_LLO; \
2815 \
2816 temp[0] = mipsdsp_mul_q31_q31(ac, rs_t, rt_t, env); \
2817 if (temp[0] >= 0) { \
2818 temp[1] = 0x00; \
2819 } else { \
2820 temp[1] = ~0ull; \
2821 } \
2822 \
2823 acc[0] = env->active_tc.LO[ac]; \
2824 acc[1] = env->active_tc.HI[ac]; \
2825 \
2826 temp_sum = acc[0] + temp[0]; \
2827 if (((uint64_t)temp_sum < (uint64_t)acc[0]) && \
2828 ((uint64_t)temp_sum < (uint64_t)temp[0])) { \
2829 acc[1] += 1; \
2830 } \
2831 acc[0] = temp_sum; \
2832 acc[1] += temp[1]; \
2833 \
2834 env->active_tc.HI[ac] = acc[1]; \
2835 env->active_tc.LO[ac] = acc[0]; \
2836 }
2837
2838 MAQ_S_L_PW(maq_s_l_pwl, 32);
2839 MAQ_S_L_PW(maq_s_l_pwr, 0);
2840
2841 #undef MAQ_S_L_PW
2842
2843 #define DM_OPERATE(name, func, is_add, sigext) \
2844 void helper_##name(target_ulong rs, target_ulong rt, uint32_t ac, \
2845 CPUMIPSState *env) \
2846 { \
2847 int32_t rs1, rs0; \
2848 int32_t rt1, rt0; \
2849 int64_t tempBL[2], tempAL[2]; \
2850 int64_t acc[2]; \
2851 int64_t temp[2]; \
2852 int64_t temp_sum; \
2853 \
2854 temp[0] = 0x00; \
2855 temp[1] = 0x00; \
2856 \
2857 MIPSDSP_SPLIT64_32(rs, rs1, rs0); \
2858 MIPSDSP_SPLIT64_32(rt, rt1, rt0); \
2859 \
2860 if (sigext) { \
2861 tempBL[0] = (int64_t)mipsdsp_##func(rs1, rt1); \
2862 tempAL[0] = (int64_t)mipsdsp_##func(rs0, rt0); \
2863 \
2864 if (tempBL[0] >= 0) { \
2865 tempBL[1] = 0x0; \
2866 } else { \
2867 tempBL[1] = ~0ull; \
2868 } \
2869 \
2870 if (tempAL[0] >= 0) { \
2871 tempAL[1] = 0x0; \
2872 } else { \
2873 tempAL[1] = ~0ull; \
2874 } \
2875 } else { \
2876 tempBL[0] = mipsdsp_##func(rs1, rt1); \
2877 tempAL[0] = mipsdsp_##func(rs0, rt0); \
2878 tempBL[1] = 0; \
2879 tempAL[1] = 0; \
2880 } \
2881 \
2882 acc[1] = env->active_tc.HI[ac]; \
2883 acc[0] = env->active_tc.LO[ac]; \
2884 \
2885 temp_sum = tempBL[0] + tempAL[0]; \
2886 if (((uint64_t)temp_sum < (uint64_t)tempBL[0]) && \
2887 ((uint64_t)temp_sum < (uint64_t)tempAL[0])) { \
2888 temp[1] += 1; \
2889 } \
2890 temp[0] = temp_sum; \
2891 temp[1] += tempBL[1] + tempAL[1]; \
2892 \
2893 if (is_add) { \
2894 temp_sum = acc[0] + temp[0]; \
2895 if (((uint64_t)temp_sum < (uint64_t)acc[0]) && \
2896 ((uint64_t)temp_sum < (uint64_t)temp[0])) { \
2897 acc[1] += 1; \
2898 } \
2899 temp[0] = temp_sum; \
2900 temp[1] = acc[1] + temp[1]; \
2901 } else { \
2902 temp_sum = acc[0] - temp[0]; \
2903 if ((uint64_t)temp_sum > (uint64_t)acc[0]) { \
2904 acc[1] -= 1; \
2905 } \
2906 temp[0] = temp_sum; \
2907 temp[1] = acc[1] - temp[1]; \
2908 } \
2909 \
2910 env->active_tc.HI[ac] = temp[1]; \
2911 env->active_tc.LO[ac] = temp[0]; \
2912 }
2913
2914 DM_OPERATE(dmadd, mul_i32_i32, 1, 1);
2915 DM_OPERATE(dmaddu, mul_u32_u32, 1, 0);
2916 DM_OPERATE(dmsub, mul_i32_i32, 0, 1);
2917 DM_OPERATE(dmsubu, mul_u32_u32, 0, 0);
2918 #undef DM_OPERATE
2919 #endif
2920
2921 /** DSP Bit/Manipulation Sub-class insns **/
2922 target_ulong helper_bitrev(target_ulong rt)
2923 {
2924 int32_t temp;
2925 uint32_t rd;
2926 int i;
2927
2928 temp = rt & MIPSDSP_LO;
2929 rd = 0;
2930 for (i = 0; i < 16; i++) {
2931 rd = (rd << 1) | (temp & 1);
2932 temp = temp >> 1;
2933 }
2934
2935 return (target_ulong)rd;
2936 }
2937
2938 #define BIT_INSV(name, posfilter, sizefilter, ret_type) \
2939 target_ulong helper_##name(CPUMIPSState *env, target_ulong rs, \
2940 target_ulong rt) \
2941 { \
2942 uint32_t pos, size, msb, lsb; \
2943 target_ulong filter; \
2944 target_ulong temp, temprs, temprt; \
2945 target_ulong dspc; \
2946 \
2947 dspc = env->active_tc.DSPControl; \
2948 \
2949 pos = dspc & posfilter; \
2950 size = (dspc >> 7) & sizefilter; \
2951 \
2952 msb = pos + size - 1; \
2953 lsb = pos; \
2954 \
2955 if (lsb > msb || (msb > TARGET_LONG_BITS)) { \
2956 return rt; \
2957 } \
2958 \
2959 filter = ((int32_t)0x01 << size) - 1; \
2960 filter = filter << pos; \
2961 temprs = (rs << pos) & filter; \
2962 temprt = rt & ~filter; \
2963 temp = temprs | temprt; \
2964 \
2965 return (target_long)(ret_type)temp; \
2966 }
2967
2968 BIT_INSV(insv, 0x1F, 0x1F, int32_t);
2969 #ifdef TARGET_MIPS64
2970 BIT_INSV(dinsv, 0x7F, 0x3F, target_long);
2971 #endif
2972
2973 #undef BIT_INSV
2974
2975
2976 /** DSP Compare-Pick Sub-class insns **/
2977 #define CMP_HAS_RET(name, func, split_num, filter, bit_size) \
2978 target_ulong helper_##name(target_ulong rs, target_ulong rt) \
2979 { \
2980 uint32_t rs_t, rt_t; \
2981 uint8_t cc; \
2982 uint32_t temp = 0; \
2983 int i; \
2984 \
2985 for (i = 0; i < split_num; i++) { \
2986 rs_t = (rs >> (bit_size * i)) & filter; \
2987 rt_t = (rt >> (bit_size * i)) & filter; \
2988 cc = mipsdsp_##func(rs_t, rt_t); \
2989 temp |= cc << i; \
2990 } \
2991 \
2992 return (target_ulong)temp; \
2993 }
2994
2995 CMP_HAS_RET(cmpgu_eq_qb, cmpu_eq, 4, MIPSDSP_Q0, 8);
2996 CMP_HAS_RET(cmpgu_lt_qb, cmpu_lt, 4, MIPSDSP_Q0, 8);
2997 CMP_HAS_RET(cmpgu_le_qb, cmpu_le, 4, MIPSDSP_Q0, 8);
2998
2999 #ifdef TARGET_MIPS64
3000 CMP_HAS_RET(cmpgu_eq_ob, cmpu_eq, 8, MIPSDSP_Q0, 8);
3001 CMP_HAS_RET(cmpgu_lt_ob, cmpu_lt, 8, MIPSDSP_Q0, 8);
3002 CMP_HAS_RET(cmpgu_le_ob, cmpu_le, 8, MIPSDSP_Q0, 8);
3003 #endif
3004
3005 #undef CMP_HAS_RET
3006
3007
3008 #define CMP_NO_RET(name, func, split_num, filter, bit_size) \
3009 void helper_##name(target_ulong rs, target_ulong rt, \
3010 CPUMIPSState *env) \
3011 { \
3012 int##bit_size##_t rs_t, rt_t; \
3013 int##bit_size##_t flag = 0; \
3014 int##bit_size##_t cc; \
3015 int i; \
3016 \
3017 for (i = 0; i < split_num; i++) { \
3018 rs_t = (rs >> (bit_size * i)) & filter; \
3019 rt_t = (rt >> (bit_size * i)) & filter; \
3020 \
3021 cc = mipsdsp_##func((int32_t)rs_t, (int32_t)rt_t); \
3022 flag |= cc << i; \
3023 } \
3024 \
3025 set_DSPControl_24(flag, split_num, env); \
3026 }
3027
3028 CMP_NO_RET(cmpu_eq_qb, cmpu_eq, 4, MIPSDSP_Q0, 8);
3029 CMP_NO_RET(cmpu_lt_qb, cmpu_lt, 4, MIPSDSP_Q0, 8);
3030 CMP_NO_RET(cmpu_le_qb, cmpu_le, 4, MIPSDSP_Q0, 8);
3031
3032 CMP_NO_RET(cmp_eq_ph, cmp_eq, 2, MIPSDSP_LO, 16);
3033 CMP_NO_RET(cmp_lt_ph, cmp_lt, 2, MIPSDSP_LO, 16);
3034 CMP_NO_RET(cmp_le_ph, cmp_le, 2, MIPSDSP_LO, 16);
3035
3036 #ifdef TARGET_MIPS64
3037 CMP_NO_RET(cmpu_eq_ob, cmpu_eq, 8, MIPSDSP_Q0, 8);
3038 CMP_NO_RET(cmpu_lt_ob, cmpu_lt, 8, MIPSDSP_Q0, 8);
3039 CMP_NO_RET(cmpu_le_ob, cmpu_le, 8, MIPSDSP_Q0, 8);
3040
3041 CMP_NO_RET(cmp_eq_qh, cmp_eq, 4, MIPSDSP_LO, 16);
3042 CMP_NO_RET(cmp_lt_qh, cmp_lt, 4, MIPSDSP_LO, 16);
3043 CMP_NO_RET(cmp_le_qh, cmp_le, 4, MIPSDSP_LO, 16);
3044
3045 CMP_NO_RET(cmp_eq_pw, cmp_eq, 2, MIPSDSP_LLO, 32);
3046 CMP_NO_RET(cmp_lt_pw, cmp_lt, 2, MIPSDSP_LLO, 32);
3047 CMP_NO_RET(cmp_le_pw, cmp_le, 2, MIPSDSP_LLO, 32);
3048 #endif
3049 #undef CMP_NO_RET
3050
3051 #if defined(TARGET_MIPS64)
3052
3053 #define CMPGDU_OB(name) \
3054 target_ulong helper_cmpgdu_##name##_ob(target_ulong rs, target_ulong rt, \
3055 CPUMIPSState *env) \
3056 { \
3057 int i; \
3058 uint8_t rs_t, rt_t; \
3059 uint32_t cond; \
3060 \
3061 cond = 0; \
3062 \
3063 for (i = 0; i < 8; i++) { \
3064 rs_t = (rs >> (8 * i)) & MIPSDSP_Q0; \
3065 rt_t = (rt >> (8 * i)) & MIPSDSP_Q0; \
3066 \
3067 if (mipsdsp_cmpu_##name(rs_t, rt_t)) { \
3068 cond |= 0x01 << i; \
3069 } \
3070 } \
3071 \
3072 set_DSPControl_24(cond, 8, env); \
3073 \
3074 return (uint64_t)cond; \
3075 }
3076
3077 CMPGDU_OB(eq)
3078 CMPGDU_OB(lt)
3079 CMPGDU_OB(le)
3080 #undef CMPGDU_OB
3081 #endif
3082
3083 #define PICK_INSN(name, split_num, filter, bit_size, ret32bit) \
3084 target_ulong helper_##name(target_ulong rs, target_ulong rt, \
3085 CPUMIPSState *env) \
3086 { \
3087 uint32_t rs_t, rt_t; \
3088 uint32_t cc; \
3089 target_ulong dsp; \
3090 int i; \
3091 target_ulong result = 0; \
3092 \
3093 dsp = env->active_tc.DSPControl; \
3094 for (i = 0; i < split_num; i++) { \
3095 rs_t = (rs >> (bit_size * i)) & filter; \
3096 rt_t = (rt >> (bit_size * i)) & filter; \
3097 cc = (dsp >> (24 + i)) & 0x01; \
3098 cc = cc == 1 ? rs_t : rt_t; \
3099 \
3100 result |= (target_ulong)cc << (bit_size * i); \
3101 } \
3102 \
3103 if (ret32bit) { \
3104 result = (target_long)(int32_t)(result & MIPSDSP_LLO); \
3105 } \
3106 \
3107 return result; \
3108 }
3109
3110 PICK_INSN(pick_qb, 4, MIPSDSP_Q0, 8, 1);
3111 PICK_INSN(pick_ph, 2, MIPSDSP_LO, 16, 1);
3112
3113 #ifdef TARGET_MIPS64
3114 PICK_INSN(pick_ob, 8, MIPSDSP_Q0, 8, 0);
3115 PICK_INSN(pick_qh, 4, MIPSDSP_LO, 16, 0);
3116 PICK_INSN(pick_pw, 2, MIPSDSP_LLO, 32, 0);
3117 #endif
3118 #undef PICK_INSN
3119
3120 target_ulong helper_packrl_ph(target_ulong rs, target_ulong rt)
3121 {
3122 uint32_t rsl, rth;
3123
3124 rsl = rs & MIPSDSP_LO;
3125 rth = (rt & MIPSDSP_HI) >> 16;
3126
3127 return (target_long)(int32_t)((rsl << 16) | rth);
3128 }
3129
3130 #if defined(TARGET_MIPS64)
3131 target_ulong helper_packrl_pw(target_ulong rs, target_ulong rt)
3132 {
3133 uint32_t rs0, rt1;
3134
3135 rs0 = rs & MIPSDSP_LLO;
3136 rt1 = (rt >> 32) & MIPSDSP_LLO;
3137
3138 return ((uint64_t)rs0 << 32) | (uint64_t)rt1;
3139 }
3140 #endif
3141
3142 /** DSP Accumulator and DSPControl Access Sub-class insns **/
3143 target_ulong helper_extr_w(target_ulong ac, target_ulong shift,
3144 CPUMIPSState *env)
3145 {
3146 int32_t tempI;
3147 int64_t tempDL[2];
3148
3149 shift = shift & 0x1F;
3150
3151 mipsdsp_rndrashift_short_acc(tempDL, ac, shift, env);
3152 if ((tempDL[1] != 0 || (tempDL[0] & MIPSDSP_LHI) != 0) &&
3153 (tempDL[1] != 1 || (tempDL[0] & MIPSDSP_LHI) != MIPSDSP_LHI)) {
3154 set_DSPControl_overflow_flag(1, 23, env);
3155 }
3156
3157 tempI = (tempDL[0] >> 1) & MIPSDSP_LLO;
3158
3159 tempDL[0] += 1;
3160 if (tempDL[0] == 0) {
3161 tempDL[1] += 1;
3162 }
3163
3164 if ((!(tempDL[1] == 0 && (tempDL[0] & MIPSDSP_LHI) == 0x00)) &&
3165 (!(tempDL[1] == 1 && (tempDL[0] & MIPSDSP_LHI) == MIPSDSP_LHI))) {
3166 set_DSPControl_overflow_flag(1, 23, env);
3167 }
3168
3169 return (target_long)tempI;
3170 }
3171
3172 target_ulong helper_extr_r_w(target_ulong ac, target_ulong shift,
3173 CPUMIPSState *env)
3174 {
3175 int64_t tempDL[2];
3176
3177 shift = shift & 0x1F;
3178
3179 mipsdsp_rndrashift_short_acc(tempDL, ac, shift, env);
3180 if ((tempDL[1] != 0 || (tempDL[0] & MIPSDSP_LHI) != 0) &&
3181 (tempDL[1] != 1 || (tempDL[0] & MIPSDSP_LHI) != MIPSDSP_LHI)) {
3182 set_DSPControl_overflow_flag(1, 23, env);
3183 }
3184
3185 tempDL[0] += 1;
3186 if (tempDL[0] == 0) {
3187 tempDL[1] += 1;
3188 }
3189
3190 if ((tempDL[1] != 0 || (tempDL[0] & MIPSDSP_LHI) != 0) &&
3191 (tempDL[1] != 1 && (tempDL[0] & MIPSDSP_LHI) != MIPSDSP_LHI)) {
3192 set_DSPControl_overflow_flag(1, 23, env);
3193 }
3194
3195 return (target_long)(int32_t)(tempDL[0] >> 1);
3196 }
3197
3198 target_ulong helper_extr_rs_w(target_ulong ac, target_ulong shift,
3199 CPUMIPSState *env)
3200 {
3201 int32_t tempI, temp64;
3202 int64_t tempDL[2];
3203
3204 shift = shift & 0x1F;
3205
3206 mipsdsp_rndrashift_short_acc(tempDL, ac, shift, env);
3207 if ((tempDL[1] != 0 || (tempDL[0] & MIPSDSP_LHI) != 0) &&
3208 (tempDL[1] != 1 || (tempDL[0] & MIPSDSP_LHI) != MIPSDSP_LHI)) {
3209 set_DSPControl_overflow_flag(1, 23, env);
3210 }
3211 tempDL[0] += 1;
3212 if (tempDL[0] == 0) {
3213 tempDL[1] += 1;
3214 }
3215 tempI = tempDL[0] >> 1;
3216
3217 if ((tempDL[1] != 0 || (tempDL[0] & MIPSDSP_LHI) != 0) &&
3218 (tempDL[1] != 1 || (tempDL[0] & MIPSDSP_LHI) != MIPSDSP_LHI)) {
3219 temp64 = tempDL[1];
3220 if (temp64 == 0) {
3221 tempI = 0x7FFFFFFF;
3222 } else {
3223 tempI = 0x80000000;
3224 }
3225 set_DSPControl_overflow_flag(1, 23, env);
3226 }
3227
3228 return (target_long)tempI;
3229 }
3230
3231 #if defined(TARGET_MIPS64)
3232 target_ulong helper_dextr_w(target_ulong ac, target_ulong shift,
3233 CPUMIPSState *env)
3234 {
3235 uint64_t temp[3];
3236
3237 shift = shift & 0x3F;
3238
3239 mipsdsp_rndrashift_acc(temp, ac, shift, env);
3240
3241 return (int64_t)(int32_t)(temp[0] >> 1);
3242 }
3243
3244 target_ulong helper_dextr_r_w(target_ulong ac, target_ulong shift,
3245 CPUMIPSState *env)
3246 {
3247 uint64_t temp[3];
3248 uint32_t temp128;
3249
3250 shift = shift & 0x3F;
3251 mipsdsp_rndrashift_acc(temp, ac, shift, env);
3252
3253 temp[0] += 1;
3254 if (temp[0] == 0) {
3255 temp[1] += 1;
3256 if (temp[1] == 0) {
3257 temp[2] += 1;
3258 }
3259 }
3260
3261 temp128 = temp[2] & 0x01;
3262
3263 if ((temp128 != 0 || temp[1] != 0) &&
3264 (temp128 != 1 || temp[1] != ~0ull)) {
3265 set_DSPControl_overflow_flag(1, 23, env);
3266 }
3267
3268 return (int64_t)(int32_t)(temp[0] >> 1);
3269 }
3270
3271 target_ulong helper_dextr_rs_w(target_ulong ac, target_ulong shift,
3272 CPUMIPSState *env)
3273 {
3274 uint64_t temp[3];
3275 uint32_t temp128;
3276
3277 shift = shift & 0x3F;
3278 mipsdsp_rndrashift_acc(temp, ac, shift, env);
3279
3280 temp[0] += 1;
3281 if (temp[0] == 0) {
3282 temp[1] += 1;
3283 if (temp[1] == 0) {
3284 temp[2] += 1;
3285 }
3286 }
3287
3288 temp128 = temp[2] & 0x01;
3289
3290 if ((temp128 != 0 || temp[1] != 0) &&
3291 (temp128 != 1 || temp[1] != ~0ull)) {
3292 if (temp128 == 0) {
3293 temp[0] = 0x0FFFFFFFF;
3294 } else {
3295 temp[0] = 0x0100000000ULL;
3296 }
3297 set_DSPControl_overflow_flag(1, 23, env);
3298 }
3299
3300 return (int64_t)(int32_t)(temp[0] >> 1);
3301 }
3302
3303 target_ulong helper_dextr_l(target_ulong ac, target_ulong shift,
3304 CPUMIPSState *env)
3305 {
3306 uint64_t temp[3];
3307 target_ulong result;
3308
3309 shift = shift & 0x3F;
3310
3311 mipsdsp_rndrashift_acc(temp, ac, shift, env);
3312 result = (temp[1] << 63) | (temp[0] >> 1);
3313
3314 return result;
3315 }
3316
3317 target_ulong helper_dextr_r_l(target_ulong ac, target_ulong shift,
3318 CPUMIPSState *env)
3319 {
3320 uint64_t temp[3];
3321 uint32_t temp128;
3322 target_ulong result;
3323
3324 shift = shift & 0x3F;
3325 mipsdsp_rndrashift_acc(temp, ac, shift, env);
3326
3327 temp[0] += 1;
3328 if (temp[0] == 0) {
3329 temp[1] += 1;
3330 if (temp[1] == 0) {
3331 temp[2] += 1;
3332 }
3333 }
3334
3335 temp128 = temp[2] & 0x01;
3336
3337 if ((temp128 != 0 || temp[1] != 0) &&
3338 (temp128 != 1 || temp[1] != ~0ull)) {
3339 set_DSPControl_overflow_flag(1, 23, env);
3340 }
3341
3342 result = (temp[1] << 63) | (temp[0] >> 1);
3343
3344 return result;
3345 }
3346
3347 target_ulong helper_dextr_rs_l(target_ulong ac, target_ulong shift,
3348 CPUMIPSState *env)
3349 {
3350 uint64_t temp[3];
3351 uint32_t temp128;
3352 target_ulong result;
3353
3354 shift = shift & 0x3F;
3355 mipsdsp_rndrashift_acc(temp, ac, shift, env);
3356
3357 temp[0] += 1;
3358 if (temp[0] == 0) {
3359 temp[1] += 1;
3360 if (temp[1] == 0) {
3361 temp[2] += 1;
3362 }
3363 }
3364
3365 temp128 = temp[2] & 0x01;
3366
3367 if ((temp128 != 0 || temp[1] != 0) &&
3368 (temp128 != 1 || temp[1] != ~0ull)) {
3369 if (temp128 == 0) {
3370 temp[1] &= ~0x00ull - 1;
3371 temp[0] |= ~0x00ull - 1;
3372 } else {
3373 temp[1] |= 0x01;
3374 temp[0] &= 0x01;
3375 }
3376 set_DSPControl_overflow_flag(1, 23, env);
3377 }
3378 result = (temp[1] << 63) | (temp[0] >> 1);
3379
3380 return result;
3381 }
3382 #endif
3383
3384 target_ulong helper_extr_s_h(target_ulong ac, target_ulong shift,
3385 CPUMIPSState *env)
3386 {
3387 int64_t temp, acc;
3388
3389 shift = shift & 0x1F;
3390
3391 acc = ((int64_t)env->active_tc.HI[ac] << 32) |
3392 ((int64_t)env->active_tc.LO[ac] & 0xFFFFFFFF);
3393
3394 temp = acc >> shift;
3395
3396 if (temp > (int64_t)0x7FFF) {
3397 temp = 0x00007FFF;
3398 set_DSPControl_overflow_flag(1, 23, env);
3399 } else if (temp < (int64_t)0xFFFFFFFFFFFF8000ULL) {
3400 temp = 0xFFFF8000;
3401 set_DSPControl_overflow_flag(1, 23, env);
3402 }
3403
3404 return (target_long)(int32_t)(temp & 0xFFFFFFFF);
3405 }
3406
3407
3408 #if defined(TARGET_MIPS64)
3409 target_ulong helper_dextr_s_h(target_ulong ac, target_ulong shift,
3410 CPUMIPSState *env)
3411 {
3412 int64_t temp[2];
3413 uint32_t temp127;
3414
3415 shift = shift & 0x1F;
3416
3417 mipsdsp_rashift_acc((uint64_t *)temp, ac, shift, env);
3418
3419 temp127 = (temp[1] >> 63) & 0x01;
3420
3421 if ((temp127 == 0) && (temp[1] > 0 || temp[0] > 32767)) {
3422 temp[0] &= 0xFFFF0000;
3423 temp[0] |= 0x00007FFF;
3424 set_DSPControl_overflow_flag(1, 23, env);
3425 } else if ((temp127 == 1) &&
3426 (temp[1] < 0xFFFFFFFFFFFFFFFFll
3427 || temp[0] < 0xFFFFFFFFFFFF1000ll)) {
3428 temp[0] &= 0xFFFF0000;
3429 temp[0] |= 0x00008000;
3430 set_DSPControl_overflow_flag(1, 23, env);
3431 }
3432
3433 return (int64_t)(int16_t)(temp[0] & MIPSDSP_LO);
3434 }
3435
3436 #endif
3437
3438 target_ulong helper_extp(target_ulong ac, target_ulong size, CPUMIPSState *env)
3439 {
3440 int32_t start_pos;
3441 int sub;
3442 uint32_t temp;
3443 uint64_t acc;
3444
3445 size = size & 0x1F;
3446
3447 temp = 0;
3448 start_pos = get_DSPControl_pos(env);
3449 sub = start_pos - (size + 1);
3450 if (sub >= -1) {
3451 acc = ((uint64_t)env->active_tc.HI[ac] << 32) |
3452 ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO);
3453 temp = (acc >> (start_pos - size)) &
3454 (((uint32_t)0x01 << (size + 1)) - 1);
3455 set_DSPControl_efi(0, env);
3456 } else {
3457 set_DSPControl_efi(1, env);
3458 }
3459
3460 return (target_ulong)temp;
3461 }
3462
3463 target_ulong helper_extpdp(target_ulong ac, target_ulong size,
3464 CPUMIPSState *env)
3465 {
3466 int32_t start_pos;
3467 int sub;
3468 uint32_t temp;
3469 uint64_t acc;
3470
3471 size = size & 0x1F;
3472 temp = 0;
3473 start_pos = get_DSPControl_pos(env);
3474 sub = start_pos - (size + 1);
3475 if (sub >= -1) {
3476 acc = ((uint64_t)env->active_tc.HI[ac] << 32) |
3477 ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO);
3478 temp = (acc >> (start_pos - size)) &
3479 (((uint32_t)0x01 << (size + 1)) - 1);
3480
3481 set_DSPControl_pos(start_pos - (size + 1), env);
3482 set_DSPControl_efi(0, env);
3483 } else {
3484 set_DSPControl_efi(1, env);
3485 }
3486
3487 return (target_ulong)temp;
3488 }
3489
3490
3491 #if defined(TARGET_MIPS64)
3492 target_ulong helper_dextp(target_ulong ac, target_ulong size, CPUMIPSState *env)
3493 {
3494 int start_pos;
3495 int len;
3496 int sub;
3497 uint64_t tempB, tempA;
3498 uint64_t temp;
3499
3500 temp = 0;
3501
3502 size = size & 0x3F;
3503 start_pos = get_DSPControl_pos(env);
3504 len = start_pos - size;
3505 tempB = env->active_tc.HI[ac];
3506 tempA = env->active_tc.LO[ac];
3507
3508 sub = start_pos - (size + 1);
3509
3510 if (sub >= -1) {
3511 temp = (tempB << (64 - len)) | (tempA >> len);
3512 temp = temp & ((0x01 << (size + 1)) - 1);
3513 set_DSPControl_efi(0, env);
3514 } else {
3515 set_DSPControl_efi(1, env);
3516 }
3517
3518 return temp;
3519 }
3520
3521 target_ulong helper_dextpdp(target_ulong ac, target_ulong size,
3522 CPUMIPSState *env)
3523 {
3524 int start_pos;
3525 int len;
3526 int sub;
3527 uint64_t tempB, tempA;
3528 uint64_t temp;
3529
3530 temp = 0;
3531 size = size & 0x3F;
3532 start_pos = get_DSPControl_pos(env);
3533 len = start_pos - size;
3534 tempB = env->active_tc.HI[ac];
3535 tempA = env->active_tc.LO[ac];
3536
3537 sub = start_pos - (size + 1);
3538
3539 if (sub >= -1) {
3540 temp = (tempB << (64 - len)) | (tempA >> len);
3541 temp = temp & ((0x01 << (size + 1)) - 1);
3542 set_DSPControl_pos(sub, env);
3543 set_DSPControl_efi(0, env);
3544 } else {
3545 set_DSPControl_efi(1, env);
3546 }
3547
3548 return temp;
3549 }
3550
3551 #endif
3552
3553 void helper_shilo(target_ulong ac, target_ulong rs, CPUMIPSState *env)
3554 {
3555 int8_t rs5_0;
3556 uint64_t temp, acc;
3557
3558 rs5_0 = rs & 0x3F;
3559 rs5_0 = (int8_t)(rs5_0 << 2) >> 2;
3560
3561 if (unlikely(rs5_0 == 0)) {
3562 return;
3563 }
3564
3565 acc = (((uint64_t)env->active_tc.HI[ac] << 32) & MIPSDSP_LHI) |
3566 ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO);
3567
3568 if (rs5_0 > 0) {
3569 temp = acc >> rs5_0;
3570 } else {
3571 temp = acc << -rs5_0;
3572 }
3573
3574 env->active_tc.HI[ac] = (target_ulong)(int32_t)((temp & MIPSDSP_LHI) >> 32);
3575 env->active_tc.LO[ac] = (target_ulong)(int32_t)(temp & MIPSDSP_LLO);
3576 }
3577
3578 #if defined(TARGET_MIPS64)
3579 void helper_dshilo(target_ulong shift, target_ulong ac, CPUMIPSState *env)
3580 {
3581 int8_t shift_t;
3582 uint64_t tempB, tempA;
3583
3584 shift_t = (int8_t)(shift << 1) >> 1;
3585
3586 tempB = env->active_tc.HI[ac];
3587 tempA = env->active_tc.LO[ac];
3588
3589 if (shift_t != 0) {
3590 if (shift_t >= 0) {
3591 tempA = (tempB << (64 - shift_t)) | (tempA >> shift_t);
3592 tempB = tempB >> shift_t;
3593 } else {
3594 shift_t = -shift_t;
3595 tempB = (tempB << shift_t) | (tempA >> (64 - shift_t));
3596 tempA = tempA << shift_t;
3597 }
3598 }
3599
3600 env->active_tc.HI[ac] = tempB;
3601 env->active_tc.LO[ac] = tempA;
3602 }
3603
3604 #endif
3605 void helper_mthlip(target_ulong ac, target_ulong rs, CPUMIPSState *env)
3606 {
3607 int32_t tempA, tempB, pos;
3608
3609 tempA = rs;
3610 tempB = env->active_tc.LO[ac];
3611 env->active_tc.HI[ac] = (target_long)tempB;
3612 env->active_tc.LO[ac] = (target_long)tempA;
3613 pos = get_DSPControl_pos(env);
3614
3615 if (pos > 32) {
3616 return;
3617 } else {
3618 set_DSPControl_pos(pos + 32, env);
3619 }
3620 }
3621
3622 #if defined(TARGET_MIPS64)
3623 void helper_dmthlip(target_ulong rs, target_ulong ac, CPUMIPSState *env)
3624 {
3625 uint8_t ac_t;
3626 uint8_t pos;
3627 uint64_t tempB, tempA;
3628
3629 ac_t = ac & 0x3;
3630
3631 tempA = rs;
3632 tempB = env->active_tc.LO[ac_t];
3633
3634 env->active_tc.HI[ac_t] = tempB;
3635 env->active_tc.LO[ac_t] = tempA;
3636
3637 pos = get_DSPControl_pos(env);
3638
3639 if (pos <= 64) {
3640 pos = pos + 64;
3641 set_DSPControl_pos(pos, env);
3642 }
3643 }
3644 #endif
3645
3646 void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env)
3647 {
3648 uint8_t mask[6];
3649 uint8_t i;
3650 uint32_t newbits, overwrite;
3651 target_ulong dsp;
3652
3653 newbits = 0x00;
3654 overwrite = 0xFFFFFFFF;
3655 dsp = env->active_tc.DSPControl;
3656
3657 for (i = 0; i < 6; i++) {
3658 mask[i] = (mask_num >> i) & 0x01;
3659 }
3660
3661 if (mask[0] == 1) {
3662 #if defined(TARGET_MIPS64)
3663 overwrite &= 0xFFFFFF80;
3664 newbits &= 0xFFFFFF80;
3665 newbits |= 0x0000007F & rs;
3666 #else
3667 overwrite &= 0xFFFFFFC0;
3668 newbits &= 0xFFFFFFC0;
3669 newbits |= 0x0000003F & rs;
3670 #endif
3671 }
3672
3673 if (mask[1] == 1) {
3674 overwrite &= 0xFFFFE07F;
3675 newbits &= 0xFFFFE07F;
3676 newbits |= 0x00001F80 & rs;
3677 }
3678
3679 if (mask[2] == 1) {
3680 overwrite &= 0xFFFFDFFF;
3681 newbits &= 0xFFFFDFFF;
3682 newbits |= 0x00002000 & rs;
3683 }
3684
3685 if (mask[3] == 1) {
3686 overwrite &= 0xFF00FFFF;
3687 newbits &= 0xFF00FFFF;
3688 newbits |= 0x00FF0000 & rs;
3689 }
3690
3691 if (mask[4] == 1) {
3692 overwrite &= 0x00FFFFFF;
3693 newbits &= 0x00FFFFFF;
3694 #if defined(TARGET_MIPS64)
3695 newbits |= 0xFF000000 & rs;
3696 #else
3697 newbits |= 0x0F000000 & rs;
3698 #endif
3699 }
3700
3701 if (mask[5] == 1) {
3702 overwrite &= 0xFFFFBFFF;
3703 newbits &= 0xFFFFBFFF;
3704 newbits |= 0x00004000 & rs;
3705 }
3706
3707 dsp = dsp & overwrite;
3708 dsp = dsp | newbits;
3709 env->active_tc.DSPControl = dsp;
3710 }
3711
3712 void helper_wrdsp(target_ulong rs, target_ulong mask_num, CPUMIPSState *env)
3713 {
3714 return cpu_wrdsp(rs, mask_num, env);
3715 }
3716
3717 uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env)
3718 {
3719 uint8_t mask[6];
3720 uint32_t ruler, i;
3721 target_ulong temp;
3722 target_ulong dsp;
3723
3724 ruler = 0x01;
3725 for (i = 0; i < 6; i++) {
3726 mask[i] = (mask_num & ruler) >> i ;
3727 ruler = ruler << 1;
3728 }
3729
3730 temp = 0x00;
3731 dsp = env->active_tc.DSPControl;
3732
3733 if (mask[0] == 1) {
3734 #if defined(TARGET_MIPS64)
3735 temp |= dsp & 0x7F;
3736 #else
3737 temp |= dsp & 0x3F;
3738 #endif
3739 }
3740
3741 if (mask[1] == 1) {
3742 temp |= dsp & 0x1F80;
3743 }
3744
3745 if (mask[2] == 1) {
3746 temp |= dsp & 0x2000;
3747 }
3748
3749 if (mask[3] == 1) {
3750 temp |= dsp & 0x00FF0000;
3751 }
3752
3753 if (mask[4] == 1) {
3754 #if defined(TARGET_MIPS64)
3755 temp |= dsp & 0xFF000000;
3756 #else
3757 temp |= dsp & 0x0F000000;
3758 #endif
3759 }
3760
3761 if (mask[5] == 1) {
3762 temp |= dsp & 0x4000;
3763 }
3764
3765 return temp;
3766 }
3767
3768 target_ulong helper_rddsp(target_ulong mask_num, CPUMIPSState *env)
3769 {
3770 return cpu_rddsp(mask_num, env);
3771 }
3772
3773
3774 #undef MIPSDSP_LHI
3775 #undef MIPSDSP_LLO
3776 #undef MIPSDSP_HI
3777 #undef MIPSDSP_LO
3778 #undef MIPSDSP_Q3
3779 #undef MIPSDSP_Q2
3780 #undef MIPSDSP_Q1
3781 #undef MIPSDSP_Q0
3782
3783 #undef MIPSDSP_SPLIT32_8
3784 #undef MIPSDSP_SPLIT32_16
3785
3786 #undef MIPSDSP_RETURN32_8
3787 #undef MIPSDSP_RETURN32_16
3788
3789 #ifdef TARGET_MIPS64
3790 #undef MIPSDSP_SPLIT64_16
3791 #undef MIPSDSP_SPLIT64_32
3792 #undef MIPSDSP_RETURN64_16
3793 #undef MIPSDSP_RETURN64_32
3794 #endif
Qemu copy for testing